Methods for forming oxide layers

Abstract

This invention discloses a method for forming an oxide layer, comprising: Step 1, forming a polycrystalline silicon layer on the surface of a silicon substrate, wherein the thickness of the polycrystalline silicon layer is set according to the desired thickness of a first oxide layer; Step 2, oxidizing the entire polycrystalline silicon layer to form the first oxide layer using a thermal oxidation process. By utilizing the characteristic that the oxidation rate of the polycrystalline silicon layer is faster than that of the silicon substrate, the thermal process of forming the first oxide layer is reduced, thereby controlling the diffusion of dopant impurities on the silicon substrate. This invention can reduce the thermal process of oxide layer formation and control the diffusion of dopant impurities on the silicon substrate during oxide layer formation, thereby preventing adverse effects on device performance when a thick oxide layer is formed.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a method for forming an oxide layer. Background Technology

[0002] Thick oxide layers are widely present in power devices and are used to achieve isolation, field plates, and barrier layers for ion implantation.

[0003] Currently, thick oxide layers are typically formed by directly oxidizing silicon on a silicon substrate or silicon epitaxial layer with oxygen. The higher the oxidation temperature, the faster the oxidation rate. Common examples include 600V VDMOS or IGBTs, where the oxide layer thickness at the terminals is typically 1.6μm.

[0004] If pure oxygen, commonly known as dry oxidation, is used, forming a 1.6 μm oxide layer at 1100°C requires as much as 118 hours. Even with wet oxygen (oxygen + hydrogen), the process still takes 330 minutes at 1100°C. This high thermal process increases substrate back-spreading, meaning heavily doped impurities from the silicon substrate diffuse into the lightly doped epitaxial layer. Since the epitaxial layer formed on the silicon substrate surface typically serves as a drift region for breakdown voltage, the diffusion of heavily doped impurities alters its performance, reducing its breakdown voltage. To achieve the same breakdown voltage, the epitaxial layer thickness needs to be increased, which in turn increases cost, as epitaxial processes are relatively expensive in semiconductor integrated circuit manufacturing. Besides the adverse effects of silicon substrate back-spreading, the high thermal process of oxide layer formation also affects the doping concentration distribution of other devices on the wafer, negatively impacting device performance. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a method for forming an oxide layer, which can reduce the thermal process of the oxide layer formation process and control the diffusion of doped impurities on the silicon substrate during the oxide layer formation process, thereby preventing the formation of a thick oxide layer from having an adverse effect on device performance.

[0006] To solve the above-mentioned technical problems, the method for forming an oxide layer provided by the present invention includes the following steps:

[0007] Step 1: Provide a silicon substrate, and deposit polycrystalline silicon on the surface of the silicon substrate to form a polycrystalline silicon layer. The thickness of the polycrystalline silicon layer is set according to the required thickness of the first oxide layer.

[0008] Step 2: The polycrystalline silicon layer is completely oxidized to form the first oxide layer using a thermal oxidation process. By taking advantage of the fact that the oxidation rate of the polycrystalline silicon layer is faster than that of the silicon substrate, the thermal process of forming the first oxide layer is reduced, thereby controlling the diffusion of doped impurities on the silicon substrate.

[0009] A further improvement is that, in step one, a silicon epitaxial layer is formed on the surface of the silicon substrate, and the polycrystalline silicon layer is formed on the surface of the silicon epitaxial layer.

[0010] A further improvement is that the silicon substrate has a heavily doped structure of a first conductivity type, and the silicon epitaxial layer has a lightly doped structure of a first conductivity type.

[0011] A further improvement is that, in step one, before forming the polycrystalline silicon layer, a step of thermally oxidizing the silicon substrate to form a second oxide layer is included; the polycrystalline silicon layer is formed on the surface of the second oxide layer, and after step two is completed, the first oxide layer and the second oxide layer are superimposed to form a total oxide layer; the interface between the total oxide layer and the silicon substrate is improved by the second oxide layer.

[0012] A further improvement is that, in step one, after the polycrystalline silicon layer is formed, a step of doping the polycrystalline silicon layer is also included, which utilizes the characteristic that the oxidation rate of the doped polycrystalline silicon layer increases to further reduce the thermal process of the first oxide layer.

[0013] A further improvement is that the polycrystalline silicon layer is divided into multiple polycrystalline silicon sub-layers, and the first oxide layer is also divided into multiple first oxide sub-layers; each first oxide sub-layer is formed by thermal oxidation of the corresponding polycrystalline silicon sub-layer.

[0014] Each polycrystalline silicon sublayer is formed using the polycrystalline silicon deposition process described in step one, and the first oxide sublayer corresponding to each polycrystalline silicon sublayer is formed using the thermal oxidation process described in step two; the first oxide layer is formed by repeating the polycrystalline silicon deposition process described in step one and the thermal oxidation process described in step two the same number of times as the number of polycrystalline silicon sublayers.

[0015] Taking advantage of the characteristic that the thinner the polycrystalline silicon layer, the lower the oxidation rate, the final oxidation rate of the polycrystalline silicon layer is determined by the oxidation rate of each polycrystalline silicon sub-layer after the polycrystalline silicon layer is split into each polycrystalline silicon sub-layer. This can improve the final oxidation rate of the polycrystalline silicon layer and reduce the thermal process of forming the first oxide layer.

[0016] A further improvement is that the first oxide layer is formed on the flat surface of the silicon substrate and serves as part of the field oxide layer of the terminal region of the power device.

[0017] On a top view, the first oxide layer has a patterned structure, and the area surrounded by the patterned first oxide layer is an active region, in which the surface of the active region does not contain the first oxide layer.

[0018] A further improvement is that the power devices include VDMOS and IGBT.

[0019] A further improvement is that the maximum thickness of the first oxide layer is greater than 1.6 μm.

[0020] A further improvement is that the patterning process of the first oxide layer includes:

[0021] In step one, the polycrystalline silicon layer is formed on all surfaces of the silicon substrate, including the terminal region and the active region.

[0022] In step two, the first oxide layer is formed on all surfaces of the silicon substrate.

[0023] The active region is defined using photolithography, and the first oxide layer on the surface of the active region is removed by etching.

[0024] A further improvement is that the patterning process of the first oxide layer includes:

[0025] In step one, the polycrystalline silicon layer is formed on all surfaces of the silicon substrate, including the terminal region and the active region;

[0026] Step two includes the following steps:

[0027] A first mask layer is formed on the surface of the polycrystalline silicon layer;

[0028] The active region is defined by photolithography, and the first mask layer in the active region is removed by etching.

[0029] Next, step two is performed, in which the polysilicon layer in the active region is oxidized to form the first oxide layer, and the polysilicon layer outside the active region is covered by the first mask layer and is not oxidized.

[0030] Then, the first mask layer and the polysilicon layer outside the formation region of the active region are removed.

[0031] A further improvement is that the first oxide layer fills the isolation trench and serves as part of the trench isolation structure;

[0032] Prior to step one, the process includes forming isolation trenches in the silicon substrate;

[0033] In step one, the polycrystalline silicon layer is formed on the inner surface of the isolation trench;

[0034] In step two, after the first oxide layer is formed, the isolation trench is completely filled.

[0035] A further improvement is that the depth of the isolation trench is more than 1 μm.

[0036] A further improvement is that the first oxide layer fills the gate trench of the SGT MOSFET device and serves as part of the shielding dielectric layer;

[0037] Prior to step one, the process includes forming a gate trench in the silicon substrate;

[0038] In step one, the polysilicon layer is formed on the inner surface of the gate trench;

[0039] In step two, after the first oxide layer is formed, the middle region of the gate trench is not filled and serves as the formation region of the source polysilicon of the SGT MOSFET device.

[0040] A further improvement is that the maximum thickness of the shielding medium layer is 0.6 μm or more.

[0041] Unlike existing semiconductor integrated circuit manufacturing processes where oxide layers on silicon substrates are formed by thermal oxidation of the silicon substrate itself, such as dry or wet oxidation, this invention employs a polycrystalline silicon deposition followed by polycrystalline silicon thermal oxidation. Since the oxidation rate of polycrystalline silicon is greater than that of a single-crystal silicon substrate (i.e., a silicon wafer), this invention can significantly reduce oxidation time when the required oxide layer thickness is the same. This reduces the thermal process of oxide layer formation and controls the diffusion of dopants on the silicon substrate during oxide layer formation. Consequently, it prevents the formation of thick oxide layers from adversely affecting device performance, primarily due to the outward diffusion of dopant on the silicon substrate.

[0042] When a silicon epitaxial layer is formed on the surface of a silicon substrate, the voltage withstand capability of the silicon epitaxial layer remains good because the outward expansion of the silicon substrate is reduced. Therefore, it is not necessary to increase the thickness of the silicon epitaxial layer to eliminate the adverse effect of the reduced voltage withstand capability of the silicon epitaxial layer caused by the outward expansion of the silicon substrate. Therefore, compared with the prior art, the present invention can reduce the thickness of the silicon epitaxial layer, thereby saving costs.

[0043] In addition, reducing the thermal oxidation time of the oxide layer can save process time. Since process time is also a process cost in semiconductor integrated circuit manufacturing, saving process costs is a good practice.

[0044] Furthermore, since the present invention only requires adjusting the thickness of the polysilicon layer to adjust the thickness of the first oxide layer, and steps one and two can be repeated, the present invention can easily obtain the required oxide layer thickness. In contrast, the thickness of the oxide layer formed by thermal oxidation in existing methods is limited because the thicker the oxide layer, the more difficult it is for oxygen to diffuse to the oxide layer and silicon interface, thus slowing down the oxidation rate as the oxide layer thickness increases, eventually making it impractical. Therefore, the present invention can improve the thickness of the oxide layer formed by the thermal oxidation process.

[0045] In addition, the present invention can also be combined with a second oxide layer formed by thermal oxidation of a silicon substrate. The second oxide layer improves the interface performance between the total oxide layer and the surface of the silicon substrate, while the first oxide layer increases the thickness of the total oxide layer and reduces the thermal process of the total oxide layer. Since the second oxide layer is thinner, the thermal oxidation rate of the second oxide layer is also faster, and the thermal process can be controlled, ultimately achieving a good combined effect. Attached Figure Description

[0046] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0047] Figure 1 This is a flowchart of the method for forming the oxide layer according to the first embodiment of the present invention;

[0048] Figures 2A-2B This is a schematic diagram of the device structure in each step of the oxide layer formation method of the first embodiment of the present invention;

[0049] Figures 3A-3B This is a schematic diagram of the device structure in each step of the oxide layer formation method according to the second embodiment of the present invention;

[0050] Figure 4 This is a schematic diagram of the device structure formed by the oxide layer formation method of the third embodiment of the present invention;

[0051] Figure 5 This is a schematic diagram of the device structure formed by the oxide layer formation method of the fourth embodiment of the present invention;

[0052] Figure 6 This is a schematic diagram of the device structure during the formation process of the oxide layer formation method according to the fifth embodiment of the present invention;

[0053] Figure 7 This is a schematic diagram of the device structure during the formation process of the oxide layer in the sixth embodiment of the present invention;

[0054] Figure 8 This is a schematic diagram of the device structure during the formation process of the oxide layer in the seventh embodiment of the present invention. Detailed Implementation

[0055] The method for forming the oxide layer in the first embodiment of the present invention:

[0056] like Figure 1 The diagram shown is a flowchart of the method for forming an oxide layer according to the first embodiment of the present invention; as shown Figures 2A to 2B The diagram shown is a schematic representation of the device structure in each step of the oxide layer formation method according to the first embodiment of the present invention; the oxide layer formation method provided by the present invention includes the following steps:

[0057] Step 1, such as Figure 2A As shown, a silicon substrate 1 is provided, and a polycrystalline silicon layer 2 is formed by polycrystalline silicon deposition on the surface of the silicon substrate 1. The thickness of the polycrystalline silicon layer 2 is set according to the required thickness of the first oxide layer 3.

[0058] Preferably, a silicon epitaxial layer is formed on the surface of the silicon substrate 1, and the polycrystalline silicon layer 2 is formed on the surface of the silicon epitaxial layer.

[0059] The silicon substrate 1 has a heavily doped structure of a first conductivity type, and the silicon epitaxial layer has a lightly doped structure of a first conductivity type.

[0060] Step Two, as follows Figure 2B As shown, the polysilicon layer 2 is completely oxidized to form the first oxide layer 3 using a thermal oxidation process. By taking advantage of the fact that the oxidation rate of the polysilicon layer 2 is faster than that of the silicon substrate 1, the thermal process of forming the first oxide layer 3 is reduced, thereby controlling the diffusion of doped impurities on the silicon substrate 1.

[0061] A further improvement of the first embodiment of the present invention is that, in step one, after the polycrystalline silicon layer 2 is formed, a step of doping the polycrystalline silicon layer 2 is further included, taking advantage of the characteristic that the oxidation rate of the doped polycrystalline silicon layer 2 will increase to further reduce the thermal process of the first oxide layer 3.

[0062] The method of the first embodiment of the present invention is further illustrated below using specific parameters as an example:

[0063] If a 1.6 μm thick silicon dioxide layer is required, the thickness of the polycrystalline silicon layer 2 deposited in step one is 0.74 μm. The thickness of the first oxide layer 3 formed after completely oxidizing the polycrystalline silicon layer 2 in step two is exactly 1.6 μm. However, compared to existing methods that directly oxidize the silicon substrate 1, the first embodiment of this invention can significantly improve the formation rate of the first oxide layer 3 and reduce the thermal process because the oxidation rate of polycrystalline silicon is faster than the oxidation rate of the monocrystalline silicon on the silicon substrate 1.

[0064] As a further improvement to the first embodiment of the present invention to further increase the rate of polycrystalline silicon thermal oxidation, a heavily doped N-type ion implantation can be performed after the polycrystalline silicon layer 2 is deposited in step one. A typical condition is an energy of 60 keV and a 5e15cm² depth. -3 The dosage is [specifically], and the impurity is phosphorus. This improved method allows for a reduction in oxidation time to half to one-third of that without ion implantation, at the same oxide layer thickness and oxidation temperature.

[0065] Unlike existing semiconductor integrated circuit manufacturing processes where oxide layers formed on silicon substrate 1 are formed by thermal oxidation of the silicon substrate 1 itself, such as dry oxidation or wet oxidation, in the first embodiment of this invention, the oxide layer formed on silicon substrate 1 is formed by polycrystalline silicon deposition plus polycrystalline silicon thermal oxidation. Since the oxidation rate of polycrystalline silicon is greater than that of single-crystal silicon substrate 1, i.e., silicon wafer, when the required oxide layer thickness is the same, the first embodiment of this invention can greatly reduce the oxidation time, thereby reducing the thermal process of oxide layer formation and controlling the diffusion of dopant impurities on silicon substrate 1 during oxide layer formation. This prevents the formation of a thick oxide layer from adversely affecting device performance, mainly including the effect of dopant diffusion on silicon substrate 1.

[0066] When a silicon epitaxial layer is formed on the surface of silicon substrate 1, the voltage withstand capability of the silicon epitaxial layer remains good because the outward expansion of silicon substrate 1 is reduced. Therefore, it is not necessary to increase the thickness of the silicon epitaxial layer to eliminate the adverse effect of the reduced voltage withstand capability of the silicon epitaxial layer caused by the outward expansion of silicon substrate 1. Therefore, compared with the prior art, the first embodiment of the present invention can reduce the thickness of the silicon epitaxial layer, thereby saving costs.

[0067] In addition, reducing the thermal oxidation time of the oxide layer can save process time. Since process time is also a process cost in semiconductor integrated circuit manufacturing, saving process costs is a good practice.

[0068] Furthermore, since the thickness of the first oxide layer 3 can be adjusted by only adjusting the thickness of the polysilicon layer 2 in the first embodiment of the present invention, and steps one and two can be repeated, the first embodiment of the present invention can easily obtain the oxide layer of the required thickness. In contrast, the thickness of the oxide layer formed by thermal oxidation in existing methods is limited because the thicker the oxide layer, the more difficult it is for oxygen to diffuse to the oxide layer and silicon interface, which slows down the oxidation rate as the oxide layer thickness increases, eventually making it impractical. Therefore, the first embodiment of the present invention can improve the thickness of the oxide layer formed by the thermal oxidation process.

[0069] Method for forming oxide layer according to the second embodiment of the present invention:

[0070] like Figures 3A to 3BThe diagram shown is a schematic representation of the device structure in each step of the oxide layer formation method according to the second embodiment of the present invention. The difference between the oxide layer formation method of the second embodiment of the present invention and the oxide layer formation method of the first embodiment of the present invention is that the oxide layer formation method of the second embodiment of the present invention has the following characteristics:

[0071] like Figure 3A As shown, in step one, before forming the polycrystalline silicon layer 2, the step of thermally oxidizing the silicon substrate 1 to form a second oxide layer 4 is also included; the polycrystalline silicon layer 2 is formed on the surface of the second oxide layer 4.

[0072] like Figure 3B As shown, after step two is completed, the first oxide layer 3 and the second oxide layer 4 are stacked to form a total oxide layer 5; the interface between the total oxide layer 5 and the silicon substrate 1 is improved by the second oxide layer 4.

[0073] In the second embodiment of the present invention, a second oxide layer 4 formed by thermal oxidation of silicon substrate 1 is incorporated. The second oxide layer 4 is used to improve the interface performance between the total oxide layer 5 and the surface of silicon substrate 1. The first oxide layer 3 is used to increase the thickness of the total oxide layer 5 and reduce the thermal process of the total oxide layer 5. Since the second oxide layer 4 is thinner, the thermal oxidation rate of the second oxide layer 4 is also faster, and the thermal process can be controlled, ultimately achieving a good combined effect.

[0074] The method of the second embodiment of the present invention is further illustrated below using specific parameters as an example:

[0075] The second oxide layer 4 is formed by conventional oxidation processes, namely, dry oxidation or wet oxidation, directly oxidizing the silicon substrate 1. To reduce the thermal process, wet oxidation is more effective. The thickness of the second oxide layer 4 can be...

[0076] (It can be either a dry oxide layer or a wet oxide layer, but a wet oxide layer is preferred because it has a faster growth rate and less thermal stress.) First, grow an oxide layer with a thickness of 0.2 μm. In this way, the interface between the final total oxide layer 5 and the silicon substrate 1 is determined by the interface between the second oxide layer 4 and the silicon substrate 1, which is better than the interface between the first oxide layer 3 and the silicon substrate 1 corresponding to Figure 2B.

[0077] Then, the polycrystalline silicon layer 2 is formed by polycrystalline silicon deposition in step one, and the thickness of the polycrystalline silicon layer 2 is 0.64 μm.

[0078] Then, the polycrystalline silicon undergoes thermal oxidation in step two to form the first oxide layer 3. Finally, a superimposed layer structure consisting of the second oxide layer 4 and the first oxide layer 3 is formed, namely the total oxide layer 5.

[0079] The method for forming the oxide layer in the third embodiment of the present invention:

[0080] like Figure 4 The diagram shown is a schematic representation of the device structure formed by the oxide layer formation method of the third embodiment of the present invention. The difference between the oxide layer formation method of the third embodiment and the oxide layer formation method of the second embodiment is that the oxide layer formation method of the third embodiment has the following characteristics:

[0081] The polycrystalline silicon layer 2 is divided into multiple polycrystalline silicon sub-layers, and the first oxide layer 3 is also divided into multiple first oxide sub-layers; each first oxide sub-layer is formed by thermal oxidation of the corresponding polycrystalline silicon sub-layer. Figure 4 In the diagram, the first oxide layer 3 is divided into two first oxide sub-layers, which are marked with labels 3a and 3b, respectively.

[0082] Each polycrystalline silicon sublayer is formed using the polycrystalline silicon deposition process described in step one, and the first oxide sublayer corresponding to each polycrystalline silicon sublayer is formed using the thermal oxidation process described in step two; the polycrystalline silicon deposition process described in step one and the thermal oxidation process described in step two are repeated the same number of times as the number of polycrystalline silicon sublayers to form the first oxide layer 3.

[0083] Taking advantage of the characteristic that the thinner the polycrystalline silicon layer, the lower the oxidation rate, the polycrystalline silicon layer 2 is divided into each polycrystalline silicon sub-layer, so that the final oxidation rate of the polycrystalline silicon layer 2 is determined by the oxidation rate of each polycrystalline silicon sub-layer. This can improve the final oxidation rate of the polycrystalline silicon layer 2 and reduce the thermal process of forming the first oxide layer 3.

[0084] The third embodiment of the present invention will be further described below in conjunction with the principles and parameters:

[0085] Because the growth process of the oxide layer consists of the following three steps:

[0086] After oxygen flows out of the vent in the gas supply section, it diffuses onto the surface of the oxide layer.

[0087] Oxygen diffuses from the oxide layer surface to the silicon surface, i.e., the interface between silicon and the oxide layer.

[0088] Oxygen reacts with silicon to form SiO2, which is an oxide layer. In other words, oxygen and silicon react to form an oxide layer after contact.

[0089] Therefore, as the oxide layer thickness increases, it becomes more difficult for oxygen to diffuse from the oxide layer surface to the interface between silicon and the oxide layer.

[0090] This means that when the oxide layer is relatively thin, the time required to grow a certain oxide layer thickness is directly proportional to tox and t, where t is the oxidation time. However, when the oxide layer is relatively thick, the time t required to grow a certain oxide layer thickness... ox It is proportional to This refers to the square root of the oxidation time. In other words, the oxidation rate is faster when the oxide layer is thinner, and slower as the oxide layer thickness increases.

[0091] Polycrystalline silicon oxidizes faster than monocrystalline silicon, but it still follows the formula mentioned above.

[0092] To further reduce the thermal process of oxidation, the method of the third embodiment of the present invention can be used:

[0093] The method of the third embodiment of the present invention can be improved based on the method of the first embodiment of the present invention, or it can be improved based on the method of the second embodiment of the present invention. The following description will take the method improved based on the method of the second embodiment of the present invention as an example.

[0094] First, growth is performed on the surface of the silicon substrate 1 using a thermal oxidation process such as wet oxidation. The second oxide layer 4.

[0095] Then, a 0.32 μm polycrystalline silicon sublayer is deposited. Next, the polycrystalline silicon is thermally oxidized to form the first oxide sublayer 3a. Then, another 0.32 μm polycrystalline silicon sublayer is deposited, followed by polycrystalline silicon thermal oxidation to form the first oxide sublayer 3b. Finally, the total oxide layer 5 of 1.6 μm is formed by the superposition of the second oxide layer 4, the first oxide sublayers 3a and 3b.

[0096] Figure 4 The CCP employs a two-stage thermal oxidation process for polycrystalline silicon, each time forming a 0.7μm oxide layer, and... Figure 3B Compared to the previous method of thermal oxidation of polycrystalline silicon to form a 1.4μm second oxide layer, the total time at 1100℃ is only 55% of the original, which is close to half of the original.

[0097] Increasing the number of cycles, using more polysilicon deposition and oxidation processes, can further reduce the thermal complexity. For thick oxide layers, theoretically, using N deposition and oxidation cycles can reduce the thermal complexity to approximately 1 / N of the original.

[0098] The method for forming the oxide layer in the fourth embodiment of the present invention:

[0099] The fourth embodiment of the present invention is a further application of the methods of the first to third embodiments described above, such as... Figure 5The diagram shown is a schematic representation of a device structure formed by the oxide layer formation method of the fourth embodiment of the present invention; the first oxide layer 3 is formed on the flat surface of the silicon substrate 1 and serves as a component of the field oxide layer in the terminal region of the power device. Figure 5 The following description uses the first oxide layer 3 formed by the method of the first embodiment of the present invention as an example of the field oxide layer. In other embodiments, when the method of the second embodiment of the present invention is used, the total oxide layer 5 formed by the superposition of the second oxide layer 4 and the first oxide layer 3 is used as the field oxide layer.

[0100] On the top view, the first oxide layer 3 has a patterned structure, and the area surrounded by the patterned first oxide layer 3 is an active region, in which the surface of the active region does not contain the first oxide layer 3.

[0101] The power devices include VDMOS and IGBT.

[0102] The maximum thickness of the first oxide layer 3 is more than 1.6 μm.

[0103] The patterning process of the first oxide layer 3 includes:

[0104] In step one, the polycrystalline silicon layer 2 is formed on all surfaces of the silicon substrate 1, including the terminal region and the active region.

[0105] In step two, the first oxide layer 3 is formed on all surfaces of the silicon substrate 1.

[0106] The active region is defined by photolithography, and the first oxide layer 3 on the surface of the active region is removed by etching.

[0107] During etching, it is desirable that the edge of the first oxide layer 3 after etching is not perpendicular, but rather at a certain angle. This is to ensure that polysilicon residue remains on the slope during subsequent processes, such as polysilicon or metal filling and subsequent etching. Such residue could potentially cause short circuits in the device.

[0108] The fifth embodiment of the present invention is a method for forming an oxide layer:

[0109] like Figure 6 The diagram shown is a schematic representation of the device structure during the formation process of the oxide layer in the fifth embodiment of the present invention. The difference between the oxide layer formation method of the fifth embodiment and the oxide layer formation method of the fourth embodiment is that the oxide layer formation method of the fourth embodiment has the following characteristics:

[0110] The patterning process of the first oxide layer 3 includes:

[0111] In step one, the polycrystalline silicon layer 2 is formed on all surfaces of the silicon substrate 1, including the terminal region and the active region;

[0112] Step two includes the following steps:

[0113] A first mask layer 101 is formed on the surface of the polysilicon layer 2, and typically the first mask layer 101 is a silicon nitride layer.

[0114] A photoresist pattern 102 is formed using a photolithography process to define the formation area of ​​the active region, and an etching process is performed to remove the first mask layer 101 in the formation area of ​​the active region.

[0115] Next, step two is performed. In step two, the polysilicon layer 2 in the active region is oxidized to form the first oxide layer 3, and the polysilicon layer 2 outside the active region is covered by the first mask layer 101 and is not oxidized.

[0116] Then, the photoresist pattern 102, the first mask layer 101, and the polysilicon layer 2 outside the formation area of ​​the active region are removed.

[0117] The method for forming the oxide layer in the sixth embodiment of the present invention:

[0118] The sixth embodiment of the present invention is a further application of the methods of the first to third embodiments described above, such as... Figure 7 The diagram shown is a schematic diagram of the device structure during the formation process of the oxide layer in the sixth embodiment of the present invention; the first oxide layer 3 is filled in the isolation trench and serves as a component of the trench isolation structure; Figure 7 The following description uses the total oxide layer 5, formed by the superposition of the second oxide layer 4 and the first oxide layer 3, as an example of the trench isolation structure formed by the method of the second embodiment of the present invention. In other embodiments, when the method of the first embodiment of the present invention is used, the first oxide layer 3 is used as the trench isolation structure.

[0119] In the sixth embodiment of the present invention:

[0120] Prior to step one, there is a step of forming isolation trenches in the silicon substrate 1.

[0121] The trench isolation structure is a deep trench isolation structure, and the depth of the isolation trench is more than 1 μm, and even exceeds 20 μm in some cases.

[0122] Then, thermal oxidation, such as wet oxidation, is performed on the surface of the silicon substrate 1, including the inner surface of the isolation trench, to form the second oxide layer 4.

[0123] Then, the polysilicon deposition process in step one is performed, in which the polysilicon layer 2 is formed on the inner surface of the isolation trench.

[0124] Then, the polycrystalline silicon thermal oxidation process continues in step two. In step two, after the first oxide layer 3 is formed, the isolation trench is completely filled.

[0125] Note that because the isolation trench is a deep trench, in the polycrystalline silicon thermal oxidation process of step two, oxygen needs to diffuse from the surface of the silicon substrate 1 into the isolation trench, thus forming a concentration gradient, with a high concentration near the surface and a low concentration inside the isolation trench. Therefore, the oxidation rate is also faster at the surface and slower inside.

[0126] Therefore, the deposited polycrystalline silicon layer 2 is difficult to completely oxidize and will seal prematurely, resulting in holes. Moreover, due to the crystal orientation, the oxidation rate of the sidewalls is fast, which will lead to polycrystalline silicon residue in corners and at the bottom of deep trenches.

[0127] However, since this is for the purpose of isolation, these problems are acceptable.

[0128] The method for forming the oxide layer in the seventh embodiment of the present invention:

[0129] The seventh embodiment of the present invention is a further application of the methods of the first to third embodiments described above, such as... Figure 8 The diagram shown is a schematic diagram of the device structure during the formation process of the oxide layer in the seventh embodiment of the present invention; the first oxide layer 3 is filled in the gate trench of the SGT MOSFET device and serves as a component of the shielding dielectric layer 204.

[0130] Prior to step one, a step of forming a gate trench in the silicon substrate 1 is included.

[0131] Figure 8 In this process, a silicon epitaxial layer 201 is also formed on the surface of the silicon substrate 1, and the gate trench is formed in the silicon epitaxial layer 201.

[0132] In step one, the polysilicon layer 2 is formed on the inner surface of the gate trench; Figure 8 In the diagram, the area where the gate trench is formed is shown by arrow line 202, and the mesa area between the gate trenches is shown by arrow line 203.

[0133] In step two, after the first oxide layer 3 is formed, the middle region of the gate trench is not filled and serves as the formation region of the source polysilicon 205 of the SGT MOSFET device.

[0134] When using the method of the first embodiment of the present invention, the first oxide layer 3 is directly used as the shielding medium layer 204; when using the method of the second embodiment of the present invention, the total oxide layer 5 formed by the superposition of the second oxide layer 4 and the first oxide layer 3 is used as the shielding medium layer 204.

[0135] Depend on Figure 8 As shown, after forming the shielding dielectric layer 204, the following steps are also included:

[0136] The source polycrystalline silicon 205 is formed.

[0137] A gate dielectric layer 207 and a polysilicon gate 206 are formed. Figure 8 The diagram shows a top-bottom structure between the polysilicon gate 206 and the source polysilicon 205. In other embodiments, a left-right structure is also possible.

[0138] A channel region 208, a source region 209, an interlayer film 210, a contact hole 211, and a front metal layer 212 are formed. The front metal layer 212 is patterned to form the source and the gate.

[0139] The silicon epitaxial layer 201 at the bottom of the channel region 208 serves as the drift region.

[0140] Figure 8 In this configuration, the source polysilicon 206 is connected to the source electrode and serves as the source field plate. When the device is reverse biased, the source polysilicon 206 and the drift region 201 undergo lateral depletion, thereby significantly increasing the doping concentration of the drift region 201 without reducing the device breakdown voltage. However, the shielding dielectric layer 204 needs to have a certain thickness to withstand the corresponding drain-source voltage. The higher the breakdown voltage that the SGTMOSFET needs to withstand, the thicker the shielding dielectric layer 204 needs to be.

[0141] For current 100V SGT MOSFET devices, the thickness of the shielding dielectric layer 204 is 0.6μm. The shielding dielectric layer 204 can be formed using the method of the second embodiment of the present invention, including: firstly, forming the second oxide layer 4 using a thermal oxidation process, the thickness of the second oxide layer 4 being 0.2μm; then performing polysilicon deposition and polysilicon thermal oxidation to form the first oxide layer 3, the thickness of the first oxide layer 3 being 0.4μm.

[0142] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A method for forming an oxide layer, characterized by, The method comprises the following steps: Step 1: providing a silicon substrate, depositing polysilicon on the surface of the silicon substrate to form a polysilicon layer, and setting the thickness of the polysilicon layer according to the thickness of a required first oxide layer; The silicon substrate has a first conductive type heavy doping structure, and the silicon epitaxial layer has a first conductive type light doping structure; Step 2: using a thermal oxidation process to oxidize the polysilicon layer to form the first oxide layer, and using the characteristic that the oxidation rate of the polysilicon layer is faster than the oxidation rate of the silicon substrate to reduce the thermal process of forming the first oxide layer to control the diffusion of doping impurities on the silicon substrate; In step 1, after the polysilicon layer is formed, the polysilicon layer is doped, and the oxidation rate of the doped polysilicon layer is increased to further reduce the thermal process of the first oxide layer; The polysilicon layer is divided into a plurality of polysilicon sub-layers, and the first oxide layer is also divided into a plurality of first oxide sub-layers; each layer of the first oxide sub-layer is formed by thermal oxidation of the corresponding layer of the polysilicon sub-layer; Each layer of the polysilicon sub-layer is formed by the polysilicon deposition process of step 1, and the corresponding first oxide sub-layer of each layer of the polysilicon sub-layer is formed by the thermal oxidation process of step 2; the polysilicon deposition process of step 1 and the thermal oxidation process of step 2 are repeated the same number of times as the number of layers of the polysilicon sub-layer to form the first oxide layer; Using the characteristic that the thinner the thickness of the polysilicon layer, the faster the oxidation rate, after the polysilicon layer is divided into each polysilicon sub-layer, the final oxidation rate of the polysilicon layer is determined by the oxidation rate of each polysilicon sub-layer, thereby the final oxidation rate of the polysilicon layer can be improved and the thermal process of forming the first oxide layer can be reduced; In step 1, before the polysilicon layer is formed, a step of thermally oxidizing the silicon substrate to form a second oxide layer is further included; the polysilicon layer is formed on the surface of the second oxide layer, and after step 2 is completed, a total oxide layer is formed by stacking the first oxide layer and the second oxide layer; the second oxide layer improves the interface between the total oxide layer and the silicon substrate. The first oxide layer is formed on the flat surface of the silicon substrate and serves as a component part of the field oxide layer of the terminal region of the power device; 2. The method for forming an oxide layer according to claim 1, wherein: In a top view, the first oxide layer has a patterned structure, and the region surrounded by the patterned first oxide layer is an active region, and the surface of the active region is free of the first oxide layer. The power device includes a VDMOS and an IGBT.

3. The method for forming an oxide layer according to claim 2, wherein: The maximum thickness of the first oxide layer is greater than or equal to 1.6 μm.

4. The method for forming an oxide layer according to claim 2, wherein: The patterning process of the first oxide layer comprises:

5. The method for forming an oxide layer according to Claim 2, wherein: In step 1, the polysilicon layer is formed on all surfaces of the silicon substrate including the terminal region and the active region; In step 2, the first oxide layer is formed on all surfaces of the silicon substrate; A photolithography process is used to define the formation region of the active region, and etching is performed to remove the first oxide layer on the surface of the active region. ​ 6. The method for forming an oxide layer according to claim 2, wherein: The patterning process of the first oxide layer comprises: In step one, the polysilicon layer is formed on all surfaces of the silicon substrate including the termination region and the active region; Before step two, there is a step of: forming a first mask layer on the surface of the polysilicon layer; using photolithography process to define the forming area of the active region, and performing etching process to remove the first mask layer in the forming area of the active region; Then, step two is performed, in which the polysilicon layer in the forming area of the active region is oxidized to form the first oxide layer, and the polysilicon layer outside the forming area of the active region is covered by the first mask layer and is not oxidized; Then, the first mask layer and the polysilicon layer outside the forming area of the active region are removed.

7. The method for forming an oxide layer according to Claim 1, wherein: The first oxide layer is filled in the isolation trench and serves as a component of the trench isolation structure; Before step one, there is a step of forming an isolation trench in the silicon substrate; In step one, the polysilicon layer is formed on the inner surface of the isolation trench; In step two, after the formation of the first oxide layer, the isolation trench is completely filled.

8. The method for forming an oxide layer according to Claim 7, wherein: The depth of the isolation trench is more than 1 μm.

9. The method for forming an oxide layer according to Claim 1, wherein: The first oxide layer is filled in the gate trench of the SGTMOSFET device and serves as a component of the shielding dielectric layer; Before step one, there is a step of forming a gate trench in the silicon substrate; In step one, the polysilicon layer is formed on the inner surface of the gate trench; In step two, after the formation of the first oxide layer, the middle area of the gate trench is not filled and serves as the forming area of the source polysilicon of the SGTMOSFET device.

10. The method for forming an oxide layer according to claim 9, wherein: The maximum thickness of the shielding dielectric layer is more than 0.6 μm.

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