Display substrate, manufacturing method thereof, and display device

Abstract

The present invention provides a display substrate, a manufacturing method thereof, and a display device, relating to the technical field of displays. The problem to be solved is that in large-size display products, due to the excessive length of signal lines, the brightness of different regions of the screen is different, and the brightness uniformity of the screen becomes poor. The display substrate includes a pixel region, a plurality of sub-pixels, a plurality of first power supply lines, and a fan-out region. The included angle between the second direction and the first direction is in the range of 80° to 100°; at least a part of the first power supply line extends along the first direction; the outer side of the pixel region has a first side and a second side arranged along the first direction, and the fan-out region is located on the first side. The display substrate provided by the present invention is used for display.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and in particular, to a display substrate, a manufacturing method thereof, and a display device. Background Art

[0002] Currently, large screens have become the trend of mobile phone development. However, as the screen size increases, the signal lines in the screen become longer. The longer the signal lines are, the greater the IR drop generated on the signal lines during screen display, and the more serious the voltage loading on the signal lines, resulting in different brightness in different areas of the screen and poor brightness uniformity of the screen. Summary of the Invention

[0003] The purpose of the present invention is to provide a display substrate, a manufacturing method thereof, and a display device, which are used to solve the problem that in large-size display products, due to the overly long signal lines, the brightness in different areas of the screen is different and the brightness uniformity of the screen is poor.

[0004] To achieve the above purpose, the present invention provides the following technical solutions:

[0005] A first aspect of the present invention provides a display substrate, including: a pixel area and a peripheral area located around the pixel area. The display substrate further includes:

[0006] Multiple first power lines, at least a part of the first power lines is located in the pixel area, and the part of the first power lines located in the pixel area extends along a first direction;

[0007] A fan-out area provided in the peripheral area. The outer side of the pixel area has a first side and a second side arranged along the first direction, and the fan-out area is located on the first side;

[0008] Multiple sub-pixels provided in the pixel area. The multiple sub-pixels include at least one pair of first-color sub-pixels and multiple other-color sub-pixels. Each pair of first-color sub-pixels includes a first pixel block and a second pixel block that both emit first-color light and are arranged along a second direction. The minimum distance between the first pixel block and the second pixel block in each pair of first-color sub-pixels is less than or equal to the minimum distance between two same-color sub-pixels among the multiple other-color sub-pixels. The included angle between the second direction and the first direction is in the range of 80° to 100°.

[0009] Optionally, the length of the pixel area in the first direction is less than its length in the second direction. The display substrate further includes:

[0010] Multiple gate lines, at least a part of the gate lines is located in the pixel area, and the part of the gate lines located in the pixel area extends along the second direction;

[0011] A plurality of data lines, at least a part of the data lines is located in the pixel region, and the part of the data lines located in the pixel region extends along a first direction.

[0012] Optionally, the length of the first power supply line in the first direction is less than the length of the gate line in the second direction.

[0013] Optionally, the length D1 of the first power supply line in the first direction satisfies: 20% L2 ≤ D1 ≤ 90% L2, where L2 represents the length of the display substrate in the second direction.

[0014] Optionally, the display substrate further includes a gate driving circuit. The outer side of the pixel region has a third side and a fourth side arranged along the second direction, and the gate driving circuit is located on the third side and / or the fourth side.

[0015] Optionally, the display substrate further includes: a first power supply pattern disposed in the peripheral region, and the first power supply pattern includes:

[0016] A first sub-pattern, the first sub-pattern includes a first straight edge portion and a first corner portion in an arc shape coupled to the first straight edge portion; the first straight edge portion extends along the second direction, and the first straight edge portion is respectively coupled to the plurality of first power supply lines; the included angle a between the curvature radius direction of the first corner portion and the second direction satisfies: 0° ≤ a ≤ 90°.

[0017] Optionally, the peripheral region includes a bending region, and the first power supply pattern further includes:

[0018] A second sub-pattern, at least a part of the second sub-pattern extends along the second direction, the second sub-pattern is located on the second side of the bending region, the first sub-pattern is located on the first side of the bending region, and the first side and the second side are arranged along the first direction;

[0019] A plurality of conductive connection portions, the plurality of conductive connection portions are arranged along the second direction, the conductive connection portions extend along the first direction, at least a part of the conductive connection portions is located in the bending region, and the conductive connection portions are respectively coupled to the first sub-pattern and the second sub-pattern.

[0020] Optionally, the display substrate further includes:

[0021] A cathode at least partially located in the pixel region;

[0022] A second power supply pattern disposed in the peripheral region, the second power supply pattern being coupled to the cathode, the second power supply pattern including: a second straight edge portion and a second corner portion coupled to the second straight edge portion, the second straight edge portion extending along the second direction; an included angle a between a curvature radius direction of the second corner portion and the second direction satisfies: 0°≤a≤90°.

[0023] Optionally, a positive projection of the first power supply pattern on the substrate of the display substrate is located between a positive projection of the pixel region on the substrate and a positive projection of a part of the second power supply pattern on the substrate.

[0024] Optionally, the display substrate further includes a first transfer pattern, a positive projection of the first transfer pattern on the substrate of the display substrate and a positive projection of the second power supply pattern on the substrate have a first overlapping region, a positive projection of the first transfer pattern on the substrate of the display substrate and a positive projection of the cathode on the substrate have a second overlapping region, the first transfer pattern is coupled to the second power supply pattern through a via hole disposed in the first overlapping region, and the first transfer pattern is coupled to the cathode through a via hole disposed in the second overlapping region.

[0025] Optionally, the first transfer pattern surrounds the pixel region.

[0026] Optionally, each of the sub-pixels includes a light-emitting element and a pixel driving circuit, the light-emitting element includes a cathode, a light-emitting layer, and an anode stacked in sequence, the anode is located between the light-emitting layer and the substrate of the display substrate, the pixel driving circuit includes a first connection portion, a driving transistor, and a threshold compensation transistor located between the anode and the substrate, the first connection portion extends along a first direction, a first pole of the threshold compensation transistor is electrically connected to a first pole of the driving transistor, and a second pole of the threshold compensation transistor is electrically connected to a gate of the driving transistor through the first connection portion;

[0027] The first pixel block includes a first effective light-emitting region, the second pixel block includes a second effective light-emitting region, in the first pixel block, a minimum distance between a positive projection of the first connection portion on a straight line extending along the second direction and a positive projection of the first effective light-emitting region on the straight line is a first distance, or, the positive projection of the first connection portion on the straight line extending along the second direction and the positive projection of the first effective light-emitting region on the straight line overlap; in the second pixel block, a minimum distance between a positive projection of the first connection portion on the straight line and a positive projection of the second effective light-emitting region on the straight line is a second distance, and the first distance is less than the second distance;

[0028] In the first pixel block, the overlapping area between the positive projection of the anode on the substrate and the positive projection of the first connection part on the substrate is the first overlapping area. In the second pixel block, the overlapping area between the positive projection of the anode on the substrate and the positive projection of the first connection part on the substrate is the second overlapping area. The ratio of the first overlapping area to the second overlapping area is 0.8 to 1.2.

[0029] Optionally, each of the sub-pixels includes a light-emitting element and a pixel driving circuit for driving the light-emitting element. The light-emitting element includes a cathode, a light-emitting layer, and an anode sequentially stacked in a direction close to the substrate of the display substrate. Each of the anodes includes a main electrode and a connection electrode;

[0030] The multiple sub-pixels include multiple third-color sub-pixels and multiple second-color sub-pixels. Each of the third-color sub-pixels includes a third effective light-emitting area. The shape of the main electrode of the third-color sub-pixel is the same as the shape of the third effective light-emitting area, and the positive projection of the third effective light-emitting area on the substrate is located within the positive projection of the main electrode on the substrate. Each of the second-color sub-pixels includes a fourth effective light-emitting area. The shape of the main electrode of the second-color sub-pixel is the same as the shape of the fourth effective light-emitting area, and the positive projection of the fourth effective light-emitting area on the substrate is located within the positive projection of the main electrode on the substrate;

[0031] The multiple data lines are located on a side of the anode facing the substrate. At least one of the main electrodes of the third-color sub-pixels and the second-color sub-pixels overlaps with at least two data lines;

[0032] The display substrate further includes:

[0033] A planarization layer, located between the film layer where the multiple data lines are located and the film layer where the anode is located; and,

[0034] An interlayer insulating layer, located between the film layer where the multiple data lines are located and the substrate of the display substrate,

[0035] Wherein, each of the sub-pixels includes a second connection part disposed on the same layer as the data line,

[0036] In the third-color sub-pixel, the connection electrode is connected to the second connection part through a first via hole penetrating the planarization layer. The second connection part is electrically connected to the pixel driving circuit through a first connection hole penetrating the interlayer insulating layer. Along a direction perpendicular to the substrate, neither the first via hole nor the first connection hole overlaps with the main electrode, and the positive projections of the first via hole and the first connection hole on a first straight line extending along the first direction overlap.

[0037] Optionally, each of the sub-pixels includes a light-emitting element, the light-emitting element includes a cathode, a light-emitting layer, and an anode that are sequentially stacked, the cathode is located on a side of the anode away from the substrate of the display substrate, and the plurality of sub-pixels include a plurality of second-color sub-pixels, and each of the second-color sub-pixels includes a fourth effective light-emitting region;

[0038] A plurality of data lines are located on a side of the anode facing the substrate of the display substrate;

[0039] Each of the sub-pixels further includes a second connection portion disposed on the same layer as the plurality of data lines, and the second connection portion is connected to the anode;

[0040] In a direction perpendicular to the substrate, the anode of each of the second-color sub-pixels overlaps with the data line, the first power line, and the second connection portion, and among the portions where the data line, the first power line, and the second connection portion overlap with the anode, the first power line and the data line are located on both sides of the second connection portion, and the second connection portion includes a first sub-connection portion connected to each other and a second sub-connection portion located on a side of the first sub-connection portion close to the first power line, both the first sub-connection portion and the second sub-connection portion overlap with the anode, in the first direction, the size of the first sub-connection portion is larger than the size of the second sub-connection portion, and the ratio of the minimum distance between the edges of the first sub-connection portion and the data line close to each other to the minimum distance between the edges of the second sub-connection portion and the first power line close to each other is 0.4 to 2.2.

[0041] Based on the technical solution of the above display substrate, a second aspect of the present invention provides a display device including the above display substrate.

[0042] Based on the technical solution of the above display substrate, a third aspect of the present invention provides a method for manufacturing a display substrate, the display substrate includes a pixel region and a peripheral region located around the pixel region, and the length of the pixel region in the first direction is less than its length in the second direction; the manufacturing method includes:

[0043] Manufacturing a plurality of first power lines, at least a part of the first power lines is located in the pixel region, and the part of the first power lines located in the pixel region extends in the first direction;

[0044] Forming a fan-out region disposed in the peripheral region, the outer side of the pixel region has a first side and a second side arranged in the first direction, and the fan-out region is located on the first side;

[0045] Manufacture a plurality of sub-pixels disposed in the pixel region, the plurality of sub-pixels including at least one first color sub-pixel pair and a plurality of other color sub-pixels. Each of the first color sub-pixel pairs includes a first pixel block and a second pixel block that both emit first color light and are arranged along a second direction. The minimum distance between the first pixel block and the second pixel block in each of the first color sub-pixel pairs is less than or equal to the minimum distance between two same-color sub-pixels among the plurality of other color sub-pixels. The included angle between the second direction and the first direction is in the range of 80° to 100°.

[0046] In the technical solution provided by the present invention, by setting the length of the pixel region in the first direction to be less than its length in the second direction, at least part of the first power line extends along the first direction, and along the first direction, the fan-out region is located on one side of the pixel region, so that the first power line can extend along the short side of the display substrate, and the fan-out region is located on the side where the long side of the display substrate is located. Therefore, in the technical solution provided by the present invention, the length of the first power line changes from being close to L2 to being close to L1, and the IR drop on the first power line is proportional to its length. After shortening the length of the first power line, the voltage loading on the first power line decreases, thereby reducing the brightness difference between the near-IC end and the far-IC end of the display substrate and improving the display brightness uniformity and the image quality of the displayed image. Moreover, the technical solution provided by the present invention also effectively improves the color shift phenomenon. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0048] Figure 1 It is a schematic diagram of the output characteristic curve of a transistor and the current-voltage working curve of an OLED;

[0049] Figure 2 It is a schematic structural diagram of a display substrate provided by an embodiment of the present invention;

[0050] Figure 3 It is a schematic diagram of a pixel block, a sub-data line, and a first sub-power line provided by an embodiment of the present invention;

[0051] Figure 4 It is a schematic diagram of a sub-pixel structure provided by an embodiment of the present invention;

[0052] Figure 5 It is a basic structural diagram of a display substrate provided by an embodiment of the present invention;

[0053] Figure 6Schematic diagram of the relationship between brightness uniformity and Vss provided by an embodiment of the present invention;

[0054] Figure 7 Schematic diagram of brightness sampling provided by an embodiment of the present invention;

[0055] Figure 8a For Figure 2 First enlarged schematic diagram of part C1 in

[0056] Figure 8b For Figure 2 Second enlarged schematic diagram of part C1 in

[0057] Figure 9 Schematic diagram of the structure of the first power supply pattern provided by an embodiment of the present invention;

[0058] Figure 10 For Figure 2 Enlarged schematic diagram of part C2 in

[0059] Figure 11a First schematic diagram of the structure of the second power supply pattern provided by an embodiment of the present invention;

[0060] Figure 11b Second schematic diagram of the structure of the second power supply pattern provided by an embodiment of the present invention;

[0061] Figure 12 Scheme of a display product in the related art;

[0062] Figure 13 Scheme of a display product provided by an embodiment of the present invention;

[0063] Figure 14 Schematic diagram of the H-direction color deviation symmetry curve;

[0064] Figure 15 Schematic diagram of the V-direction color deviation symmetry curve;

[0065] Figure 16 Schematic diagram of the structure of the pixel driving circuit provided by an embodiment of the present invention;

[0066] Figure 17 For Figure 2 Enlarged schematic diagram of part C3 in

[0067] Figure 18 For Figure 17 Cross-sectional schematic diagram along the A1A2 direction in

[0068] Figure 19 For Figure 2 Enlarged schematic diagram of part C4 in

[0069] Figure 20 For Figure 19Schematic cross-sectional view along the B1B2 direction;

[0070] Figure 21 is Figure 8a Enlarged schematic view of part C5 in Specific implementation manner

[0071] In order to further illustrate the display substrate, its manufacturing method, and the display device provided by the embodiments of the present invention, the following will be described in detail with reference to the accompanying drawings of the specification.

[0072] As shown in Figure 1, Figure 1 It shows the output characteristic curve of the driving transistor DTFT (such as label 10) and the current-voltage operating curve of the organic light-emitting diode (English: Organic Light-Emitting Diode, abbreviated as OLED) in the sub-pixel driving circuit (such as label 11 and label 12). The OLED emits light by current driving, and the intersection of the current-voltage operating curve and the output characteristic curve is the operating current applied across the OLED. It can be seen from Figure 1 that when the voltage Vds applied across the OLED is relatively large, the intersection C of the two curves is in the saturation region, that is, the operating current of the OLED is relatively stable. However, as Vds decreases, the current-voltage curve of the OLED moves to the left. When Vds drops to a certain extent, the intersection of the two curves will move from the saturation region of the DTFT characteristic curve to the linear region (such as intersection A), resulting in unstable operating current of the OLED and uneven light emission brightness of the screen.

[0073] It should be noted that Figure 1 in , Vth represents the threshold voltage of the driving transistor DTFT, Vgs represents the voltage difference between the gate and source of the driving transistor DTFT, and Ids represents the driving current of the OLED. Figure 1 The left side of the dashed line in is the linear region, and the right side of the dashed line is the saturation region.

[0074] Due to the existence of a certain resistance on the power supply line in the display product, there will be an IR Drop when the power supply line transmits the power signal. When the IR Drop is relatively large, the voltage Vds across the OLED will decrease, making it easy for the current-voltage operating curve of the OLED to move from the saturation region to the linear region. As the sub-pixel is farther away from the driving chip IC end, the IR Drop on the power supply line will continuously increase, and the driving current in the corresponding linear region will continuously decrease, resulting in a continuous decrease in the screen brightness as the distance from the IC end increases, and the brightness uniformity of the screen deteriorates. Moreover, due to the different characteristics of the red sub-pixel, green sub-pixel, and blue sub-pixel, serious IR Drop will cause uneven colors up and down on the screen.

[0075] Please refer to Figures 2 to 4, embodiments of the present invention provide a display substrate, including: a pixel region 20 and a peripheral region located around the pixel region 20, the included angle between the second direction and the first direction being in the range of 80° to 100°; the display substrate further includes:

[0076] Multiple first power supply lines 21, at least a part of the first power supply lines 21 being located in the pixel region 20, and the part of the first power supply lines 21 located in the pixel region 20 extending along the first direction;

[0077] A fan-out region 30 disposed in the peripheral region, the outer side of the pixel region having a first side and a second side arranged along the first direction, and the fan-out region 30 being located on the first side;

[0078] Multiple sub-pixels disposed in the pixel region 20, the multiple sub-pixels including at least one first color sub-pixel pair 22 and multiple other color sub-pixels, each first color sub-pixel pair 22 including a first pixel block 221 and a second pixel block 222 that both emit first color light and are arranged along the second direction, and the minimum distance between the first pixel block 221 and the second pixel block 222 in each first color sub-pixel pair 22 being less than or equal to the minimum distance between two same-color sub-pixels among the multiple other color sub-pixels.

[0079] Exemplarily, the pixel region 20 includes a display region, multiple sub-pixels with display functions are disposed in the pixel region 20, and virtual pixels located around the multiple sub-pixels, and these virtual pixels do not have display functions.

[0080] Exemplarily, the peripheral region surrounds the pixel region 20.

[0081] Exemplarily, the first direction includes a horizontal direction, and the second direction includes a vertical direction.

[0082] Exemplarily, the included angle between the second direction and the first direction is in the range of 80° to 100°, and the endpoint values may be included.

[0083] Exemplarily, the multiple first power supply lines 21 are arranged along the second direction, and at least a part of each first power supply line 21 extends along the first direction. The first power supply lines 21 are used to transmit a positive power supply signal Vdd. The first power supply lines 21 include a part located in the pixel region 20 and a part located in the peripheral region.

[0084] Exemplarily, within the pixel region 20, there is also a power supply compensation pattern that at least partially extends along the second direction, and the power supply compensation pattern is electrically connected to the multiple first power supply lines 21, so as to form a mesh-like power supply structure in the pixel region 20. Exemplarily, the power supply compensation pattern and the first power supply lines 21 are disposed in different layers.

[0085] As shown in Figure 2 and Figure 17 shown, the display substrate further includes a fan-out region 30, which is located in the peripheral region. Along the first direction, the fan-out region 30 is located on one side of the pixel region 20, that is, on the side where the long side of the pixel region 20 is located. The fan-out region 30 is provided with a plurality of fan-out lines, and at least one end of at least some of the fan-out lines is coupled to the data line 41, and at least one end of at least some of the fan-out lines is coupled to a driving chip in the display substrate. Exemplarily, the plurality of fan-out lines are arranged in the same layer and made of the same material; or, a part of the plurality of fan-out lines are arranged in the same layer and made of the same material, and another part of the plurality of fan-out lines are arranged in the same layer and made of the same material, but these two parts of the fan-out lines are arranged in different layers.

[0086] As shown in Figure 2 and Figure 17 shown, more specifically, the plurality of fan-out lines include a plurality of first fan-out lines 301 and a plurality of second fan-out lines 302. The plurality of first fan-out lines 301 correspond to a part of the data lines in the display substrate one by one, and each first fan-out line is respectively coupled to the corresponding data line and the corresponding pin in the driving chip IC. The plurality of second fan-out lines 302 correspond to another part of the data lines in the display substrate one by one, and each second fan-out line 302 is respectively coupled to the corresponding data line and the corresponding pin in the driving chip IC.

[0087] Exemplarily, the plurality of first fan-out lines 301 are arranged in the same layer and made of the same material as the gate line 24 and the reset signal line 26 in the display substrate, and the plurality of second fan-out lines 302 are arranged in the same layer and made of the same material as the initialization signal line 25 in the display substrate.

[0088] The display substrate further includes a driving chip IC, and the fan-out region 30 is located between the driving chip and the pixel region 20.

[0089] It should be noted that Figure 18 is Figure 17 a schematic cross-sectional view along the A1A2 direction in Figure 18 which the substrate 40, the active pattern 90, the anode 2311, the first gate insulating layer GI1, the second gate insulating layer GI2, the interlayer insulating layer ILD, and the planarization layer PLN are schematically shown. The first sub-power line 210 is coupled to the active pattern 90 through a via, which better ensures the etching uniformity of the part directly below the first sub-power line 210 and its surrounding structures.

[0090] Exemplarily, the first pixel block 221 includes a first anode 2211, and the second pixel block 222 includes a second anode 2221.

[0091] Exemplarily, the first pixel block 221 includes a first organic light-emitting pattern 2210, the second pixel block 222 includes a second organic light-emitting pattern 2220, and the first organic light-emitting pattern 2210 and the second organic light-emitting pattern 2220 are made of an organic light-emitting material.

[0092] Exemplarily, both the first pixel block 221 and the second pixel block 222 included in the first color sub-pixel pair 22 are green pixel blocks, such as G1 and G2.

[0093] Exemplarily, both the first pixel block 221 and the second pixel block 222 are pentagonal structures, and the first pixel block 221 and the second pixel block 222 are symmetrically arranged.

[0094] Exemplarily, the minimum distance between the first pixel block and the second pixel block is between 5 micrometers and 20 micrometers, and the endpoint values may be included.

[0095] Exemplarily, the other color sub-pixels include a red sub-pixel R and a blue sub-pixel B.

[0096] Exemplarily, the minimum distance between two same-color sub-pixels among the multiple other color sub-pixels includes: the minimum distance between anodes of two red sub-pixels; the minimum distance between anodes of two blue sub-pixels; Exemplarily, the minimum distance is between 5 micrometers and 20 micrometers, and the endpoint values may be included.

[0097] Exemplarily, the minimum distance between two same-color sub-pixels among the multiple other color sub-pixels includes: the minimum distance between organic light-emitting patterns of two red sub-pixels; the minimum distance between organic light-emitting patterns of two blue sub-pixels; Exemplarily, the minimum distance is between 5 micrometers and 20 micrometers, and the endpoint values may be included.

[0098] According to the specific structure of the above display substrate, in the display substrate provided by the embodiment of the present invention, by setting the length of the pixel region 20 in the first direction to be less than its length in the second direction, at least a part of the first power line 21 extends along the first direction, and along the first direction, the fan-out region 30 is located on one side of the pixel region 20, so that the first power line 21 can extend along the short side of the display substrate, and the fan-out region 30 is located on the side where the long side of the display substrate is located; therefore, as Figure 5As shown in the figure, in the display substrate provided by the embodiment of the present invention, the length of the first power line 21 changes from being close to L2 to being close to L1. The IR drop on the first power line 21 is proportional to its length. After shortening the length of the first power line 21, the voltage loading on the first power line 21 decreases, thereby reducing the brightness difference between the near-IC end and the far-IC end of the display substrate and improving the display brightness uniformity and the image quality of the displayed image.

[0099] More specifically, a mobile phone screen is selected, and by changing the Vdd-Vss voltage difference applied to it, the influence of the IR Drop on the first power line 21 on the screen brightness uniformity is simulated. Vdd is the voltage value of the positive power signal transmitted on the first power line 21, and Vss is the voltage value of the negative power signal transmitted on the second power line (i.e., the negative power signal line).

[0100] The specific method is as follows: As Figure 6 shown in Table 1, the Vdd voltage of the screen is fixed at a certain specific value, and the voltage applied to the screen is changed by adjusting the Vss voltage. Then, the screen brightness uniformity at different operating voltages is tested. To increase the reliability of the results, three gray levels (255 / 220 / 200 gray levels) of the white screen are selected for testing, and the test results are as follows. It can be seen from the test results that when the negative pressure of Vss is small, the brightness uniformity of the screen increases almost linearly. However, when the negative pressure of Vss increases to a certain extent, the uniformity of the screen tends to be stable and no longer changes significantly with the change of Vss. In addition, the difference in brightness uniformity under different gray levels, as well as the sequence of the uniformity increasing continuously and then tending to be stable, further verifies the principle and feasibility of the present invention.

[0101] It should be noted that both Vdd and Vss are externally provided voltages. Exemplarily, the Vdd-Vss voltage difference is 7V. If there is no voltage drop on the first power line 21, then the actual operating voltage of the OLED is 7V. If a part of the voltage drop is consumed on the first power line 21, such as the IR drop is 1V, then the actual operating voltage applied to the OLED is 6V.

[0102] When the provided Vdd-Vss voltage difference is fixed, the smaller the IR drop, the closer the actual operating voltage across the OLED is to the provided Vdd-Vss voltage difference, and vice versa. Therefore, when there is an IR drop, the actual operating voltage across the OLED at the proximal end of the IC is closer to the provided Vdd-Vss voltage difference, and the actual operating voltage across the OLED at the distal end of the IC is less than the provided Vdd-Vss voltage difference.

[0103] During actual simulation, it is assumed by default that there is no voltage drop in the first power supply line 21. By changing Vss, the actual operating voltage across the OLED is adjusted, that is, the voltage difference between Vdd and Vss. Therefore, by adjusting Vss to reduce the voltage difference between Vdd and Vss, that is, to reduce the actual operating voltage across the OLED, the display brightness situation of the IC far end with IR drop can be simulated.

[0104]

[0105] Table 1

[0106] It should be noted that, as Figure 7 shown, a test method for the screen brightness uniformity is illustrated. Nine regions (such as the X region) are selected in the screen, the brightness values of these nine regions are measured, and the minimum brightness value measured in these nine regions is compared with the maximum brightness value to obtain the screen brightness uniformity.

[0107] As Figure 17 shown, in some embodiments, the length of the pixel region 20 in the first direction is less than its length in the second direction, and the display substrate further includes:

[0108] Multiple gate lines 24, at least part of the gate lines 24 is located in the pixel region 20, and the part of the gate lines 24 located in the pixel region 20 extends along the second direction;

[0109] Multiple data lines 41, at least part of the data lines 41 is located in the pixel region 20, and the part of the data lines 41 located in the pixel region 20 extends along the first direction.

[0110] As Figure 19 shown, exemplarily, the multiple gate lines 24 are arranged along the first direction, and at least part of each gate line 24 extends along the second direction. The gate lines 24 include a part located in the pixel region 20 and a part located in the peripheral region, and the part located in the peripheral region is coupled to the corresponding gate driving circuit Gate GOA to receive the gate scanning signal provided by the gate driving circuit Gate GOA.

[0111] Exemplarily, the multiple data lines 41 are arranged along the second direction, and at least part of each data line 41 extends along the first direction. The data lines 41 include a part located in the pixel region 20 and a part located in the fan-out region 30 in the peripheral region.

[0112] As Figure 2 shown, in some embodiments, it is set that the length of the first power supply line 21 in the first direction is less than the length of the gate lines 24 in the second direction.

[0113] The above setting method effectively shortens the length of the first power line 21, reduces the voltage loading on the first power line 21, thereby reducing the brightness difference between the near-IC end and the far-IC end of the display substrate, and improving the display brightness uniformity and the image quality of the displayed image.

[0114] As Figure 2 shown, in some embodiments, the length D1 of the first power line 21 in the first direction satisfies: 20% L2 ≤ D1 ≤ 90% L2, where L2 represents the length of the display substrate in the second direction.

[0115] The above setting method effectively shortens the length of the first power line 21, reduces the voltage loading on the first power line 21, thereby reducing the brightness difference between the near-IC end and the far-IC end of the display substrate, and improving the display brightness uniformity and the image quality of the displayed image.

[0116] As Figure 2 and Figure 19 shown, in some embodiments, the display substrate further includes a gate driving circuit GOA. The outside of the pixel region 20 has a third side and a fourth side arranged in the second direction, and the gate driving circuit GOA is located on the third side and / or the fourth side.

[0117] Exemplarily, the gate driving circuit GOA includes a plurality of Gate GOAs, and the Gate GOA is used to provide corresponding scanning signals for the gate lines 24 and the reset signal lines 26.

[0118] It should be noted that, as Figure 19 shown, the Gate GOA can be coupled to the corresponding gate lines 24 and reset signal lines 26 through a second transfer pattern 28. Exemplarily, the second transfer pattern 28 is provided on the same layer and made of the same material as the sub-data lines 41 in the display substrate, and can be formed in the same lithography process. Exemplarily, the orthographic projection of the second transfer pattern 28 on the substrate at least partially overlaps with the orthographic projection of the output end of the Gate GOA on the substrate, and at the overlapping portion, the second transfer pattern 28 is coupled to the output end of the Gate GOA through a via; the orthographic projection of the second transfer pattern 28 on the substrate at least partially overlaps with the orthographic projection of the gate line 24 on the substrate, and at the overlapping portion, the second transfer pattern 28 is coupled to the gate line 24 through a via; the orthographic projection of the second transfer pattern 28 on the substrate at least partially overlaps with the orthographic projection of the reset signal line 26 on the substrate, and at the overlapping portion, the second transfer pattern 28 is coupled to the reset signal line 26 through a via.

[0119] Exemplarily, the gate driving circuit GOA further includes a plurality of EM GOAs, and the EM GOA is configured to provide corresponding scan signals for the light emission control signal lines 27 in the display substrate.

[0120] Exemplarily, the gate driving circuit GOA is located on two opposite sides of the pixel region 20 along the second direction.

[0121] The above-mentioned arrangement of the gate driving circuit GOA on at least one side of the pixel region 20 along the second direction enables the gate driving circuit GOA to be located on the side where the short side of the display substrate is located, thereby avoiding the gate driving circuit GOA occupying the space on the long side of the display substrate and being more conducive to reducing the layout difficulty on the long side of the display substrate.

[0122] Such as Figure 2 、 Figures 8a to 10 、 Figure 21 As shown, in some embodiments, the display substrate further includes: a first power supply pattern disposed in the peripheral region, and the first power supply pattern includes:

[0123] A first sub-pattern 501, the first sub-pattern 501 includes a first straight edge portion 5011 and an arc-shaped first corner portion 5012 coupled to the first straight edge portion 5011; the first straight edge portion 5011 extends along the second direction, and the first straight edge portion 5011 is respectively coupled to the plurality of first power supply lines 21; the included angle a between the curvature radius direction of the first corner portion 5012 and the second direction satisfies: 0° ≤ a ≤ 90°.

[0124] Specifically, the display substrate further includes the first power supply pattern, and the first power supply pattern is on the same side as the driving chip in the display substrate, and the first power supply pattern is configured to connect the plurality of first power supply lines 21 to the driving chip.

[0125] Exemplarily, the first power supply pattern and the plurality of first power supply lines 21 form an integral structure and are provided on the same layer and with the same material as the data lines.

[0126] Exemplarily, the first straight edge portion 5011 is located on the side where the long side of the display substrate is located, and at least a part of the first corner portion 5012 is located in the corner region of the display substrate.

[0127] Exemplarily, at least a part of the first straight edge portion 5011 extends into the pixel region 20.

[0128] Exemplarily, the first straight edge portion 5011 and the first corner portion 5012 form an integral structure.

[0129] Exemplarily, the radius of curvature direction of the first corner portion 5012 is the radius of curvature direction of the inner boundary of the first corner portion 5012 close to the pixel region 20; or, the radius of curvature direction of the first corner portion 5012 is the radius of curvature direction of the outer boundary of the first corner portion 5012 away from the pixel region 20.

[0130] Exemplarily, the first corner portion 5012 has a first width in the radius of curvature direction, and the first width remains unchanged in the direction from the long side of the display substrate to the short side of the display substrate.

[0131] Exemplarily, the first corner portion 5012 has a first width in the radius of curvature direction, and the first width gradually increases in the direction from the long side of the display substrate to the short side of the display substrate.

[0132] As Figure 8a and Figure 8b shown, exemplarily, the first corner portion 5012 has a first width in the radius of curvature direction, and the first width gradually decreases in the direction from the long side of the display substrate to the short side of the display substrate.

[0133] In the display substrate provided by the above embodiment, by providing the first corner portion 5012 in the corner area of the display substrate, the space in the corner area of the display substrate is effectively utilized, and the resistance of the first power pattern is reduced, so that it is more beneficial to reduce the voltage loading generated on the first power line 21.

[0134] As Figure 2 、 Figures 8a to 10 shown, in some embodiments, the peripheral area includes a bending area 31, and the first power pattern further includes:

[0135] A second sub-graph 502, at least a part of the second sub-graph 502 extends along the second direction, the second sub-graph 502 is located on the second side of the bending area 31, the first sub-graph 501 is located on the first side of the bending area 31, and the first side and the second side are arranged along the first direction;

[0136] A plurality of conductive connection portions 504, the plurality of conductive connection portions 504 are arranged along the second direction, the conductive connection portions 504 extend along the first direction, at least a part of the conductive connection portions 504 is located in the bending area 31, and the conductive connection portions 504 are respectively coupled to the first sub-graph 501 and the second sub-graph 502.

[0137] Exemplarily, the bending area 31 extends along the second direction.

[0138] Exemplarily, the first power supply pattern is an integral structure.

[0139] Exemplarily, the first power supply pattern further includes two first lead-in portions 503 symmetrically arranged. The first end of each first lead-in portion 503 is coupled to the driving chip of the display substrate, and both ends of the second sub-pattern 502 are respectively coupled to the second ends of the two first lead-in portions 503.

[0140] Exemplarily, the plurality of conductive connection portions 504 are arranged at equal intervals along the second direction.

[0141] Exemplarily, the plurality of conductive connection portions 504 include an odd number of conductive connection portions 504. Among the odd number of conductive connection portions 504, one intermediate conductive connection portion 504 overlaps with the center line extending along the first direction in the pixel region 20, and the remaining plurality of non-intermediate conductive connection portions 504 among the odd number of conductive connection portions 504 are symmetrically arranged with respect to the intermediate conductive connection portion.

[0142] Exemplarily, along the second direction, the width of the intermediate conductive connection portion 504 is greater than the width of the non-intermediate conductive connection portion 504.

[0143] Exemplarily, along the second direction, the widths of the non-intermediate conductive connection portions 504 are all equal.

[0144] Connecting the first sub-pattern 501 and the second sub-pattern 502 through the plurality of conductive connection portions 504 can better ensure the connection performance of the first sub-pattern 501 and the second sub-pattern 502 in the bending region 31.

[0145] Setting the first power supply pattern to include the first sub-pattern 501, the second sub-pattern 502, and the plurality of conductive connection portions 504 as described above can better reduce the resistance of the first power supply pattern, which is beneficial to the uniformity of the display substrate.

[0146] As Figure 2 、 Figure 8a 、 Figure 11a 、 Figure 11b 、 Figure 19 and Figure 21 shown, in some embodiments, the display substrate further includes:

[0147] A cathode 620 at least partially located in the pixel region 20;

[0148] A second power supply pattern 60 disposed in the peripheral region, the second power supply pattern 60 being coupled to the cathode 620, the second power supply pattern 60 including: a second straight edge portion 601 and a second corner portion 602 coupled to the second straight edge portion 601, the second straight edge portion 601 extending along the second direction; an included angle a between the curvature radius direction of the second corner portion 602 and the second direction satisfies: 0° ≤ a ≤ 90°.

[0149] Exemplarily, the second power supply pattern 60 is used to transmit a negative power signal to the cathode 620.

[0150] Exemplarily, the second power supply pattern 60 includes: two symmetrically arranged second incoming line portions 603, two symmetrically arranged second straight edge portions 601, two symmetrically arranged second corner portions 602, and a surrounding portion 604; a first end of each of the incoming line portions is coupled to a driving chip IC in the display substrate, the two second straight edge portions 601 correspond to the two second incoming line portions 603 one by one, a first end of the second straight edge portion 601 is coupled to a second end of the corresponding second incoming line portion 603, the two second corner portions 602 correspond to the two second straight edge portions 601 one by one, a first end of the second corner portion 602 is coupled to a second end of the corresponding second straight edge portion 601, the surrounding portion 604 surrounds two short sides and one long side of the pixel region 20, two ends of the surrounding portion 604 are coupled to second ends of the two second corner portions 602, and a positive projection of the second power supply pattern 60 on the substrate of the display substrate surrounds the pixel region 20.

[0151] Exemplarily, the second power supply pattern 60 is an integral structure.

[0152] Exemplarily, the curvature radius direction of the second corner portion 602 is the curvature radius direction of the inner boundary of the second corner portion 602 close to the pixel region 20; or, the curvature radius direction of the second corner portion 602 is the curvature radius direction of the outer boundary of the second corner portion 602 far from the pixel region 20.

[0153] Exemplarily, the second corner portion 602 has a second width in the curvature radius direction, and in the direction from the long side of the display substrate to the short side of the display substrate, the second width remains unchanged.

[0154] As Figure 8a and Figure 11a shown, exemplarily, the second corner portion 602 has a second width in the curvature radius direction, and in the direction from the long side of the display substrate to the short side of the display substrate, the second width gradually increases.

[0155] As Figure 8b andFigure 11b As shown, for example, the second corner portion 602 has a second width in the radius of curvature direction, and the second width gradually decreases in the direction from the long side of the display substrate to the short side of the display substrate.

[0156] In the display substrate provided in the above embodiment, by providing the second corner portion 602 in the corner area of the display substrate, the space in the corner area of the display substrate is effectively utilized, and the resistance of the second power supply pattern 60 is reduced, thereby being more beneficial to the display uniformity of the display substrate.

[0157] Such as Figure 2 、 Figure 9 、 Figure 19 And Figure 20 As shown, in some embodiments, the orthographic projection of the first power supply pattern on the substrate of the display substrate is located between the orthographic projection of the pixel region 20 on the substrate and the orthographic projection of a part of the second power supply pattern 60 on the substrate.

[0158] Such as Figure 2 、 Figure 9 、 Figure 19 And Figure 20 As shown, in some embodiments, the display substrate further includes a first transfer pattern 610. The orthographic projection of the first transfer pattern 610 on the substrate 40 of the display substrate and the orthographic projection of the second power supply pattern 60 (such as the surrounding portion 604) on the substrate 40 have a first overlapping region. The orthographic projection of the first transfer pattern 610 on the substrate 40 of the display substrate and the orthographic projection of the cathode 620 on the substrate 40 have a second overlapping region. The first transfer pattern 610 is coupled to the second power supply pattern 60 (such as the surrounding portion 604) through a via provided in the first overlapping region, and the first transfer pattern 610 is coupled to the cathode 620 through a via provided in the second overlapping region.

[0159] Exemplarily, the first transfer pattern 610 is provided on the same layer and made of the same material as the anode.

[0160] It should be noted that Figure 20 also shows a planarization layer PLN and a pixel definition layer PDL.

[0161] In some embodiments, the first transfer pattern 610 is provided to surround the pixel region 20. This setting method enables the cathode 620 to achieve a large-area electrical connection with the second power supply pattern 60 around the pixel region 20, which is beneficial to better reducing the voltage drop of the cathode.

[0162] Such as Figure 2 And Figure 3As shown, in some embodiments, the multiple data lines include sub-data lines 41 corresponding to each sub-pixel, and the multiple first power supply lines 21 include first sub-power supply lines 210 corresponding to each sub-pixel;

[0163] The sub-pixel includes a sub-pixel driving circuit, and multiple sub-pixel driving circuits included in the multiple sub-pixels are arranged in an array; the multiple sub-pixel driving circuits are divided into multiple rows of sub-pixel driving circuits, and each row of sub-pixel driving circuits includes multiple sub-pixel driving circuits arranged along the second direction; the multiple sub-pixel driving circuits are divided into multiple columns of sub-pixel driving circuits, and each column of sub-pixel driving circuits includes multiple sub-pixel driving circuits arranged along the first direction;

[0164] The sub-data lines 41 corresponding to the sub-pixel driving circuits in the same column are sequentially coupled to form a data line;

[0165] The first sub-power supply lines 210 corresponding to the sub-pixel driving circuits in the same column are sequentially coupled to form a first power supply line 21.

[0166] Exemplarily, the sub-pixel driving circuit includes a 7T1C structure.

[0167] Exemplarily, the sub-data lines 41 corresponding to the sub-pixel driving circuits in the same column are sequentially coupled to form an integral structure.

[0168] Exemplarily, the first sub-power supply lines 210 corresponding to the sub-pixel driving circuits in the same column are sequentially coupled to form an integral structure.

[0169] It should be noted that since the display effect difference of the display substrate at the left and right viewing angles will affect the consumer experience, the display substrate also needs to meet corresponding specifications in terms of color shift symmetry. The smaller the color shift difference (△JNCD) at the same viewing angle on both the left and right sides, the better the display effect of the display substrate, and the more easily it can be recognized and accepted by customers and consumers. In current OLED display products, there is generally a problem of poor color shift symmetry, which is strongly related to the flatness of the anode layer in RGB sub-pixels. Therefore, how to optimize the flatness of the anode layer and improve the left and right color shift symmetry of the display product is an urgent problem to be solved in the display industry.

[0170] In the related art, in the pixel arrangement structure based on GGRB, due to the mesh stretching method of the Fine Metal Mask (FMM), the relative position relationship between the anode of the RGB sub-pixel and the underlying signal line is that the long side extension direction of the sub-pixel opening area is parallel to the underlying signal line. Therefore, when designing the display substrate, the relative position relationship between the anode and the underlying signal line is particularly important. If the relative position relationship between the underlying signal line and the anode of the sub-pixel is an asymmetric design, it will cause the anode side of the sub-pixel to bulge, affecting light emission, resulting in inconsistent RGB monochromatic ratios in the left and right viewing angles, and easily causing asymmetric left and right color deviation phenomena. Limited by the size of the display substrate, it is difficult to ensure that the underlying signal line completely avoids the anode of the sub-pixel, resulting in the continuous existence of the problem of asymmetric left and right color deviation. Therefore, it is particularly important to eliminate the influence of asymmetric left and right color deviation through design changes.

[0171] As Figure 3 and Figure 4 shown, in some embodiments, the positive projection of the first pixel block 221 on the substrate of the display substrate and the positive projection of the sub-data line 41' corresponding to the sub-pixel to which it belongs on the substrate have a first overlapping area; and / or, the positive projection of the first pixel block 221 on the substrate and the positive projection of the first sub-power line 210' corresponding to the sub-pixel to which it belongs on the substrate have a second overlapping area; along the second direction, the first overlapping area and the second overlapping area are oppositely arranged.

[0172] Exemplarily, the sub-data line and the first sub-power line are arranged on the same layer and made of the same material.

[0173] Exemplarily, both the sub-data line and the first sub-power line are made of the first source-drain metal layer or the second source-drain metal layer in the display substrate.

[0174] The above setting method is more conducive to the flatness of the first pixel block 221, thereby effectively improving the color deviation phenomenon of the first color sub-pixel pair 22.

[0175] In some embodiments, the width of the first overlapping area along the first direction is less than or equal to the maximum width of the first pixel block 221 along the first direction; and / or, the width of the second overlapping area along the first direction is less than or equal to the maximum width of the first pixel block 221 along the first direction.

[0176] The above setting method enables the first pixel block 221 to have better flatness in both the first direction and the second direction, thereby better improving the color deviation phenomenon of the first color sub-pixel pair 22.

[0177] In some embodiments, a positive projection of the second pixel block 222 on the substrate of the display substrate and a positive projection of a sub-data line 41 corresponding to an adjacent sub-pixel along a second direction on the substrate have a third overlapping region; a positive projection of the second pixel block 222 on the substrate and a positive projection of a first sub-power line 210 corresponding to an adjacent sub-pixel along the second direction on the substrate have a fourth overlapping region;

[0178] Along the second direction, the third overlapping region and the fourth overlapping region are oppositely arranged.

[0179] The above arrangement is more conducive to the flatness of the second pixel block 222, thereby effectively improving the color shift phenomenon of the second color sub-pixel pair.

[0180] In some embodiments, it is set that a width of the third overlapping region along the first direction is less than or equal to a maximum width of the second pixel block 222 along the first direction; and / or, a width of the fourth overlapping region along the first direction is less than or equal to the maximum width of the second pixel block 222 along the first direction.

[0181] The above arrangement enables the second pixel block 222 to have good flatness both in the first direction and in the second direction, thereby better improving the color shift phenomenon of the second color sub-pixel pair.

[0182] As Figure 3 and Figure 4 shown, in some embodiments, at least some other color sub-pixels include a second color sub-pixel 231 and a third color sub-pixel 233. At least a part of an anode 2311 included in the second color sub-pixel 231 extends along the second direction, and at least a part of an anode 2331 included in the third color sub-pixel 233 extends along the second direction.

[0183] In the display substrate provided by the above embodiments, the relative positional relationship between the anode in each sub-pixel and the sub-data line and the first sub-power line below it is changed. For example, when an included angle between the first direction and the second direction is equal to 90 degrees, as Figure 3 shown, an extending direction of the anode is perpendicular to extending directions of the sub-data line 41(41') and the first sub-power line 210(210'), so that positive projections of the sub-data line 41 and the first sub-power line 210 on the substrate can pass through a positive projection of the anode on the substrate along the first direction, and the width of the anode in the first direction is relatively narrow. Therefore, the color shift asymmetry under the left and right side viewing angles of the display panel can be significantly improved.

[0184] Moreover, the length of the anode in the second direction in the sub-pixel is longer than its length in the first direction. Since the slope of the anode in its long side direction (i.e., the second direction) is relatively less affected by the sub-data line and the first sub-power line on the one hand, and on the other hand, the color shift symmetry in the long side direction view is also less affected by the slope of the pixel block, the color shift asymmetry in the long side direction of the sub-pixel, that is, in the views of the upper and lower sides of the display panel, can also be effectively controlled.

[0185] As Figure 3 and Figure 4 shown, in some embodiments, in other color sub-pixels, the orthographic projection of the anode on the substrate of the display substrate and the orthographic projection of the sub-data line 41 corresponding to the sub-pixel to which it belongs on the substrate have a fifth overlapping region.

[0186] In some embodiments, in other color sub-pixels, the orthographic projection of the anode on the substrate of the display substrate and the orthographic projection of the sub-data line 41' corresponding to the adjacent sub-pixel along the second direction on the substrate have a sixth overlapping region.

[0187] In some embodiments, along the second direction, the fifth overlapping region and the sixth overlapping region are oppositely arranged.

[0188] The above arrangement is more conducive to the flatness of the anode in other color sub-pixels, thereby effectively improving the color shift phenomenon of other color sub-pixels.

[0189] In some embodiments, the width of the fifth overlapping region along the first direction is less than or equal to the maximum width of the anode along the first direction; and / or, the width of the sixth overlapping region along the first direction is less than or equal to the maximum width of the anode along the first direction.

[0190] The above arrangement makes the anode have good flatness in both the first direction and the second direction in other color sub-pixels, thereby better improving the color shift phenomenon of other color sub-pixels.

[0191] In some embodiments, in other color sub-pixels, the orthographic projection of the anode on the substrate of the display substrate and the orthographic projection of the first sub-power line 210 corresponding to the sub-pixel to which it belongs on the substrate have a seventh overlapping region.

[0192] In some embodiments, in other color sub-pixels, the orthographic projection of the anode on the substrate of the display substrate and the orthographic projection of the first sub-power line 210' corresponding to the adjacent sub-pixel along the second direction on the substrate have an eighth overlapping region.

[0193] In some embodiments, along the second direction, the seventh overlapping region and the eighth overlapping region are oppositely arranged.

[0194] The above setting method is more conducive to the flatness of the anode in other color sub-pixels, thereby effectively improving the color deviation phenomenon of other color sub-pixels.

[0195] In some embodiments, the width of the seventh overlapping region along the first direction is less than or equal to the maximum width of the anode along the first direction; and / or, the width of the eighth overlapping region along the first direction is less than or equal to the maximum width of the anode along the first direction.

[0196] The above setting method enables the anode to have better flatness in both the first direction and the second direction in other color sub-pixels, thereby better improving the color deviation phenomenon of other color sub-pixels.

[0197] More specifically, as Figure 12 shown, it is a solution of a display product in the related art, and as Figure 13 shown is the implementation solution proposed in the embodiment of the present invention. Here, it is stipulated that the long side of the display substrate is the V direction, and the short side is the H direction. The differences in chromaticity of V+, V-, H+ and H- at the same viewing angle are represented by JNCD (color difference) values. The smaller the JNCD value, the better the left-right color deviation symmetry of the display panel. Taking the short side direction as an example, assuming that the chromaticity of the H+ direction at a certain viewing angle is (u1, v1), and the chromaticity of the H- direction at the same viewing angle is (u2, v2), then the left-right color deviation difference of the H direction at this viewing angle is △JNCD = [(u1 - u2)^2 + (v1 - v2)^2]^0.5 / 0.004.

[0198] Next, based on display substrates of the same size, the effects of the above two solutions on color deviation symmetry are verified, and the comparison results are as Figure 14 shown. The color coordinates of the display products of the above two solutions in the short side direction (i.e., the H direction) at different viewing angles are respectively measured, and the JNCD differences between the left and right sides at three viewing angles of 30°, 45° and 60° are selected for comparison. Figure 14 The dotted line in it is the measured data of the display product in the related art, and the solid line is the measured data of the display substrate provided by the embodiment of the present invention. It can be seen that the △JNCD of the display substrate provided by the embodiment of the present invention is less than 0.5JNCD at each viewing angle, and the △JNCD at each viewing angle is significantly lower than that of the display product in the related art.

[0199] In addition, the color coordinates of the display substrate provided by the embodiment of the present invention in the long side direction (i.e., the V direction) at different viewing angles are measured, and the JNCD differences between the upper and lower sides at three viewing angles of 30°, 45° and 60° are calculated. The results are as Figure 15As shown, the measured ΔJNCD of multiple display substrates at each viewing angle in the long side direction is also within 0.5 JNCD, and the color shift symmetry is excellent. Therefore, the display substrate provided by the embodiment of the present invention can effectively improve the left - right color shift symmetry. The color shift symmetry on both sides of the long side and the short side of the display substrate has been significantly improved, thereby enhancing the performance of the display product and better meeting the requirements of customers and the usage experience of consumers.

[0200] As Figure 3 and Figure 16 As shown, in some embodiments, each of the sub - pixels includes a light - emitting element and a pixel driving circuit. The light - emitting element includes a cathode, a light - emitting layer, and an anode stacked in sequence. The anode is located between the light - emitting layer and the substrate of the display substrate. The pixel driving circuit includes a first connection portion 70, a driving transistor, and a threshold compensation transistor located between the anode and the substrate. The first connection portion 70 extends along a first direction. The first pole of the threshold compensation transistor is electrically connected to the first pole of the driving transistor, and the second pole of the threshold compensation transistor is electrically connected to the gate of the driving transistor T3 through the first connection portion 70;

[0201] The first pixel block includes a first effective light - emitting area (such as the area where the first organic light - emitting pattern 2210 is located), and the second pixel block includes a second effective light - emitting area (such as the area where the second organic light - emitting pattern 2220 is located). In the first pixel block, the minimum distance between the positive projection of the first connection portion 70 on a straight line extending along the second direction and the positive projection of the first effective light - emitting area on the straight line is a first distance, or the positive projection of the first connection portion 70 on the straight line extending along the second direction overlaps with the positive projection of the first effective light - emitting area on the straight line; in the second pixel block, the minimum distance between the positive projection of the first connection portion 70 on the straight line and the positive projection of the second effective light - emitting area on the straight line is a second distance, and the first distance is less than the second distance;

[0202] In the first pixel block, the overlapping area between the positive projection of the anode on the substrate and the positive projection of the first connection portion 70 on the substrate is a first overlapping area. In the second pixel block, the overlapping area between the positive projection of the anode on the substrate and the positive projection of the first connection portion 70 on the substrate is a second overlapping area. The ratio of the first overlapping area to the second overlapping area is 0.8 - 1.2.

[0203] Exemplarily, the first connection portion 70 is made of the same layer and the same material as the data line.

[0204] Exemplarily, the light - emitting layer is made of an organic light - emitting material.

[0205] Exemplarily, the first effective light-emitting region and the second effective light-emitting region are regions for forming the light-emitting layer.

[0206] Each pixel driving circuit includes a data writing transistor T4, a driving transistor T3, a threshold compensation transistor T2, and a first reset control transistor T7. A first pole of the threshold compensation transistor T2 is connected to a first pole of the driving transistor T3, and a second pole of the threshold compensation transistor T2 is connected to a gate of the driving transistor T3; a first pole of the first reset control transistor T7 is connected to a reset power signal line to receive a reset signal Vinit, and a second pole of the first reset control transistor T7 is connected to the light-emitting unit; a first pole of the data writing transistor T4 is connected to a second pole of the driving transistor T3. For example, the pixel driving circuit of each sub-pixel further includes a storage capacitor C, a first light-emitting control transistor T6, a second light-emitting control transistor T5, and a second reset transistor T1. A gate of the data writing transistor T4 is electrically connected to a scan signal line to receive a scan signal Gate; a first pole of the storage capacitor C is electrically connected to a power signal line, and a second pole of the storage capacitor C is electrically connected to a gate of the driving transistor T3; a gate of the threshold compensation transistor T2 is electrically connected to the scan signal line to receive a compensation control signal; a gate of the first reset transistor T7 is electrically connected to a reset control signal line to receive a reset control signal Reset(N + 1); a first pole of the second reset transistor T1 is electrically connected to the reset power signal line to receive the reset signal Vinit, a second pole of the second reset transistor T1 is electrically connected to a gate of the driving transistor T3, and a gate of the second reset transistor T1 is electrically connected to the reset control signal line to receive a reset control signal Reset(N); a gate of the first light-emitting control transistor T6 is electrically connected to a light-emitting control signal line to receive a light-emitting control signal EM; a first pole of the second light-emitting control transistor T5 is electrically connected to the power signal line to receive a first power signal VDD, a second pole of the second light-emitting control transistor T5 is electrically connected to a second pole of the driving transistor T3, a gate of the second light-emitting control transistor T5 is electrically connected to the light-emitting control signal line to receive the light-emitting control signal EM, and a cathode of the light-emitting element 11 is connected to a voltage terminal VSS. The above-mentioned power signal line refers to a signal line for outputting a voltage signal VDD, and can be connected to a voltage source to output a constant voltage signal, such as a positive voltage signal.

[0207] Setting the display substrate to the above structure is beneficial to reducing the layout space occupied by each sub-pixel and improving the resolution of the display substrate.

[0208] As Figure 3 shown, in some embodiments, each of the sub-pixels includes a light-emitting element and a pixel driving circuit for driving the light-emitting element. The light-emitting element includes a cathode, a light-emitting layer, and an anode that are sequentially stacked in a direction close to the substrate of the display substrate. Each of the anodes includes a main electrode and a connection electrode;

[0209] The multiple sub-pixels include multiple third-color sub-pixels 233 and multiple second-color sub-pixels 231. Each of the third-color sub-pixels 233 includes a third effective light-emitting region (such as the region where the third organic light-emitting pattern 2330 is located). The shape of the main electrode of the third-color sub-pixel 233 is the same as the shape of the third effective light-emitting region, and the orthographic projection of the third effective light-emitting region on the substrate is located within the orthographic projection of the main electrode on the substrate. Each of the second-color sub-pixels 231 includes a fourth effective light-emitting region (such as the region where the fourth organic light-emitting pattern 2310 is located). The shape of the main electrode of the second-color sub-pixel 231 is the same as the shape of the fourth effective light-emitting region, and the orthographic projection of the fourth effective light-emitting region on the substrate is located within the orthographic projection of the main electrode on the substrate;

[0210] The multiple data lines (such as the marked 41 and 41') are located on the side of the anode facing the substrate, and the main electrode of at least one of the third-color sub-pixels 233 and the second-color sub-pixels 231 overlaps with at least two data lines;

[0211] The display substrate further includes:

[0212] A planarization layer located between the film layer where the multiple data lines are located and the film layer where the anode is located; and,

[0213] An interlayer insulating layer located between the film layer where the multiple data lines are located and the substrate of the display substrate,

[0214] wherein each of the sub-pixels includes a second connection portion 232 disposed on the same layer as the data line,

[0215] In the third-color sub-pixel 233, the connection electrode is connected to the second connection portion 232 through a first via hole penetrating the planarization layer, and the second connection portion 232 is electrically connected to the pixel driving circuit through a first connection hole penetrating the interlayer insulating layer. Along the direction perpendicular to the substrate, neither the first via hole nor the first connection hole overlaps with the main electrode, and the orthographic projections of the first via hole and the first connection hole on a first straight line extending along the first direction overlap.

[0216] Exemplarily, the main electrode of the third-color sub-pixel 233 and the third effective light-emitting region are both hexagonal.

[0217] Exemplarily, the main electrode of the second-color sub-pixel 231 and the fourth effective light-emitting region are both hexagonal.

[0218] Exemplarily, the second color sub-pixel includes one or more of a red sub-pixel, a blue sub-pixel, and a green sub-pixel. The third color sub-pixel includes one or more of a red sub-pixel, a blue sub-pixel, and a green sub-pixel.

[0219] Exemplarily, the main electrode of at least one of the third color sub-pixel 233 and the second color sub-pixel 231 overlaps two data lines (such as the marked 41 and 41'), and the two data lines are arranged along the second direction.

[0220] Exemplarily, the third color sub-pixel 233 includes an anode 2331, and the second color sub-pixel 231 includes an anode 2311.

[0221] Setting the display substrate to the above structure not only helps to reduce the layout space occupied by each sub-pixel and improve the resolution of the display substrate, but also makes the main electrodes of each sub-pixel have good flatness, which is beneficial to improving the color deviation phenomenon generated by the display substrate.

[0222] As Figure 3 shown, in some embodiments, each of the sub-pixels includes a light-emitting element, the light-emitting element includes a cathode, a light-emitting layer, and an anode that are sequentially stacked, the cathode is located on a side of the anode away from the substrate of the display substrate, the plurality of sub-pixels include a plurality of second color sub-pixels 231, and each of the second color sub-pixels 231 includes a fourth effective light-emitting region (such as the region where the fourth organic light-emitting pattern 2310 is located);

[0223] A plurality of data lines are located on a side of the anode facing the substrate of the display substrate;

[0224] Each of the sub-pixels further includes a second connection portion 232 disposed on the same layer as the plurality of data lines, and the second connection portion 232 is connected to the anode;

[0225] In a direction perpendicular to the substrate, the anodes 2311 of the second color sub-pixels 231 overlap with the data lines (such as the marked 41 and 41'), the first power supply line 21, and the second connection portion 232. In the overlapping portions of the data line, the first power supply line, and the second connection portion 232 with the anode, the first power supply line 21 and the data line are located on both sides of the second connection portion 232. The second connection portion 232 includes a first sub-connection portion 2320 connected to each other and a second sub-connection portion 2321 located on the side of the first sub-connection portion 2320 close to the first power supply line. Both the first sub-connection portion 2320 and the second sub-connection portion 2321 overlap with the anode. Along the first direction, the size of the first sub-connection portion 2320 is larger than that of the second sub-connection portion 2321, and the ratio of the minimum distance between the edges of the first sub-connection portion 2320 close to the data line to the minimum distance between the edges of the second sub-connection portion 2321 close to the first power supply signal line is 0.4 to 2.2.

[0226] Exemplarily, the second color sub-pixel includes one or more of a red sub-pixel, a blue sub-pixel, and a green sub-pixel.

[0227] Setting the display substrate to the above structure not only helps to reduce the layout space occupied by each sub-pixel and improve the resolution of the display substrate, but also makes the main electrodes of each sub-pixel have good flatness, which is beneficial to improving the color shift phenomenon generated by the display substrate.

[0228] The embodiment of the present invention further provides a display device, including the display substrate provided in the above embodiment.

[0229] In the display substrate provided in the above embodiment, by setting the length of the pixel region 20 in the first direction to be less than its length in the second direction, at least part of the data line extends in the first direction, at least part of the first power supply line 21 extends in the first direction, and along the first direction, the fan-out region 30 is located on one side of the pixel region 20, so that both the data line and the first power supply line 21 extend along the short side of the display substrate, and the fan-out region 30 is located on the side where the long side of the display substrate is located; therefore, as Figure 5 shown, in the display substrate provided in the above embodiment, the length of the first power supply line 21 changes from being close to L2 to being close to L1, and the IR drop on the first power supply line 21 is proportional to its length. After shortening the length of the first power supply line 21, the voltage loading on the first power supply line 21 decreases, thereby reducing the brightness difference between the near-IC end and the far-IC end of the display substrate and improving the display brightness uniformity and the image quality of the displayed image.

[0230] Moreover, the display substrate provided by the above embodiments effectively improves the color shift phenomenon.

[0231] The display device provided by the embodiments of the present invention also has the above beneficial effects when including the above display substrate, which will not be elaborated here.

[0232] It should be noted that the display device may be: any product or component with a display function such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc.

[0233] The embodiments of the present invention also provide a method for manufacturing a display substrate. The display substrate includes a pixel region 20 and a peripheral region located around the pixel region 20. The included angle between the second direction and the first direction is in the range of 80° to 100°; the manufacturing method includes:

[0234] Manufacture a plurality of first power supply lines 21. At least a part of the first power supply lines 21 is located in the pixel region 20, and the part of the first power supply lines 21 located in the pixel region extends along the first direction;

[0235] Form a fan-out region 30 disposed in the peripheral region. The outer side of the pixel region has a first side and a second side arranged along the first direction, and the fan-out region is located on the first side;

[0236] Manufacture a plurality of sub-pixels disposed in the pixel region 20. The plurality of sub-pixels include at least one pair of first color sub-pixels 22 and a plurality of other color sub-pixels. Each pair of first color sub-pixels 22 includes a first pixel block 221 and a second pixel block 222 that both emit first color light and are arranged along the second direction. The minimum distance between the first pixel block 221 and the second pixel block 222 in each pair of first color sub-pixels 22 is less than or equal to the minimum distance between two same-color sub-pixels among the plurality of other color sub-pixels.

[0237] Exemplarily, the length of the pixel region 20 in the first direction is less than its length in the second direction.

[0238] In the display substrate manufactured by using the manufacturing method provided by the embodiments of the present invention, by setting the length of the pixel region 20 in the first direction to be less than its length in the second direction, at least a part of the data lines extends along the first direction, at least a part of the first power supply lines 21 extends along the first direction, and along the first direction, the fan-out region 30 is located on one side of the pixel region 20, so that both the data lines and the first power supply lines 21 extend along the short side of the display substrate, and the fan-out region 30 is located on the side where the long side of the display substrate is located; therefore, as Figure 5As shown, in the display substrate manufactured by using the manufacturing method provided in the embodiment of the present invention, the length of the first power line 21 changes from being close to L2 to being close to L1. Since the IR drop on the first power line 21 is proportional to its length, after shortening the length of the first power line 21, the voltage loading falling on the first power line 21 decreases, thereby reducing the brightness difference between the near-IC end and the far-IC end of the display substrate and improving the display brightness uniformity and the image quality of the displayed image.

[0239] Moreover, the display substrate manufactured by using the manufacturing method provided in the embodiment of the present invention effectively improves the color shift phenomenon.

[0240] It should be noted that the various embodiments in this specification are described in a progressive manner. The same or similar parts among the various embodiments can be referred to each other, and the key points of each embodiment are the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the product embodiments, they are described relatively simply, and the relevant parts can be referred to the partial description of the product embodiments.

[0241] Unless otherwise defined, the technical terms or scientific terms used in this disclosure should have the ordinary meanings understood by those of ordinary skill in the field to which the present invention belongs. The "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. The terms such as "including" or "comprising" mean that the elements or objects appearing before this term cover the elements or objects listed after this term and their equivalents, without excluding other elements or objects. The terms such as "connected", "coupled" or "linked" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left" and "right" are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0242] It can be understood that when an element such as a layer, a film, a region or a substrate is referred to as being "on" or "under" another element, the element can be "directly" on or under the other element, or there may be intermediate elements.

[0243] In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in a suitable manner in any one or more embodiments or examples.

[0244] As described above, it is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of changes or substitutions, which should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims described above.

Claims

1. A display substrate, characterized in that, Comprising: A pixel region and a peripheral region located around the pixel region, and the display substrate further includes: A plurality of first power supply lines, at least a part of the first power supply lines is located in the pixel region, and the part of the first power supply lines located in the pixel region extends along a first direction; A fan-out region disposed in the peripheral region, the outside of the pixel region has a first side and a second side arranged along the first direction, and the fan-out region is located on the first side; A plurality of sub-pixels disposed in the pixel region, the plurality of sub-pixels include at least one pair of first color sub-pixels and a plurality of other color sub-pixels, each pair of the first color sub-pixels includes a first pixel block and a second pixel block that both emit first color light and are arranged along a second direction, and the minimum distance between the first pixel block and the second pixel block in each pair of the first color sub-pixels is less than or equal to the minimum distance between two same-color sub-pixels among the plurality of other color sub-pixels, and the included angle between the second direction and the first direction is in the range of 80° to 100°; The length of the pixel region in the first direction is less than its length in the second direction, and the display substrate further includes: A plurality of gate lines, at least a part of the gate lines is located in the pixel region, and the part of the gate lines located in the pixel region extends along the second direction; A plurality of data lines, at least a part of the data lines is located in the pixel region, and the part of the data lines located in the pixel region extends along the first direction; Each of the sub-pixels includes a light-emitting element and a pixel driving circuit, the light-emitting element includes a cathode, a light-emitting layer, and an anode that are sequentially stacked, the anode is located between the light-emitting layer and the substrate of the display substrate, the pixel driving circuit includes a first connection portion, a driving transistor, and a threshold compensation transistor located between the anode and the substrate, the first connection portion extends along the first direction, a first pole of the threshold compensation transistor is electrically connected to a first pole of the driving transistor, and a second pole of the threshold compensation transistor is electrically connected to a gate of the driving transistor through the first connection portion; The first pixel block includes a first effective light-emitting region, the second pixel block includes a second effective light-emitting region, in the first pixel block, the minimum distance between the positive projection of the first connection portion on a straight line extending along the second direction and the positive projection of the first effective light-emitting region on the straight line is a first distance, or the positive projection of the first connection portion on the straight line extending along the second direction and the positive projection of the first effective light-emitting region on the straight line overlap; in the second pixel block, the minimum distance between the positive projection of the first connection portion on the straight line and the positive projection of the second effective light-emitting region on the straight line is a second distance, and the first distance is less than the second distance; In the first pixel block, the overlapping area between the positive projection of the anode on the substrate and the positive projection of the first connection portion on the substrate is a first overlapping area. In the second pixel block, the overlapping area between the positive projection of the anode on the substrate and the positive projection of the first connection portion on the substrate is a second overlapping area. The ratio of the first overlapping area to the second overlapping area is 0.8 to 1.

2.

2. The display substrate according to claim 1, wherein The length of the first power line in the first direction is less than the length of the gate line in the second direction.

3. The display substrate according to claim 1, wherein The length D1 of the first power line in the first direction satisfies: 20% L2 ≤ D1 ≤ 90% L2, where L2 represents the length of the display substrate in the second direction.

4. The display substrate according to claim 1, wherein The display substrate further includes a gate driving circuit. The outer side of the pixel region has a third side and a fourth side arranged along the second direction, and the gate driving circuit is located on the third side and / or the fourth side.

5. The display substrate according to claim 1, wherein The display substrate further includes: a first power pattern disposed in the peripheral region, and the first power pattern includes: A first sub-pattern, the first sub-pattern includes a first straight edge portion and a first corner portion in an arc shape coupled to the first straight edge portion; the first straight edge portion extends along the second direction, and the first straight edge portion is respectively coupled to the plurality of first power lines; the included angle a between the curvature radius direction of the first corner portion and the second direction satisfies: 0° ≤ a ≤ 90°.

6. The display substrate according to claim 5, wherein The peripheral region includes a bending region, and the first power pattern further includes: A second sub-pattern, at least a part of the second sub-pattern extends along the second direction, the second sub-pattern is located on the second side of the bending region, the first sub-pattern is located on the first side of the bending region, and the first side and the second side are arranged along the first direction; A plurality of conductive connection portions, the plurality of conductive connection portions are arranged along the second direction, the conductive connection portions extend along the first direction, at least a part of the conductive connection portions is located in the bending region, and the conductive connection portions are respectively coupled to the first sub-pattern and the second sub-pattern.

7. The display substrate according to claim 5, wherein The display substrate further includes: A cathode at least partially located in the pixel region; A second power pattern disposed in the peripheral region, the second power pattern is coupled to the cathode, and the second power pattern includes: a second straight edge portion and a second corner portion coupled to the second straight edge portion, the second straight edge portion extends along the second direction; the included angle a between the curvature radius direction of the second corner portion and the second direction satisfies: 0° ≤ a ≤ 90°.

8. The display substrate according to claim 7, characterized in that The positive projection of the first power pattern on the substrate of the display substrate is located between the positive projection of the pixel region on the substrate and the positive projection of a part of the second power pattern on the substrate.

9. The display substrate according to claim 7, wherein The display substrate further includes a first transfer pattern. A positive projection of the first transfer pattern on the substrate of the display substrate and a positive projection of the second power supply pattern on the substrate have a first overlapping region. A positive projection of the first transfer pattern on the substrate of the display substrate and a positive projection of the cathode on the substrate have a second overlapping region. The first transfer pattern is coupled to the second power supply pattern through a via disposed in the first overlapping region, and the first transfer pattern is coupled to the cathode through a via disposed in the second overlapping region.

10. The display substrate according to claim 9, wherein The first transfer pattern surrounds the pixel region.

11. The display substrate according to claim 1, wherein each of the sub-pixels includes a light-emitting element and a pixel driving circuit for driving the light-emitting element. The light-emitting element includes a cathode, a light-emitting layer, and an anode sequentially stacked in a direction close to the substrate of the display substrate. Each of the anodes includes a main electrode and a connection electrode; the plurality of sub-pixels include a plurality of third-color sub-pixels and a plurality of second-color sub-pixels. Each of the third-color sub-pixels includes a third effective light-emitting region. The shape of the main electrode of the third-color sub-pixel is the same as the shape of the third effective light-emitting region, and a positive projection of the third effective light-emitting region on the substrate is located within a positive projection of the main electrode on the substrate. Each of the second-color sub-pixels includes a fourth effective light-emitting region. The shape of the main electrode of the second-color sub-pixel is the same as the shape of the fourth effective light-emitting region, and a positive projection of the fourth effective light-emitting region on the substrate is located within a positive projection of the main electrode on the substrate; the plurality of data lines are located on a side of the anode facing the substrate, and the main electrode of at least one of the third-color sub-pixels and the second-color sub-pixels overlaps at least two data lines; the display substrate further includes: a planarization layer located between the film layer where the plurality of data lines are located and the film layer where the anode is located; and an interlayer insulating layer located between the film layer where the plurality of data lines are located and the substrate of the display substrate, wherein each of the sub-pixels includes a second connection portion disposed on the same layer as the data line, in the third-color sub-pixel, the connection electrode is connected to the second connection portion through a first via penetrating the planarization layer, and the second connection portion is electrically connected to the pixel driving circuit through a first connection hole penetrating the interlayer insulating layer. In a direction perpendicular to the substrate, neither the first via nor the first connection hole overlaps with the main electrode, and a positive projection of the first via and the first connection hole on a first straight line extending in the first direction has an overlap.

12. The display substrate according to claim 1, wherein each of the sub-pixels includes a light-emitting element. The light-emitting element includes a cathode, a light-emitting layer, and an anode sequentially stacked. The cathode is located on a side of the anode away from the substrate of the display substrate. The plurality of sub-pixels include a plurality of second-color sub-pixels. Each of the second-color sub-pixels includes a fourth effective light-emitting region; A plurality of data lines are located on one side of the anode facing the substrate of the display substrate; Each of the sub-pixels further includes a second connection portion disposed on the same layer as the plurality of data lines, and the second connection portion is connected to the anode; In a direction perpendicular to the substrate, the anode of each of the second color sub-pixels overlaps with the data line, the first power line, and the second connection portion. Among the overlapping portions of the data line, the first power line, and the second connection portion with the anode, the first power line and the data line are located on both sides of the second connection portion. The second connection portion includes a first sub-connection portion connected to each other and a second sub-connection portion located on the side of the first sub-connection portion close to the first power line. Both the first sub-connection portion and the second sub-connection portion overlap with the anode. In the first direction, the size of the first sub-connection portion is larger than the size of the second sub-connection portion, and the ratio of the minimum distance between the edges of the first sub-connection portion and the data line close to each other to the minimum distance between the edges of the second sub-connection portion and the first power line close to each other is 0.4 to 2.

2.

13. A display device, characterized in that, Comprising the display substrate according to any one of claims 1 to 12.

14. A method for manufacturing a display substrate, characterized in that, The display substrate includes a pixel region and a peripheral region located around the pixel region. The length of the pixel region in the first direction is less than its length in the second direction; The manufacturing method includes: Manufacturing a plurality of first power lines, at least a part of the first power lines is located in the pixel region, and the part of the first power lines located in the pixel region extends in the first direction; Forming a fan-out region disposed in the peripheral region. The outer side of the pixel region has a first side and a second side arranged in the first direction, and the fan-out region is located on the first side; Manufacturing a plurality of sub-pixels disposed in the pixel region. The plurality of sub-pixels include at least one pair of first color sub-pixels and a plurality of other color sub-pixels. Each pair of first color sub-pixels includes a first pixel block and a second pixel block that both emit first color light and are arranged in the second direction. The minimum distance between the first pixel block and the second pixel block in each pair of first color sub-pixels is less than or equal to the minimum distance between two same-color sub-pixels among the plurality of other color sub-pixels. The included angle between the second direction and the first direction is in the range of 80° to 100°; The length of the pixel region in the first direction is less than its length in the second direction. The display substrate further includes: A plurality of gate lines, at least a part of the gate lines is located in the pixel region, and the part of the gate lines located in the pixel region extends in the second direction; A plurality of data lines, at least a part of the data lines is located in the pixel region, and the part of the data lines located in the pixel region extends in the first direction; Each of the sub-pixels includes a light-emitting element and a pixel driving circuit. The light-emitting element includes a cathode, a light-emitting layer, and an anode which are stacked in sequence. The anode is located between the light-emitting layer and the substrate of the display substrate. The pixel driving circuit includes a first connection portion, a driving transistor, and a threshold compensation transistor located between the anode and the substrate. The first connection portion extends in a first direction. A first pole of the threshold compensation transistor is electrically connected to a first pole of the driving transistor. A second pole of the threshold compensation transistor is electrically connected to a gate of the driving transistor through the first connection portion; The first pixel block includes a first effective light-emitting region, and the second pixel block includes a second effective light-emitting region. In the first pixel block, a minimum distance between a positive projection of the first connection portion on a straight line extending in the second direction and a positive projection of the first effective light-emitting region on the straight line is a first distance, or the positive projection of the first connection portion on the straight line extending in the second direction and the positive projection of the first effective light-emitting region on the straight line overlap; in the second pixel block, a minimum distance between a positive projection of the first connection portion on the straight line and a positive projection of the second effective light-emitting region on the straight line is a second distance, and the first distance is less than the second distance; In the first pixel block, an overlapping area between a positive projection of the anode on the substrate and a positive projection of the first connection portion on the substrate is a first overlapping area. In the second pixel block, an overlapping area between a positive projection of the anode on the substrate and a positive projection of the first connection portion on the substrate is a second overlapping area. A ratio of the first overlapping area to the second overlapping area is 0.8 to 1.2.

Images