Display device

Abstract

This application relates to a display device. The display device includes: a display area and a non-display area, the non-display area being adjacent to the display area; a first scan line extending in the row direction and transmitting a first scan signal; a first pixel portion electrically connected to the first scan line; a second pixel portion electrically connected to the first scan line and spaced apart from the first pixel portion in the row direction; and a first inspection pad disposed between the first pixel portion and the second pixel portion and electrically connected to the first scan line.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0166124, filed on December 1, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to display devices. This disclosure relates to display devices having a reduced non-display area. Background Technology

[0004] A tiled display device has a structure in which multiple display devices are combined with each other. The display devices display images of different parts, and the viewer can view an image in which multiple parts of the image are combined.

[0005] However, the seams in a tiled display device can be defined by the non-display area (e.g., bezel) of each element in the display device. To improve viewer attention and / or to provide the best viewing experience, eliminating these seams becomes necessary. For example, it is necessary to develop display devices with reduced non-display areas.

[0006] It will be understood that this background section is intended to provide some useful context for understanding the art. However, this background section may also include concepts, ideas, or knowledge that were known or understood by a person skilled in the art prior to the corresponding valid application date, and are not related to the subject matter disclosed herein. Summary of the Invention

[0007] The purpose of this disclosure is to provide a display device having a reduced non-display area.

[0008] The purpose of this disclosure is not limited to the above-mentioned purposes, and modifications may be made within the spirit and scope of this disclosure.

[0009] An embodiment provides a display device, which may include: a display area and a non-display area, the non-display area being adjacent to the display area; a first scan line extending in a row direction and transmitting a first scan signal; a first pixel portion electrically connected to the first scan line; a second pixel portion electrically connected to the first scan line and spaced apart from the first pixel portion in the row direction; and a first inspection pad disposed between the first pixel portion and the second pixel portion and electrically connected to the first scan line.

[0010] The first pixel portion can be set in the first outermost region of the display area adjacent to the non-display area.

[0011] The display device may also include a second inspection pad electrically connected to the first scan line and spaced apart from the first inspection pad in the row direction.

[0012] The display device may further include: a third pixel portion electrically connected to the first scan line and spaced apart from the second pixel portion in the row direction; and a fourth pixel portion electrically connected to the first scan line and spaced apart from the third pixel portion in the row direction, wherein a second inspection pad may be disposed between the third pixel portion and the fourth pixel portion.

[0013] The fourth pixel portion can be set in the second outermost region of the display area adjacent to the non-display area, and facing the first pixel portion.

[0014] The display device may further include: a second scan line extending in the row direction and transmitting a second scan signal; and a third inspection pad spaced apart from the first inspection pad in the row direction and electrically connected to the second scan line.

[0015] The second pixel portion can be set between the first inspection pad and the third inspection pad.

[0016] The first pixel portion may include: a first conductive pattern disposed on a substrate; an active pattern disposed on the first conductive pattern; a second conductive pattern disposed on the active pattern; and a third conductive pattern disposed on the second conductive pattern and electrically connected to the first conductive pattern and the active pattern, wherein the first inspection pad and the third conductive pattern may be disposed on the same layer.

[0017] The display device may further include: a data line extending in a column direction intersecting the row direction and transmitting data voltage, the data line and the first conductive pattern being disposed on the same layer; and a data bridge electrically connecting the data line and the first pixel portion, the data bridge and the third conductive pattern being disposed on the same layer.

[0018] The display device may further include: a sensing voltage line extending in a column direction intersecting the row direction and transmitting a sensing voltage, the sensing voltage line and a first conductive pattern being disposed on the same layer; and a sensing voltage bridge electrically connecting the sensing voltage line and a first pixel portion, the sensing voltage bridge and a third conductive pattern being disposed on the same layer.

[0019] The display device may further include: a high power supply voltage line extending in a column direction intersecting the row direction and transmitting a high power supply voltage, the high power supply voltage line corresponding to a first conductive pattern; and a high power supply voltage bridge electrically connecting the high power supply voltage line and a first pixel portion, the high power supply voltage bridge corresponding to a third conductive pattern.

[0020] The display device may further include: a low power supply voltage line extending in a column direction intersecting the row direction and transmitting a low power supply voltage, the low power supply voltage line being disposed on the same layer as a first conductive pattern; and a low power supply voltage bridge electrically connecting the low power supply voltage line and a first pixel portion, the low power supply voltage bridge being disposed on the same layer as a third conductive pattern.

[0021] The first pixel portion may include: a first connecting electrode disposed on a third conductive pattern; a second connecting electrode disposed on the third conductive pattern and spaced apart from the first connecting electrode; a nano-light-emitting element disposed on the first connecting electrode; a first driving electrode disposed on the nano-light-emitting element and electrically contacting the first connecting electrode; and a second driving electrode electrically contacting the second connecting electrode, wherein the second driving electrode and the first driving electrode are disposed on the same layer.

[0022] The first pixel portion may include a color conversion pattern set on the nano-light-emitting element.

[0023] The first pixel portion may include a color filter set on the color conversion pattern.

[0024] An embodiment provides a display device, which may include: a display area and a non-display area, the non-display area being adjacent to the display area; a first voltage line extending in a column direction and transmitting a first voltage; a first pixel portion electrically connected to the first voltage line; a second pixel portion electrically connected to the first voltage line and spaced apart from the first pixel portion in the column direction; and an inspection pad electrically connected to the first voltage line.

[0025] The first pixel portion may include: a first conductive pattern disposed on a substrate; an active pattern disposed on the first conductive pattern; a second conductive pattern disposed on the active pattern; and a third conductive pattern disposed on the second conductive pattern and electrically connected to the first conductive pattern and the active pattern, and the pads and the first conductive pattern are checked to be disposed on the same layer.

[0026] An embodiment provides a display device, which may include: a display area and a non-display area, the non-display area being adjacent to the display area; a first voltage line extending in a column direction and transmitting a first voltage; a second voltage line extending in a column direction and transmitting a second voltage; a first pixel portion electrically connected to the first voltage line and the second voltage line; a second pixel portion electrically connected to the first voltage line and the second voltage line and spaced apart from the first pixel portion in the column direction; and an inspection pad electrically connected to the second voltage line, wherein the second voltage line may be disposed between the first voltage line and the first pixel portion.

[0027] The first pixel portion may include: a first conductive pattern disposed on a substrate; an active pattern disposed on the first conductive pattern; a second conductive pattern disposed on the active pattern; and a third conductive pattern disposed on the second conductive pattern and electrically connected to the first conductive pattern and the active pattern, and the pads and the third conductive pattern are checked to be disposed on the same layer.

[0028] The second voltage line and the first conductive pattern can be set on the same layer.

[0029] The display device according to the embodiment may include inspection pads disposed in the display area and scan drivers disposed in the display area. For example, the inspection pads and scan drivers may be disposed between pixel columns. Therefore, the non-display area surrounding or adjacent to the display area can be reduced. The inspection pads may be electrically connected to lines transmitting signals and / or voltages. Therefore, the location of defects in the lines can be detected by inspecting the inspection pads.

[0030] However, the effects of this disclosure are not limited to those described above, and various modifications can be made within the spirit and scope of this disclosure. Attached Figure Description

[0031] The above and other aspects and features of this disclosure will become more apparent from the detailed description of embodiments thereof with reference to the accompanying drawings, in which:

[0032] Figure 1 A top view of a tiled display device in which display devices are combined with each other according to an embodiment is shown.

[0033] Figure 2 A top view shows the housing components of the display device according to an embodiment.

[0034] Figure 3 It shows Figure 2 A block diagram of the display device.

[0035] Figure 4 It shows that it includes Figure 2 The equivalent circuit diagram of the sub-pixel portion in the display device.

[0036] Figure 5 It shows Figure 2 A magnified view of region "A".

[0037] Figure 6 It shows Figure 2 A magnified view of region "B".

[0038] Figure 7 It shows Figure 2 A schematic cross-sectional view of the display device.

[0039] Figure 8 A top view of a display device according to an embodiment is shown.

[0040] Figure 9 A top view of a display device according to an embodiment is shown.

[0041] Figure 10 It shows Figure 9 A magnified view of region "C".

[0042] Figure 11 It shows Figure 9 A schematic cross-sectional view of the display device.

[0043] Figure 12 A top view of a display device according to an embodiment is shown.

[0044] Figure 13 It shows Figure 12 A magnified view of region "D".

[0045] Figure 14 It shows Figure 12 A schematic cross-sectional view of the display device. Detailed Implementation

[0046] In the following, embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals are used in the drawings for one or more identical constituent elements, and repeated descriptions of one or more identical constituent elements will be omitted.

[0047] In the accompanying drawings, for ease of description and clarity, the dimensions, thickness, scale, and size of the components may be exaggerated. The same reference numerals denote the same components throughout.

[0048] As used in this article, the singular forms “a,” “one,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0049] In the specification and claims, for purposes of meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used to connect parts of speech or to connect parts of speech in an antonymous manner, and can be understood to be equivalent to "and / or".

[0050] In the specification and claims, for purposes of meaning and interpretation, the phrase “at least one of…” is intended to include the meaning of “at least one selected from the group of…”. For example, “at least one of A and B” can be understood to mean “A, B, or A and B”.

[0051] It will be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0052] For ease of description, the spatial relative terms “below,” “under,” “down,” “above,” “up,” etc., may be used herein to describe the relationship between one element or component and another element or component as shown in the figures. It will be understood that, in addition to the orientation depicted in the figures, the spatial relative terms are intended to include different orientations of the device in use or operation. For example, in the case where the device shown in the figures is flipped, a device positioned “below” or “under” another device may be placed “above” another device. Therefore, the descriptive term “below” can include both a lower position and an upper position. The device may also be oriented in other directions, and therefore the spatial relative terms may be interpreted differently depending on the orientation.

[0053] The term “overlapping” or “overlapping” means that the first object may be above or below the second object, or on one side of the second object, and that the second object may be above or below the first object, or on one side of the first object. Additionally, the term “overlapping” may include stacking, overlapping, facing or oriented towards, extending over, covering or partially covering, or may be any other suitable term as will be understood and appreciated by one of ordinary skill in the art.

[0054] When an element is described as “not overlapping” with another element or “...is not overlapping” with another element, it may include elements spaced apart from each other, offset from each other, or positioned next to each other, or may include any other suitable terms as will be understood and appreciated by one of ordinary skill in the art.

[0055] The terms "facing" and "oriented" mean that the first element can be directly or indirectly opposite the second element. In the case where a third element is inserted between the first and second elements, the first and second elements can be understood as being indirectly opposite each other, but still facing each other.

[0056] It will be understood that when an element (or region, layer, part, etc.) is referred to in the specification as being "on" another element, "connected" to another element, or "attached to" another element, it may be directly disposed on, directly connected to, or directly attached to the other element, or an intermediate element may be disposed between them.

[0057] It will be understood that the terms “connected to” or “linked to” can include physical or electrical connections, or physical or electrical connections.

[0058] The terms “comprising,” “containing,” “including,” and / or “including,” “has,” “have,” and / or “having,” and variations thereof, when used in this specification, indicate the presence of the stated features, integrals, steps, operations, elements, components, and / or groups thereof, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0059] The phrase "in a plan view" means viewing an object from above, and the phrase "in a schematic sectional view" means viewing a section of an object that has been vertically cut from the side.

[0060] As used herein, “about” or “approximately” includes the value as well as the average of the specific value within an acceptable range of variation, determined by a person skilled in the art considering the measurement in question and the errors associated with the measurement of the specific quantity (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the value.

[0061] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms, such as those defined in commonly used dictionaries, shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art and shall not be interpreted as having an idealized or overly formal meaning unless expressly so defined herein.

[0062] Figure 1 A top view of a tiled display device in which display devices are combined with each other according to an embodiment is shown.

[0063] Reference Figure 1 The display devices according to the embodiments can be combined with each other to form a tiled display device (TDD). For example, a first display device DD1, a second display device DD2, a third display device DD3, and a fourth display device DD4 can be combined with each other. The first display device DD1 can display a first image, the second display device DD2 can display a second image, the third display device DD3 can display a third image, and the fourth display device DD4 can display a fourth image. A viewer can view an image in which the first to fourth images are combined.

[0064] In this embodiment, the first display device DD1, the second display device DD2, the third display device DD3, and the fourth display device DD4 may have substantially the same structure. For example, the second display device DD2 may be substantially symmetrical to the first display device DD1 in the first direction D1. The third display device DD3 may be substantially symmetrical to the first display device DD1 in the second direction D2. For example, the second direction D2 may be substantially perpendicular to the first direction D1. The first direction D1 may be a row direction, and the second direction D2 may be a column direction.

[0065] Figure 2 The housing components of the display device according to the embodiment are shown in top view, and Figure 3 It shows Figure 2 A block diagram of the display device.

[0066] Reference Figure 2 and Figure 3 According to the embodiment, the first display device DD1 can be divided into a display area DA and a non-display area NDA. For example, multiple pixel portions PX, a scan driver SDV, a first inspection pad PD1, a second inspection pad PD2, and a third inspection pad PD3 can be disposed in the display area DA. The non-display area NDA can be disposed around or adjacent to the display area DA. The non-display area NDA can be a region in which pixel portions PX may not be disposed. For example, multiple data integrated circuits DIC can be disposed in the non-display area NDA.

[0067] The pixel portion PX can be located in the display area DA of the first display device DD1. The pixel portion PX can receive a first scan signal SS1, a second scan signal SS2, and a third scan signal SS3 from the scan driver SDV, and can receive a data voltage DATA from the data driver DDV. The pixel portion PX can receive a high power supply voltage VDD, a low power supply voltage VSS, and a sensing voltage INIT.

[0068] The scan driver SDV can be located in the display area DA of the first display device DD1. The scan driver SDV can receive the scan control signal SCTRL from the timing controller CON (T-CON). The scan driver SDV can generate a first scan signal SS1, a second scan signal SS2, and a third scan signal SS3. The first scan signal SS1 and the second scan signal SS2 can be transmitted through the first scan line SL1, and the third scan signal SS3 can be transmitted through the second scan line SL2.

[0069] In the implementation method, such as Figure 2As shown, the scan driver SDV can be partitioned and inserted into the display area DA. For example, the scan driver SDV may include a first part scan driver SDV-P1, a second part scan driver SDV-P2, and a third part scan driver SDV-P3. The first part scan driver SDV-P1, the second part scan driver SDV-P2, and the third part scan driver SDV-P3 can be installed between pixel columns, respectively. When the scan driver SDV is partitioned and set in the display area DA, the non-display area NDA can be reduced.

[0070] The data driver DDV can be located in the non-display area NDA of the first display device DD1. The data driver DDV can receive data control signals DCTRL and output image data ODAT from the timing controller CON (T-CON). The data driver DDV can generate data voltage DATA. The data voltage DATA can be transmitted to the first data line DL1, the second data line DL2, and the third data line DL3 (see...). Figure 5 ).

[0071] In this implementation, the data driver DDV can be implemented using a data integrated circuit DIC. For example, the data integrated circuit DIC can be located on one side of the first display device DD1. Therefore, the size of the non-display area NDA, where the data integrated circuit DIC may not be located, can be reduced.

[0072] The timing controller CON (T-CON) can receive control signals CTRL and input image data IDAT from external devices. The timing controller CON (T-CON) can generate data control signals DCTRL, output image data ODAT, and scan control signals SCTRL. The timing controller CON (T-CON) can control the data driver DDV and the scan driver SDV.

[0073] In the implementation method, such as Figure 2As shown, a pixel portion PX may include a first pixel portion PX1, a second pixel portion PX2, a third pixel portion PX3, and a fourth pixel portion PX4. For example, the first pixel portion PX1, the second pixel portion PX2, the third pixel portion PX3, and the fourth pixel portion PX4 may be arranged in a pixel row or a single pixel row. The first pixel portion PX1 may be located in the first outermost region of the display area DA adjacent to the non-display area NDA. The second pixel portion PX2 may be spaced apart from the first pixel portion PX1 in the first direction D1. The fourth pixel portion PX4 may be located in the second outermost region of the display area DA adjacent to the non-display area NDA, and may face the first pixel portion PX1. The third pixel portion PX3 may be spaced apart from the fourth pixel portion PX4 in the first direction D1. However, the arrangement and position of the pixel portions are not limited thereto, and other arrangements and positions are possible within the spirit and scope of this disclosure.

[0074] The first pixel portion PX1, the second pixel portion PX2, the third pixel portion PX3, and the fourth pixel portion PX4 can be electrically connected to the first scan line SL1. In other words, the first pixel portion PX1, the second pixel portion PX2, the third pixel portion PX3, and the fourth pixel portion PX4 can receive the first scan signal SS1 and the second scan signal SS2 from the first scan line SL1. The first pixel portion PX1, the second pixel portion PX2, the third pixel portion PX3, and the fourth pixel portion PX4 can also be electrically connected to the second scan line SL2. In other words, the first pixel portion PX1, the second pixel portion PX2, the third pixel portion PX3, and the fourth pixel portion PX4 can receive the third scan signal SS3 from the second scan line SL2.

[0075] In the implementation method, such as Figure 2 As shown, the first display device DD1 may include a first inspection pad PD1, a second inspection pad PD2, and a third inspection pad PD3 disposed in the display area DA. The first inspection pad PD1, the second inspection pad PD2, and the third inspection pad PD3 may be inspection pads used to perform open-circuit / short-circuit (OS) checks. For example, an OS check may be an inspection to detect circuit defects (e.g., open circuits or short circuits in a circuit). The first inspection pad PD1, the second inspection pad PD2, and the third inspection pad PD3 may be pads contacted by probe pins.

[0076] The first inspection pad PD1 and the second inspection pad PD2 can be electrically connected to the first scan line SL1. In other words, the first inspection pad PD1 and the second inspection pad PD2 can be inspection pads used to detect the location of defects on the first scan line SL1. The first inspection pad PD1 can be disposed between the first pixel portion PX1 and the second pixel portion PX2, and the second inspection pad PD2 can be spaced apart from the first inspection pad PD1 in the first direction D1. For example, the second inspection pad PD2 can be disposed between the third pixel portion PX3 and the fourth pixel portion PX4. In other words, the second inspection pad PD2 can face the first inspection pad PD1. However, this disclosure is not limited thereto.

[0077] In one implementation, the first inspection pad PD1 can be a supply pad, while the second inspection pad PD2 can be a receiving pad. However, depending on the method used to perform the OS check, the second inspection pad PD2 can be omitted.

[0078] In one embodiment, the third inspection pad PD3 may be electrically connected to the second scan line SL2. In other words, the third inspection pad PD3 may be a pad used to detect the location of defects on the second scan line SL2. The third inspection pad PD3 may be spaced apart from the first inspection pad PD1 in the first direction D1. In another embodiment, if the first display device DD1 does not include the second scan line SL2, the third inspection pad PD3 may be omitted.

[0079] However, the positions of the first inspection pad PD1, the second inspection pad PD2, and the third inspection pad PD3 are not limited to the above-described embodiments. The first inspection pad PD1, the second inspection pad PD2, and the third inspection pad PD3 can be located within the display area DA. In other words, the first inspection pad PD1, the second inspection pad PD2, and the third inspection pad PD3 can be located between pixel portions PX.

[0080] Figure 4 It shows that it includes Figure 2 The equivalent circuit diagram of the sub-pixel portion in the display device.

[0081] Reference Figure 3 and Figure 4 Each pixel portion PX can include multiple sub-pixel portions. For example, the first pixel portion PX1 can be as follows: Figure 5 The diagram shows a first sub-pixel portion SPX1, a second sub-pixel portion SPX2, and a third sub-pixel portion SPX3. The circuit structures of the first sub-pixel portion SPX1, the second sub-pixel portion SPX2, and the third sub-pixel portion SPX3 can be substantially the same.

[0082] The first sub-pixel portion SPX1 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a light-emitting element LED.

[0083] The first transistor T1 may include a first terminal (e.g., a source terminal), a second terminal (e.g., a drain terminal), and a gate terminal. A high supply voltage VDD may be provided to the first terminal. The second terminal may be electrically connected to a light-emitting element (LED). The gate terminal may be electrically connected to a second transistor T2. The first transistor T1 may generate a drive current based on the high supply voltage VDD and the data voltage DATA.

[0084] The second transistor T2 may include a first terminal (e.g., a source terminal), a second terminal (e.g., a drain terminal), and a gate terminal. The first terminal may receive a data voltage DATA. The second terminal may be electrically connected to the first transistor T1. The gate terminal may receive a first scan signal SS1. The second transistor T2 may transmit the data voltage DATA in response to the first scan signal SS1.

[0085] The third transistor T3 may include a first terminal (e.g., a source terminal), a second terminal (e.g., a drain terminal), and a gate terminal. The first terminal may be electrically connected to the first transistor T1. The second terminal may receive a sensed voltage INIT. The gate terminal may receive a second scan signal SS2. The third transistor T3 may transmit the sensed voltage INIT in response to the second scan signal SS2.

[0086] The fourth transistor T4 may include a first terminal (e.g., a source terminal), a second terminal (e.g., a drain terminal), and a gate terminal. The first terminal may receive a low supply voltage VSS. The second terminal may be electrically connected to the first transistor T1. The gate terminal may receive a third scan signal SS3. The fourth transistor T4 may transmit the low supply voltage VSS in response to the third scan signal SS3. For example, the fourth transistor T4 may be a transistor used for black frame insertion.

[0087] Figure 5 It shows Figure 2 An enlarged view of region "A", and Figure 6 It shows Figure 2 A magnified view of region "B".

[0088] Reference Figure 5The first inspection pad PD1 can be formed together with the first scan line SL1 and can be located between the first pixel portion PX1 and the second pixel portion PX2. The first pixel portion PX1 can include a first sub-pixel portion SPX1, a second sub-pixel portion SPX2 and a third sub-pixel portion SPX3, and the structures of the first sub-pixel portion SPX1, the second sub-pixel portion SPX2 and the third sub-pixel portion SPX3 can be substantially the same.

[0089] For example, the first data line DL1, the second data line DL2, and the third data line DL3 can extend in the second direction D2. The first data line DL1 can provide data voltage DATA to the first sub-pixel portion SPX1 through the first data bridge DB1.

[0090] The first low power supply voltage line VSSL1 can extend in the second direction D2. The first low power supply voltage line VSSL1 can provide a low power supply voltage VSS to the first sub-pixel portion SPX1 through the first low power supply voltage bridge VSSB1.

[0091] The first high power supply voltage line VDDL1 can extend in the second direction D2. The first high power supply voltage line VDDL1 can provide a high power supply voltage VDD to the first sub-pixel portion SPX1 through the first high power supply voltage bridge VDDB1.

[0092] The first sensing voltage line INITL1 can extend in the second direction D2. The first sensing voltage line INITL1 can provide a sensing voltage INIT to the first sub-pixel portion SPX1 through the first sensing voltage bridge INITB1.

[0093] A high power supply voltage mesh line VDDML can be disposed on the first high power supply voltage line VDDL1 and can extend in the first direction D1. The high power supply voltage mesh line VDDML can be electrically connected to the first high power supply voltage line VDDL1 and can prevent voltage drop of the high power supply voltage VDD.

[0094] The first scan line SL1 can be formed on the same layer or the same layer as the high power supply voltage mesh line VDDML, and can extend in the first direction D1. The first scan line SL1 can provide a first scan signal SS1 to the first scan bridge SB1. In response to the first scan signal SS1, a data voltage DATA can be provided to the first sub-pixel portion SPX1. The first scan line SL1 can provide a second scan signal SS2 to the second scan bridge SB2. In response to the second scan signal SS2, a sensing voltage INIT can be provided to the first sub-pixel portion SPX1.

[0095] The first inspection pad PD1 can be formed on the same layer or the same layer as the first scan line SL1, and can be electrically connected to the first scan line SL1. In other words, the first inspection pad PD1 and the first scan line SL1 can be integrated with each other. The defect location of the first scan line SL1 can be detected by the first inspection pad PD1.

[0096] The second scan line SL2 can be formed or disposed on the same layer as the first scan line SL1, and can extend in the first direction D1. The second scan line SL2 can provide a third scan signal SS3 to the third scan bridge SB3. In response to the third scan signal SS3, a low power supply voltage VSS can be provided to the first sub-pixel portion SPX1.

[0097] A low-supply-voltage mesh line VSSML can be disposed on a first low-supply-voltage line VSSL1 and can extend in a first direction D1. The low-supply-voltage mesh line VSSML can be electrically connected to the first low-supply-voltage line VSSL1 and can prevent voltage drop of the low-supply-voltage line VSS.

[0098] Reference Figure 6 The third inspection pad PD3 can be formed together with the second scan line SL2 and can be spaced apart from the first inspection pad PD1 in the first direction D1. For example, the second pixel portion PX2 can be disposed between the first inspection pad PD1 and the third inspection pad PD3. The second pixel portion PX2 may include a fourth sub-pixel portion SPX4, a fifth sub-pixel portion SPX5, and a sixth sub-pixel portion SPX6, and the structures of the fourth sub-pixel portion SPX4, the fifth sub-pixel portion SPX5, and the sixth sub-pixel portion SPX6 can be substantially the same as the structures of the first sub-pixel portion SPX1, the second sub-pixel portion SPX2, and the third sub-pixel portion SPX3.

[0099] The fourth data line DL4, the fifth data line DL5, and the sixth data line DL6 can be substantially the same as the first data line DL1, the second data line DL2, and the third data line DL3. Similarly, the second low power supply voltage line VSSL2, the second high power supply voltage line VDDL2, and the second sensing voltage line INITL2 can be substantially the same as the first low power supply voltage line VSSL1, the first high power supply voltage line VDDL1, and the first sensing voltage line INITL1. The fourth scan bridge SB4, the fifth scan bridge SB5, and the sixth scan bridge SB6 can be substantially the same as the first scan bridge SB1, the second scan bridge SB2, and the third scan bridge SB3. Furthermore, the second data bridge DB2, the second low power supply voltage bridge VSSB2, the second high power supply voltage bridge VDDB2, and the second sensing voltage bridge INITB2 can be substantially the same as the first data bridge DB1, the first low power supply voltage bridge VSSB1, the first high power supply voltage bridge VDDB1, and the first sensing voltage bridge INITB1.

[0100] The third inspection pad PD3 can be formed on the same layer or the same layer as the second scan line SL2, and can be electrically connected to the second scan line SL2. In other words, the third inspection pad PD3 and the second scan line SL2 can be integrated with each other. The location of defects in the second scan line SL2 can be detected by the third inspection pad PD3.

[0101] Figure 7 It shows Figure 2 A schematic cross-sectional view of the display device.

[0102] Reference Figure 5 , Figure 7 and Figure 8 The first sub-pixel portion SPX1 may include a substrate SUB, a first conductive pattern CP1, a buffer layer BFR, an active pattern ACT, a gate insulating layer GI, a second conductive pattern CP2, a first insulating layer ILD1, a third conductive pattern CP3, a fourth conductive pattern CP4, a second insulating layer ILD2, a via insulating layer VIA, a first connecting electrode CE1, a second connecting electrode CE2, a first passivation pattern PAS1, a light-emitting element LED, a first driving electrode DE1, a second driving electrode DE2, a second passivation pattern PAS2, a pixel defining layer PDL, a black matrix BM, a color conversion pattern QD, a planarization layer OC, and a color filter CF.

[0103] The substrate SUB may include transparent or opaque materials. For example, within the spirit and scope of this disclosure, the substrate SUB may include glass, quartz, plastic, etc.

[0104] A first conductive pattern CP1 may be disposed on a substrate SUB. The first conductive pattern CP1 may include a conductive material. For example, the first conductive pattern CP1 may include a metal. Figure 7The first conductive pattern CP1 shown may correspond to the first high power supply voltage line VDDL1, but this disclosure is not limited thereto. In embodiments, for example, the first conductive pattern CP1 may be disposed on the same layer or the same layer as the data lines DL1 to DL6, the low power supply voltage lines VSSL1 and VSSL2, and the sensing voltage lines INITL1 and INITL2.

[0105] The buffer layer BFR can be disposed on the substrate SUB and can cover or overlap the first conductive pattern CP1. The buffer layer BFR may include an insulating material. For example, within the spirit and scope of this disclosure, the buffer layer BFR may include silicon oxide, silicon nitride, silicon oxynitride, etc.

[0106] The active pattern ACT can be disposed on the buffer layer BFR. The active pattern ACT can include semiconductor materials. For example, within the spirit and scope of this disclosure, the active pattern ACT can include amorphous silicon, polycrystalline silicon, metal oxide, etc.

[0107] The gate insulating layer GI can be disposed on the buffer layer BFR and can cover or overlap the active pattern ACT. The gate insulating layer GI may include an insulating material.

[0108] The second conductive pattern CP2 can be disposed on the gate insulating layer GI. The second conductive pattern CP2 can overlap with the active pattern ACT and can include metallic material.

[0109] The first insulating layer ILD1 may be disposed on the gate insulating layer GI, and may cover or overlap the second conductive pattern CP2. The first insulating layer ILD1 may include an insulating material.

[0110] The third conductive pattern CP3 can be disposed on the first insulating layer ILD1. The third conductive pattern CP3 can be electrically connected to the first conductive pattern CP1 and the active pattern ACT. Figure 7 The third conductive pattern CP3 shown may correspond to the first high power supply voltage bridge VDDB1, but this disclosure is not limited thereto. In embodiments, for example, the third conductive pattern CP3 may be disposed on the same layer or the same layer as the first scan line SL1, the second scan line SL2, the data bridges DB1 and DB2, the low power supply voltage bridges VSSB1 and VSSB2, and the sensing voltage bridges INITB1 and INITB2.

[0111] The fourth conductive pattern CP4 can be disposed on the same layer or the same layer as the third conductive pattern CP3. The fourth conductive pattern CP4 can be electrically connected to the active pattern ACT and the first connecting electrode CE1.

[0112] The second insulating layer ILD2 may be disposed on the first insulating layer ILD1, and may cover or overlap the third conductive pattern CP3 and the fourth conductive pattern CP4. The second insulating layer ILD2 may include insulating material.

[0113] A via insulating layer VIA can be disposed on the second insulating layer ILD2. The via insulating layer VIA may include insulating material. An opening exposing the second insulating layer ILD2 and a contact hole exposing the fourth conductive pattern CP4 can be formed in the via insulating layer VIA.

[0114] The first passivation pattern PAS1 can be disposed in the opening. The light-emitting element LED can be disposed on the first passivation pattern PAS1. The second passivation pattern PAS2 can be disposed on the light-emitting element LED. The first passivation pattern PAS1 and the second passivation pattern PAS2 can fix or set the light-emitting element LED in place.

[0115] The first driving electrode DE1 can be in electrical contact with the first connecting electrode CE1 and the light-emitting element LED. The first driving electrode DE1 can provide a driving current to the light-emitting element LED. The second driving electrode DE2 can be in electrical contact with the second connecting electrode CE2 and the light-emitting element LED. The second driving electrode DE2 can provide a low power supply voltage VSS to the light-emitting element LED. In an embodiment, for example, the first driving electrode DE1 and the second driving electrode DE2 can be disposed on the same layer or the same layer.

[0116] The light-emitting element (LED) can be disposed between the first driving electrode DE1 and the second driving electrode DE2. In an embodiment, the LED can be a nano-light-emitting diode. The LED can include an active layer and can emit light within a given wavelength range. For example, the LED can emit blue light having a peak wavelength in the range of about 440 nm to about 480 nm.

[0117] The pixel defining layer (PDL) can be disposed on the via insulating layer (VIA) and can define the light-emitting area. For example, the pixel defining layer (PDL) can be configured to surround the light-emitting area.

[0118] A black matrix (BM) can be disposed on the pixel-defining layer (PDL). The black matrix (BM) can block light transmission. For example, the black matrix (BM) can include organic light-blocking materials and hydrophobic components.

[0119] The color conversion pattern QD can be disposed on the second passivation pattern PAS2. In an embodiment, the color conversion pattern QD may include a base resin, a scatterer, and a wavelength converter. The base resin may include a transparent organic material and may have relatively high light transmittance. The scatterer may have a refractive index different from that of the base resin and may form an optical interface with the base resin. The wavelength converter can convert or transform the peak wavelength of the incident light. For example, the wavelength converter can convert blue light into red light in the range of about 610 nm to about 650 nm.

[0120] The planarization layer OC can be set on the black matrix BM and the color conversion pattern QD. The planarization layer OC can have a substantially flat upper surface.

[0121] A color filter CF can be placed on the planarization layer OC. The color filter CF can selectively transmit light of a first color (e.g., red) and selectively block light of a second color (e.g., green) and a third color (e.g., blue).

[0122] In this implementation, the first inspection pad PD1 may be disposed on the same layer or the same layer as the third conductive pattern CP3. For example, the first inspection pad PD1 may be disposed on the same layer or the same layer as the first scan line SL1 and the second scan line SL2.

[0123] In this embodiment, the third inspection pad PD3 may be disposed on the same layer or the same layer as the third conductive pattern CP3. For example, the third inspection pad PD3 may be disposed on the same layer or the same layer as the first inspection pad PD1, the first scan line SL1, and the second scan line SL2.

[0124] Figure 8 A top view of a display device according to an embodiment is shown.

[0125] Reference Figure 8 Apart from setting the position of the scan driver SDV and setting the position of the first inspection pad PD1, the first display device DD1' according to the embodiment can be related to the above-mentioned reference. Figure 2 The first display device DD1 described is essentially the same.

[0126] For example, the scan driver SDV and the first inspection pad PD1 can be set in the display area DA.

[0127] The scan driver SDV may include a first scan driver SDV-P1, a second scan driver SDV-P2, and a third scan driver SDV-P3, and the first scan driver SDV-P1, the second scan driver SDV-P2, and the third scan driver SDV-P3 may each be mounted between pixel columns.

[0128] The first inspection pad PD1 can be electrically connected to the first scan line SL1 and can be positioned between any pixel columns. If needed, the position of the first inspection pad PD1 can be freely set in the display area DA.

[0129] As described above, the first display device DD1' may not include the above reference. Figure 2 The second inspection pad PD2 and the third inspection pad PD3 are described.

[0130] Figure 9 A top view of the display device according to an embodiment is shown. Figure 10 It shows Figure 9 A magnified view of region "C", and Figure 11 It shows Figure 9 A schematic cross-sectional view of the display device.

[0131] Reference Figure 9 According to the embodiment, the first display device DD1 can be divided into a display area DA and a non-display area NDA. For example, multiple pixel portions PX, a scan driver SDV, and an inspection pad PD can be disposed in the display area DA. The non-display area NDA can be disposed around or adjacent to the display area DA. The non-display area NDA can be a region in which no pixel portions PX are disposed. For example, multiple data integrated circuits DIC can be disposed in the non-display area NDA. However, the scan driver SDV and the data integrated circuits DIC can be related to the above-mentioned... Figure 2 The described scan driver SDV and data integrated circuit DIC are essentially the same.

[0132] In the implementation method, such as Figure 9 As shown, the pixel portion PX may include a first pixel portion PX1 and a second pixel portion PX2. For example, the first pixel portion PX1 and the second pixel portion PX2 may be disposed in a pixel column or a single pixel column. The first pixel portion PX1 may be disposed in the outermost region of the display area DA adjacent to the non-display area NDA. The second pixel portion PX2 may be spaced apart from the first pixel portion PX1 in the second direction D2.

[0133] The first pixel portion PX1 and the second pixel portion PX2 can be electrically connected to the first voltage line. In other words, the first pixel portion PX1 and the second pixel portion PX2 can receive a first voltage from the first voltage line. The first voltage line can be any voltage line extending in the second direction D2 and transmitting voltage to the first pixel portion PX1 and the second pixel portion PX2. In an embodiment, the first voltage line can be a sensing voltage line INITL. However, the first voltage line is not limited to this.

[0134] The inspection pad (PD) can be an inspection pad used to perform OS checks. For example, the inspection pad (PD) can be the pad that the probe pin contacts.

[0135] The inspection pad PD can be electrically connected to the sensing voltage line INITL. In other words, the inspection pad PD can be an inspection pad used to detect the location of defects in the sensing voltage line INITL. The inspection pad PD can be set to be adjacent to the first pixel portion PX1. However, the position of the inspection pad PD can be freely set as needed.

[0136] Reference Figure 10 The inspection pad PD can be formed together with the sensing voltage line INITL and can be positioned adjacent to the first pixel portion PX1. In other words, the inspection pad PD can be formed or disposed on the same layer as the sensing voltage line INITL and can be electrically connected to the sensing voltage line INITL. The location of defects in the sensing voltage line INITL can be detected by the inspection pad PD.

[0137] Reference Figure 11 In this implementation, the inspection pad PD can be disposed on the same layer or the same layer as the first conductive pattern CP1. For example, the inspection pad PD can be disposed on the same layer or the same layer as the high power supply voltage line VDDL, the low power supply voltage line VSSL, the data line DL, and the sensing voltage line INITL.

[0138] Figure 12 A top view of the display device according to an embodiment is shown. Figure 13 It shows Figure 12 A magnified view of region "D", and Figure 14 It shows Figure 12 A schematic cross-sectional view of the display device.

[0139] Reference Figure 12 According to the embodiment, the first display device DD1" can be divided into a display area DA and a non-display area NDA. For example, multiple pixel portions PX, a scan driver SDV, and an inspection pad PD can be disposed in the display area DA. The non-display area NDA can be disposed around or adjacent to the display area DA. The non-display area NDA can be an area in which pixel portions PX may not be disposed. For example, multiple data integrated circuits DIC can be disposed in the non-display area NDA. However, the scan driver SDV and the data integrated circuits DIC can be related to the above-mentioned references. Figure 2 The described scan driver SDV and data integrated circuit DIC are essentially the same.

[0140] In the implementation method, such as Figure 12As shown, the pixel portion PX may include a first pixel portion PX1 and a second pixel portion PX2. For example, the first pixel portion PX1 and the second pixel portion PX2 may be disposed in a pixel column or a single pixel column. The first pixel portion PX1 may be disposed in the outermost region of the display area DA adjacent to the non-display area NDA. The second pixel portion PX2 may be spaced apart from the first pixel portion PX1 in the second direction D2.

[0141] The first pixel portion PX1 and the second pixel portion PX2 can be electrically connected to the second voltage line. In other words, the first pixel portion PX1 and the second pixel portion PX2 can receive a second voltage from the second voltage line. The second voltage line can be any voltage line extending in the second direction D2 and transmitting voltage to the first pixel portion PX1 and the second pixel portion PX2. In an embodiment, the second voltage line can be a high power supply voltage line VDDL. However, the second voltage line is not limited to this.

[0142] The inspection pad (PD) can be an inspection pad used to perform OS checks. For example, the inspection pad (PD) can be the pad that the probe pin contacts.

[0143] The inspection pad PD can be electrically connected to the high power supply voltage line VDDL. In other words, the inspection pad PD can be an inspection pad used to detect the location of defects on the high power supply voltage line VDDL. The inspection pad PD can be set to be adjacent to the first pixel portion PX1. However, the position of the inspection pad PD can be freely set as needed.

[0144] Reference Figure 13 The sensing voltage line INITL can extend in the second direction D2 and can transmit the sensing voltage INIT. The high power supply voltage line VDDL can extend in the second direction D2 and can transmit the high power supply voltage VDD. The high power supply voltage line VDDL can be positioned between the sensing voltage line INITL and the first pixel portion PX1.

[0145] The inspection pad (PD) may include a raised PDP. The raised PDP may extend toward and be electrically connected to the high power supply line (VDDL). In other words, the inspection pad (PD) can be an inspection pad used to detect the location of defects on the high power supply line (VDDL).

[0146] Reference Figure 14In one embodiment, the inspection pad PD can be disposed on the same layer or the same layer as the third conductive pattern CP3. For example, the inspection pad PD can be disposed on the same layer or the same layer as the first scan line SL1, the second scan line SL2, the data bridge DB, the high power supply voltage bridge VDDB, the low power supply voltage bridge VSSB, and the sensing voltage bridge INITB. The sensing voltage line INITB and the second scan bridge SB2 can be disposed below or below the inspection pad PD. In another embodiment, for example, the high power supply voltage line VDDL can be disposed on the same layer or the same layer as the first conductive pattern CP1.

[0147] The display devices DD1, DD1', DD1" and DD1"' according to the embodiments may include inspection pads PD, PD1, PD2 and PD3 disposed in the display area DA and a scan driver SDV disposed in the display area DA. For example, the inspection pads and the scan driver may be disposed between pixel columns. Therefore, the non-display area surrounding or adjacent to the display area can be reduced. The inspection pads may be electrically connected to lines transmitting signals and / or voltages. Therefore, the location of defects in the lines can be detected by inspecting the inspection pads.

[0148] This disclosure can be applied to display devices and electronic devices including such display devices. For example, within the spirit and scope of this disclosure, it can be applied to high-resolution smartphones, mobile phones, smart tablets, smartwatches, tablet PCs, vehicle navigation systems, televisions, computer displays, laptops, etc.

[0149] Although this disclosure has been described in conjunction with what is believed to be a practical implementation, it will be understood that this disclosure is not limited to the disclosed implementation, but rather, this disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims and this disclosure.

Claims

1. A display device comprising: a display region and a non-display region adjacent to the display region; a first scan line extending in a row direction and transmitting a first scan signal; a first pixel portion electrically connected to the first scan line; a second pixel portion electrically connected to the first scan line and spaced apart from the first pixel portion in the row direction; and a first inspection pad provided between the first pixel portion and the second pixel portion and electrically connected to the first scan line, wherein the first pixel portion includes: a first conductive pattern provided on a substrate; an active pattern provided on the first conductive pattern; a second conductive pattern provided on the active pattern; and a third conductive pattern provided on the second conductive pattern and electrically connected to the first conductive pattern and the active pattern, and the first inspection pad and the third conductive pattern are provided on the same layer. The first pixel portion is provided in a first outermost region of the display region adjacent to the non-display region.

2. The display device according to claim 1, wherein 3. The display device according to claim 1, further comprising: a second inspection pad electrically connected to the first scan line and spaced apart from the first inspection pad in the row direction.

4. The display device according to claim 3, further comprising: a third pixel portion electrically connected to the first scan line and spaced apart from the second pixel portion in the row direction; and a fourth pixel portion electrically connected to the first scan line and spaced apart from the third pixel portion in the row direction, wherein the second inspection pad is provided between the third pixel portion and the fourth pixel portion. The fourth pixel portion is provided in a second outermost region of the display region adjacent to the non-display region and faces the first pixel portion.

6. The display device according to claim 1, further comprising:

5. The display device of claim 4, wherein, a second scan line extending in the row direction and transmitting a second scan signal; and a third inspection pad spaced apart from the first inspection pad in the row direction and electrically connected to the second scan line. The second pixel portion is provided between the first inspection pad and the third inspection pad.

8. The display device according to claim 1, further comprising: a data line extending in a column direction intersecting the row direction and transmitting a data voltage, the data line being provided on the same layer as the first conductive pattern; and 7. The display device of claim 6, wherein, a data bridge electrically connecting the data line and the first pixel portion, the data bridge and the third conductive pattern being provided on the same layer.

9. The display device according to claim 1, further comprising: a sense voltage line extending in a column direction intersecting the row direction and transmitting a sense voltage, the sense voltage line being provided on the same layer as the first conductive pattern; and a sense voltage bridge electrically connecting the sense voltage line and the first pixel portion, the sense voltage bridge and the third conductive pattern being provided on the same layer.

10. The display device according to claim 1, further comprising: ​ ​ ​ ​ ​ a high power supply voltage line extending in a column direction intersecting the row direction and transmitting a high power supply voltage, the high power supply voltage line corresponding to the first conductive pattern; and a high power supply voltage bridge electrically connecting the high power supply voltage line and the first pixel portion, the high power supply voltage bridge corresponding to the third conductive pattern.

11. The display device according to claim 1, further comprising: a low power supply voltage line extending in a column direction intersecting the row direction and transmitting a low power supply voltage, the low power supply voltage line being provided on the same layer as the first conductive pattern; and a low power supply voltage bridge electrically connecting the low power supply voltage line and the first pixel portion, the low power supply voltage bridge and the third conductive pattern being provided on the same layer.

12. The display device of claim 1, wherein, the first pixel portion includes: a first connection electrode provided over the third conductive pattern; a second connection electrode provided over the third conductive pattern and spaced apart from the first connection electrode; a nano light emitting element provided over the first connection electrode; a first drive electrode provided over the nano light emitting element and in electrical contact with the first connection electrode; and a second drive electrode in electrical contact with the second connection electrode, the second drive electrode and the first drive electrode being provided on the same layer.

13. The display device of claim 12, wherein, the first pixel portion includes a color conversion pattern provided over the nano light emitting element.

14. The display device of claim 13, wherein, the first pixel portion includes a color filter provided over the color conversion pattern.

15. A display device comprising: a display region and a non-display region adjacent to the display region; a first voltage line extending in a column direction and transmitting a first voltage; a first pixel portion electrically connected to the first voltage line; a second pixel portion electrically connected to the first voltage line and spaced apart from the first pixel portion in the column direction; and an inspection pad electrically connected to the first voltage line, wherein the first pixel portion includes a first conductive pattern provided over a substrate, and the inspection pad and the first conductive pattern are provided on the same layer. the first pixel portion further includes:

16. The display device of claim 15, wherein, an active pattern provided over the first conductive pattern; a second conductive pattern provided over the active pattern; and a third conductive pattern provided over the second conductive pattern and electrically connected to the first conductive pattern and the active pattern.

17. A display device comprising: a display region and a non-display region adjacent to the display region; a first voltage line extending in a column direction and transmitting a first voltage; a second voltage line extending in the column direction and transmitting a second voltage; a first pixel portion electrically connected to the first voltage line and the second voltage line; a second pixel portion electrically connected to the first voltage line and the second voltage line and spaced apart from the first pixel portion in the column direction; and an inspection pad electrically connected to the second voltage line, and wherein the second voltage line is provided between the first voltage line and the first pixel portion. the first pixel portion includes: a first conductive pattern provided over a substrate; 18. The display device of claim 17, wherein, an active pattern provided over the first conductive pattern; ​ ​ a second conductive pattern disposed on the active pattern; and a third conductive pattern disposed on the second conductive pattern and electrically connected to the first conductive pattern and the active pattern, and the inspection pad and the third conductive pattern are disposed on the same layer.

19. The display device of claim 18, wherein, the second voltage line and the first conductive pattern are disposed on the same layer.

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