De-skewing circuit for differential signals

Abstract

The present application provides a deskew circuit for differential signals. A first common mode voltage generating circuit generates a first common mode voltage signal according to a first differential input signal and a second differential input signal. A voltage buffer circuit is coupled to the first common mode voltage generating circuit and has an input impedance higher than a predetermined value. The voltage buffer circuit buffers the first common mode voltage signal, the first differential input signal and the second differential input signal to generate a second common mode voltage signal, a third differential input signal and a fourth differential input signal. A second common mode voltage generating circuit is coupled to the voltage buffer circuit and generates a third common mode voltage signal according to the third differential input signal and the fourth differential input signal. An output circuit generates a deskewed output signal according to the third differential input signal, the fourth differential input signal, the second common mode voltage signal and the third common mode voltage signal.

Description

Technical Field

[0001] This invention relates to a differential signal receiving circuit, and more particularly to a differential signal deskewing circuit. Background Technology

[0002] When it comes to communication systems, differential circuits generally offer superior performance compared to single-ended circuits due to their higher linearity and better immunity to common-mode interference. Differential signals must be transmitted together through the same environment along two closely spaced transmission paths, thus effectively suppressing electromagnetic interference (EMI).

[0003] However, the lengths of the two transmission cables used to transmit differential signal pairs typically differ slightly, resulting in a difference in the arrival times of the positive and negative phases of the differential signal pair, causing a delay skew. Several solutions have been proposed to improve the delay skew, such as using delay units to compensate for it. However, with increasingly higher transmission rates in real-world applications and the requirement for impedance matching in differential receiver designs, the design of de-skew circuits to improve the delay skew of differential signal pairs faces many challenges. Summary of the Invention

[0004] In view of this, the present invention proposes a deskipation circuit for differential signals, which can be applied to high-speed transmission applications under the condition of impedance matching.

[0005] This invention provides a deskipation circuit for differential signals, comprising a first common-mode voltage generation circuit, a voltage buffer circuit, a second common-mode voltage generation circuit, and an output circuit. The first common-mode voltage generation circuit generates a first common-mode voltage signal based on a first differential input signal and a second differential input signal. The voltage buffer circuit is coupled to the first common-mode voltage generation circuit and has an input impedance higher than a preset value. The voltage buffer circuit buffers the first common-mode voltage signal, the first differential input signal, and the second differential input signal to generate a second common-mode voltage signal, a third differential input signal, and a fourth differential input signal. The second common-mode voltage generation circuit is coupled to the voltage buffer circuit and generates a third common-mode voltage signal based on the third differential input signal and the fourth differential input signal. The output circuit is coupled to the second common-mode voltage generation circuit and the voltage buffer circuit and generates a deskipated output signal based on the third differential input signal, the fourth differential input signal, the second common-mode voltage signal, and the third common-mode voltage signal.

[0006] Based on the above, in embodiments of the present invention, a voltage buffer circuit is provided between the first common-mode voltage generation circuit and the second common-mode voltage generation circuit. The voltage buffer circuit has a high input impedance to isolate the second common-mode voltage generation circuit from the signal input terminal. Therefore, the circuit components within the second common-mode voltage generation circuit do not affect the input impedance of the differential signal receiver, allowing for more flexible configuration of the circuit components within the second common-mode voltage generation circuit while meeting the impedance matching requirements specified by the transmission standard, thus making it suitable for high-speed transmission applications. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of a differential signal transmission system according to an embodiment of the present invention;

[0008] Figure 2 This is a block diagram of a deskipation circuit for a differential signal receiver according to an embodiment of the present invention;

[0009] Figure 3 This is a circuit diagram of a deskewing circuit for a differential signal receiver according to an embodiment of the present invention;

[0010] Figure 4 This is a schematic diagram of a voltage buffer according to an embodiment of the present invention;

[0011] Figure 5 It is an equivalent circuit diagram showing the presence of parasitic capacitance without a voltage buffer circuit.

[0012] Figure 6 It is an equivalent circuit diagram showing the presence of parasitic capacitance when a voltage buffer circuit is set. Detailed Implementation

[0013] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component symbols are used in the drawings and description to denote the same or similar parts.

[0014] Figure 1 This is a schematic diagram of a differential signal transmission system according to an embodiment of the present invention. Please refer to... Figure 1 The differential signal transmission system 100 may include a differential signal transmitter 101, a transmission cable 102, and a differential signal receiver 103. This invention does not limit the signal transmission standard used in the differential signal transmission system 100, such as the Universal Serial Bus (USB) standard or the High Resolution Multimedia Interface (HDMI) standard, etc. For example, the differential signal transmitter 101 may be a USB signal transmitter, the transmission cable 102 may be a USB transmission cable, and the differential signal receiver 103 may be a USB signal receiver.

[0015] The differential signal transmitter 101 can transmit signals through the transmission cable 102. For example, the transmission cable 102 can be of any suitable connection type, such as a coaxial cable, a twisted pair, or any type of transmission bus, to provide a connection between the differential signal transmitter 101 and the differential signal receiver 103. The differential transmission signals Vip and Vin can be provided to the signal receiving terminals of the differential signal receiver 103 through the transmission cable 102. It should be noted that when the differential transmission signals Vip and Vin are transmitted from the transmission cable 102 to the differential signal receiver 103, the transmission line impedance of the transmission cable 102 and the termination impedance of the differential signal receiver 103 need to be matched to avoid signal reflection that could affect signal transmission quality.

[0016] The differential signal receiver 103 includes a de-skew circuit 20. The de-skew circuit 20 generates a de-skew output signal Vout based on the differential transmission signals Vip and Vin. The de-skew output signal Vout is an output signal generated by de-skewing the voltage difference between the differential transmission signals Vip and Vin. The de-skew output signal Vout can consist of a series of pulses, and the waveforms of these pulses are related to the bit data to be transmitted.

[0017] Figure 2 This is a block diagram of a deskipation circuit for a differential signal receiver according to an embodiment of the present invention. Please refer to... Figure 2 The deskew circuit 20 may include a first common-mode voltage generation circuit 210, a voltage buffer circuit 220, a second common-mode voltage generation circuit 230, and an output circuit 240. The first common-mode voltage generation circuit 210 generates a first common-mode voltage signal VCM1 based on a first differential input signal Vipx and a second differential input signal Vinx, such that the amplitude of the first common-mode voltage signal VCM1 is determined by the first differential input signal Vipx and the second differential input signal Vinx. In one embodiment, the first differential input signal Vipx and the second differential input signal Vinx may be the same as or different from the differential transmission signals Vip and Vin, depending on the circuit configuration between the first common-mode voltage generation circuit 210 and the signal receiving terminal. In one embodiment, the first common-mode voltage signal VCM1 may further be generated based on a bias voltage provided by a voltage source, such that the actual voltage range of the first common-mode voltage signal VCM1 is determined by the bias voltage provided by the voltage source.

[0018] A voltage buffer circuit 220 is coupled to a first common-mode voltage generation circuit 210. The voltage buffer circuit 220 has an input impedance that is higher than a preset value. For example, the input impedance of the voltage buffer circuit 220 can be in the mega ohms range. The preset value is, for example, 1 mega ohm, but the invention is not limited thereto. The voltage buffer circuit 220 has the characteristics of high input impedance and low output impedance, which can isolate the influence between the preceding and following circuits. The voltage buffer circuit 220 is used to buffer the first common-mode voltage signal VCM1, the first differential input signal Vipx, and the second differential input signal Vinx to generate a second common-mode voltage signal VCM2, a third differential input signal Vp1, and a fourth differential input signal Vn1. In one embodiment, the voltage buffer circuit 220 can be a unity-gain buffer circuit or a level shifter circuit, and can maintain the voltage phase and voltage swing of the output voltage signal the same as the voltage phase and voltage swing of the input signal. In other words, the first common-mode voltage signal VCM1 and the second common-mode voltage signal VCM2 are in phase and have the same swing amplitude; the first differential input signal Vipx and the third differential input signal Vp1 are in phase and have the same swing amplitude; and the second differential input signal Vinx and the fourth differential input signal Vn1 are in phase and have the same swing amplitude. Specifically, in one embodiment, the voltage buffer circuit 220 may include a plurality of voltage buffers, which are used to buffer the first common-mode voltage signal VCM1, the first differential input signal Vipx, and the second differential input signal Vinx, respectively.

[0019] The second common-mode voltage generation circuit 230 is coupled to the voltage buffer circuit 220 and generates a third common-mode voltage signal VCMA based on the third differential input signal Vp1 and the fourth differential input signal Vn1. Specifically, the second common-mode voltage generation circuit 230 receives the third differential input signal Vp1 and the fourth differential input signal Vn1 from the voltage buffer circuit 220 to generate the third common-mode voltage signal VCMA between the third differential input signal Vp1 and the fourth differential input signal Vn1. The third common-mode voltage signal VCMA is the average voltage value of the third differential input signal Vp1 and the fourth differential input signal Vn1. It should be noted that the first common-mode voltage generation circuit 210 and the second common-mode voltage generation circuit 230 generate the first common-mode voltage signal VCM1 and the third common-mode voltage signal VCMA based on different impedance values.

[0020] Output circuit 240 is coupled to second common-mode voltage generation circuit 230 and voltage buffer circuit 220. Output circuit 240 generates a de-skew output signal Vout based on the third differential input signal Vp1, the fourth differential input signal Vn1, the second common-mode voltage signal VCM2, and the third common-mode voltage signal VCMA. Specifically, output circuit 240 adjusts the voltage difference between the third differential input signal Vp1 and the fourth differential input signal Vn1 based on the comparison result between the second common-mode voltage signal VCM2 and the third common-mode voltage signal VCMA, thereby generating the de-skew output signal Vout.

[0021] It is worth mentioning that by placing the voltage buffer circuit 220 between the first common-mode voltage generation circuit 210 and the second common-mode voltage generation circuit 230, the second common-mode voltage generation circuit 230 in the later stage does not become a load on the first common-mode voltage generation circuit 210 in the earlier stage. Therefore, the second common-mode voltage generation circuit 230 does not affect the termination impedance of the differential signal receiver 103, and thus the impedance configuration of the circuit components inside the second common-mode voltage generation circuit 230 can be more flexible without being limited by impedance matching. If the impedance of the circuit components inside the second common-mode voltage generation circuit 230 can be reduced, the differential signal receiver 103 can be more suitable for high-speed transmission applications.

[0022] Figure 3 This is a circuit diagram of a deskipation circuit for a differential signal receiver according to an embodiment of the present invention. Please refer to... Figure 3 In addition to the first common-mode voltage generating circuit 210, the voltage buffer circuit 220, the second common-mode voltage generating circuit 230, and the output circuit 240, the deskipation circuit 20 may also include a coupling circuit 250.

[0023] In this embodiment, the coupling circuit 250 is coupled to the first common-mode voltage generating circuit 210, receiving differential transmission signals Vip and Vin and generating a first differential input signal Vipx and a second differential input signal Vinx based on the capacitance values. Specifically, the coupling circuit 250 may include capacitors C1 and C2, with the same capacitance value. One end of capacitor C1 receives the differential transmission signal Vip, while the other end outputs the first differential input signal Vipx. One end of capacitor C2 receives the differential transmission signal Vin, while the other end outputs the second differential input signal Vinx. Through the AC coupling of capacitors C1 and C2, capacitors C1 and C2 can isolate the DC component of the differential transmission signals Vip and Vin, and allow the first common-mode voltage signal VCM1 to be flexibly set. Therefore, if the first common-mode voltage signal VCM1 generated by the first common-mode voltage generating circuit 210 can be adjusted according to requirements, the subsequent output circuit 240 can be designed more easily.

[0024] In this embodiment, the voltage buffer circuit 220 includes a first voltage buffer 221, a second voltage buffer 222, and a third voltage buffer 223. The first voltage buffer 221 buffers the first differential input signal Vipx to generate a third differential input signal Vp1. The second voltage buffer 222 buffers the first common-mode voltage signal VCM1 to generate a second common-mode voltage signal VCM2. The third voltage buffer 223 buffers the second differential input signal Vinx to generate a fourth differential input signal Vn1. In one embodiment, the first voltage buffer 221, the second voltage buffer 222, and the third voltage buffer 223 are unity-gain amplifier circuits with high input impedance and low output impedance. For example, the first voltage buffer 221, the second voltage buffer 222, and the third voltage buffer 223 may be voltage followers or source followers, etc.

[0025] Figure 4 This is a schematic diagram of a voltage buffer according to an embodiment of the present invention. Please refer to... Figure 4 In this embodiment, the first voltage buffer 221, the second voltage buffer 222, and the third voltage buffer 223 can each be implemented as a voltage follower 41. The negative input terminal of the voltage follower 41 is coupled to its output terminal, and the positive input terminal of the voltage follower 41 is used to receive the input signal S3. The output terminal of the voltage follower 41 provides the output signal S4. For the first voltage buffer 221, the input signal S3 of the voltage follower 41 is the first differential input signal Vipx, and the output signal S4 of the voltage follower 41 is the third differential input signal Vp1. For the second voltage buffer 222, the input signal S3 of the voltage follower 41 is the first common-mode voltage signal VCM1, and the output signal S4 of the voltage follower 41 is the second common-mode voltage signal VCM2. For the third voltage buffer 223, the input signal S3 of the voltage follower 41 is the second differential input signal Vinx, and the output signal S4 of the voltage follower 41 is the fourth differential input signal Vn1.

[0026] Please refer to again Figure 3The first common-mode voltage generation circuit 210 includes a first resistor R1 and a second resistor R2. The first common-mode voltage generation circuit 210 determines the first common-mode voltage signal VCM1 between the first differential input signal Vipx and the second differential input signal Vinx through the first resistor R1, the second resistor R2, and the bias voltage provided by the voltage source 211. In one embodiment, the resistance value of the first resistor R1 is the same as the resistance value of the second resistor R2. One end of the first resistor R1 receives the first differential input signal Vipx and is coupled to the input terminal of the first voltage buffer 221. One end of the second resistor R2 receives the second differential input signal Vinx and is coupled to the input terminal of the third voltage buffer 223. The other end of the first resistor R1 is coupled to the other end of the second resistor R2. Furthermore, the other ends of the first resistor R1 and the other ends of the second resistor R2 are also coupled to the voltage source 211 and output the first common-mode voltage signal VCM1 to the second voltage buffer 222. The voltage source 211 can be a DC voltage source or an AC voltage source; the present invention is not limited thereto. Specifically, the first resistor R1 and the second resistor R2 can be used to detect the average voltage of the first differential input signal Vipx and the second differential input signal Vinx, and this average voltage will be carried on the voltage provided by the voltage source 211 to generate the first common-mode voltage signal VCM1.

[0027] The second common-mode voltage generation circuit 230 includes a third resistor R3 and a fourth resistor R4. The second common-mode voltage generation circuit 230 can detect a third common-mode voltage signal VCMA between the third differential input signal Vp1 and the fourth differential input signal Vn1 through the third resistor R3 and the fourth resistor R4. In one embodiment, the resistance value of the third resistor R3 is the same as the resistance value of the fourth resistor R4. One end of the third resistor R3 is coupled to the output terminal of the first voltage buffer 221. One end of the fourth resistor R4 is coupled to the output terminal of the third voltage buffer 223. The other end of the third resistor R3 is coupled to the other end of the fourth resistor R4. Furthermore, the other end of the third resistor R3 and the other end of the fourth resistor R4 output the third common-mode voltage signal VCMA. Specifically, the third resistor R3 and the fourth resistor R4 can be used to detect the average voltage of the third differential input signal Vp1 and the fourth differential input signal Vn1, thereby generating the third common-mode voltage signal VCMA. In one embodiment, the resistance values ​​of the third resistor R3 and the fourth resistor R4 are different from the resistance values ​​of the first resistor R1 and the second resistor R2, so as to produce different RC delays.

[0028] Output circuit 240 includes a first differential amplifier 241, a second differential amplifier 242, and an adder / subtractor 243. The first differential amplifier 241 generates a first output signal S1 based on a third differential input signal Vp1 and a fourth differential input signal Vn1. Specifically, the first differential amplifier 241 compares the third differential input signal Vp1 with the fourth differential input signal Vn1 and provides the first output signal S1 at its output terminal based on the phase difference between the two. The second differential amplifier 242 generates a second output signal S2 based on a second common-mode voltage signal VCM2 and a third common-mode voltage signal VCMA. Similarly, the second differential amplifier 242 compares the second common-mode voltage signal VCM2 with the third common-mode voltage signal VCMA and provides the second output signal S2 at its output terminal based on the phase difference between the two. The adder / subtractor 243 is coupled to the output terminals of the first differential amplifier 241 and the second differential amplifier 242, and performs addition and subtraction operations based on the first output signal S1 and the second output signal S2 to generate a deskipated output signal Vout. Therefore, the first output signal S1 can be corrected into the deskipated output signal Vout based on the second output signal S2.

[0029] It should be noted that, in this embodiment, the first voltage buffer 221, the second voltage buffer 222, and the third voltage buffer 223 can isolate the second common-mode voltage generation circuit 230, so that the impedance values ​​of the third resistor R3 and the fourth resistor R4 within the second common-mode voltage generation circuit 230 will not affect the terminal impedance of the differential signal receiver 103. Therefore, the impedance values ​​of the third resistor R3 and the fourth resistor R4 can be set without considering the input impedance values ​​specified by the communication interface standard. In one embodiment, the resistance values ​​of the third resistor R3 and the fourth resistor R4 can be smaller than the resistance values ​​of the first resistor R1 and the second resistor R2, thus making them more suitable for high-speed transmission.

[0030] For example, the following explanation uses the USB 3.0 standard (i.e., USB 3.1 Gen 1 or USB 3.2 Gen 1x1) as an example. According to the USB 3.0 standard, the transmission rate is 5Gbps, and the single-ended termination impedance of the receiving end should be between 36 ohms and 60 ohms. Assuming the termination impedance is set to 50 ohms, and the bandwidth requirement is set to 2.5 times the transmission rate, approximately 12.5Gbps, then to achieve the required bandwidth of 12.5Gbps, the relationship between the RC time constant and bandwidth is as follows: Then Without the voltage buffer circuit 220, please refer to Figure 5 , Figure 5This is an equivalent circuit diagram showing the presence of parasitic capacitance without a voltage buffer circuit. Assuming the parasitic capacitance Cp connected in series between the reference ground and the third resistor R3 is 10 farads (f), the impedance of the third resistor R3 can be calculated using the aforementioned formula. The impedance is 1.27k ohms. Similarly, the impedance of the fourth resistor R4 can also be 1.27k ohms. In this case, assuming the impedance of the first resistor R1 and the second resistor R2 is 1M ohms, and the impedance of the pre-stage circuit (not shown) of the deskipation circuit 20 is 50 ohms. With the pre-stage impedance connected in parallel with the first resistor R1 and the third resistor R3, the equivalent impedance is 48.1 ohms, which deviates from the preset 50 ohms by 3.8%.

[0031] Therefore, to increase the transmission rate without a voltage buffer circuit, the impedance of the third resistor R3 needs to be reduced. However, reducing the impedance of the third resistor R3 will affect the overall termination impedance of the differential signal receiver 103, and may even cause it to fail to meet the set impedance matching. For example, under the same settings, to increase the transmission rate to 10Gbps, which complies with the USB 3.2 Gen 2 standard, the impedance of the third resistor R3 must be reduced to at least 636 ohms. In this case, the equivalent impedance of the first resistor R1 and the third resistor R3 in parallel is 46.3 ohms, which increases the deviation from the preset 50 ohms to 7.2%.

[0032] On the other hand, please refer to Figure 6 , Figure 6 This diagram illustrates the equivalent circuit with parasitic capacitance when a voltage buffer circuit is present. With the voltage buffer circuit 220 in place, due to its high input impedance, the third resistor R3 and the fourth resistor R4, regardless of their values, do not affect the overall termination impedance of the differential signal receiver 103. Assuming the first resistor R1 and the second resistor R2 have an impedance of 1 MΩ, and the pre-stage impedance of the deskipation circuit 20 (not shown) is 50 ohms, then with the first resistor R1 and the third resistor R3 connected in parallel, the equivalent impedance is 49.97 ohms, which conforms to the USB 3.0 standard and deviates from the preset 50 ohms by only 0.06%. Therefore, by using a voltage buffer circuit to block the influence of the third resistor R3 and the fourth resistor R4 on the final pre-stage impedance, the termination impedance matching can be effectively stabilized.

[0033] In summary, in the embodiments of the present invention, a voltage buffer circuit is provided between the first common-mode voltage generation circuit and the second common-mode voltage generation circuit. The voltage buffer circuit has a high input impedance to isolate the second common-mode voltage generation circuit from the signal input terminal. Therefore, the circuit components within the second common-mode voltage generation circuit do not affect the input impedance of the differential signal receiver, allowing for more flexible configuration of the circuit components within the second common-mode voltage generation circuit while meeting the impedance matching requirements specified by the transmission standard, and thus making it suitable for high-speed transmission applications.

[0034] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A deskipation circuit for differential signals, suitable for installation within a differential signal receiver, characterized in that, include: The first common-mode voltage generating circuit generates a first common-mode voltage signal based on the first differential input signal and the second differential input signal; A voltage buffer circuit, coupled to the first common-mode voltage generating circuit, has an input impedance higher than a preset value, buffering the first common-mode voltage signal, the first differential input signal, and the second differential input signal to generate a second common-mode voltage signal, a third differential input signal, and a fourth differential input signal; The second common-mode voltage generating circuit is coupled to the voltage buffer circuit and generates a third common-mode voltage signal based on the third differential input signal and the fourth differential input signal, wherein the voltage buffer circuit is disposed between the first common-mode voltage generating circuit and the second common-mode voltage generating circuit. as well as The output circuit is coupled to the second common-mode voltage generation circuit and the voltage buffer circuit, and generates a deskipation output signal based on the third differential input signal, the fourth differential input signal, the second common-mode voltage signal, and the third common-mode voltage signal.

2. The deskew circuit for differential signals according to claim 1, characterized in that, It also includes a coupling circuit that is coupled to the first common-mode voltage generating circuit, receives the differential transmission signal and generates the first differential input signal and the second differential input signal based on the capacitance value.

3. The deskew circuit for differential signals according to claim 1, characterized in that, The voltage buffer circuit includes a first voltage buffer, a second voltage buffer, and a third voltage buffer. The first voltage buffer is used to buffer the first differential input signal to generate the third differential input signal, the second voltage buffer is used to buffer the first common-mode voltage signal to generate the second common-mode voltage signal, and the third voltage buffer is used to buffer the second differential input signal to generate the fourth differential input signal.

4. The deskew circuit for differential signals according to claim 3, characterized in that, The first common-mode voltage generating circuit includes a first resistor and a second resistor. One end of the first resistor receives the first differential input signal and is coupled to the input terminal of the first voltage buffer. One end of the second resistor receives the second differential input signal and is coupled to the input terminal of the third voltage buffer. The other end of the first resistor and the other end of the second resistor are coupled to a voltage source and output the first common-mode voltage signal to the second voltage buffer.

5. The deskew circuit for differential signals according to claim 4, characterized in that, The resistance value of the first resistor is the same as the resistance value of the second resistor.

6. The deskew circuit for differential signals according to claim 3, characterized in that, The second common-mode voltage generating circuit includes a third resistor and a fourth resistor. One end of the third resistor is coupled to the output terminal of the first voltage buffer, and one end of the fourth resistor is coupled to the output terminal of the third voltage buffer. The other end of the third resistor and the other end of the fourth resistor output the third common-mode voltage signal.

7. The deskew circuit for differential signals according to claim 6, characterized in that, The first common-mode voltage generating circuit includes a first resistor and a second resistor. One end of the first resistor receives the first differential input signal, one end of the second resistor receives the second differential input signal, and the other end of the first resistor is coupled to the other end of the second resistor. The resistance values ​​of the third resistor and the fourth resistor are less than the resistance values ​​of the first resistor and the second resistor.

8. The deskew circuit for differential signals according to claim 1 or 6, characterized in that, The output circuit includes: The first differential amplifier generates a first output signal based on the third differential input signal and the fourth differential input signal; The second differential amplifier generates a second output signal based on the second common-mode voltage signal and the third common-mode voltage signal; and The adder / subtractor is coupled to the output terminals of the first differential amplifier and the second differential amplifier, and performs addition and subtraction operations based on the first output signal and the second output signal to generate the deskew output signal.

9. The deskew circuit for differential signals according to claim 6, characterized in that, The resistance value of the third resistor is the same as the resistance value of the fourth resistor.

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