Analog multiplexer with current injection protection

Abstract

A multi-branch analog multiplexer includes protection circuitry to help dissipate positive and negative injection currents without increasing the size of hardening transistors in each branch, thereby avoiding an increase in leakage current and enabling an analog-to-digital converter to operate with the required precision. The protection circuitry is attached to the bases of the hardening transistors to lower the threshold voltage of the hardening devices, thereby enabling the hardening devices to handle more injection current.

Description

Technical Field

[0001] This invention relates to an analog multiplexer, and specifically to an analog multiplexer having low leakage current and minimizing the effects of current injection. Background Technology

[0002] As the geometry of CMOS transistors becomes increasingly smaller, the safe operating voltage on internal transistors becomes increasingly lower. Therefore, larger geometry transistors must be used in the I / O circuitry of the device's inputs and outputs to protect the device from excessive voltages, thus preventing damage to the device's internal logic. Current injection on analog input pins presents additional problems. Injected current can cause a decrease in the accuracy of the analog-to-digital converter (ADC). Furthermore, current injection on analog inputs can cause errors in adjacent analog channels. The expected injection current is typically specified in the recommended operating conditions in the device datasheet and is generally in the range of 1 to 5 mA.

[0003] Analog muxes are typically used to feed multiple inputs into a single ADC input. It is desirable that analog muxes be able to handle injected current when deactivated. Furthermore, it is desirable that analog muxes produce the lowest possible leakage current and noise coupling, as very accurate ADCs are often required in processing systems, such as microcontrollers and microprocessors implemented in systems-on-a-chip. Summary of the Invention

[0004] In some embodiments, an analog multiplexer (MUX) includes a plurality of branch circuits, each branch circuit being configured to receive a corresponding input signal and provide a corresponding output signal. A multiplexer (MUX) output is coupled to the plurality of branch circuits, wherein the MUX output is configured to provide the corresponding output signal provided by a selected branch circuit among the plurality of branch circuits as a MUX output signal. Each branch circuit includes: a first transistor of a first conduction type having a first current electrode configured to receive the corresponding input signal for the branch circuit, a second current electrode coupled to a circuit node, and a control electrode; a second transistor of the first conduction type having a first current electrode coupled to the circuit node, a second current electrode configured to provide the corresponding output signal, and a control electrode; and a transistor of the first conduction type... A third transistor of the opposite second conduction type has a first current electrode coupled to the circuit node, a second current electrode coupled to a first voltage supply terminal, and a control electrode, wherein the branch circuit is configured to turn on the third transistor and turn off the first transistor and the second transistor when the branch circuit is not selected, and the branch circuit is configured to turn off the third transistor and turn on the first transistor and the second transistor when the branch circuit is selected; and a switching circuit coupled between the base electrode of the third transistor and the circuit node, wherein the switching circuit is configured to turn on when the branch circuit is not selected and not turn on when the branch circuit is selected.

[0005] In other respects, the analog MUX may additionally include: a fourth transistor of the second conduction type, having a first current electrode coupled to the base electrode of the third transistor, a control electrode coupled to a second voltage supply terminal different from the first voltage supply terminal, and a second current electrode coupled to the first voltage supply terminal.

[0006] On the other hand, in each of the plurality of branch circuits: the control electrodes of the first transistor, the second transistor and the third transistor may each be coupled to receive an enable signal, which is asserted when the branch circuit is selected and denied when the branch circuit is not selected.

[0007] On the other hand, the first conduction type is N-type, and the first voltage supply terminal provides a first supply voltage that is greater than the second supply voltage provided by the second voltage supply terminal.

[0008] On the other hand, the enable signal can be implemented as a high-level active signal, such that the enable signal is asserted as logic high when the branch circuit is selected, and is denied as logic low when the branch circuit is not selected.

[0009] On the other hand, the first conduction type is P-type, and the first voltage supply terminal provides a first supply voltage that is lower than the second supply voltage provided by the second voltage supply terminal.

[0010] On the other hand, the enable signal is implemented as a low-level active signal, such that when the branch circuit is selected, the enable signal is asserted as a logic level low, and when the branch circuit is not selected, the enable signal is negated as a logic level high.

[0011] In another aspect, the switching circuit may include: a fourth transistor of a third conduction type having a first current electrode coupled to the base electrode of the third transistor, a second electrode coupled to the circuit node, and a control electrode coupled to receive the enable signal; and a fifth transistor of the opposite fourth conduction type, having a first current electrode coupled to the base electrode of the third transistor, a second electrode coupled to the circuit node, and an inverted control electrode for receiving the enable signal.

[0012] On the other hand, the corresponding input signal, the corresponding output signal, and the MUX output signal can be analog signals.

[0013] In another aspect, each of the plurality of branch circuits may further include: a fourth transistor of the second conduction type having a first current electrode coupled to receive the corresponding input signal for the branch circuit, a second current electrode coupled to the second circuit node, and a control electrode; and a fifth transistor of the second conduction type having a first current electrode coupled to the second circuit node, a second current electrode coupled to provide the corresponding output signal, and a control electrode; and a sixth transistor of the first conduction type having a first current electrode coupled to the second circuit node, a second current electrode coupled to the second voltage supply terminal, and a control electrode. The branch circuit may be configured to turn on the sixth transistor and turn off the fourth and fifth transistors when the branch circuit is not selected, and the branch circuit may be configured to turn off the sixth transistor and turn on the fourth and fifth transistors when the branch circuit is selected, and a second switching circuit is coupled between the base electrode of the sixth transistor and the second circuit node, wherein the second switching circuit is configured to be on when the branch circuit is not selected and off when the branch circuit is selected.

[0014] On the other hand, the analog MUX may further include a seventh transistor of the first conduction type, the seventh transistor having a first current electrode coupled to the base electrode of the sixth transistor, a control electrode coupled to the first voltage supply terminal, and a second current electrode coupled to the second voltage supply terminal.

[0015] On the other hand, in each of the plurality of branch circuits: the control electrodes of the first transistor, the second transistor, and the third transistor may each be coupled to receive an enable signal, which is asserted when the branch circuit is selected and negated when the branch circuit is not selected; and the control electrodes of the fourth transistor, the fifth transistor, and the sixth transistor are each coupled to receive the inverted version of the enable signal.

[0016] In other embodiments, a processing system may include: a processing element; a memory device coupled to the processing element; input / output (I / O) circuitry coupled to the processing element, the I / O circuitry including an analog multiplexer comprising: a plurality of branch circuits, each branch circuit configured to receive a corresponding input signal and provide a corresponding output signal; and a multiplexer output coupled to the plurality of branch circuits. The MUX output may be configured to provide the corresponding output signal provided by a selected branch circuit of the plurality of branch circuits as a MUX output signal, each branch circuit comprising: a first transistor of a first conduction type having a first current electrode configured to receive the corresponding input signal for the branch circuit, a second current electrode coupled to a circuit node, and a control electrode; a second transistor of the first conduction type having a first current electrode coupled to the circuit node, a second current electrode configured to provide the corresponding output signal, and a control electrode; and a third transistor of a second conduction type opposite to the first conduction type having a first current electrode coupled to the circuit node, a second current electrode coupled to a first voltage supply, and a control electrode. The control electrodes of the first, second, and third transistors may each be coupled to receive an enable signal, which is asserted when the branch circuit is selected and negated when the branch circuit is not selected. The analog multiplexer may further include: a fourth transistor of the second conduction type having a first current electrode coupled to the base electrode of the third transistor, a control electrode coupled to a second voltage supply terminal different from the first voltage supply terminal, and a second current electrode coupled to the first voltage supply terminal; and a switching circuit coupled between the base electrode of the third transistor and the circuit node, wherein the switching circuit is configured to conduct when the enable signal is negated and to deconduct when the enable signal is asserted.

[0017] In other aspects, the switching circuit may include: a fifth transistor of a third conduction type having a first current electrode coupled to the base electrode of the third transistor, a second electrode coupled to the circuit node, and a control electrode coupled to receive the enable signal; and a sixth transistor of a fourth conduction type opposite to the third conduction type, having a first current electrode coupled to the base electrode of the third transistor, a second electrode coupled to the circuit node, and an inverted control electrode for receiving the enable signal.

[0018] In another embodiment, an integrated circuit device may include: an analog multiplexer including a plurality of branch circuits, each branch circuit being configured to receive a corresponding input signal and provide a corresponding output signal; and a multiplexer (MUX) output coupled to the plurality of branch circuits. The MUX output may be configured to provide the corresponding output signal provided by a selected branch circuit among the plurality of branch circuits as a MUX output signal. Each branch circuit may include a pair of n-type transistors connected in series between a corresponding input and a corresponding output of the branch circuit via a first circuit node. The control electrode of each of the pair of n-type transistors may be coupled to receive an enable signal, which is asserted when the branch circuit is selected and negated when the branch circuit is not selected. A first p-type transistor may be coupled between the first circuit node and a first voltage supply terminal, wherein the control electrode of the first p-type transistor is coupled to receive the enable signal. A first switching circuit may be coupled between the first circuit node and the base electrode of the first p-type transistor, wherein the switching circuit is configured to conduct when the enable signal is negated and to deconduct when the enable signal is asserted. A pair of p-type transistors may be connected in series between the corresponding input and the corresponding output of the branch circuit via a second circuit node, wherein the control electrode of each of the pair of p-type transistors is coupled to receive the inverted enable signal. A first n-type transistor may be coupled between the second circuit node and a second voltage supply terminal, wherein the control electrode of the first n-type transistor is coupled to receive the inverted enable signal. A second switching circuit may be coupled between the second circuit node and the base electrode of the first n-type transistor, wherein the switching circuit is configured to conduct when the enable signal is denied and to deconduct when the enable signal is asserted.

[0019] In other aspects, the integrated circuit device may further include: a second p-type transistor coupled between the base electrode of the first p-type transistor and the first voltage supply terminal and having a control electrode coupled to the second voltage supply terminal, wherein the first voltage supply terminal is configured to provide a first supply voltage and the second voltage supply terminal is configured to provide a second supply voltage less than the first supply voltage; and a second n-type transistor coupled between the base electrode of the first n-type transistor and the second voltage supply terminal and having a control electrode coupled to the first voltage supply terminal.

[0020] In another aspect, the first switching circuit may include: a third p-type transistor coupled between the first circuit node and the base electrode of the first p-type transistor and having a control electrode coupled to receive the enable signal; and a third n-type transistor coupled in parallel with the second p-type transistor between the first circuit node and the base electrode of the first p-type transistor and having the inverted control electrode coupled to receive the enable signal.

[0021] In another aspect, the second switching circuit may include: a fourth p-type transistor coupled between the second circuit node and the base electrode of the first n-type transistor and having a control electrode coupled to receive the enable signal; and a fourth n-type transistor coupled in parallel with the third p-type transistor between the second circuit node and the base electrode of the first n-type transistor and having the inverted control electrode coupled to receive the enable signal.

[0022] On the other hand, the enable signal is implemented as a high-level active signal, such that when the branch circuit is selected, the enable signal is asserted as a logic level high, and when the branch circuit is not selected, the enable signal is negated as a logic level low.

[0023] On the other hand, the MUX output signal is provided to the analog-to-digital converter (ADC). Attached Figure Description

[0024] Further details, aspects, and embodiments of the invention will be described by way of example only with reference to the accompanying drawings. In the drawings, similar reference numerals are used to identify similar or functionally similar elements. Elements in the drawings are shown for simplicity and clarity and are not necessarily drawn to scale.

[0025] Figure 1 A simplified block diagram illustrating an embodiment of an analog multiplexer coupled to an analog-to-digital converter is shown.

[0026] Figure 2 Show Figure 1A simplified block diagram of an embodiment of the first branch of an analog multiplexer.

[0027] Figure 3 It shows where it can be used Figure 1 A block diagram of an embodiment of a processing system for analog multiplexers and analog-to-digital converters. Detailed Implementation

[0028] The analog multiplexer / anamux embodiments disclosed herein operate with low leakage and low noise coupling. Even in deactivated analog multiplexer branches, positive and negative current injections are handled using contesting well biasing. Contesting well biasing is applicable to hardening both N-type and P-type devices, protecting them from current injection. Contesting well biasing provides additional capability to discharge injected current in N-type devices and power the injection circuitry in P-type devices, while keeping the size of both N-type and P-type hardened devices relatively small.

[0029] Figure 1 A simplified block diagram of an embodiment of input circuitry 100 is shown, which includes an analog multiplexer 102 coupled to an analog-to-digital converter (ADC) 110. Analog multiplexer 102 may include one or more input branches 104, 106, 108, shown as IN0, IN1, ..., INn. A corresponding input branch, independent of the other input branches, can be enabled one at a time via an indexed enable signal EN(i). When a particular input branch is enabled, the output from the enabled input branch is provided as an input to ADC 110.

[0030] The ADC 110 is an integrated circuit that converts analog signals into digital signals. These digital signals can then be used by a digital processing system (not shown) that performs various processing functions in devices such as cellular phones, laptops, desktop computers, tablets, gaming systems, robotic industrial control systems, temperature control, power grid control, water and electricity control, advanced driver assistance systems, infotainment, connectivity, powertrain systems, braking systems, vehicle bodies, driver control, aircraft, electrical systems, and automotive processors for many other applications that may use embedded or non-embedded processing devices.

[0031] The ADC 110 can be implemented in various architectures, such as successive approximation, oversampling (sigma-delta), or pipeline, and can be selected based on the type of application or usage, speed, accuracy, linearity, resolution, supply voltage, and / or other parameters and performance factors.

[0032] Figure 2 Show Figure 1 A simplified block diagram of an embodiment of the input branch 104 of an analog multiplexer 102, the input branch 104 including P-type transistors 202, 204 and N-type transistors 230, 232 representing a transmission gate between input pad 234 and output pad 236. The input branch 104 of the analog multiplexer also includes protection circuits 206, 208, which are used when the input branch 104 of the analog multiplexer is not enabled to dissipate positive injection current or supply negative injection current, thereby preventing the injection current from affecting the ADC 110 (…). Figure 1 The operation of the analog multiplexer is as follows: When the input branch 104 of the analog multiplexer is enabled, the protection circuits 206 and 208 do not operate, and the input from the input branch 104 of the analog multiplexer is conducted from the input pad 234 to the output pad 236.

[0033] P-type transistor 202 includes a first current electrode coupled to input pad 234 and a second current electrode coupled to a grid point including nodes A and B and coupled to the first current electrode of P-type transistor 204. The second current electrode of P-type transistor 204 is coupled to output pad 236. The control gates of P-type transistors 202 and 204 are coupled to each other and to a complement of the enable signal for input branch 104 of the analog multiplexer, shown as ENb(0). The input branches 106 and 108 of the other analog multiplexers are coupled to a complement of their respective enable signals.

[0034] N-type transistor 230 includes a first current electrode coupled to input pad 234, a second current electrode coupled to a dot including nodes C and D, and a first current electrode of N-type transistor 232. The second current electrode of N-type transistor 230 is coupled to output pad 236. The control gates of N-type transistors 230 and 232 are coupled to each other and to an enable signal, shown as EN(0), for input branch 104 of the analog multiplexer. Input branches 106 and 108 of the other analog multiplexers are coupled to their respective enable signals.

[0035] Protection circuit 206 includes an N-type transistor 212, which includes a first current electrode coupled to node A, a second current electrode coupled to ground 220, and a supplementary control electrode coupled to an enable signal. P-type transistor 214 and N-type transistor 216 form a transmission gate 217. P-type transistor 214 includes a first current electrode coupled to the first current electrode of N-type transistor 216 and a second current electrode coupled to the second current electrode of N-type transistor 216. The control electrode of P-type transistor 214 is coupled to the enable signal EN(0), and the control electrode of N-type transistor 216 is coupled to a supplementary enable signal ENb(0). The first current electrodes of P-type transistor 214 and N-type transistor 216 are further coupled to the substrate of N-type transistor 212. The second current electrodes of P-type transistor 214 and N-type transistor 216 are further coupled to nodes A and B, the second current electrode of P-type transistor 202, and the first current electrode of P-type transistor 204.

[0036] N-type transistor 218 includes a first current electrode coupled to the base electrode of N-type transistor 212 and first current electrodes of P-type transistor 214 and N-type transistor 216. N-type transistor 218 further includes a second current electrode coupled to ground 220 and a control electrode coupled to the supply voltage VDDA.

[0037] Protection circuit 208 includes a P-type transistor 224, which includes a first current electrode coupled to node D, a second current electrode coupled to the supply voltage VDDA, and a control electrode coupled to an enable signal EN(0). P-type transistor 226 and N-type transistor 228 form a transmission gate 229. P-type transistor 226 includes a first current electrode coupled to the first current electrode of N-type transistor 228 and a second current electrode coupled to the second current electrode of N-type transistor 228. The control electrode of P-type transistor 226 is coupled to the enable signal EN(0), and the control electrode of N-type transistor 228 is coupled to a supplementary ENb(0) of the enable signal. The first current electrodes of P-type transistor 226 and N-type transistor 228 are further coupled to the base electrode of P-type transistor 224. The second current electrodes of P-type transistor 226 and N-type transistor 228 are further coupled to nodes C and D, the second current electrode of N-type transistor 230, and the first current electrode of N-type transistor 232.

[0038] P-type transistor 222 includes a base electrode first current electrode coupled to P-type transistor 224, and first current electrodes for P-type transistor 226 and N-type transistor 228. P-type transistor 222 also includes a second current electrode coupled to the supply voltage VDDA 210 and a control electrode coupled to ground.

[0039] N-type transistor 212 and P-type transistor 224 can be referred to as "hardened transistors" used for dissipating or supplying current injection. In analog multiplexer 102 ( Figure 1 During operation, with the input branch 104 of the analog multiplexer enabled (EN(0) asserted and ENb(0) deasserted), transmission gates 217 and 229 are turned off. The base electrode of N-type transistor 212 is attached to ground 220 by N-type transistor 218. The base electrode of P-type transistor 224 is attached to VDDA through P-type transistor 222 in conduction mode. Both N-type transistor 212 and P-type transistor 224 are turned off. With the input branch 104 of the analog multiplexer enabled, there is no current injection from the input branch 104 of the analog multiplexer during normal ADC conversion. Transmission gates 217 and 229 and transistors 218 and 222 allow transistors 212 and 224 to be smaller than the size required to remove injected current when the input branch 104 of the analog multiplexer is not enabled. The smaller transistors 212 and 224 produce lower leakage current, which improves the accuracy of ADC 110.

[0040] In current injection mode, input branch 104 of the analog multiplexer is disabled (EN(0) is de-asserted and ENb(0) is asserted) and transmission gates 217 and 229 are turned on. The base electrode of the hardened N-type transistor 212 remains attached to ground via N-type transistor 218 and is also connected to node A, which is pulled to ground via N-type transistor 212. The base electrode of the hardened P-type transistor 224 remains attached to the supply voltage VDDA via P-type transistor 222 and is also coupled to node D, which is pulled to VDDA via P-type transistor 224.

[0041] During positive current injection, the input voltage is a diode voltage (e.g., 0.7~0.8V) higher than the supply voltage VDDA. The injected current discharges to ground through P-type transistor 202 and N-type transistor 212. Due to the small size of N-type transistor 212, node A will be charged above ground, resulting in a decrease in the threshold voltage of N-type transistor 212 due to the body bias effect from transmission gate 217, and N-type transistor 212 being able to handle more channel current. However, the size of N-type transistor 212 may not be able to handle the injected current. Even with the threshold voltage offset, node A will rise further, and once node A is above the diode voltage, the body-source diode of N-type transistor 212 begins to conduct and is able to discharge the remaining injected current.

[0042] Once the injected current dissipates, the substrate of N-type transistor 212 is pulled back to ground through the always-on N-type transistor 218. Therefore, the 'competitive well bias' structure can handle the injected current. Furthermore, leakage is low due to the small size of N-type transistors 212, 218, and transmission gate 217.

[0043] During negative current injection, the input voltage can be lower than the diode voltage at ground 220 (0.7~0.8 V). The injected negative current originates from the supply voltage VDDA through N-type transistor 230 and P-type transistor 224. Due to the small size of P-type transistor 224, node D will discharge below the supply voltage VDDA. As a result, the threshold voltage of P-type transistor 224 will decrease due to the body bias effect, and P-type transistor 224 can handle more channel current. The size of P-type transistor 224 may not be able to handle the entire injected current even with the threshold voltage offset. To overcome this possibility, once the diode voltage at node D drops below the supply voltage VDDA, node D will drop further. At this time, the source-body diode of P-type transistor 224 will begin to conduct and supply the remaining injected current. Once the injected current dissipates, the body of P-type transistor 224 will be pulled back to the supply voltage VDDA through the always-on P-type transistor 222. Therefore, the 'competitive well bias' structure can handle the entire negative injected current. Furthermore, due to the small size of transistors 222, 228, and 224 in the protection circuit 208, the leakage current is low.

[0044] Figure 3 It shows where it can be used Figure 1 A block diagram of an embodiment of a processing system using an analog multiplexer / anamux and an analog-to-digital converter (ADC) 110. While processing system 300 is provided as an example using an analog multiplexer and ADC 110, the analog multiplexer and ADC 110 can be used in processing systems with other architectures and for other purposes.

[0045] Processing system 300 may include a hypervisor 304 and a host device 302 having two or more processors assigned to virtual machines 306, 308, 310, and 312. Each virtual machine 306 to 312 may include all or at least a portion of one or more processors in processor element 314, a memory device 316 storing boot and application software 318, and an input / output (I / O) circuitry system 320. Other components may be included in processing system 300.

[0046] Remote peripheral device 330 is coupled to interconnect 324. Each peripheral device can be assigned a domain identifier as a component of peripheral device subgroups 332-338, based on the domain in virtual machines 306-312 associated with the remote peripheral device 330. Domain assignments for components in virtual machines 306-312 and remote peripheral device 330 can be stored in memory 316 in one or more files (not shown) containing domain configuration information.

[0047] Parameters that can be transmitted between the master device 302 and the remote peripheral device 330 may include domain identifiers, peripheral device addresses, and access attributes such as security / non-security attributes and privileged / non-privileged attributes, requests for data or other information, and responses to requests. The interconnect 324 also routes requests and responses between virtual machines 306-312 and the remote peripheral device 330.

[0048] Hypervisor 304 can create one or more virtual machines 306-312 within processing system 300. Virtual machines 306-312 are private execution environments run by hypervisor 304 and are referred to as domains. Each domain can run a different operating system simultaneously on processing system 300. Hypervisor 304 can be implemented in hardware or in software that runs directly on hardware resources, such as processor element 314, memory 316, and input / output (I / O) circuitry system 320. One of the virtual machines 306-312 can be a control domain running a complete instance of an operating system, and other domains can run complete instances of operating systems that may be different from the operating systems running in the control domain or other guest domains. Hypervisor 304 partitions, shares, manages, and monitors hardware resources and acts as an interface between hardware resources and domains. Therefore, hypervisor 304 performs the low-level operations required to provide a virtualization platform. The control domain can perform all other tasks. For example, the control domain can determine which guest domains have been created, which resources each guest domain can access, and how much memory has been allocated to each guest domain. An example of a commercial product that can be used with Hypervisor 304 is COQOS from OpenSynergy, Inc., San Diego, California, USA. However, other suitable hypervisor products may also be used.

[0049] Hypervisor 304 may include a scheduler for scheduling domains onto processor element 314. Each domain, including control domains, includes one or more virtual processors that it owns and does not share with other domains. Hypervisor 304 may be integrated with or work in conjunction with a bootloader to assist in the creation of virtual machines 306-312 during boot. System firmware (not shown) may use the first processor element to start the bootloader. The bootloader may load domain configuration information, kernel image, and device tree from the boot partition in memory 316 of virtual machines 306-312.

[0050] Once the hypervisor 304 has configured virtual machines 308-312, it can then switch to hypervisor mode, initialize the hypervisor registers, and transfer control to the passenger kernel. On the control kernel, the hypervisor 304 can then perform the same operations on the passenger kernel running on it (i.e., initialize the passenger kernel's data structures, switch to hypervisor mode, initialize the hypervisor registers, and transfer control to the passenger kernel). After startup, the distinction between the primary and secondary kernels can be ignored, and the hypervisor 304 treats both kernels equally.

[0051] The main device 302 may be implemented using a system-on-a-chip (SoC) that includes multiple processing cores, referred to as a multi-core processor. For example, the main device 302 may be implemented using a SoC with an ARM architecture or any other architecture. In other embodiments, the main device 302 may include a multi-core processor that is not a system-on-a-chip to provide the same or similar environment. For example, the multi-core processor may be a general-purpose computing multi-core processor on a motherboard supporting multiple processing cores. In another embodiment, the main device 302 may be implemented using multiple networking processing cores. In one embodiment, the main device 302 may be implemented using a cloud computing architecture or other distributed computing architecture.

[0052] Processor element 314 is a virtualization element that may each include one or more processing cores to perform computational and general processing tasks, run application software 318, manage input / output (I / O) circuitry 320, run an operating system, etc. Note that individual processing cores may be shared among virtual machines 306-312, and each virtual machine 306-312 may use more than one processing core.

[0053] The domains associated with virtual machines 306-312 can be configured for various purposes. For example, in an automobile, the domain of virtual machine 306 can be used for the powertrain controller of a remote peripheral device, which may include an engine, transmission, brakes, battery management system, steering system, airbags, and shock absorbers. The domain of virtual machine 308 can be used for the body controller of a remote peripheral device, which may include HVAC, mirrors, interior lighting, doors, seats, steering wheel, sunroof, and windshield wipers. The domain of virtual machine 310 can be used for the cockpit controller of a remote peripheral device, which may include a touch display and voice recognition amplifier. The domain of virtual machine 312 can be used for the connectivity controller of a remote peripheral device, which may include vehicle-to-everything, broadcast radio, cellular, WiFi, Bluetooth, near-field communication, and smart car access components. Other domains and functions may be implemented in processing system 300 for other purposes, with the automotive domain being just one example.

[0054] In various embodiments, any number and / or type of domains (e.g., two domains, three domains, five domains, eight domains, sixteen domains, etc.) may be supported in addition to or instead of the four domains listed herein. In selected embodiments, two or more distinct operating system environments are provided (e.g., one per domain). Each operating system environment may be dedicated to a different core (or multiple cores) of a multi-core system-on-a-chip (SoC). Any number and / or type of operating environments may be provided and may be used in devices and equipment other than automotive applications.

[0055] The memory device 316 may include one or more random access memory (RAM) devices, such as a dual data rate (DDR) RAM module, a quad serial peripheral interface (QUADSPI) memory, a system-on-chip RAM module, an on-chip graphics RAM module, a boot read-only memory (ROM) module, and other suitable memory devices.

[0056] Application software 318 may be stored in memory 316 within the SoC or in a memory device external to the host device 302, and loaded into the internal memory device 316 during startup. Various types of application software 318 may be used depending on the functionality to be provided by the processing system 300. Using the automotive example described above, application software 318 may include various controllers for remote peripheral devices 330, such as powertrain domain controllers, body domain controllers, cockpit domain controllers, and connectivity domain controllers. Other types of application software 188 may be used in addition to or in place of automotive-related application software 318.

[0057] Input / output (I / O) circuitry 320 provides connectivity between virtual machines 306-312 and remote peripheral devices 330. I / O pins (not shown) are driven by pad drivers that provide logic level shifting, protection against potentially damaging electrostatic discharge, and amplification of internal signals to provide sufficient current drive for use outside the master device 302. Input / output (I / O) circuitry 320 typically includes pads or pins connected to corresponding input pull-up devices, electrostatic discharge protection devices, input buffers, level shifters, output drivers, and output pull-down devices. Analog multiplexer 102 or its input branch 104 and ADC 110 may be included in input / output (I / O) circuitry 320 to receive analog data from remote peripheral devices 330 and convert the analog data into digital data, which may then be processed by processor element 314 and stored in memory 316. Other components may be included in input / output (I / O) circuitry 320.

[0058] The input / output (I / O) circuitry 320 can be coupled directly or via a network interface card (not shown) to the interconnect 324. The connection between the input / output (I / O) circuitry 320, the interconnect 324, and the domain access control can be wired or wireless. Any suitable interconnect technology can be used. For wired networks, an example of a suitable interconnect technology is Ethernet, which allows multiple virtual machines 306-312 to communicate with a remote peripheral device 330, and can be implemented using Ethernet cables plugged into Ethernet switches, routers, hubs, bridges, etc. Messages sent to and from the interconnect 324 can conform to protocols suitable for the interconnect technology used. When using Ethernet, for example, data streams can be divided into frames or packets, also called messages, each including a source address and destination address, payload, and error checking, so that corrupted frames can be discarded and replacement frames retransmitted.

[0059] One or more remote peripheral devices 330 can send or receive data to or from portable media devices, data storage devices, servers, mobile phones, radios for AM, FM and digital or satellite broadcasting, etc., which are connected via connector hardware such as one or more USB connectors, FireWire connectors, Lightning connectors, or wireless communication connections that use infrared communication, Bluetooth communication, ZigBee communication, Wi-Fi communication, LAN and / or WLAN communication for data transmission.

[0060] For automotive applications, for example, one or more remote peripheral devices 330 may be connected to one or more local interconnect networks (LIN) and / or controller area networks (CAN) to allow communication between vehicle components. Vehicle sensors may be included in one or more such remote peripheral devices 330, such as gyroscopes, accelerometers, three-dimensional accelerometers, inclinometers, thermometers, etc. Other remote peripheral devices 330 may be used in addition to or in place of the remote peripheral devices 330 described herein.

[0061] It should now be understood that for processing systems and integrated circuits using multiple I / O inputs multiplexed into a single ADC channel, the analog multiplexer 102 can be used to support mux functions with smaller devices and lower leakage currents than previously possible. For example, if the ADC channel specifies a current injection of + / -3 mA, then at current injections below + / -3 mA, the MOS transistors may turn on / off earlier than the ESD bipolar device due to the lower threshold voltage of the I / O circuitry. In previous systems, the hardened transistors in the analog multiplexer had to be large enough to discharge the injected current. MOS drivers in the I / O cells also helped to discharge more than 50% of the injected current, but the analog input pads of the device under development may not include MOS output drivers. Therefore, the injected current is ideally fully discharged by the analog multiplexer 102. However, there are limitations on how large the size of the hardened device in the analog multiplexer can be without compromising the accuracy required by the ADC 110. The embodiment of the analog multiplexer 102 with protection circuits 206, 208 provides a novel competing well bias configuration to discharge the injected current without increasing the leakage current.

[0062] Because the embodiments of the invention shown can be implemented to a great extent using electronic components and circuits known to those skilled in the art, the details will not be explained to any greater extent than that shown above as necessary, in order to understand and learn the basic concepts of the invention and to avoid obscuring or distracting from the teachings of the invention.

[0063] In the foregoing description, the invention has been described with reference to specific examples of embodiments thereof. However, it will be apparent that various modifications and changes may be made to the description without departing from the broader spirit and scope of the invention as set forth in the appended claims.

[0064] As discussed herein, a connection can be any type of connection suitable for transmitting signals from or to a corresponding node, unit, or device, for example, via an intermediate means. Therefore, unless otherwise implied or stated, a connection can be, for example, a direct connection or an indirect connection. A connection can be shown or described as a single connection, multiple connections, a unidirectional connection, or a bidirectional connection. However, different embodiments can vary the implementation of the connection. For example, separate unidirectional connections can be used instead of bidirectional connections, and vice versa. Furthermore, a single connection that transmits multiple signals in a continuous or time-division multiplexing manner can be used instead of multiple connections. Similarly, a single connection carrying multiple signals can be divided into various different connections carrying subsets of those signals. Therefore, there are many options for transmitting signals.

[0065] Although the specific conduction type or polarity of the potential has been described in the examples, it should be understood that the conduction type and polarity of the potential are reversible.

[0066] Any arrangement of components that achieve the same functionality is effectively “associated” in order to achieve the desired functionality. Therefore, any two components combined in this document to achieve a particular functionality can be considered “associated” with each other in order to achieve the desired functionality, regardless of the architecture or intermediate components. Similarly, any two such associated components can also be considered “operably connected” or “operably coupled” with each other to achieve the desired functionality.

[0067] Furthermore, those skilled in the art should recognize that the boundaries between the operations described above are merely illustrative. Multiple operations may be combined into a single operation, a single operation may be distributed among additional operations, and the execution of operations may at least partially overlap in time. Additionally, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be modified in various other embodiments.

[0068] However, other modifications, variations, and alternatives are also possible. Therefore, the specification and drawings should be considered illustrative rather than restrictive.

[0069] The word 'comprising' does not exclude the presence of elements or steps other than those listed in the claims. Furthermore, as used herein, the terms "a" or "an" are defined as one or more. Moreover, the use of introductory phrases such as "at least one" and "one or more" in the claims should not be construed as implying that another claim element introduced by the indefinite article "a" or "an" limits any particular claim containing such an introduced claim element to an invention containing only one such element, even when the same claim includes the introductory phrase "one or more" or "at least one" and indefinite articles such as "a" or "an." The same applies to the use of definite articles. Unless otherwise stated, terms such as "first" and "second" are used to arbitrarily distinguish the elements described by such terms. Therefore, these terms are not necessarily intended to indicate temporal or other priorities of these elements. The mere fact that certain measures are recited in different claims does not imply that a combination of these measures cannot be used to gain an advantage.

Claims

1. An analog multiplexer (MUX), characterized in that, include: Multiple branch circuits, each configured to receive a corresponding input signal and provide a corresponding output signal; as well as A multiplexer MUX output coupled to the plurality of branch circuits, wherein the MUX output is configured to provide a corresponding output signal provided by a selected branch circuit among the plurality of branch circuits as a MUX output signal, each of the plurality of branch circuits comprising: A first transistor of a first conduction type has a first current electrode configured to receive the corresponding input signal for the branch circuit, a second current electrode coupled to a circuit node, and a control electrode. The second transistor of the first conduction type has a first current electrode coupled to the circuit node, a second current electrode configured to provide the corresponding output signal, and a control electrode. A third transistor of a second conduction type, opposite to the first conduction type, has a first current electrode coupled to the circuit node, a second current electrode coupled to a first voltage supply terminal, and a control electrode, wherein the branch circuit is configured to turn on the third transistor and turn off the first transistor and the second transistor when the branch circuit is not selected, and the branch circuit is configured to turn off the third transistor and turn on the first transistor and the second transistor when the branch circuit is selected. A switching circuit coupled between the base electrode of the third transistor and the circuit node, wherein the switching circuit is configured to be turned on when the branch circuit is not selected and not turned on when the branch circuit is selected.

2. The analog MUX according to claim 1, characterized in that, In each of the plurality of branch circuits: The control electrodes of the first transistor, the second transistor, and the third transistor are each coupled to receive an enable signal, which is asserted when the branch circuit is selected and denied when the branch circuit is not selected.

3. The analog MUX according to claim 2, characterized in that, The switching circuit includes: A fourth transistor of a third conduction type has a first current electrode coupled to the base electrode of the third transistor, a second electrode coupled to the circuit node, and a control electrode coupled to receive the enable signal; and A fifth transistor of a fourth conduction type, opposite to the third conduction type, has a first current electrode coupled to the base electrode of the third transistor, a second electrode coupled to the circuit node, and an inverted control electrode that receives the enable signal.

4. The analog MUX according to claim 1, characterized in that, Each of the plurality of branch circuits further includes: The fourth transistor of the second conduction type has a first current electrode coupled to receive the corresponding input signal for the branch circuit, a second current electrode coupled to the second circuit node, and a control electrode. The fifth transistor of the second conduction type has a first current electrode coupled to the second circuit node, a second current electrode coupled to provide the corresponding output signal, and a control electrode. The sixth transistor of the first conduction type has a first current electrode coupled to the second circuit node, a second current electrode coupled to the second voltage supply terminal, and a control electrode, wherein the branch circuit is configured to turn on the sixth transistor and turn off the fourth and fifth transistors when the branch circuit is not selected, and the branch circuit is configured to turn off the sixth transistor and turn on the fourth and fifth transistors when the branch circuit is selected. A second switching circuit is coupled between the base electrode of the sixth transistor and the second circuit node, wherein the second switching circuit is configured to be turned on when the branch circuit is not selected and not turned on when the branch circuit is selected.

5. A processing system, characterized in that, include: Processing components; A memory device coupled to the processing element; Input / output I / O circuitry coupled to the processing element, the I / O circuitry including an analog multiplexer, the analog multiplexer comprising: Multiple branch circuits, each configured to receive a corresponding input signal and provide a corresponding output signal; and A multiplexer output coupled to the plurality of branch circuits, wherein the multiplexer output is configured to provide a corresponding output signal provided by a selected branch circuit among the plurality of branch circuits as a multiplexer output signal, each of the plurality of branch circuits comprising: A first transistor of a first conduction type has a first current electrode configured to receive the corresponding input signal for the branch circuit, a second current electrode coupled to a circuit node, and a control electrode. The second transistor of the first conduction type has a first current electrode coupled to the circuit node, a second current electrode configured to provide the corresponding output signal, and a control electrode. A third transistor of a second conduction type, opposite to the first conduction type, has a first current electrode coupled to the circuit node, a second current electrode coupled to a first voltage supply terminal, and a control electrode, wherein the control electrodes of the first transistor, the second transistor, and the third transistor are each coupled to receive an enable signal, which is asserted when the branch circuit is selected and negated when the branch circuit is not selected. The fourth transistor of the second conduction type has a first current electrode coupled to the base electrode of the third transistor, a control electrode coupled to a second voltage supply terminal different from the first voltage supply terminal, and a second current electrode coupled to the first voltage supply terminal. A switching circuit coupled between the base electrode of the third transistor and the circuit node, wherein the switching circuit is configured to turn on when the enable signal is denied and to turn off when the enable signal is asserted.

6. The processing system according to claim 5, characterized in that, The switching circuit includes: A fifth transistor of a third conduction type has a first current electrode coupled to the base electrode of the third transistor, a second electrode coupled to the circuit node, and a control electrode coupled to receive the enable signal; and A sixth transistor of a fourth conduction type, opposite to the third conduction type, has a first current electrode coupled to the base electrode of the third transistor, a second electrode coupled to the circuit node, and an inverted control electrode that receives the enable signal.

7. An integrated circuit device, characterized in that, include: An analog multiplexer includes multiple branch circuits, each of which is configured to receive a corresponding input signal and provide a corresponding output signal; as well as A multiplexer MUX output coupled to the plurality of branch circuits, wherein the MUX output is configured to provide a corresponding output signal provided by a selected branch circuit among the plurality of branch circuits as a MUX output signal, each of the plurality of branch circuits comprising: A pair of n-type transistors are connected in series between corresponding inputs and corresponding outputs of the branch circuit via a first circuit node, wherein the control electrode of each of the pair of n-type transistors is coupled to receive an enable signal, the enable signal being asserted when the branch circuit is selected and denied when the branch circuit is not selected; A first p-type transistor is coupled between the first circuit node and the first voltage supply terminal, wherein the control electrode of the first p-type transistor is coupled to receive the enable signal; A first switching circuit is coupled between the first circuit node and the base electrode of the first p-type transistor, wherein the switching circuit is configured to turn on when the enable signal is denied and to turn off when the enable signal is asserted. A pair of p-type transistors are connected in series between the corresponding input and the corresponding output of the branch circuit via a second circuit node, wherein the control electrode of each of the pair of p-type transistors is coupled to receive the inverted enable signal; A first n-type transistor, coupled between the second circuit node and the second voltage supply terminal, wherein the control electrode of the first n-type transistor is coupled to receive the inverted enable signal; and A second switching circuit is coupled between the second circuit node and the base electrode of the first n-type transistor, wherein the switching circuit is configured to turn on when the enable signal is denied and to turn off when the enable signal is asserted.

8. The integrated circuit device according to claim 7, characterized in that, In addition, including: A second p-type transistor is coupled between the base electrode of the first p-type transistor and the first voltage supply terminal and has a control electrode coupled to the second voltage supply terminal, wherein the first voltage supply terminal is configured to provide a first supply voltage and the second voltage supply terminal is configured to provide a second supply voltage lower than the first supply voltage. as well as The second n-type transistor is coupled between the base electrode of the first n-type transistor and the second voltage supply terminal and has a control electrode coupled to the first voltage supply terminal.

9. The integrated circuit device according to claim 8, characterized in that, The first switching circuit includes: A third p-type transistor, coupled between the first circuit node and the base electrode of the first p-type transistor, and having a control electrode coupled to receive the enable signal; and A third n-type transistor is coupled in parallel with the second p-type transistor between the first circuit node and the base electrode of the first p-type transistor, and has an inverted control electrode coupled to receive the enable signal.

10. The integrated circuit device according to claim 8, characterized in that, The enable signal is implemented as a high-level active signal, such that when the branch circuit is selected, the enable signal is asserted as a logic level high, and when the branch circuit is not selected, the enable signal is negated as a logic level low.

Images