Signal selection circuit with feedback and light sensing distance chip

Abstract

The present application discloses a signal selection circuit with feedback and a light sensing distance chip. The signal selection circuit with feedback includes a quenching reset module, a selection mark module and a TDC unit. The circuit realizes enable signal feedback by utilizing selection mark units of different levels, thereby outputting the address number of the quenching reset unit itself. When the trigger signal of a quenching reset unit is 1, the signal output terminal signal of the selection mark unit connected to the quenching reset unit on the first layer is 1, and the signal is transmitted backward through the selection mark units of other layers, so that the signal output terminal signal of the selection mark unit of the last layer is 1; the selection mark unit of the last layer transmits the first enable input terminal signal forward through the selection mark units of other layers. When multiple quench units share a TDC unit, one of the quench units can be selected to output its own ID, thereby avoiding the use of MUX and improving chip area utilization.

Description

Technical Field

[0001] The present application relates to the technical field of optical distance measurement, and in particular to a signal selection circuit with feedback and an optical distance sensing chip. Background Art

[0002] Based on the dTOF (direct time off light, direct flight distance measurement) SPAD (Single Photon Avalanche Diode) ranging chip, when the SPAD receives a photon and an avalanche occurs, the avalanche process will be ended through the quenching reset circuit (quench circuit), and an avalanche pulse signal will be generated and sent to the TDC (Time to Digital Convert) circuit. The TDC circuit detects the received avalanche pulse signal within a fixed time, eliminates noise interference, and converts the time signal into a digital signal.

[0003] At present, considering the area and power consumption of the entire chip, multiple SPADs usually share a TDC circuit to complete the direct flight distance measurement of SPAD, and each SPAD unit is connected to a quenching reset unit. For simplicity, it can be expressed as multiple quenching reset units sharing one TDC unit. In order to determine which SPAD specifically receives the photon, the ID of its corresponding quench unit must be output during each detection process. Under normal circumstances, at a sampling moment, even if multiple quenching reset units are triggered, TDC can only process the trigger signal of one of the quenching reset units. When multiple quenching reset units are triggered at the same time or the triggering time interval is short, the output ID becomes very uncertain, that is, it is impossible to determine which quenching reset unit is triggered.

[0004] In the prior art, a signal multiple-selection method of a MUX (multiplexer, digital selector) circuit can be used to select a quenching reset unit from multiple quenching reset units to output its ID; however, a MUX circuit equivalent to the number of bits of the ID is required each time multiple selections are made. If the ID has 5 bits, at least 5 MUX circuits are required each time multiple selections are made, which occupies a large area of ​​the chip. Summary of the invention

[0005] In view of this, the embodiments of the present application provide a signal selection circuit with feedback and a light sensing distance chip to solve the problem of how to perform signal selection when multiple quenching reset units share a TDC unit without using a MUX circuit so as to reduce the chip area.

[0006] In a first aspect, an embodiment of the present application provides a signal selection circuit with feedback, the circuit comprising:

[0007] A quenching reset module, comprising N quenching reset units, each of which is used to output a trigger signal (trig), wherein N is an integer greater than 1;

[0008] A DCM (with selection mark) module, comprising M DCM units, wherein the DCM units are used to select signals for the quenching reset units, and the DCM units are arranged on different selection layers; when the trigger signal (trig) of one of the quenching reset units is 1, the signal output terminal signal (Q) of the DCM unit connected to the quenching reset unit on the first layer is 1, and the signal is transmitted backward through the DCM units of other layers, so that the signal output terminal signal (Q) of the DCM unit of the last layer is 1, and the first enable input terminal signal (EN1) of the DCM unit of the last layer is set to 1, and the DCM unit of the last layer transmits the first enable input terminal signal forward through the DCM units of other layers, so that the second enable input terminal signal (EN2) of one of the quenching reset units is 1, and M is an integer greater than 1, and M is less than N;

[0009] The quenching reset unit whose trigger signal (trig) is 1 is further configured to output its own (ID) address number after receiving a second enable input signal (EN2) of 1;

[0010] The TDC unit is used to receive the signal output end signal (Q) of the DCM unit of the last layer, and is also used to receive its own address number output by the quenching reset unit with a trigger signal (trig) of 1 after receiving the signal output end signal (Q) of 1, wherein the 1 represents that the signal is valid.

[0011] According to the aspects described above and any possible implementation, an implementation is further provided, in which the ratio of the number of the DCM units in the Lth layer to the number of the DCM units in the L+1th layer in the selection layer is 2 or 3.

[0012] According to the aspects described above and any possible implementation method, an implementation method is further provided, wherein the DCM unit of the first layer is used to select one of the two quenching reset units connected to it; the DCM unit of the second layer is used to select one of the two DCM units of the first layer connected to it; and so on, the DCM unit of the last layer is used to select one of the two DCM units of the second to last layer connected to it.

[0013] According to the above aspects and any possible implementation, an implementation is further provided, wherein each DCM unit comprises: a first signal input terminal, a second signal input terminal, and a signal output terminal; and further comprises: a first enable input terminal, and two second enable output terminals; the first signal input terminal and the corresponding second enable output terminal are both connected to a previous module; the second signal input terminal and the corresponding second enable output terminal are both connected to another previous module;

[0014] Among them, if the signal of one signal input terminal is 1 first, then the signal of the signal output terminal is 1; when the signal of the first enable input terminal is 1, the signal of the signal input terminal that is 1 first, its corresponding second enable output terminal signal is 1.

[0015] According to the above aspects and any possible implementation, an implementation is further provided, wherein each DCM unit comprises: a first signal input terminal, a second signal input terminal, and a signal output terminal; and further comprises: a first enable input terminal, and two second enable output terminals; the first signal input terminal and the corresponding second enable output terminal are both connected to a previous module; the second signal input terminal and the corresponding second enable output terminal are both connected to another previous module;

[0016] Among them, when the signals of the two signal input terminals are 1 at the same time, the signal output terminal signal is 1; when

[0017] When the first enable input terminal signal is 1, the two signal input terminal signals are 1 at the same time, which automatically selects a second enable output terminal signal and sets it to 1.

[0018] According to the above aspects and any possible implementation, there is further provided an implementation, wherein the DCM unit comprises 1 OR gate, 2 NAND gates, and 2 AND gates;

[0019] An OR gate, whose two inputs are connected to the two signal input terminals and whose output is connected to the signal output terminal;

[0020] A first NAND gate, one input of which is connected to the first signal input terminal, and the other input of which is connected to the output terminal of the second NAND gate;

[0021] The second NAND gate has one input connected to the second signal input terminal and another input connected to the output terminal of the first NAND gate;

[0022] A first AND gate, one input of which is connected to the output terminal of the first NAND gate, another input of which is connected to the first enable input terminal, and an output of which is connected to a second enable output terminal corresponding to the second signal input terminal;

[0023] The second AND gate has one input connected to the output terminal of the second NAND gate, another input connected to the first enable input terminal, and an output connected to the second enable output terminal corresponding to the first signal input terminal.

[0024] According to the above aspects and any possible implementation manner, there is further provided an implementation manner, wherein the DCM unit further includes a second OR gate connected in parallel with the first OR gate.

[0025] According to the above aspects and any possible implementation manner, there is further provided an implementation manner, wherein the circuit further includes:

[0026] 4 quenching reset units, used to output a trigger signal (trig);

[0027] Two first-stage selection marking units are respectively used to select the four connected quenching reset units, and when the trigger signal (trig) of one or more of the quenching reset units is 1, the signal output terminal signal (Q) of the first-stage DCM unit connected thereto is 1;

[0028] 1 second-stage DCM unit, used to select the two connected first-stage DCM units, when the signal output terminal signal (Q) of the first-stage DCM unit is 1, the signal output terminal signal (Q) of the second-stage DCM unit is 1, and when the signal output terminal signal (Q) is 1, the first enable input terminal signal (EN) of the second-stage DCM unit is 1;

[0029] The first-stage DCM unit whose signal output terminal signal is 1 is further used to receive the second-stage DCM unit whose output terminal signal is 1;

[0030] The quenching reset unit whose trigger signal (trig) is 1 is also used to receive the second enable output terminal signal whose output of the first-stage DCM unit is 1, and output its own address number;

[0031] The TDC unit is used to receive the signal output end signal (Q) of the second-level DCM unit, and is also used to receive its own address number output by the quenching reset unit with a trigger signal (trig) of 1 after receiving the signal output end signal (Q) with a signal of 1, wherein the 1 represents that the signal is valid.

[0032] According to the above aspects and any possible implementation manner, there is further provided an implementation manner, wherein the circuit further includes:

[0033] 8 quenching reset units, used to output the trigger signal (trig);

[0034] The four first-stage DCM units are respectively used to select the eight connected quenching reset units, and when the trigger signal (trig) of one or more of the quenching reset units is 1, the signal output terminal signal (Q) of the first-stage DCM unit connected thereto is 1;

[0035] Two second-stage DCM units are used to select the four connected first-stage DCM units, and when the signal output terminal signal (Q) of one or more of the first-stage DCM units is 1, the signal output terminal signal (Q) of one of the second-stage DCM units is 1;

[0036] 1 third-stage DCM unit, used to select the two connected second-stage DCM units, when the signal output terminal signal (Q) of one of the second-stage DCM units is 1, the signal output terminal signal (Q) of the third-stage DCM unit is 1, and when the signal output terminal signal (Q) is 1, the input terminal signal (EN) of the third-stage DCM unit is 1;

[0037] The second-stage DCM unit whose signal output terminal signal (Q) is 1 is also used to receive the second enable output terminal signal whose output of the third-stage DCM unit is 1;

[0038] The first-stage DCM unit whose signal output terminal signal (Q) is 1 is also used to receive the second enable output terminal signal whose output of the second-stage DCM unit is 1;

[0039] The quenching reset unit outputting the trigger signal (trig) is also used to receive the second enable output terminal signal of 1 output by the first-stage DCM unit, and output its own (ID) address number;

[0040] The TDC unit is used to receive the signal output end signal (Q) of the third-level DCM unit, and is also used to receive its own address number output by the quenching reset unit with a trigger signal (trig) of 1 after receiving the signal output end signal (Q) with a signal of 1, wherein the 1 represents that the signal is valid.

[0041] In a second aspect, an embodiment of the present application provides an optical sensing distance sensing chip, wherein the optical sensing distance sensing chip includes a signal selection circuit with feedback as described in the first aspect.

[0042] In the embodiment of the present application, a signal selection circuit with feedback is adopted, and signal feedback is realized by using DCM units of different levels, so that a quenching reset unit is selected from multiple quenching reset units to output its own address number. Among them, when the trigger signal of a quenching reset unit is 1, the signal output terminal signal of the DCM unit connected to the quenching reset unit on the first layer is 1, and the signal is transmitted backward through the DCM units of other layers, so that the signal output terminal signal of the DCM unit of the last layer is 1, and at this time, the first enable input terminal signal of the DCM unit of the last layer is 1; the DCM unit of the last layer transmits the first enable input terminal signal forward through the DCM units of other layers, so that the second enable input terminal signal of one of the quenching reset units is 1. In this way, when multiple quenching reset units share one TDC unit, that is, many to one, the ID of a quenching reset unit itself can be correctly selected and output, thereby improving the chip area utilization without using MUX. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0044] Figure 1 It is a schematic diagram of a 4-input circuit with labeled feedback in an embodiment of the present application;

[0045] Figure 2 It is a schematic diagram of an 8-input circuit with labeled feedback in an embodiment of the present application;

[0046] Figure 3 It is a circuit structure diagram of DCM. DETAILED DESCRIPTION

[0047] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0048] It should be clear that the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0049] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0050] It should be understood that the term "and / or" used in this article is only a description of the same field of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0051] It should be understood that, although the terms first, second, third, etc. may be used to describe preset ranges, etc. in the embodiments of the present application, these preset ranges should not be limited to these terms. These terms are only used to distinguish preset ranges from each other. For example, without departing from the scope of the embodiments of the present application, the first preset range may also be referred to as the second preset range, and similarly, the second preset range may also be referred to as the first preset range.

[0052] The word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrases "if it is determined" or "if (stated condition or event) is detected" may be interpreted as "when it is determined" or "in response to determining" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)", depending on the context.

[0053] The present application provides a signal selection circuit with feedback, the circuit comprising:

[0054] A quench reset module (quench module), comprising N quench reset units, each quench reset unit being used to output a trigger signal (trig), wherein N is an integer greater than 1;

[0055] In one embodiment, the quenching reset module is a collectively referred circuit module, which may specifically include a plurality of quenching reset units, each of which uniquely corresponds to a SPAD, that is, the SPAD can also be uniquely identified according to the ID of the quenching reset unit. When the SPAD receives a photon, the quenching reset unit corresponding to the SPAD sets the trigger signal to 1, and can pass the trigger signal of 1 to subsequent modules / units. It should be noted that in this application, signals of 1 are all considered valid signals.

[0056] A DCM (DecesionMark, selection mark) module includes M DCM units, and the DCM units are used to select signals for quenching reset units. The DCM units are arranged on different selection layers; when the trigger signal (trig) of a quenching reset unit is 1, the signal output terminal signal (Q) of the DCM unit connected to the quenching reset unit on the first layer is 1, and the signal is transmitted backward through the DCM units of other layers, so that the signal output terminal signal (Q) of the DCM unit of the last layer is 1, and the first enable input terminal signal (EN1) of the DCM unit of the last layer is set to 1, and the DCM unit of the last layer transmits the first enable input terminal signal forward through the DCM units of other layers, so that the second enable input terminal signal (EN2) of one of the quenching reset units is 1, M is an integer greater than 1, and M is less than N.

[0057] In one embodiment, the DCM module includes a plurality of DCM units located on different selection layers. The ratio of the number of DCM units in the first layer to the number of quenching reset units is 1:2 or 1:3. When the SPAD receives an optical signal, the trigger signal of the corresponding quenching reset unit is set to 1, and the trigger signal of 1 is sent to the DCM unit connected to the quenching reset unit.

[0058] After receiving the trigger signal with the signal being 1, the DCM unit at the first layer sets the signal output terminal signal of the DCM unit to 1, and transmits the signal output terminal signal of the DCM unit to the DCM units at the subsequent layers in sequence according to the connection relationship between the DCM units at the layers, so that the signal output terminal signal of the DCM units at the subsequent layers is set to 1. After receiving the signal 1 transmitted by the DCM unit at the second-to-last layer, the DCM unit at the last layer sets its own signal output terminal signal to 1, and sets the first enable input terminal signal of the DCM unit at the last layer to 1 according to the signal output terminal signal set to 1.

[0059] The DCM unit of the last layer transmits the first enable input terminal signal forward through the DCM units of other layers, selects a quenching reset unit according to the first enable input terminal signal, and sets the second enable input terminal signal of the quenching reset unit to 1. The first enable input terminal signal is a judgment node for initiating signal feedback selection. When the first enable input terminal signal is set to 1, the DCM unit will feed back the first enable input terminal signal with a signal of 1, so that the DCM unit of the previous layer can select a quenching reset unit as the ID output object according to the first enable input terminal signal.

[0060] It can be understood that the DCM module implements the function of marking feedback. Every time the SPAD is detected to generate a trigger signal of signal 1 in the quenching reset unit, it is equivalent to marking the quenching reset unit. The signal output end signal of the multi-level DCM unit is set to 1 by using the trigger signal of signal 1, and the first enable input end signal with a propagation signal of 1 is fed back by the last layer of DCM units, so that every time a trigger signal is generated, a quenching reset unit will be selected as the ID output object through the DCM module. Among them, the number of bits occupied by the first enable input end signal and the trigger signal are both 1, and the signal selection circuit with feedback only transmits according to the signal with the number of bits occupied by 1 each time, and only one quenching reset unit will be selected as the ID output object each time.

[0061] The quenching reset unit with a trigger signal (trig) of 1 is further configured to output its own (ID) address number after receiving a second enable input signal (EN2) of 1.

[0062] In one embodiment, after the signal is transmitted through the multi-level DCM units, the quenching reset unit with the trigger signal of 1 is generated, and finally receives a signal of 1, which can be called a second enable input terminal signal according to the function. The quenching reset unit will output the corresponding ID according to the received second enable input terminal signal.

[0063] It should be understood that in the present application, the effective signal transmitted by the signal selection circuit with feedback is 1, the signal itself occupies 1 bit, the signal is named only according to the function it implements in the circuit, there is no essential difference between signals with different names, and the information transmitted is 1.

[0064] The TDC unit is used to receive the signal output end signal (Q) of the DCM unit of the last layer, and is also used to receive its own address number output by the quenching reset unit with a trigger signal (trig) of 1 after receiving the signal output end signal (Q) of 1.

[0065] In one embodiment, the TDC unit may be connected to a plurality of quenching and resetting units. After receiving the signal from the signal output terminal of the last layer, the TDC unit will also receive the ID of a selected quenching and resetting unit through the feedback of the signal from the first enable input terminal.

[0066] Further, the ratio of the number of DCM units in the Lth layer to the number of DCM units in the L+1th layer in the selection layer is 2 or 3, and L is an integer greater than 0.

[0067] In one embodiment, a DCM unit can be configured to connect 2 or 3 quenching reset units. Then the DCM unit of the L+1th layer is also correspondingly connected to 2 or 3 DCM units of the Lth layer. It can be understood that the DCM units are arranged in a hierarchical relationship, and after each layer is added, the DCM units will be reduced proportionally until there is only one DCM unit left in the last layer. In this way, when multiple trigger signals are generated at the same time, the signal channel can be reduced to 1 and the first enable input terminal signal can be fed back one by one through the DCM units of the last layer, so that in the case of multiple trigger signals, the ID of the quenching reset unit can still be selected and output.

[0068] Furthermore, the DCM units of the first layer are used to select one of the two quenching reset units connected to them; the DCM units of the second layer are used to select one of the two DCM units of the first layer connected to them; and so on, the DCM units of the last layer are used to select one of the two DCM units of the second-to-last layer connected to them.

[0069] In one embodiment, the signal selection circuit with feedback in the present application can be specifically set as a two-choice selection circuit. With each subsequent layer, the number of DCM units is reduced by half, which is equivalent to taking only one of every two signals to enter the next layer after each DCM selection layer. In this way, when the DCM unit of the last layer feeds back the first enable input terminal signal, the quench with a trigger signal of 1 is marked when the DCM unit transmits it. Through this mark, the quench unit that is triggered first can be found, so the quench unit that is triggered first will output its ID number first. In this way, when the TDC unit is one-to-many quench units / SPADs, the ID of a triggered quench unit itself can be output with certainty, thereby improving the chip area utilization without using MUX.

[0070] Figure 1 This is a schematic diagram of a 4-input circuit with labeled feedback in one embodiment of the present application.

[0071] In the figure, 301, 302, 303, and 304 are quench units, each of which has at least one input terminal ID_EN, two output terminals ID_OUT, and a trigger signal trig, and the initial state of trig is 0. When ID_EN is 1, ID_OUT outputs its ID number. After the SPAD corresponding to the quench unit detects a photon, trig (trigger signal) is set to 1.

[0072] 305, 306, 307 are DCM units with tag feedback. Each DCM unit has at least three inputs A, B and EN, and three outputs A_EN, B_EN and Q. Their initial states are all 0. When one of A and B becomes 1, Q becomes 1. A_EN and / or B_EN will be output only when EN is 1. 308 is a TDC unit, which receives the output Q of 307 to convert the photon flight time.

[0073] In one embodiment, as long as one of the SPADs corresponding to the quench unit among 301, 302, 303, and 304 detects a photon, such as 301, the trig of 301 will become 1. After the input end A of 305 receives 1, the Q of 305 is also set to 1, and so on, the Q of 307 is also set to 1 accordingly.

[0074] When the Q terminal of 307 becomes 1, the EN of 307 can be set to 1 through the preset logic judgment unit, and then A_EN of 307 can output a signal to set EN of 305 to 1; after EN of 305 becomes 1, then the output terminal A_EN of 305 outputs 1 to ID_EN of 301, and 301 outputs its ID1.

[0075] from Figure 1 It can be seen that after any quench unit 301-304 sends a trig signal with a signal of 1, the signal 1 is transmitted layer by layer through a two-choice method, and in the DCM unit, the signal 1 is represented by Q until it is transmitted to the Q of the DCM unit 307 of the last layer, and EN is set to 1 according to the Q signal of 1, and A_EN or B_EN in 307 is selected according to the EN, and the signal is fed back to 305 or 306. Similarly, 301, 302, 303, and 304 use EN to select in the quench unit, and finally output the ID of a quench reset unit.

[0076] Furthermore, if more than two trig signals are triggered continuously within a time period, the feedback signal path will be selected in priority according to the triggering time of the trig signals. For example, if 301 and 302 trigger the trig signal of 1 in a short time interval, 307 will prioritize setting A_EN of 307 to 1 according to the EN signal of 1, and in 305, similarly, prioritize setting A_EN in 305 to 1, and then prioritize setting ID_EN in 301 to 1, so the quench unit of 301 is selected and outputs its ID number.

[0077] Furthermore, if more than two trig signals are triggered continuously within a time period, the feedback signal path can be preferentially selected according to the selection logic of the circuit itself. For example, if 301 and 302 simultaneously trigger a trig with a signal of 1, then since the trig triggers are both from 301 and 302 (belonging to the same selection path), 307 will select A_EN in 307. After the selection, in 305, A_EN or B_EN in 305 will be automatically selected and set to 1 according to the selection logic of the circuit itself, and ID1 or ID2 will be output accordingly. However, the above two methods ensure that only one quench will output an ID number when multiple quench units are triggered, so it is clear which quench unit the TDC is connected to at a certain moment.

[0078] Figure 2 This is a schematic diagram of an 8-input circuit with labeled feedback in an embodiment of the present application.

[0079] from Figure 2 As you can see, in fact Figure 2 of Figure 1 The only difference is the number of quench unit inputs. Each quench unit corresponds to two DCM units, and similarly, every two DCM units correspond to one DCM unit in the next level.

[0080] In one embodiment, when the trig of 8 quench units changes to 1 at the same time, the signal will be fed back after selecting one of the signals of the 3-level DCM units. In the feedback stage, the IDs of the 8 quench units are output in sequence according to the selection logic of the circuit itself. It can be understood that this application only focuses on whether the ID of the quench unit can be output one by one. As for which one comes first and which one comes later, when the trig is triggered at the same time, the circuit can make the selection by itself. This application only needs to ensure that one ID is output each time.

[0081] Figure 3 It is a circuit specific implementation structure diagram of the DCM unit.

[0082] like Figure 3As shown, 101 and 102 are both two-input OR gates, their two inputs are connected respectively, and their outputs are also connected together. The two inputs are from the outputs of two quenching reset units, marked as A and B, respectively. When one of the two inputs A and B is 1, the output Q is 1. It is also feasible to use one OR gate here. Using two OR gate inputs cross-connected can achieve the consistency of the signal delay of the two input ends. 103 and 104 are both two-input NAND gates, and 105 and 106 are two-input AND gates. One input of 103 comes from the output A of a quenching reset unit, and the output B of another quenching reset unit is connected to an input of 104; the other input terminal signal of 103 is connected to the output terminal signal of 104, and the output terminal signal of 103 is connected to an input terminal signal of 104; one input terminal signal of 105 and 106 is commonly connected to the external signal EN (first enable input terminal signal), the other input terminal signal of 105 is connected to the output of 103, and the other input terminal signal of 106 is connected to the output of 104; the output of 105 is B_EN, and the output of 106 is A_EN.

[0083] Figure 3 In the initial state, all input and output signals are reset to 0. According to the logic value table of the NAND gate, the initial values ​​of 201 and 202 are 1. Specifically, when A becomes 1, Q becomes 1, 201 is 0, 202 is 1, and when EN becomes 1, the output A_EN becomes 1 and B_EN remains 0. Even if A and B are triggered at the same time, that is, when inputs A and B are 1 at the same time, the output Q becomes 1. 201 and 202 will both become 1. Figure 3 From the structure of NAND gates 103 and 104 shown in the figure, it can be seen that the state where A, B, 201, and 202 are all 1 is an unstable state. After stabilization, only one of 201 and 202 must be 1 and the other is 0. Here, it is assumed that 201 is 1 and 202 is 0; when EN becomes 1, the output B_EN is 1 and A_EN remains 0, thus achieving the purpose of simultaneously triggering and outputting only one of the IDs.

[0084] In this application, since a small number of logic units are used and no MUX is used, the chip area can be effectively saved while ensuring that no data is wasted and the correct ID is output. The reusability of the DCM unit can also reduce the burden of design work.

[0085] It should be understood that other Figure 3 The deformation circuits of the DCM units have the same logic implementation but different logic units, and should all fall within the protection scope of this application.

[0086] In the embodiment of the present application, a signal selection circuit with feedback is adopted, and signal feedback is realized by using DCM units of different levels, so as to output the address number of the quench reset unit itself. Among them, when the trigger signal of a quench reset unit is 1, the signal output terminal signal of the DCM unit connected to the quench reset unit on the first layer is 1, and the signal is transmitted backward through the DCM units of other layers, so that the signal output terminal signal of the DCM unit of the last layer is 1, and the first enable input terminal signal of the DCM unit of the last layer is 1 at this time; the DCM unit of the last layer transmits the first enable input terminal signal forward through the DCM units of other layers, so that the second enable input terminal signal of one of the quench units is 1. In this way, when multiple quench units correspond to one TDC unit, one quench unit's own ID can be selected to be output, thereby avoiding the use of MUX and improving chip area utilization.

[0087] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0088] The embodiment of the present application also provides an optical sensing distance sensing chip, which includes the signal selection circuit with feedback of the above embodiment. Compared with the traditional optical sensing distance sensing chip, the chip area of ​​the optical sensing distance sensing chip is smaller.

[0089] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0090] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A signal selection circuit with feedback, characterized in that: include: A quenching reset module, comprising N quenching reset units, each of which is used to output a trigger signal, wherein N is an integer greater than 1; A selection mark module includes M selection mark units, wherein the selection mark units are used to select signals for the quenching reset units, and the selection mark units are arranged on different selection layers; when the trigger signal of one of the quenching reset units is 1, the signal output terminal signal of the selection mark unit connected to the quenching reset unit on the first layer is 1, and the signal is transmitted backward through the selection mark units of other layers, so that the signal output terminal signal of the selection mark unit of the last layer is 1, and the first enable input terminal signal of the selection mark unit of the last layer is set to 1, and the selection mark unit of the last layer transmits the first enable input terminal signal forward through the selection mark units of other layers, so that the second enable input terminal signal of one of the quenching reset units is 1, and M is an integer greater than 1, and M is less than N; The quenching reset unit whose trigger signal is 1 is further configured to output its own address number after receiving a second enable input signal of 1; The TDC unit is used to receive the signal output end signal of the selection mark unit of the last layer, and is also used to receive its own address number output by the quenching reset unit with a trigger signal of 1 after receiving the signal output end signal with a signal of 1, wherein the 1 represents that the signal is valid.

2. The circuit according to claim 1, characterized in that The ratio of the number of the selection marking units in the Lth layer to the number of the selection marking units in the L+1th layer in the selection layer is 2 or 3.

3. The circuit according to claim 1, characterized in that The selection marking units of the first layer are used to select one of the two quenching and resetting units connected to it; the selection marking units of the second layer are used to select one of the two selection marking units of the first layer connected to it; and so on, the selection marking units of the last layer are used to select one of the two selection marking units of the second to last layer connected to it.

4. The circuit according to claim 3, characterized in that Each selection mark unit includes: a first signal input terminal, a second signal input terminal, and a signal output terminal; and also includes: a first enable input terminal and two second enable output terminals; the first signal input terminal and the corresponding second enable output terminal are both connected to a previous module; the second signal input terminal and the corresponding second enable output terminal are both connected to another previous module; Among them, if the signal of one signal input terminal is 1 first, then the signal of the signal output terminal is 1; when the signal of the first enable input terminal is 1, the signal of the signal input terminal that is 1 first, its corresponding second enable output terminal signal is 1.

5. The circuit according to claim 3, characterized in that Each selection mark unit includes: a first signal input terminal, a second signal input terminal, and a signal output terminal; and also includes: a first enable input terminal and two second enable output terminals; the first signal input terminal and the corresponding second enable output terminal are both connected to a previous module; the second signal input terminal and the corresponding second enable output terminal are both connected to another previous module; Among them, when the signals of the two signal input terminals are 1 at the same time, the signal output terminal signal is 1; when the first enable input terminal signal is 1, the two signal input terminal signals are 1 at the same time, and it automatically selects a second enable output terminal signal and sets it to 1.

6. The circuit according to claim 4 or 5, characterized in that The selection marking unit includes 1 OR gate, 2 NAND gates, and 2 AND gates; An OR gate, whose two inputs are connected to the two signal input terminals and whose output is connected to the signal output terminal; A first NAND gate, one input of which is connected to the first signal input terminal, and the other input of which is connected to the output terminal of the second NAND gate; The second NAND gate has one input connected to the second signal input terminal and another input connected to the output terminal of the first NAND gate; A first AND gate, one input of which is connected to the output terminal of the first NAND gate, another input of which is connected to the first enable input terminal, and an output of which is connected to a second enable output terminal corresponding to the second signal input terminal; The second AND gate has one input connected to the output terminal of the second NAND gate, another input connected to the first enable input terminal, and an output connected to the second enable output terminal corresponding to the first signal input terminal.

7. The circuit according to claim 6, characterized in that The selection mark unit further includes a second OR gate connected in parallel with the first OR gate.

8. The circuit according to claim 1, characterized in that The circuit further comprises: The four quenching reset units are used to output a trigger signal; Two first-stage selection marking units are respectively used to select the four connected quenching reset units. When the trigger signal of one or more of the quenching reset units is 1, the signal output terminal signal of the first-stage selection marking unit connected thereto is 1; 1 second-level selection mark unit, used to select the two connected first-level selection mark units, when the signal output terminal signal of the first-level selection mark unit is 1, the signal output terminal signal of the second-level selection mark unit is 1, and when the signal output terminal signal is 1, the first enable input terminal signal of the second-level selection mark unit is 1; The first-stage selection mark unit whose signal output terminal signal is 1 is also used to receive the second-stage enable output terminal signal whose output is 1 of the second-stage selection mark unit; The quenching reset unit whose trigger signal is 1 is further used to receive the second enable output terminal signal whose output of the first-stage selection mark unit is 1, and output its own address number; The TDC unit is used to receive the signal output end signal of the second-level selection mark unit, and is also used to receive its own address number output by the quenching reset unit with a trigger signal of 1 after receiving the signal output end signal with a signal of 1, wherein the 1 represents that the signal is valid.

9. The circuit according to claim 1, characterized in that The circuit further comprises: 8 quenching reset units, used to output the trigger signal; The four first-stage selection marking units are respectively used to select the eight connected quenching reset units. When the trigger signal of one or more of the quenching reset units is 1, the signal output terminal signal of the first-stage selection marking unit connected thereto is 1; Two second-stage selection marking units are used to select the four connected first-stage selection marking units, and when the signal output terminal signal of one or more of the first-stage selection marking units is 1, the signal output terminal signal of one of the second-stage selection marking units is 1; 1 third-level selection marking unit, used to select the two connected second-level selection marking units, when the signal output terminal signal of one of the second-level selection marking units is 1, the signal output terminal signal of the third-level selection marking unit is 1, and when the signal output terminal signal is 1, the input terminal signal of the third-level selection marking unit is 1; The second-stage selection mark unit whose signal output terminal signal is 1 is further used to receive the second enable output terminal signal whose output of the third-stage selection mark unit is 1; The first-stage selection mark unit whose signal output terminal signal is 1 is also used to receive the second-stage enable output terminal signal whose output is 1 of the second-stage selection mark unit; The quenching reset unit outputting the trigger signal is further used to receive the second enable output terminal signal of 1 output by the first-stage selection mark unit, and output its own address number; The TDC unit is used to receive the signal output end signal of the third-level selection mark unit, and is also used to receive its own address number output by the quenching reset unit with a trigger signal of 1 after receiving the signal output end signal with a signal of 1, wherein the 1 represents that the signal is valid.

10. An optical sensing chip, characterized in that: The optical sensing distance chip comprises the signal selection circuit with feedback as described in any one of claims 1-9.

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