Display device

Abstract

A display device is provided. The display device includes: a substrate; a first bank structure and a second bank structure arranged to be spaced apart from each other on the substrate; a first electrode and a second electrode, the first electrode being arranged on the first bank structure and the second electrode being arranged on the second bank structure; and a light-emitting element arranged between the first electrode and the second electrode, wherein each of the first bank structure and the second bank structure includes a base layer, an upper layer arranged on the base layer, and an intermediate layer arranged between the base layer and the upper layer, and the first electrode and the second electrode are arranged to respectively cover the first bank structure and the second bank structure.

Description

Technical Field

[0001] The present invention relates to a display device. Background Art

[0002] The importance of display devices has been steadily increasing with the development of multimedia technology. In response, various types of display devices such as organic light-emitting displays and liquid crystal displays (LCDs) have been used.

[0003] A display device is a device for displaying images and includes a display panel such as an organic light-emitting display panel or a liquid crystal display panel. The light-emitting display panel may include a light-emitting element such as a light-emitting diode (LED), and examples of the light-emitting diode include an organic light-emitting diode (OLED) using an organic material as a fluorescent material and an inorganic light-emitting diode using an inorganic material as a fluorescent material. Summary of the Invention

[0004] Technical Problem

[0005] Aspects of the present disclosure provide a display device including an emission region in which a light-emitting element is disposed and a non-emission region in which a circuit element is disposed.

[0006] Aspects of the present disclosure also provide a display device that reduces the number of manufacturing processes of the display device by forming members disposed in the emission region and the non-emission region in the same process.

[0007] It should be noted that aspects of the present disclosure are not limited thereto, and other aspects not mentioned herein will be apparent to those of ordinary skill in the art from the following description.

[0008] Technical Solution

[0009] According to an embodiment of the present disclosure, a display device includes: a substrate; a first bank structure and a second bank structure disposed to be spaced apart from each other on the substrate; a first electrode disposed on the first bank structure and a second electrode disposed on the second bank structure; and a light-emitting element disposed between the first electrode and the second electrode, wherein each of the first bank structure and the second bank structure includes a base layer, an upper layer disposed on the base layer, and an intermediate layer disposed between the base layer and the upper layer, and the first electrode and the second electrode are disposed to respectively cover the first bank structure and the second bank structure.

[0010] An emission region and a non-emission region may be defined in the substrate, and the first bank structure, the second bank structure, and the light-emitting element may be disposed in the emission region.

[0011] The display device may further include a first transistor disposed in the non-emission region of the substrate, and including a first active material layer, a first gate electrode disposed on the first active material layer, and source / drain electrodes in contact with at least a partial region of the first active material layer, wherein the first gate electrode may be disposed at the same layer as the base layer of each of the first bank structure and the second bank structure.

[0012] The source / drain electrodes of the first transistor may be disposed at the same layer as the upper layer of each of the first bank structure and the second bank structure.

[0013] The first electrode may be at least partially disposed in the non-emission region, and a part of the first electrode disposed in the non-emission region may be in contact with the source / drain electrodes of the first transistor.

[0014] The display device may further include a third bank structure and a third electrode, the third bank structure being disposed in the emission region of the substrate and between the first bank structure and the second bank structure, and the third electrode being disposed on the third bank structure.

[0015] The light-emitting element may include a first light-emitting element disposed between the first bank structure and the third bank structure and a second light-emitting element disposed between the third bank structure and the second bank structure. The first light-emitting element may have one end electrically connected to the first electrode, and the second light-emitting element may have one end electrically connected to the second electrode.

[0016] The display device may further include a first planarization layer and an outer bank layer. The first planarization layer is disposed on the source / drain electrodes in the non-emission region, and the outer bank layer is disposed to surround the first bank structure and the second bank structure in the emission region.

[0017] The height from the upper surface of the substrate to the upper surface of the first planarization layer may be substantially the same as the height from the upper surface of the substrate to the upper surface of the outer bank layer.

[0018] The intermediate layer of each of the first bank structure and the second bank structure may be disposed to surround the outer surface of the base layer.

[0019] The upper layer may overlap at least a partial region of the base layer in the thickness direction, and the intermediate layer is between the upper layer and the base layer.

[0020] The display device may further include a first insulating layer disposed on at least a partial region of the first electrode and the second electrode, wherein the first insulating layer may be disposed so as not to overlap at least a partial region of a part of the first electrode disposed on the first bank structure.

[0021] The display device may further include a second insulating layer provided on at least a partial region of the first insulating layer, wherein the second insulating layer may be provided such that a portion of the first electrode that does not overlap with the first insulating layer is exposed.

[0022] The light-emitting element may be provided on the first insulating layer, and at least a portion of the second insulating layer may be provided on the light-emitting element and provided such that both ends of the light-emitting element are exposed.

[0023] The display device may further include a first contact electrode provided on the first electrode and a second contact electrode provided on the second electrode, wherein the first contact electrode may be in direct contact with a portion of the first electrode that does not overlap with the first insulating layer and the second insulating layer and in direct contact with one of the exposed ends of the light-emitting element.

[0024] According to an embodiment of the present disclosure, a display device includes: a substrate in which an emission region and a non-emission region are defined; a semiconductor layer provided in the non-emission region of the substrate and including a first active material layer of a first transistor; a first gate insulating layer provided on the substrate and the semiconductor layer; a first gate conductive layer provided on the first gate insulating layer and including a first gate electrode of the first transistor provided in the non-emission region and a plurality of base layers provided in the emission region; an interlayer insulating layer including a first interlayer insulating layer provided on the first gate electrode and a plurality of intermediate layers provided to cover the plurality of base layers; a first data conductive layer including source / drain electrodes of the first transistor provided on the first interlayer insulating layer and a plurality of upper layers provided on the plurality of intermediate layers; a plurality of electrodes having at least partial regions provided on the upper layers, spaced apart from each other, and facing each other; and at least one light-emitting element provided between the plurality of electrodes.

[0025] The base layers may include a first base layer and a second base layer provided to be spaced apart from each other, the intermediate layers may include a first intermediate layer provided to cover the first base layer and a second intermediate layer provided to cover the second base layer, and the upper layers may include a first upper layer provided on the first intermediate layer and a second upper layer provided on the second intermediate layer.

[0026] The electrodes may include a first electrode and a second electrode, the first electrode is provided on the first upper layer and provided to cover the first base layer and the first intermediate layer, the second electrode is provided on the second upper layer and provided to cover the second base layer and the second intermediate layer, and the light-emitting element may be electrically connected to the first electrode and the second electrode.

[0027] The display device may further include a first contact electrode provided on the first electrode and a second contact electrode provided on the second electrode, the first contact electrode may be in direct contact with the first electrode and one end of the light-emitting element, and the second contact electrode may be in direct contact with the second electrode and the other end of the light-emitting element.

[0028] The first electrode may be at least partially disposed in the non-emission region, and a portion of the first electrode disposed in the non-emission region is in contact with the source / drain electrode of the first transistor.

[0029] The display device may further include a first insulating layer disposed to cover at least a portion of the first electrode and the second electrode, wherein the light-emitting element may be disposed on the first insulating layer.

[0030] The display device may further include a second insulating layer disposed on at least a portion of the first insulating layer, wherein at least a portion of the second insulating layer may be disposed on the light-emitting element and is disposed such that both ends of the light-emitting element are exposed.

[0031] The display device may further include a planarization layer disposed on the first data conductive layer, wherein the planarization layer may include a first planarization layer disposed to overlap with the non-emission region and an outer dike layer disposed to surround the periphery of the emission region.

[0032] Details of other embodiments are included in the detailed description and the drawings.

[0033] Advantageous Effects

[0034] The display device according to an embodiment may include a dike structure, which includes a base layer and an upper layer formed at the same layer as the gate conductive layer and the data conductive layer disposed in the non-emission region. The dike structure may be disposed in the emission region to form a region in which the light-emitting element is disposed.

[0035] According to an embodiment, the number of manufacturing processes of the display device may be reduced by forming the dike structure disposed in the emission region in the same process as the circuit elements or wirings in the non-emission region.

[0036] The effects according to the embodiments are not limited to the content illustrated above, and more various effects are included in the present disclosure. Brief Description of the Drawings

[0037] Figure 1 is a plan view of a display device according to an embodiment;

[0038] Figure 2 is a schematic plan view showing wirings included in a display device according to an embodiment;

[0039] Figure 3 is an equivalent circuit diagram of one pixel included in a display device according to an embodiment;

[0040] Figure 4 is a layout diagram of one pixel of a display device according to an embodiment;

[0041] Figure 5 is a layout diagram of a sub-pixel shown Figure 4 thereof;

[0042] Figure 6 is a cross-sectional view taken along Figure 4 lines I-I' and II-II' thereof;

[0043] Figure 7 is a schematic diagram of a light-emitting element according to an embodiment;

[0044] Figures 8 to 15 is a cross-sectional view showing some of the manufacturing processes of a display device according to an embodiment;

[0045] Figure 16 is a plan view showing a step of the manufacturing process of a display device according to an embodiment;

[0046] Figures 17 to 19 is a cross-sectional view showing other processes in the manufacturing process of a display device according to an embodiment;

[0047] Figure 20 is a cross-sectional view of a display device according to another embodiment;

[0048] Figure 21 is a layout diagram of a pixel of a display device according to another embodiment;

[0049] Figure 22 is a cross-sectional view showing Figure 21 a part of the display device thereof;

[0050] Figure 23 is a layout diagram of a pixel of a display device according to another embodiment;

[0051] Figure 24 is a layout diagram of a pixel of a display device according to another embodiment;

[0052] Figure 25 is a cross-sectional view showing Figure 24 a part of the display device thereof;

[0053] Figure 26 is a layout diagram of a pixel of a display device according to another embodiment; and

[0054] Figure 27 is a cross-sectional view showing Figure 26 a part of the display device thereof. Detailed Description

[0055] The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0056] It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or an intervening layer may also be present. Throughout the specification, the same reference numerals denote the same components.

[0057] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the teachings of the present invention, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0058] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0059] Figure 1 is a schematic plan view of a display device according to an embodiment.

[0060] Reference Figure 1 , the display device 10 displays moving images or still images. The display device 10 may refer to all electronic devices that provide a display screen. For example, the display device 10 may include a television, a laptop computer, a monitor, a billboard, an Internet of Things (IoT) device, a mobile phone, a smartphone, a tablet personal computer (PC), an electronic watch, a smart watch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic notebook, an e-book, a portable multimedia player (PMP), a navigation device, a game console, a digital camera, a video camera, etc. that provide a display screen.

[0061] The display device 10 includes a display panel that provides a display screen. Examples of the display panel may include a light emitting diode (LED) display panel, an organic light emitting display panel, a quantum dot light emitting display panel, a plasma display panel, a field emission display panel, etc. Hereinafter, a case where an LED display panel is applied as an example of the display panel will be described by way of example, but the present disclosure is not limited thereto, and the same technical idea can be applied to other display panels if applicable.

[0062] The shape of the display device 10 can be modified differently. For example, the display device 10 can have shapes such as: a rectangular shape with a width greater than the length, a rectangular shape with a length greater than the width, a square shape, a rectangular shape with rounded corners (vertices), other polygonal shapes, or a circular shape. The shape of the display area DPA of the display device 10 can also be similar to the overall shape of the display device 10. In Figure 1 a display area DPA having a rectangular shape with a width greater than the length and the display device 10 are shown.

[0063] The display device 10 can include a display area DPA and a non-display area NDA. The display area DPA is an area where an image can be displayed, and the non-display area NDA is an area where no image is displayed. The display area DPA can also be referred to as an effective area, and the non-display area NDA can also be referred to as a non-effective area. The display area DPA can substantially occupy the center of the display device 10.

[0064] The display area DPA can include a plurality of pixels PX. The plurality of pixels PX can be arranged in a matrix form. In a plan view, the shape of each pixel PX can be a rectangular shape or a square shape, but is not limited thereto, and can also be a rhombus shape in which each side thereof is inclined with respect to one direction. The corresponding pixels PX can be alternately arranged in a stripe type or a pentile type. In addition, each of the pixels PX can include one or more light-emitting elements 300 that emit light in a specific wavelength band to display a specific color (see Figure 4 ).

[0065] The non-display area NDA can be provided around the display area DPA. The non-display area NDA can completely or partially surround the display area DPA. The display area DPA can have a rectangular shape, and the non-display area NDA can be provided adjacent to the four sides of the display area DPA. The non-display area NDA can constitute a border of the display device 10.

[0066] Figure 2 is a schematic plan view showing wirings included in a display device according to an embodiment.

[0067] Referring to Figure 2 , the display device 10 can include a plurality of wirings. The plurality of wirings can include scan lines SCL, sense lines SSL, data lines DTL, reference voltage lines RVL, and first voltage lines VDDL. In addition, although not shown in Figure 2 , the plurality of wirings can also include second voltage lines VSSL (see Figure 3 ).

[0068] The scan line SCL and the sense line SSL may extend in a first direction DR1. The scan line SCL and the sense line SSL may be connected to a scan driver SDR. The scan driver SDR may include a driving circuit. In the non-display area NDA, the scan driver SDR may be disposed on the other side of the display area DPA in the first direction DR1, for example, on the left side of the display area DPA, but not limited thereto. The scan driver SDR may be connected to a signal connection wiring CWL, and at least one end of the signal connection wiring CWL may be connected to an external device by forming a pad WPD_CW in the non-display area NDA.

[0069] The data line DTL and the reference voltage line RVL may extend in a second direction DR2 that intersects the first direction DR1. The first voltage line VDDL may include a portion extending in the second direction DR2. In addition, the first voltage line VDDL may further include a portion extending in the first direction DR1. Thus, the first voltage line VDDL may have a mesh structure, but not limited thereto. Although not shown in the drawings, similar to the first voltage line VDDL, the second voltage line VSSL may also include a portion extending in the second direction DR2 and a portion extending in the first direction DR1.

[0070] A wiring pad WPD may be provided at at least one end of the data line DTL, the reference voltage line RVL, and the first voltage line VDDL. Each wiring pad WPD may be provided in the non-display area NDA. In an embodiment, a wiring pad WPD_DT (hereinafter referred to as a "data pad") of the data line DTL may be provided in the non-display area NDA located on the lower side of the display area DPA, and the lower side of the display area DPA is the other side of the display area DPA in the second direction DR2, and a wiring pad WPD_RV (hereinafter referred to as a "reference voltage pad") of the reference voltage line RVL and a wiring pad WPD_VDD (hereinafter referred to as a "first power pad") of the first voltage line VDDL may be provided in the non-display area NDA located on the upper side of the display area DPA, and the upper side of the display area DPA is one side of the display area DPA in the second direction DR2. As another example, all the data pads WPD_DT, the reference voltage pads WPD_RV, and the first power pads WPD_VDD may be provided in the same area, for example, in the non-display area NDA located on the upper side of the display area DPA. As described above, an external device may be mounted on the wiring pad WPD. The external device may be mounted on the wiring pad WPD by an anisotropic conductive film, ultrasonic bonding, etc.

[0071] Each pixel PX of the display device 10 includes a pixel driving circuit. The above-described wiring can apply a driving signal to the corresponding pixel driving circuit when passing through or surrounding the corresponding pixel PX. The pixel driving circuit can include transistors and capacitors. The number of transistors and capacitors in each pixel driving circuit can be modified differently. Hereinafter, the pixel driving circuit will be described as an example using a 3T1C structure in which the pixel driving circuit includes three transistors and one capacitor, but the present disclosure is not limited thereto, and various other modified structures of the pixel PX, such as a 2T1C structure, a 7T1C structure, and a 6T1C structure, can also be applied.

[0072] Figure 3 is an equivalent circuit diagram of one pixel included in a display device according to an embodiment.

[0073] Refer to Figure 3 , in addition to the light-emitting element EL, each pixel PX of the display device 10 according to an embodiment further includes three transistors TR1, TR2, and TR3 and one storage capacitor Cst.

[0074] The light-emitting element EL emits light according to the current supplied through the first transistor TR1. A detailed description of the light-emitting element EL will be provided later.

[0075] One end of the light-emitting element EL can be connected to the first source / drain electrode of the first transistor TR1, and the other end of the light-emitting element EL can be connected to the second voltage line VSSL, to which a low-potential voltage (second source voltage) lower than the high-potential voltage (first source voltage) of the first voltage line VDDL is supplied.

[0076] The first transistor TR1 adjusts the current flowing from the first voltage line VDDL to the light-emitting element EL according to the voltage difference between its gate electrode and source electrode, where the first source voltage is supplied to the first voltage line VDDL. The gate electrode of the first transistor TR1 can be connected to the first source / drain electrode of the second transistor TR2, the first source / drain electrode of the first transistor TR1 can be connected to the first electrode of the light-emitting element EL, and the second source / drain electrode of the first transistor TR1 can be connected to the first voltage line VDDL to which the first source voltage is applied.

[0077] The second transistor TR2 is turned on by the scan signal of the scan line SCL to connect the data line DTL to the gate electrode of the first transistor TR1. The gate electrode of the second transistor TR2 can be connected to the scan line SCL, the first source / drain electrode of the second transistor TR2 can be connected to the gate electrode of the first transistor TR1, and the second source / drain electrode of the second transistor TR2 can be connected to the data line DTL.

[0078] The third transistor TR3 is turned on by the sensing signal of the sensing line SSL to connect the reference voltage line RVL to the first source / drain electrode of the first transistor TR1. The gate electrode of the third transistor TR3 may be connected to the sensing line SSL, the first source / drain electrode of the third transistor TR3 may be connected to the reference voltage line RVL, and the second source / drain electrode of the third transistor TR3 may be connected to the first source / drain electrode of the first transistor TR1.

[0079] In an embodiment, the first source / drain electrode of each of the first transistor TR1, the second transistor TR2, and the third transistor TR3 may be a source electrode, and the second source / drain electrode of each of the first transistor TR1, the second transistor TR2, and the third transistor TR3 may be a drain electrode, but the present disclosure is not limited thereto, and vice versa.

[0080] A storage capacitor Cst is formed between the gate electrode and the first source / drain electrode of the first transistor TR1. The storage capacitor Cst stores the differential voltage between the gate voltage and the first source / drain voltage of the first transistor TR1.

[0081] In addition, each of the first transistor TR1, the second transistor TR2, and the third transistor TR3 may be formed as a thin film transistor. In addition, Figure 3 it is mainly described that each of the first transistor TR1, the second transistor TR2, and the third transistor TR3 is formed as an N-type metal oxide semiconductor field effect transistor (MOSFET), but the present disclosure is not limited thereto. That is, each of the first transistor TR1, the second transistor TR2, and the third transistor TR3 may be formed as a P-type MOSFET, or some of the first transistor TR1, the second transistor TR2, and the third transistor TR3 may be formed as N-type MOSFETs, and the other transistors of the first transistor TR1, the second transistor TR2, and the third transistor TR3 may be formed as P-type MOSFETs.

[0082] Hereinafter, the structure of one pixel PX of the display device 10 according to an embodiment will be described in detail with reference to other drawings.

[0083] Figure 4 is a layout diagram showing one pixel of a display device according to an embodiment.

[0084] Reference Figure 4, each of the plurality of pixels PX may include a first sub-pixel PX1, a second sub-pixel PX2, and a third sub-pixel PX3. The first sub-pixel PX1 may emit light of a first color, the second sub-pixel PX2 may emit light of a second color, and the third sub-pixel PX3 may emit light of a third color. The first color may be blue, the second color may be green, and the third color may be red. However, the present disclosure is not limited thereto, and the corresponding sub-pixels PXn (n is a positive integer) may also emit light of the same color. Additionally, it has been shown in Figure 4 that the pixel PX includes three sub-pixels PXn, but the present disclosure is not limited thereto, and the pixel PX may include a greater number of sub-pixels PXn.

[0085] Furthermore, each of the pixels PX of the display device 10 may include an emission area EMA and a non-emission area NEA. The first sub-pixel PX1 may include a first emission area EMA1 and a first non-emission area NEA1, the second sub-pixel PX2 may include a second emission area EMA2 and a second non-emission area NEA2, and the third sub-pixel PX3 may include a third emission area EMA3 and a third non-emission area NEA3. The emission area EMA may be defined as the area where the light emitted from the light-emitting element 300 provided in each pixel PX is emitted. As described later, the light-emitting element 300 includes an active layer 330 (see Figure 7 ), and the active layer 330 may emit light of a specific wavelength band in a non-directional manner. The light emitted from the active layer 330 of the light-emitting element 300 may be emitted in the lateral direction of the light-emitting element 300 and in the direction toward both ends of the light-emitting element 300. The emission area EMA of each sub-pixel PXn may include the area where the light-emitting element 300 is provided, and include the area adjacent to the light-emitting element 300 and where the light emitted from the light-emitting element 300 is emitted. Furthermore, the present disclosure is not limited thereto, and the emission area EMA may also include the area where the light emitted from the light-emitting element 300 is reflected or refracted by other members and then emitted.

[0086] Each pixel PX or sub-pixel PXn includes a pixel driving circuit, and the pixel driving circuit can be disposed in the non-emission area NEA of each pixel PX or sub-pixel PXn. That is, the non-emission area NEA can be an area in which circuit elements or a plurality of wirings constituting the pixel driving circuit of each pixel PX or sub-pixel PXn are disposed. In addition, the non-emission area NEA can be an area other than the emission area EMA, and can be an area where the light emitted from the light-emitting element 300 does not reach and thus light is not emitted. In the display device 10 according to the embodiment, the light-emitting element 300 that emits light and the circuit elements for driving the light-emitting element 300 can be disposed in different areas, for example, disposed in the emission area EMA and the non-emission area NEA, and can not overlap with each other in the thickness direction. Therefore, the display device 10 can emit light to the upper surface or the rear surface of the area where the light-emitting element 300 is disposed. In addition, as will be described later, the bank structures 410 and 420 (see Figure 4 ) that provide the area where the light-emitting element 300 is disposed can be formed in the same process as the circuit elements or wirings in the non-emission area NEA, and the number of manufacturing processes of the display device 10 can be reduced.

[0087] Hereinafter, the arrangement of components included in each pixel PX or sub-pixel PXn will be described in more detail with reference to other drawings.

[0088] Figure 5 is a layout diagram showing Figure 4 one sub-pixel. Figure 6 is a cross-sectional view taken along line I-I' and line II-II' of Figure 4 . In Figure 5 , for ease of explanation, the outer bank layer 450 (see Figure 4 ) and the first planarization layer 180 (see Figure 4 ) provided in each sub-pixel PXn are omitted. Figure 6 The portion indicated by line I-I' of Figure 6 is a cross-section of a part of the non-emission area NEA of each sub-pixel PXn, and

[0089] The portion indicated by line II-II' of Figure 4 is a cross-section of a part of the emission area EMA of each sub-pixel PXn.

[0089] In addition to Figure 4 refer to Figure 5 and Figure 6, each pixel PX or sub-pixel PXn of the display device 10 may include a first substrate 110 and a semiconductor layer, a plurality of conductive layers, and a plurality of insulating layers disposed on the first substrate 110. The plurality of conductive layers may include a first gate conductive layer, a first data conductive layer, an electrode, and a contact electrode, and the plurality of insulating layers may include a buffer layer 115, a first gate insulating layer 130, a first passivation layer 150, a first interlayer insulating layer 170, a first planarization layer 180, a first insulating layer 510, a second insulating layer 520, a third insulating layer 530, and a fourth insulating layer 550. The semiconductor layer and the plurality of conductive layers may form the transistors TR1, TR2, and TR3 of each pixel PX, the storage capacitor Cst, a plurality of signal lines, or voltage lines, etc. described above with reference to Figure 3 The cross-section of the first transistor TR1 of the circuit elements disposed in the non-emission region NEA is only shown. The description of the other transistors (e.g., the second transistor TR2 and the third transistor TR3) of each sub-pixel PXn will be omitted. Figure 6

[0090] First, the first substrate 110 may be an insulating substrate. The first substrate 110 may be made of an insulating material such as glass, quartz, or a polymer resin. In addition, the first substrate 110 may be a rigid substrate, but may also be a flexible substrate that can be bent, folded, or curled. The emission region EMA and the non-emission region NEA may be defined in the first substrate 110, the light-emitting element 300 may be disposed in the emission region EMA of the first substrate 110, and the first transistor TR1, etc. may be disposed in the non-emission region NEA of the first substrate 110 as circuit elements.

[0091] The first light-blocking layer BML1 may be disposed on the first substrate 110. The first light-blocking layer BML1 may be disposed in the non-emission region NEA of the first substrate 110 and may be disposed to overlap a part of the first active material layer ACT1 of the first transistor TR1 to be described later. The first light-blocking layer BML1 may include a light-blocking material to prevent light from incident on the first active material layer ACT1. As an example, the first light-blocking layer BML1 may be formed of an opaque metal material that blocks light transmission. However, the present disclosure is not limited thereto, and in some cases, the first light-blocking layer BML1 may be omitted.

[0092] The buffer layer 115 is disposed on the first substrate 110 and on the first light-blocking layer BML1. The buffer layer 115 may be disposed in the entire non-emission area NEA and the emission area EMA of the first substrate 110. The buffer layer 115 may be formed on the first substrate 110 to protect the transistors TR1, TR2, and TR3 of the pixel PX from water vapor permeating through the first substrate 110 (which is prone to water vapor permeation), and may perform a surface planarization function. The buffer layer 115 may include a plurality of inorganic layers stacked alternately. For example, the buffer layer 115 may be formed as a multi-layer in which one or more inorganic layers of silicon oxide (SiO x ), silicon nitride (SiN x ), and silicon oxynitride (SiO x N y ) are stacked alternately.

[0093] The semiconductor layer is disposed on the buffer layer 115. The semiconductor layer may be disposed in the non-emission area NEA of each pixel PX or sub-pixel PXn to constitute the active material layer of each of the transistors TR1, TR2, and TR3. The semiconductor layer may include a first active material layer ACT1 of the first transistor TR1, a second active material layer ACT2 of the second transistor TR2, and a third active material layer ACT3 of the third transistor TR3.

[0094] These active material layers may be disposed to partially overlap the gate electrodes GE1, GE2, and GE3 of the first gate conductive layer to be described later. Based on the center of the non-emission area NEA of the sub-pixel PXn in the drawing, the second active material layer ACT2 may be disposed on the upper side which is one side in the second direction DR2 of the center, and the first active material layer ACT1 and the third active material layer ACT3 may be disposed on the lower side which is the other side in the second direction DR2 of the center. As shown in the drawing, the first active material layer ACT1 of the first transistor TR1 and the third active material layer ACT3 of the third transistor TR3 may be integrally formed as a single semiconductor layer, a part of the single semiconductor layer may be the first active material layer ACT1, and another part of the single semiconductor layer may be the third active material layer ACT3.

[0095] Meanwhile, in an exemplary embodiment, the semiconductor layer may include polysilicon, single-crystalline silicon, an oxide semiconductor, etc. When the semiconductor layer includes polysilicon, the first active material layer ACT1 may include a first doped region ACT1a, a second doped region ACT1b, and a first channel region ACT1c. The first doped region ACT1a and the second doped region ACT1b may be regions doped with impurities. The first channel region ACT1c may be disposed between the first doped region ACT1a and the second doped region ACT1b. Polysilicon may be formed by crystallizing amorphous silicon. Examples of the crystallization method include a rapid thermal annealing (RTA) method, a solid-phase crystallization (SPC) method, an excimer laser annealing (ELA) method, a metal-induced lateral crystallization (MILC) method, a sequential lateral solidification (SLS) method, etc., but are not limited thereto. As another example, the first active material layer ACT1 may include single-crystalline silicon, low-temperature polysilicon, amorphous silicon, etc.

[0096] However, the first active material layer ACT1 is not necessarily limited to the above examples. In an exemplary embodiment, the first active material layer ACT1 may include an oxide semiconductor. In this case, the first doped region ACT1a may be a first conductive region, and the second doped region ACT1b may be a second conductive region. When the first active material layer ACT1 includes an oxide semiconductor, the oxide semiconductor may be an oxide semiconductor including indium (In). In some embodiments, the oxide semiconductor may be indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium zinc tin oxide (IZTO), indium gallium tin oxide (IGTO), indium gallium zinc tin oxide (IGZTO), etc. However, the present disclosure is not limited thereto.

[0097] The first gate insulating layer 130 is disposed on the semiconductor layer and the buffer layer 115. The first gate insulating layer 130 may be disposed on the buffer layer 115 and on the semiconductor layer, that is, on the first active material layer ACT1, the second active material layer ACT2, and the third active material layer ACT3. That is, the first gate insulating layer 130 may be disposed entirely on the non-emission region NEA and the emission region EMA. The first gate insulating layer 130 may serve as a gate insulating film of the first transistor TR1, the second transistor TR2, and the third transistor TR3. The first gate insulating layer 130 may be formed of an inorganic material such as silicon oxide (SiO x ) or silicon nitride (SiN x ), or formed in a structure in which silicon oxide (SiO x ) and silicon nitride (SiN x ) are stacked.

[0098] The first gate conductive layer is disposed on the first gate insulating layer 130. The first gate conductive layer may include gate electrodes GE1, GE2, and GE3 of a first transistor TR1, a second transistor TR2, and a third transistor TR3 disposed in a non-emission area NEA, a scan line SCL, a sense line SSL, a second voltage line VSSL, a reference voltage distribution line RVT, and a first capacitive electrode CSE1 of a storage capacitor Cst, and base layers 411 and 421 of dam structures 410 and 420 disposed in an emission area EMA.

[0099] First, gate electrodes GE1, GE2, and GE3 of the first transistor TR1, the second transistor TR2, and the third transistor TR3 may be disposed to overlap a first active material layer ACT1, a second active material layer ACT2, and a third active material layer ACT3, respectively. The first gate electrode GE1 may overlap at least a partial area of the first active material layer ACT1, the second gate electrode GE2 may overlap at least a partial area of the second active material layer ACT2, and the third gate electrode GE3 may overlap at least a partial area of the third active material layer ACT3. The first gate electrode GE1 may be electrically connected to a first capacitive electrode CSE1 of a storage capacitor Cst, which will be described later. The second gate electrode GE2 may be electrically connected to the scan line SCL, which will be described later, and the third gate electrode GE3 may be electrically connected to the sense line SSL, which will be described later.

[0100] The scan line SCL may extend in a first direction DR1 to be disposed beyond a boundary between adjacent sub-pixels PXn. That is, a plurality of pixels PX or sub-pixels PXn adjacent to each other in the first direction DR1 may share one scan line SCL. The scan line SCL may be disposed on an upper side as one side in a second direction DR2 with respect to a center of the non-emission area NEA of the sub-pixel PXn. The scan line SCL may be electrically connected to the second gate electrode GE2 of the second transistor TR2 through a part of a first data conductive layer, which will be described later, and may transfer a scan signal to the second transistor TR2.

[0101] The sense line SSL may also extend in the first direction DR1 to be disposed beyond a boundary between adjacent sub-pixels PXn. That is, a plurality of pixels PX or sub-pixels PXn adjacent to each other in the first direction DR1 may share one sense line SSL. The sense line SSL may be disposed on a lower side as the other side in the second direction DR2 with respect to a center of the non-emission area NEA of the sub-pixel PXn. The sense line SSL may be electrically connected to the third gate electrode GE3 of the third transistor TR3 through a part of a first data conductive layer, which will be described later, and may transfer a sense signal to the third transistor TR3.

[0102] The reference voltage distribution line RVT can be disposed on the other side of the sensing line SSL in the second direction DR2 and can extend in the first direction DR1. The reference voltage distribution line RVT can be disposed to extend from the first sub-pixel PX1 to the third sub-pixel PX3, and each pixel PX (i.e., three sub-pixels PXn) can share one reference voltage distribution line RVT with each other. The reference voltage distribution line RVT can be electrically connected to the reference voltage line RVL described later and the first source / drain electrode of the third transistor TR3 of each sub-pixel PXn. Accordingly, the reference voltage distribution line RVT can transfer the reference voltage applied from the reference voltage line RVL to the third transistor TR3.

[0103] The second voltage line VSSL can be disposed on one side of the scan line SCL in the second direction DR2 and can extend in the first direction DR1. In addition, the second voltage line VSSL can be disposed in the non-display area NDA of the display device 10 and can also include a portion extending in the second direction DR2. The portion of the second voltage line VSSL extending in the second direction DR2 can be connected to the above-described wiring pad WPD, and thus, the second source voltage can be applied. The second voltage line VSSL can be electrically connected to the second electrode 220 (see Figure 4 ) to apply the second source voltage to the light-emitting element 300. Meanwhile, it has been shown in Figure 4 that the second voltage line VSSL and the second electrode 220 are connected to each other in the non-display area NDA, but the present disclosure is not limited thereto. In some cases, the second electrode 220 of the corresponding sub-pixel PXn can be electrically connected to the second voltage line VSSL at a portion of the second voltage line VSSL extending in the first direction DR1, respectively.

[0104] The first capacitive electrode CSE1 of the storage capacitor Cst is disposed between the scan line SCL and the sensing line SSL. The first capacitive electrode CSE1 of the storage capacitor Cst can be electrically connected to the first gate electrode GE1 of the first transistor TR1 and the second source / drain electrode SDE4 of the second transistor TR2.

[0105] The second source / drain electrode SDE4 of the second transistor TR2 can be in contact with one side of the second active material layer ACT2 through the first contact hole CT1 in a region where it overlaps with one side of the second active material layer ACT2. The second source / drain electrode SDE4 can be connected to the first capacitive electrode CSE1 of the storage capacitor Cst.

[0106] Meanwhile, the display device 10 may include bank structures 410 and 420 disposed in the emission area EMA, and the light-emitting elements 300 may be disposed between the bank structures 410 and 420. The bank structures 410 and 420 may include a first bank structure 410 and a second bank structure 420. The first bank structure 410 and the second bank structure 420 may be disposed for each sub-pixel PXn to form an area in the emission area EMA where the light-emitting elements 300 are disposed.

[0107] The bank structures 410 and 420 may have a multi-layer structure in which a plurality of layers are stacked. According to an embodiment, the bank structures 410 and 420 may respectively include a base layer 411 and 421, an intermediate layer 417 and 427, and an upper layer 412 and 422. Here, the base layers 411 and 421 may be disposed at the same layer as the first gate conductive layer (i.e., the first gate electrode GE1 of the first transistor TR1). That is, the first gate conductive layer may further include the base layers 411 and 421 of the bank structures 410 and 420 disposed in the emission area EMA.

[0108] The first bank structure 410 and the second bank structure 420 respectively include a first base layer 411 and a second base layer 421, and each of the first base layer 411 and the second base layer 421 is directly disposed on the first gate insulating layer 130 located in the emission area EMA. The first base layer 411 and the second base layer 421 may extend in the second direction DR2 in the emission area EMA of each sub-pixel PXn, and may be disposed to be spaced apart from each other and face each other in the first direction DR1. The lengths of the first base layer 411 and the second base layer 421 measured in the second direction DR2 may be substantially the same as each other. Other layers may also be disposed on the first base layer 411 and the second base layer 421, and the first base layer 411 and the second base layer 421 and the other layers may respectively form the bank structures 410 and 420.

[0109] However, the first base layer 411 and the second base layer 421 disposed in the emission area EMA to form the bank structures 410 and 420 may not be electrically connected to the circuit elements and wirings disposed in the non-emission area NEA. That is, the first base layer 411 and the second base layer 421 may be disposed at the first gate conductive layer, but may be electrically insulated from the circuit elements and wirings, and may be disposed in the emission area EMA to provide an area in which the light-emitting elements 300 are disposed. A more detailed description of the bank structures 410 and 420 will be provided later.

[0110] The first gate conductive layer may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. However, the present disclosure is not limited thereto.

[0111] The first passivation layer 150 is disposed on the first gate conductive layer. The first passivation layer 150 may be disposed in the non-emission area NEA to cover the active material layers ACT1, ACT2, and ACT3 of the first transistor TR1, the second transistor TR2, and the third transistor TR3, multiple signal lines, etc. The first passivation layer 150 may be formed of an inorganic material such as silicon oxide (SiO x ) or silicon nitride (SiN x ), or formed as a structure in which silicon oxide (SiO x ) and silicon nitride (SiN x ) are stacked.

[0112] The interlayer insulating layer is disposed on the first passivation layer 150 and the base layers 411 and 421 of the embankment structures 410 and 420. The interlayer insulating layer may include a first interlayer insulating layer 170 disposed on the first passivation layer 150 in the non-emission area NEA, and intermediate layers 417 and 427 of the embankment structures 410 and 420 disposed on the base layers 411 and 421 in the emission area EMA. The first interlayer insulating layer 170 and the intermediate layers 417 and 427 of the embankment structures 410 and 420 may be disposed at the same layer and formed in the same process.

[0113] The intermediate layers 417 and 427 of the embankment structures 410 and 420 may include a first intermediate layer 417 disposed on the first base layer 411 and a second intermediate layer 427 disposed on the second base layer 421. The first intermediate layer 417 and the second intermediate layer 427 may be disposed at the same layer as the first interlayer insulating layer 170 disposed in the non-emission area NEA, and may be disposed to cover the first base layer 411 and the second base layer 421 respectively. The intermediate layers 417 and 427 are disposed to cover the outer surfaces of the base layers 411 and 421 respectively, so that a part of the lower surface of the intermediate layers 417 and 427 may be in direct contact with the first gate insulating layer 130.

[0114] The first interlayer insulating layer 170 may be used as an insulating film between the first gate conductive layer and other layers disposed on the first interlayer insulating layer 170.

[0115] The first interlayer insulating layer 170 and the intermediate layers 417 and 427 may be formed of an inorganic material such as silicon oxide (SiO x ) or silicon nitride (SiN x ), or formed as a structure in which silicon oxide (SiO x) and silicon nitride (SiN x ).

[0116] The first data conductive layer is disposed on the first interlayer insulating layer 170, the intermediate layers 417 and 427. The first data conductive layer may include data lines DTL, a first voltage line VDDL, a reference voltage line RVL, first source / drain electrodes SDE1, SDE3, and SDE5 of a first transistor TR1, a second transistor TR2, and a third transistor TR3, second source / drain electrodes SDE2 and SDE4, a plurality of conductive patterns DP1 and DP2, a second capacitive electrode CSE2 of a storage capacitor Cst, and upper layers 412 and 422 of the dam structures 410 and 420. The data lines DTL, the first voltage line VDDL, and the reference voltage line RVL of the first data conductive layer may be disposed across the non-emission region NEA and the emission region EMA. The first source / drain electrodes SDE1, SDE3, and SDE5 and the second source / drain electrodes SDE2 and SDE4 of the first transistor TR1, the second transistor TR2, and the third transistor TR3, the plurality of conductive patterns DP1 and DP2, and the second capacitive electrode CSE2 of the storage capacitor Cst of the first data conductive layer may be disposed in the non-emission region NEA, and the upper layers 412 and 422 of the dam structures 410 and 420 of the first data conductive layer may be disposed in the emission region EMA.

[0117] The data line DTL may extend in a second direction DR2 so as to be disposed beyond a boundary between adjacent sub-pixels PXn. For example, a plurality of pixels PX or sub-pixels PXn adjacent to each other in the second direction DR2 may share one data line DTL with each other. The data line DTL may be disposed on the right side as one side in a first direction DR1 with respect to a center of the non-emission region NEA of the sub-pixel PXn. The data line DTL may be in contact with one side of a second active material layer ACT2 of the second transistor TR2 through a second contact hole CT2. That is, a part of the data line DTL may be the first source / drain electrode SDE3 of the second transistor TR2, and thus, a data signal applied to the data line DTL may be transmitted to the second transistor TR2.

[0118] The first voltage line VDDL may also extend in the second direction DR2 to be set to extend beyond the boundaries between adjacent sub-pixels PXn. For example, a plurality of pixels PX or sub-pixels PXn adjacent to each other in the second direction DR2 may share a first voltage line VDDL with each other. The first voltage line VDDL may be set on the left side, which is the other side in the first direction DR1, with respect to the center of the non-emission region NEA of the sub-pixel PXn. The first voltage line VDDL may be in contact with one side of the first active material layer ACT1 of the first transistor TR1 through the third contact hole CT3. That is, a part of the first voltage line VDDL may be the first source / drain electrode SDE1 of the first transistor TR1, and thus, the first source voltage applied to the first voltage line VDDL may be transferred to the first transistor TR1.

[0119] The first voltage line VDDL and the data line DTL may be set for each sub-pixel PXn. As shown in the drawings, the first voltage line VDDL and the data line DTL may be respectively set on the left side and the right side with respect to the center of each sub-pixel PXn, and may extend in the second direction DR2 to be disposed throughout the non-emission region NEA and the emission region EMA. The first voltage line VDDL and the data line DTL disposed in the emission region EMA may be disposed under the outer dam layer 450, which will be described later.

[0120] A reference voltage line RVL may be set in one pixel PX, that is, in every three sub-pixels PXn. For example, the reference voltage line RVL may be set on the right side, which is one side of the data line DTL of the third sub-pixel PX3 in the first direction DR1, and may extend in the second direction DR2. A plurality of pixels PX adjacent to each other in the second direction DR2 may share a reference voltage line RVL with each other. The reference voltage line RVL may be electrically connected to the above-mentioned reference voltage distribution line RVT, and the reference voltage applied through the reference voltage line RVL may be transferred to the third transistor TR3 of each sub-pixel PXn through the reference voltage distribution line RVT.

[0121] The second capacitive electrode CSE2 of the storage capacitor Cst is disposed between the first voltage line VDDL and the data line DTL. The second capacitive electrode CSE2 of the storage capacitor Cst may be disposed to overlap with the first capacitive electrode CSE1, and the storage capacitor Cst may be formed between the first capacitive electrode CSE1 and the second capacitive electrode CSE2. The second capacitive electrode CSE2 of the storage capacitor Cst may be connected to the second source / drain electrode SDE2 of the first transistor TR1. The second source / drain electrode SDE2 of the first transistor TR1 may be in contact with a portion of the first active material layer ACT1 and the first light blocking layer BML1 through the fourth contact hole CT4. In addition, the second source / drain electrode SDE2 of the first transistor TR1 may also be in contact with one side of the third active material layer ACT3 of the third transistor TR3 to constitute the second source / drain electrode of the third transistor TR3.

[0122] The first source / drain electrode SDE5 of the third transistor TR3 may be in contact with one side of the third active material layer ACT3 and the reference voltage distribution line RVT. The first source / drain electrode SDE5 of the third transistor TR3 may receive a reference voltage from the reference voltage distribution line RVT.

[0123] The first conductive pattern DP1 and the second conductive pattern DP2 of the first data conductive layer may be connected to a portion of the first gate conductive layer. The first conductive pattern DP1 may be connected to the scan line SCL and the second gate electrode GE2 of the second transistor TR2, and may transfer the scan signal applied from the scan line SCL to the second gate electrode GE2 of the second transistor TR2. The second conductive pattern DP2 may be connected to the sense line SSL and the third gate electrode GE3 of the third transistor TR3, and may transfer the sense signal applied from the sense line SSL to the third gate electrode GE3 of the third transistor TR3.

[0124] Meanwhile, as described above, the dam structures 410 and 420 may respectively include upper layers 412 and 422 disposed on the intermediate layers 417 and 427, and the upper layers 412 and 422 may be disposed at the same layer as the source / drain electrodes SDE1 and SDE2 of the first transistor TR1. That is, the first data conductive layer may further include the upper layers 412 and 422 of the dam structures 410 and 420 disposed in the emission region EMA.

[0125] The first bank structure 410 and the second bank structure 420 respectively include a first upper layer 412 and a second upper layer 422, and the first upper layer 412 and the second upper layer 422 are respectively directly disposed on a first intermediate layer 417 and a second intermediate layer 427 located in the emission region EMA. The first upper layer 412 and the second upper layer 422 may respectively have the same shape as the first base layer 411 and the second base layer 421. For example, the first upper layer 412 and the second upper layer 422 may extend in the second direction DR2 in the emission region EMA of each sub-pixel PXn, and may be arranged to be spaced apart from each other and face each other in the first direction DR1. The base layers 411 and 421, the intermediate layers 417 and 427, and the upper layers 412 and 422 may respectively form the bank structures 410 and 420, and the electrodes 210 and 220 to be described later may be respectively disposed on the bank structures 410 and 420.

[0126] However, similar to the base layers 411 and 421, the first upper layer 412 and the second upper layer 422 disposed in the emission region EMA to form the bank structures 410 and 420 may not be electrically connected to the circuit elements and wirings disposed in the non-emission region NEA. That is, the first upper layer 412 and the second upper layer 422 may be disposed at the first data conductive layer, but may be electrically insulated from the circuit elements and wirings, and may be disposed in the emission region EMA to provide a region in which the light-emitting element 300 is disposed.

[0127] Describing the bank structures 410 and 420 in detail, the first bank structure 410 and the second bank structure 420 may be arranged adjacent to the central portion of the emission region EMA of each sub-pixel PXn, and may be arranged to be spaced apart from each other and face each other in the first direction DR1. In addition, the first bank structure 410 and the second bank structure 420 may extend in the second direction DR2 in the emission region EMA of each sub-pixel PXn, but may terminate so as not to extend to other adjacent sub-pixels PXn in the second direction DR2. As an example, the first bank structure 410 and the second bank structure 420 may be arranged for each sub-pixel PXn to form a pattern in the entire display device 10. The bank structures 410 and 420 are arranged to be spaced apart from each other and face each other in the emission region EMA, so that a region in which the light-emitting element 300 is disposed may be formed between the bank structures 410 and 420. One first bank structure 410 and one second bank structure 420 have been shown in the drawings, but the present disclosure is not limited thereto. In some cases, a plurality of first bank structures 410 and a plurality of second bank structures 420 may be provided according to the number of the electrodes 210 and 220 to be described later, or a larger number of other bank structures 410 and 420 may also be provided.

[0128] In the display device 10 according to an embodiment, components (e.g., bank structures 410 and 420) provided in the emission area EMA of each pixel PX or sub-pixel PXn may be provided at the same layer as components (e.g., gate electrodes GE1, GE2, and GE3 or source / drain electrodes of transistors TR1, TR2, and TR3) provided in the non-emission area NEA. In the display device 10 according to an embodiment, circuit elements for driving the light-emitting element 300 and the bank structures 410 and 420 providing the area in which the light-emitting element 300 is provided may be formed in the same process, and thus, the number of manufacturing processes of the display device 10 may be reduced. In addition, the light-emitting element 300 that emits light and the circuit element (e.g., the first transistor TR1) for driving the light-emitting element 300 may be arranged not to overlap each other in the thickness direction, and the display device 10 may emit light toward the upper surface or the rear surface of the first substrate 110 on which the light-emitting element 300 is provided.

[0129] In addition, the first bank structure 410 and the second bank structure 420 are formed as a multi-layer structure in which a plurality of layers are stacked, and thus may have a structure in which at least a part thereof protrudes from the upper surface of the first substrate 110 in the emission area EMA. The protruding portions of the first bank structure 410 and the second bank structure 420 may have inclined side surfaces, and light emitted from the light-emitting element 300 provided between the first bank structure 410 and the second bank structure 420 may travel toward the inclined side surfaces of the bank structures 410 and 420. As will be described later, when the electrodes 210 and 220 provided on the bank structures 410 and 420 include materials having a high reflectivity, the light emitted from the light-emitting element 300 may be reflected on the inclined side surfaces of the bank structures 410 and 420 and emitted in the upward direction of the first substrate 110. That is, the bank structures 410 and 420 may serve as reflective partition walls that reflect the light emitted from the light-emitting element 300 toward the upward direction while providing the area in which the light-emitting element 300 is provided.

[0130] A plurality of electrodes 210 and 220 and the first insulating layer 510 may be provided on the first data conductive layer of the emission area EMA. The display device 10 according to an embodiment may include a plurality of electrodes 210 and 220 provided on the bank structures 410 and 420 and a plurality of light-emitting elements 300 provided between the plurality of electrodes 210 and 220. The plurality of electrodes 210 and 220 may include a first electrode 210 provided on the first bank structure 410 and a second electrode 220 provided on the second bank structure 420.

[0131] As Figure 5As shown, the first electrode 210 may be arranged to extend in the second direction DR2 within the emission area EMA of each sub-pixel PXn. The first electrode 210 does not extend to other adjacent sub-pixels PXn in the second direction DR2 and may be arranged to be spaced apart from the outer bank layer 450 surrounding the emission area EMA of each sub-pixel PXn. In addition, at least a partial area of the first electrode 210 may be arranged in the non-emission area NEA. The first electrode 210 may be electrically connected to the first transistor TR1 through a part of it arranged in the non-emission area NEA. As an example, as Figure 6 shown, the part of the first electrode 210 arranged in the non-emission area NEA may be in direct contact with the second source / drain electrode SDE2 of the first transistor TR1. The first electrode 210 arranged in the corresponding sub-pixel PXn may receive different electrical signals from the corresponding first transistor TR1. However, it has been shown in the drawing that the first electrode 210 is arranged to partially cover the second source / drain electrode SDE2 of the first transistor TR1, but the present disclosure is not limited thereto. In some embodiments, at least one layer may also be arranged between the first electrode 210 and the second source / drain electrode SDE2, and the first electrode 210 may be in contact with the second source / drain electrode SDE2 through a contact hole penetrating at least one layer. In addition, in some cases, the first electrode 210 may be electrically connected to the second source / drain electrode SDE2 through a bridging part arranged on another layer.

[0132] The second electrode 220 may include a second electrode main part 220S arranged to extend in the first direction DR1 and second electrode branch parts 220B branching from the second electrode main part 220S in the second direction DR2.

[0133] The second electrode main part 220S may be arranged to extend in the first direction DR1 to cross other sub-pixels PXn. That is, a plurality of sub-pixels PXn or pixels PX adjacent to each other in the first direction DR1 may share one second electrode main part 220S. The second electrode main part 220S may be electrically connected to the second voltage line VSSL. For example, the second electrode main part 220S may be electrically connected to the second voltage line VSSL through an electrode contact hole CNTS in the non-display area NDA at the outer side part of the display area DPA where a plurality of pixels PX or sub-pixels PXn are arranged. Different from the first electrode 210, the second electrode 220 may receive the same electrical signal in pixels PX or sub-pixels PXn sharing one second electrode main part 220S. However, the present disclosure is not limited thereto, and in some embodiments, the second electrode main part 220S may be omitted from the second electrode 220, and each of the second electrodes 220 arranged for each sub-pixel PXn may be electrically connected to the second voltage line VSSL.

[0134] The second electrode branch portion 220B may be spaced apart from and face the first electrode 210 in the first direction DR1. The second electrode branch portion 220B may extend in the second direction DR2, but may be spaced apart from the non-emitting region NEA so as not to be disposed in the non-emitting region NEA.

[0135] The plurality of electrodes 210 and 220 may be electrically connected to the light-emitting element 300 and may receive a predetermined voltage such that the light-emitting element 300 emits light. For example, the plurality of electrodes 210 and 220 may be electrically connected to the light-emitting element 300 through contact electrodes 261 and 262 to be described later, and the electrical signals applied to the electrodes 210 and 220 may be transmitted to the light-emitting element 300 through the contact electrodes 261 and 262. In addition, at least a part of each of the electrodes 210 and 220 may be used to form an electric field in the sub-pixel PXn to align the light-emitting element 300.

[0136] In an exemplary embodiment, the first electrode 210 may be a pixel electrode separated for each sub-pixel PXn, and the second electrode 220 may be a common electrode commonly connected along each sub-pixel PXn. One of the first electrode 210 and the second electrode 220 may be an anode electrode of the light-emitting element 300, and the other of the first electrode 210 and the second electrode 220 may be a cathode electrode of the light-emitting element 300. However, the first electrode 210 and the second electrode 220 are not limited thereto, and vice versa.

[0137] Meanwhile, as Figure 6 shown, the first electrode 210 may be disposed on the first bank structure 410, and a part of the second electrode 220 or the second electrode branch portion 220B may be disposed on the second bank structure 420. The first electrode 210 and the second electrode 220 may be disposed to cover the first bank structure 410 and the second bank structure 420, respectively. For example, the widths of the first electrode 210 and the second electrode 220 measured in one direction may be greater than the widths of the first bank structure 410 and the second bank structure 420 measured in the one direction, such that the first electrode 210 and the second electrode 220 may be disposed to cover the outer surfaces of the first bank structure 410 and the second bank structure 420, respectively. Accordingly, parts of the lower surfaces of the first electrode 210 and the second electrode 220 may be in contact with the first gate insulating layer 130, and other parts of the lower surfaces of the first electrode 210 and the second electrode 220 may be in contact with the bank structures 410 and 420, respectively.

[0138] Each of electrodes 210 and 220 may include a transparent conductive material. As an example, each of electrodes 210 and 220 may include a material such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO), but is not limited thereto. In some embodiments, each of electrodes 210 and 220 may include a conductive material having a high reflectivity. For example, each of electrodes 210 and 220 may include a metal such as silver (Ag), copper (Cu), or aluminum (Al) as a material having a high reflectivity. In this case, light incident on each of electrodes 210 and 220 may be reflected to be emitted in the upward direction of each sub-pixel PXn.

[0139] In addition, electrodes 210 and 220 may have a structure in which one or more layers made of a transparent conductive material and one or more layers made of a metal having a high reflectivity are stacked, or may be formed to include one layer of a transparent conductive material and a metal having a high reflectivity. In an exemplary embodiment, each of electrodes 210 and 220 may have a stacked structure of ITO / silver (Ag) / ITO / IZO, or may be made of an alloy including aluminum (Al), nickel (Ni), lanthanum (La), etc. However, the present disclosure is not limited thereto.

[0140] Meanwhile, one first electrode 210 and one second electrode 220 are shown in the drawings as being disposed in each sub-pixel PXn, but the present disclosure is not limited thereto. Similar to the bank structures 410 and 420, a greater number of first electrodes 210 and second electrodes 220 may be provided. In addition, the first electrode 210 and the second electrode 220 do not have to have a shape in which they extend in one direction, and may be provided in various structures. For example, the first electrode 210 and the second electrode 220 may have a partially curved or bent shape, and either the first electrode 210 or the second electrode 220 may be provided to surround the other of the first electrode 210 and the second electrode 220. The first electrode 210 and the second electrode 220 are not particularly limited in terms of their arrangement structure and shape as long as at least a partial region thereof is spaced apart from each other and faces each other, and accordingly, a region in which the light-emitting element 300 will be disposed is formed between the first electrode 210 and the second electrode 220.

[0141] The first insulating layer 510 may be integrally disposed in the emission area EMA and may be configured such that partial areas of each of the electrodes 210 and 220 are exposed. The first insulating layer 510 may be disposed not only in the area between the electrodes 210 and 220 or the bank structures 410 and 420 that are spaced apart from each other, but also on the outer side opposite to this area with respect to the bank structures 410 and 420. However, the first insulating layer 510 may include an opening (not shown) formed to expose the upper surfaces of the first electrode 210 and the second electrode 220. The opening of the first insulating layer 510 may be formed such that partial areas of the portions of the first electrode 210 and the second electrode 220 placed on the bank structures 410 and 420 are exposed.

[0142] The first insulating layer 510 may insulate the first electrode 210 and the second electrode 220 from each other while protecting the first electrode 210 and the second electrode 220. In addition, the first insulating layer 510 may prevent the light-emitting element 300 disposed on the first insulating layer 510 from coming into direct contact with other components and being damaged by other components. However, the shape and structure of the first insulating layer 510 are not limited thereto.

[0143] The first planarization layer 180 is disposed on the first data conductive layer in the non-emission area NEA, and the outer bank layer 450 is disposed on the first insulating layer 510 in the emission area EMA. The first planarization layer 180 and the outer bank layer 450 may be disposed at the same layer and may thus be formed simultaneously in one process. Therefore, the first planarization layer 180 and the outer bank layer 450 may be collectively referred to as a planarization layer. Thus, in an exemplary embodiment, the heights from the first substrate 110 to the upper surfaces of the first planarization layer 180 and the outer bank layer 450 may be substantially the same as each other. However, the present disclosure is not limited thereto.

[0144] The first planarization layer 180 may be disposed to completely cover the first data conductive layer in the non-emission area NEA. The first planarization layer 180 may be used to planarize the steps formed due to the circuit elements disposed in the non-emission area NEA while protecting the first data conductive layer.

[0145] The outer bank layer 450 may be disposed on a partial area of the emission area EMA and may be formed in the same process as the first planarization layer 180 in the non-emission area NEA. However, as Figure 6 shown, the first planarization layer 180 may be disposed to completely cover the non-emission area NEA, but the outer bank layer 450 may be disposed such that a partial area of the emission area EMA is exposed.

[0146] For example, the outer bank layer 450 may be disposed at the boundaries between corresponding sub-pixels PXn. The outer bank layer 450 may be configured to extend in a first direction DR1 and a second direction DR2, and may be configured to surround the bank structures 410 and 420, and the electrodes 210 and 220, and the region where the light-emitting elements 300 are disposed between the bank structures 410 and 420 and the electrodes 210 and 220. That is, the outer bank layer 450 may form a lattice pattern in the entire display area DPA. According to an embodiment, the height of the outer bank layer 450 may be greater than the height of the bank structures 410 and 420. The outer bank layer 450 may be used to prevent ink from overflowing into adjacent sub-pixels PXn during the inkjet process of disposing the light-emitting elements 300 in the manufacturing process of the display device 10 as described later, while partitioning adjacent sub-pixels PXn.

[0147] The light-emitting element 300 may be disposed between the first electrode 210 and the second electrode 220. One end of the light-emitting element 300 may be electrically connected to the first electrode 210, and the other end of the light-emitting element 300 may be electrically connected to the second electrode 220. The light-emitting element 300 may have both ends electrically connected to the contact electrodes 261 and 262 to be described later, and may be electrically connected to the first electrode 210 and the second electrode 220 through the contact electrodes 261 and 262, respectively.

[0148] A plurality of light-emitting elements 300 may be disposed to be spaced apart from each other and may be aligned substantially parallel to each other. The interval between the spaced-apart light-emitting elements 300 is not particularly limited. In some cases, a plurality of light-emitting elements 300 may be disposed adjacent to each other and grouped, and a plurality of other light-emitting elements 300 may be grouped in a state where they are spaced apart from the plurality of light-emitting elements 300 by a predetermined interval, or the plurality of light-emitting elements 300 may have a non-uniform density, but may be oriented and aligned in one direction. In addition, in an exemplary embodiment, the light-emitting elements 300 may have a shape in which they extend in one direction, and the direction in which the corresponding electrodes (e.g., the first electrode 210 and the second electrode branch 220B) extend and the direction in which the light-emitting elements 300 extend may be substantially perpendicular to each other. However, the present disclosure is not limited thereto, and the light-emitting elements 300 are not perpendicular to the direction in which the corresponding electrodes extend, and may also be disposed to be inclined with respect to the direction in which the corresponding electrodes extend.

[0149] The light-emitting element 300 according to an embodiment may include an active layer 330 that includes different materials to emit light in different wavelength bands to the outside. The display device 10 according to an embodiment may include the light-emitting element 300 that emits light in different wavelength bands. The light-emitting element 300 of the first sub-pixel PX1 may include an active layer 330 that emits first light having a first wavelength in a central wavelength band thereof, the light-emitting element 300 of the second sub-pixel PX2 may include an active layer 330 that emits second light having a second wavelength in a central wavelength band thereof, and the light-emitting element 300 of the third sub-pixel PX3 may include an active layer 330 that emits third light having a third wavelength in a central wavelength band thereof.

[0150] Accordingly, first light may be emitted from the first sub-pixel PX1, second light may be emitted from the second sub-pixel PX2, and third light may be emitted from the third sub-pixel PX3. In some embodiments, the first light may be blue light having a central wavelength band in the range of 450 nm to 495 nm, the second light may be green light having a central wavelength band in the range of 495 nm to 570 nm, and the third light may be red light having a central wavelength band in the range of 620 nm to 752 nm.

[0151] However, the present disclosure is not limited thereto. In some cases, each of the first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3 may further include the same type of light-emitting element 300 to emit light having substantially the same color.

[0152] The light-emitting element 300 may be disposed on the first insulating layer 510 between the corresponding electrodes 210 and 220. For example, the light-emitting element 300 may be disposed on the first insulating layer 510 provided between the bank structures 410 and 420. However, the present disclosure is not limited thereto, and although not shown in the drawings, at least some of the light-emitting elements 300 disposed in each sub-pixel PXn may also be in a region other than the region formed between the bank structures 410 and 420, for example, between the bank structures 410 and 420 and the outer bank layer 450. In addition, the light-emitting element 300 may be disposed such that a partial region thereof overlaps with the corresponding electrodes 210 and 220 in the thickness direction. In this case, one end of the light-emitting element 300 may be disposed on the first electrode 210, and the other end of the light-emitting element 300 may be disposed on the second electrode 220.

[0153] Meanwhile, although not shown in the drawings, the light-emitting element 300 may include a plurality of layers disposed in a direction parallel to the upper surface of the first substrate 110 or the first insulating layer 510. The light-emitting element 300 of the display device 10 according to an embodiment may have a shape in which it extends in one direction, and may have a structure in which a plurality of semiconductor layers are sequentially disposed in one direction. The light-emitting element 300 may be disposed such that one direction along which the light-emitting element 300 extends is parallel to the first insulating layer 510, and the plurality of semiconductor layers included in the light-emitting element 300 may be sequentially disposed along a direction parallel to the upper surface of the first insulating layer 510. However, the present disclosure is not limited thereto. In some cases, when the light-emitting element 300 has another structure, the plurality of layers may be disposed in a direction perpendicular to the first insulating layer 510. A more detailed description of the structure of the light-emitting element 300 will be provided later with reference to other drawings.

[0154] The second insulating layer 520 may be disposed on the first planarization layer 180 in the non-emission area NEA, the outer bank layer 450 in the emission area EMA, and portions of the bank structures 410 and 420, and the light-emitting element 300. The second insulating layer 520 may be disposed to completely cover the first planarization layer 180 in the non-emission area NEA, but may be disposed to expose both ends of the light-emitting element 300 in the emission area EMA and portions of the upper surfaces of the first electrode 210 and the second electrode 220.

[0155] For example, the second insulating layer 520 may be partially disposed on the light-emitting element 300 disposed between the first electrode 210 and the second electrode 220. A portion of the second insulating layer 520 disposed on the light-emitting element 300 may have a shape in which it extends in a second direction DR2 between the first electrode 210 and the second electrode 220 in the emission area EMA. As an example, a partial area of the second insulating layer 520 may form a stripe pattern or an island pattern in the emission area EMA of each sub-pixel PXn. The second insulating layer 520 may be disposed to partially surround the outer surface of the light-emitting element 300 to fix the light-emitting element 300 in the manufacturing process of the display device 10 while protecting the light-emitting element 300. Here, the second insulating layer 520 may be disposed such that both ends of the light-emitting element 300 are exposed, and the exposed both ends of the light-emitting element 300 may be in contact with contact electrodes 261 and 262 to be described later.

[0156] In addition, the second insulating layer 520 may be disposed to cover the outer embankment layer 450, the first electrode 210, and the second electrode 220, but may be disposed such that portions of the upper surfaces of the first electrode 210 and the second electrode 220 are exposed. Similar to the first insulating layer 510, the second insulating layer 520 may include an opening (not shown) formed to expose portions of the upper surfaces of the first electrode 210 and the second electrode 220. The opening of the second insulating layer 520 may be disposed to overlap with the opening of the first insulating layer 510. Accordingly, portions of the upper surfaces of the first electrode 210 and the second electrode 220 may be exposed because the first insulating layer 510 and the second insulating layer 520 are not disposed on the portions of the upper surfaces of the first electrode 210 and the second electrode 220, and the contact electrodes 261 and 262 to be described later may be disposed on the exposed portions.

[0157] A plurality of contact electrodes 261 and 262 and a third insulating layer 530 may be disposed on the second insulating layer 520 of the emission region EMA.

[0158] As Figure 5 shown, the plurality of contact electrodes 261 and 262 may have a shape in which they extend in one direction. The plurality of contact electrodes 261 and 262 may be in contact with the light emitting element 300 and the electrodes 210 and 220, respectively, and the light emitting element 300 may receive electrical signals from the first electrode 210 and the second electrode 220 through the contact electrodes 261 and 262.

[0159] The contact electrodes 261 and 262 may include a first contact electrode 261 and a second contact electrode 262. The first contact electrode 261 and the second contact electrode 262 may be disposed on the first electrode 210 and the second electrode 220, respectively. The first contact electrode 261 may be disposed on the first electrode 210 and extend in the second direction DR2, and the second contact electrode 262 may be disposed on the second electrode 220 or the second electrode branch portion 220B and extend in the second direction DR2. The first contact electrode 261 and the second contact electrode 262 may be spaced apart from each other and face each other in the first direction DR1, and may form a stripe pattern in the emission region EMA of each sub-pixel PXn.

[0160] In some embodiments, the widths of the first contact electrode 261 and the second contact electrode 262 measured in one direction may be respectively equal to or greater than the widths of the first electrode 210 and the second electrode 220 or the second electrode branch portion 220B measured in the one direction. The first contact electrode 261 and the second contact electrode 262 may be arranged to respectively cover the upper surfaces of the first electrode 210 and the second electrode 220 while respectively contacting one end and the other end of the light-emitting element 300. However, the present disclosure is not limited thereto, and in some cases, the first contact electrode 261 and the second contact electrode 262 may also be arranged to respectively cover only portions of the first electrode 210 and the second electrode 220.

[0161] According to an embodiment, the light-emitting element 300 may have a semiconductor layer exposed on its end surface in one direction in which it extends, and the first contact electrode 261 and the second contact electrode 262 may contact the light-emitting element 300 on the end surface on which the semiconductor layer is exposed. However, the present disclosure is not limited thereto. In some cases, side surfaces at both ends of the light-emitting element 300 may be partially exposed. The insulating film 380 (see Figure 7 ) around the outer surface of the semiconductor layer of the light-emitting element 300 may be partially removed in the process of forming the second insulating layer 520 covering the outer surface of the light-emitting element 300 in the manufacturing process of the display device 10, and the exposed side surfaces of the light-emitting element 300 may contact the first contact electrode 261 and the second contact electrode 262.

[0162] One first contact electrode 261 and one second contact electrode 262 have been shown to be provided in one sub-pixel PXn in the drawings, but the present disclosure is not limited thereto. The number of the first contact electrode 261 and the second contact electrode 262 may be changed according to the number of the first electrode 210 and the second electrode 220 provided in each sub-pixel PXn.

[0163] As Figure 6 shown, the first contact electrode 261 is provided on the first electrode 210 and the second insulating layer 520. The first contact electrode 261 may contact one end of the light-emitting element 300 and the exposed upper surface of the first electrode 210. One end of the light-emitting element 300 may be electrically connected to the first electrode 210 through the first contact electrode 261.

[0164] The third insulating layer 530 is disposed on the first contact electrode 261. The third insulating layer 530 can electrically insulate the first contact electrode 261 and the second contact electrode 262 from each other. The third insulating layer 530 can be disposed to cover the first contact electrode 261, but may not be disposed on the other end of the light-emitting element 300, such that the light-emitting element 300 can contact the second contact electrode 262. The third insulating layer 530 can be in partial contact with the first contact electrode 261 and the second insulating layer 520 on the upper surface of the second insulating layer 520. A side surface of the third insulating layer 530 in the direction in which the second electrode 220 is disposed can be aligned with a side surface of the second insulating layer 520. However, the present disclosure is not limited thereto.

[0165] The second contact electrode 262 is disposed on the second electrode 220, the second insulating layer 520, and the third insulating layer 530. The second contact electrode 262 can contact the other end of the light-emitting element 300 and the exposed upper surface of the second electrode 220. The other end of the light-emitting element 300 can be electrically connected to the second electrode 220 through the second contact electrode 262.

[0166] That is, the first contact electrode 261 can be disposed between the first electrode 210 and the third insulating layer 530, and the second contact electrode 262 can be disposed on the third insulating layer 530. The second contact electrode 262 can be in partial contact with the second insulating layer 520, the third insulating layer 530, the second electrode 220, and the light-emitting element 300. One end of the second contact electrode 262 in the direction in which the first electrode 210 is disposed can be disposed on the third insulating layer 530. The first contact electrode 261 and the second contact electrode 262 can be non-contact with each other through the second insulating layer 520 and the third insulating layer 530. However, the present disclosure is not limited thereto, and in some cases, the third insulating layer 530 can be omitted.

[0167] The contact electrodes 261 and 262 can include a conductive material. For example, the contact electrodes 261 and 262 can include ITO, IZO, ITZO, aluminum (Al), etc. However, the present disclosure is not limited thereto.

[0168] The fourth insulating layer 550 can be disposed over the entire emission region EMA and the non-emission region NEA on the first substrate 110. The fourth insulating layer 550 can be used to protect the components disposed on the first substrate 110 from the external environment.

[0169] Each of the first insulating layer 510, the second insulating layer 520, the third insulating layer 530, and the fourth insulating layer 550 described above can include an inorganic insulating material or an organic insulating material. In an exemplary embodiment, the first insulating layer 510, the second insulating layer 520, the third insulating layer 530, and the fourth insulating layer 550 can include an inorganic insulating material such as silicon oxide (SiO x) Silicon nitride (SiN x ) Silicon oxynitride (SiO x N y ), aluminum oxide (Al2O3), or aluminum nitride (AlN). In addition, the first insulating layer 510, the second insulating layer 520, the third insulating layer 530, and the fourth insulating layer 550 may include acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, benzocyclobutene, cardo resin, silicone resin, silsesquioxane resin, polymethyl methacrylate, polycarbonate, polymethyl methacrylate-polycarbonate synthetic resin, etc. as organic insulating materials. However, the present disclosure is not limited thereto.

[0170] At the same time, the light-emitting element 300 may be a light-emitting diode. Specifically, the light-emitting element 300 may be an inorganic light-emitting diode having a micron or nanoscale size and made of an inorganic material. The inorganic light-emitting diode may be aligned between two electrodes, and when an electric field is formed in a specific direction between the two electrodes facing each other, a polarity is formed in the two electrodes. The light-emitting element 300 may be aligned between the two electrodes by the electric field formed on the two electrodes.

[0171] The light-emitting element 300 according to an embodiment may have a shape in which it extends in one direction. The light-emitting element 300 may have a shape such as a rod shape, a wire shape, or a tube shape. In an exemplary embodiment, the light-emitting element 300 may have a cylindrical shape or a rod shape. However, the light-emitting element 300 is not limited to having the above shapes and may have various shapes. For example, the light-emitting element 300 may have a polygonal prism shape such as a cube shape, a rectangular parallelepiped shape, or a hexagonal prism shape, or a shape in which it extends in one direction but has a partially inclined outer surface. The plurality of semiconductors included in the light-emitting element 300, which will be described later, may have a structure in which they are sequentially arranged or stacked along one direction.

[0172] The light-emitting element 300 may include a semiconductor layer doped with impurities of any conductivity type (e.g., p-type or n-type). The semiconductor layer may receive an electrical signal applied from an external power source and emit the electrical signal as light in a specific wavelength band.

[0173] Figure 7 is a schematic diagram of a light-emitting element according to an embodiment.

[0174] Referring to Figure 7 , the light-emitting element 300 may include a first semiconductor layer 310, a second semiconductor layer 320, an active layer 330, an electrode layer 370, and an insulating film 380.

[0175] The first semiconductor layer 310 may be an n-type semiconductor. As an example, when the light-emitting element 300 emits light in the blue wavelength band, the first semiconductor layer 310 may include a semiconductor material having a chemical formula of Al x Ga y In 1-x-y N (0 ≤ x ≤ 1, 0 ≤ y ≤ 1, and 0 ≤ x + y ≤ 1). For example, the semiconductor material may be one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with an n-type dopant. As an example, the first semiconductor layer 310 may be doped with an n-type dopant, which may be Si, Ge, Se, Sn, etc. In an exemplary embodiment, the first semiconductor layer 310 may be made of n-GaN doped with n-type Si. The length of the first semiconductor layer 310 may be in the range of 1.5 μm to 5 μm, but is not limited thereto.

[0176] The second semiconductor layer 320 is disposed on the active layer 330, which will be described later. The second semiconductor layer 320 may be a p-type semiconductor, and as an example, when the light-emitting element 300 emits light in the blue or green wavelength band, the second semiconductor layer 320 may include a semiconductor material having a chemical formula of Al x Ga y In 1-x-y N (0 ≤ x ≤ 1, 0 ≤ y ≤ 1, and 0 ≤ x + y ≤ 1). For example, the semiconductor material may be one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with a p-type dopant. As an example, the second semiconductor layer 320 may be doped with a p-type dopant, which may be Mg, Zn, Ca, Ba, etc. In an exemplary embodiment, the second semiconductor layer 320 may be made of p-GaN doped with p-type Mg. The length of the second semiconductor layer 320 may be in the range of 0.05 μm to 0.10 μm, but is not limited thereto.

[0177] Meanwhile, each of the first semiconductor layer 310 and the second semiconductor layer 320 has been shown in the drawing as being configured as one layer, but the present disclosure is not limited thereto. According to some embodiments, depending on the material of the active layer 330, each of the first semiconductor layer 310 and the second semiconductor layer 320 may further include a greater number of layers, for example, a cladding layer or a tensile strain barrier reduction (TSBR) layer. This will be described later with reference to other drawings.

[0178] The active layer 330 is disposed between the first semiconductor layer 310 and the second semiconductor layer 320. The active layer 330 may include a material having a single quantum well structure or a multi - quantum well structure. When the active layer 330 includes a material having a multi - quantum well structure, the active layer 330 may have a structure in which a plurality of quantum layers and a plurality of well layers are alternately stacked. The active layer 330 can emit light through the combination of electron - hole pairs according to an electrical signal applied through the first semiconductor layer 310 and the second semiconductor layer 320. As an example when the active layer 330 emits light in the blue wavelength band, the active layer 330 may include a material such as AlGaN or AlGaInN. Specifically, when the active layer 330 has a multi - quantum well structure, that is, a structure in which quantum layers and well layers are alternately stacked, the quantum layer may include a material such as AlGaN or AlGaInN, and the well layer may include a material such as GaN or AlInN. In an exemplary embodiment, the active layer 330 may include AlGaInN as the material of the quantum layer and AlInN as the material of the well layer to emit blue light having a central wavelength band of 450 nm to 495 nm, as described above.

[0179] However, the present disclosure is not limited thereto, and the active layer 330 may have a structure in which a semiconductor material having a large energy bandgap and a semiconductor material having a small energy bandgap are alternately stacked, and may include other group - III to group - V semiconductor materials according to the wavelength band of the emitted light. The light emitted by the active layer 330 is not limited to the light in the blue wavelength band, and in some cases, the active layer 330 may emit light in the red and green wavelength bands. The length of the active layer 330 may be in the range of 0.05 μm to 0.10 μm, but is not limited thereto.

[0180] Meanwhile, the light emitted from the active layer 330 can be emitted not only to the outer surface of the light - emitting element 300 in the length direction but also to the two side surfaces of the light - emitting element 300. The directivity of the light emitted from the active layer 330 is not limited to one direction.

[0181] The electrode layer 370 may be an ohmic contact electrode. However, the present disclosure is not limited thereto, and the electrode layer 370 may also be a Schottky contact electrode. The light - emitting element 300 may include at least one electrode layer 370. It has been shown in Figure 7 that the light - emitting element 300 includes one electrode layer 370, but the present disclosure is not limited thereto. In some cases, the light - emitting element 300 may further include a larger number of electrode layers 370, or the electrode layer 370 may also be omitted. Even if the number of electrode layers 370 changes or the light - emitting element 300 further includes another structure, the description of the light - emitting element 300 to be provided later can be similarly applied.

[0182] When the light-emitting element 300 is electrically connected to the electrodes 210 and 220 or the contact electrodes 261 and 262, the electrode layer 370 can reduce the resistance between the light-emitting element 300 and the electrodes 210 and 220 or the contact electrodes 261 and 262. The electrode layer 370 can include a metal having electrical conductivity. The electrode layer 370 can include at least one of aluminum (Al), titanium (Ti), indium (In), gold (Au), silver (Ag), indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO). The electrode layer 370 can include a semiconductor material doped with an n-type or p-type dopant. The electrode layer 370 can include the same material or include different materials, but is not limited thereto.

[0183] The insulating film 380 is disposed to surround the outer surfaces of the plurality of semiconductor layers 310 and 320 and the electrode layer 370. In an exemplary embodiment, the insulating film 380 can be disposed to surround at least the outer surface of the active layer 330 and can extend in one direction along which the light-emitting element 300 extends. The insulating film 380 can be used to protect these components. As an example, the insulating film 380 can be formed to surround the side surface portions of these components, but can be formed to expose both ends of the light-emitting element 300 in the length direction.

[0184] It has been shown in the drawing that the insulating film 380 is formed to extend in the length direction of the light-emitting element 300 to cover the side surfaces of the first semiconductor layer 310 to the electrode layer 370, but the present disclosure is not limited thereto. The insulating film 380 can cover only some of the semiconductor layers 310 and 320 and the outer surface of the active layer 330, or can cover only a part of the outer surface of the electrode layer 370 such that the outer surface of each electrode layer 370 can be partially exposed. In addition, the insulating film 380 can also be formed such that its upper surface is circular in a cross section in a region adjacent to at least one end of the light-emitting element 300.

[0185] The thickness of the insulating film 380 can be in the range of 10 nm to 1.0 μm, but is not limited thereto. The thickness of the insulating film 380 can preferably be about 40 nm.

[0186] The insulating film 380 can include a material having insulating properties, such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN), and aluminum oxide (Al2O3). Thus, an electrical short circuit that may occur when the active layer 330 is in direct contact with the electrodes through which an electrical signal is transmitted to the light-emitting element 300 can be prevented. In addition, the insulating film 380 protects the outer surfaces of the semiconductor layers 310 and 320 and the active layer 330, and thus prevents a reduction in light-emitting efficiency.

[0187] In addition, in some embodiments, the outer surface of the insulating film 380 may be surface-treated. When manufacturing the display device 10, the light-emitting elements 300 may be ejected and aligned onto the electrodes in a state where they are dispersed in a predetermined ink. Here, in order to keep the light-emitting elements 300 in a state where the light-emitting elements 300 are dispersed and do not aggregate with other adjacent light-emitting elements 300 in the ink, a hydrophobic or hydrophilic treatment may be performed on the outer surface of the insulating film 380.

[0188] The light-emitting element 300 may have a length h of 1 μm to 10 μm or 2 μm to 6 μm, and preferably 3 μm to 5 μm. In addition, the diameter of the light-emitting element 300 may be in the range of 300 nm to 700 nm, and the aspect ratio of the light-emitting element 300 may be 1.2 to 100. However, the present disclosure is not limited thereto, and the plurality of light-emitting elements 300 included in the display device 10 may also have different diameters depending on the compositional differences between the active layers 330. Preferably, the diameter of the light-emitting element 300 may be about 500 nm.

[0189] In the display device 10 according to an embodiment, the bank structures 410 and 420 providing the regions where the light-emitting elements 300 are disposed in the emission region EMA and the circuit elements for driving the light-emitting elements 300 in the non-emission region NEA may be disposed at the same layer. Specifically, the base layers 411 and 421 and the upper layers 412 and 422 of the bank structures 410 and 420 may be disposed at the same layer as the first gate electrode GE1 and the source / drain electrodes SDE1 and SDE2 of the first transistor TR1, respectively, and thus may be formed simultaneously with the first gate electrode GE1 and the source / drain electrodes SDE1 and SDE2 of the first transistor TR1 in one process. Therefore, the number of manufacturing processes of the display device 10 according to the embodiment can be reduced.

[0190] Hereinafter, the manufacturing process of the display device 10 will be described with reference to other drawings. Hereinafter, the order of the manufacturing process of the display device 10 will be described in detail, and the description of the method of forming the corresponding members will be omitted.

[0191] Figures 8 to 15 is a cross-sectional view showing some of the manufacturing processes of the display device according to an embodiment.

[0192] First, refer to Figure 8, a first substrate 110 is prepared, and a first light-blocking layer BML1, a buffer layer 115, a first active material layer ACT1, and a first gate insulating layer 130 are formed on the first substrate 110. The buffer layer 115 and the first gate insulating layer 130 are disposed entirely on the first substrate 110, and the first light-blocking layer BML1 and the first active material layer ACT1 are disposed only in the non-emission area NEA on the first substrate 110.

[0193] Next, referring to Figure 9 , a first gate conductive layer is formed on the first gate insulating layer 130. A first gate electrode GE1 disposed in the non-emission area NEA and a first base layer 411 and a second base layer 421 disposed in the emission area EMA are formed on the first gate insulating layer 130. As described above, the first gate electrode GE1, and the first base layer 411 and the second base layer 421 may be included in the first gate conductive layer and disposed at the same layer, and may be formed simultaneously in one process.

[0194] Next, referring to Figure 10 , an interlayer insulating layer is formed on the first gate conductive layer. A first interlayer insulating layer 170 that completely covers the non-emission area NEA and a first intermediate layer 417 disposed in the emission area EMA to cover the first base layer 411 and a second intermediate layer 427 disposed to cover the second base layer 421 are formed on the first gate conductive layer. As described above, the first interlayer insulating layer 170, and the first intermediate layer 417 and the second intermediate layer 427 may be included in the interlayer insulating layer and disposed at the same layer, and may be formed simultaneously in one process.

[0195] Next, referring to Figure 11 , a first data conductive layer is formed on the interlayer insulating layer. A first source / drain electrode SDE1 and a second source / drain electrode SDE2 of a first transistor TR1 disposed in the non-emission area NEA and a first upper layer 412 disposed on the first intermediate layer 417 and a second upper layer 422 disposed on the second intermediate layer 427 in the emission area EMA are formed on the interlayer insulating layer. As described above, the source / drain electrodes SDE1 and SDE2 of the first transistor TR1, and the first upper layer 412 and the second upper layer 422 may be included in the first data conductive layer and disposed at the same layer, and may be formed simultaneously in one process. Through the above process, the first transistor TR1 can be formed in the non-emission area NEA, and the first dam structure 410 and the second dam structure 420 can be formed in the emission area EMA.

[0196] Next, referring to Figure 12 and Figure 13, the first electrode 210 and the second electrode 220 are formed on the embankment structures 410 and 420 of the emission area EMA, and a first insulating material layer 510' covering the first electrode 210 and the second electrode 220 is formed. Figure 13 No opening (not shown) is formed in the first insulating material layer 510' such that the first insulating material layer 510' can completely cover the first electrode 210 and the second electrode 220. In a subsequent process, a part of the first insulating material layer 510' is etched, and an opening (not shown) exposing the upper surfaces of the portions of the first electrode 210 and the second electrode 220 is formed, so that the first insulating layer 510 can be formed.

[0197] Next, referring to Figure 14 , a first planarization layer 180 disposed on the first data conductive layer in the non-emission area NEA and an outer embankment layer 450 disposed on the first insulating layer 510 in the emission area EMA are formed. As described above, the first planarization layer 180 and the outer embankment layer 450 are formed simultaneously in one process. In some embodiments, the first planarization layer 180 and the outer embankment layer 450 may be formed of an organic insulating material such as polyimide (PI), and the heights of the first planarization layer 180 and the outer embankment layer 450 (e.g., the heights from the upper surface of the first substrate 110 to the upper surfaces of the first planarization layer 180 and the outer embankment layer 450) may be substantially the same as each other. However, the present disclosure is not limited thereto.

[0198] Next, referring to Figure 15 , a light-emitting element 300 is disposed between the first electrode 210 and the second electrode 220 or between the first embankment structure 410 and the second embankment structure 420. In some embodiments, the light-emitting elements 300 may be ejected into the emission area EMA of each pixel PX or sub-pixel PXn in a state where they are dispersed in a predetermined ink by an inkjet process, and may be aligned between the first electrode 210 and the second electrode 220 by a process of forming an electric field between the first electrode 210 and the second electrode 220. When the light-emitting elements 300 dispersed in the ink are ejected into the emission area EMA and an alignment signal is applied to the first electrode 210 and the second electrode 220, an electric field can be formed between the first electrode 210 and the second electrode 220, and the light-emitting elements 300 can receive the dielectrophoretic force generated due to the electric field. The light-emitting elements 300 receiving the dielectrophoretic force can be aligned between the first electrode 210 and the second electrode 220 while their orientation directions and positions are changed in the ink.

[0199] Here, either the first electrode 210 or the second electrode 220 can be grounded, and alternating current (AC) power can be applied to the other of the first electrode 210 and the second electrode 220. For example, when the first electrode 210 is grounded and AC power is applied to the second electrode 220, the AC power can be directly applied to the second electrode 220 instead of the second voltage line VSSL. As described above, the process of applying AC power to the second electrode 220 can be performed through the wiring connected to the second electrode 220 in the manufacturing process of the display device 10, and then the process of disconnecting the wiring can be performed.

[0200] Figure 16 is a plan view showing a step of the manufacturing process of a display device according to an embodiment.

[0201] Figure 16 shows that the second electrode main body part 220S is provided to extend into the non-display area NDA in the manufacturing process of the display device 10. Refer to Figure 16 , the second electrode main body part 220S extends in the first direction DR1 so that the second electrode 220 can also be provided in the non-display area NDA, and although not shown in the drawings, the second electrode 220 can receive AC power applied through a pad (not shown) provided in the non-display area NDA. When the AC power is directly applied to the second electrode 220 through the pad, the AC power can be directly applied to the second electrode 220 without passing through the wiring electrically connected to the second electrode 220, such as the second voltage line VSSL. Therefore, it is possible to prevent the circuit elements and wiring of the display device 10 from being damaged due to the AC power applied to the circuit elements and wiring.

[0202] After the light-emitting element 300 is aligned between the first electrode 210 and the second electrode 220, a process of disconnecting a partial area CS (see Figure 16 ) of the second electrode main body part 220S can be performed. When the display device 10 is driven, the second electrode 220 can receive only the second source voltage through the second voltage line VSSL.

[0203] Next, contact electrodes 261 and 262 provided on the first electrode 210 and the second electrode 220 are formed to electrically connect the light-emitting element 300 and the first electrode 210 and the second electrode 220 to each other.

[0204] Figures 17 to 19 is a cross-sectional view showing other processes in the manufacturing process of a display device according to an embodiment.

[0205] First, refer to Figure 17, a second insulating layer 520 is formed on a partial region of the first insulating layer 510 and the light-emitting element 300. Although not shown in the drawings, the shape of the second insulating layer 520 can be formed by disposing an insulating material over the entire first insulating material layer 510' (see Figure 15 ) and then performing a patterning process that exposes both ends of the first electrode 210, the second electrode 220, and the light-emitting element 300. In the patterning process, the first insulating material layer 510' can also be partially removed, and thus the first insulating layer 510 can be formed. Although it has been shown in the drawings that portions of the upper surfaces of the first electrode 210 and the second electrode 220 are simultaneously exposed, the present disclosure is not limited thereto. In some cases, after performing the processes of forming the first contact electrode 261 and the third insulating layer 530, which will be described later, a process of exposing a portion of the upper surface of the second electrode 220 can be performed.

[0206] Meanwhile, in some embodiments, the process of disconnecting a partial region CS of the second electrode 220 (see Figure 16 ) can be performed in the same process as the process of forming the second insulating layer 520. In the process of forming the second insulating layer 520, when the insulating material is formed to cover the upper surface of the first insulating material layer 510' and then patterned, a partial region CS of the second electrode 220 (see Figure 16 ) can also be patterned simultaneously. In this case, the number of processes required between the process of disposing the light-emitting element 300 and the process of exposing portions of the first electrode 210 and the second electrode 220 can be further reduced.

[0207] Next, referring to Figure 18 and Figure 19 , a first contact electrode 261 disposed on the first electrode 210, a third insulating layer 530 disposed on the first contact electrode 261, and a second contact electrode 262 disposed on the second electrode 220 are formed. The description of the arrangement and structure of the first contact electrode 261, the third insulating layer 530, and the second contact electrode 262 is the same as the above description.

[0208] Next, a fourth insulating layer 550 is formed to cover the components disposed on the first substrate 110, so that the display device 10 according to the embodiment can be manufactured.

[0209] Hereinafter, various embodiments of the display device 10 will be described.

[0210] Figure 20 is a cross-sectional view of a display device according to another embodiment.

[0211] Referring to Figure 20 , in the display device 10_1 according to the embodiment, the third insulating layer 530 can be omitted. This embodiment is the same asFigure 6 The implementation mode is different in that the third insulating layer 530 is omitted. In the following, overlapping descriptions will be omitted, and the content different from the above will be mainly described.

[0212] In Figure 20 the display device 10_1 of , the third insulating layer 530 can be omitted, and the second contact electrode 262_1 can be directly disposed on the second insulating layer 520_1. In some implementation modes, when the second insulating layer 520_1 includes an organic insulating material, the first contact electrode 261_1 and the second contact electrode 262_1 can be formed simultaneously in one process. In the process of forming the second insulating layer 520_1 after the light-emitting element 300 is disposed, parts of the upper surfaces of the first electrode 210 and the second electrode 220 can be exposed simultaneously, as Figure 17 shown. Thereafter, the first contact electrode 261_1 and the second contact electrode 262_1 are formed simultaneously, but can be spaced apart from each other on the second insulating layer 520_1 disposed on the light-emitting element 300. Therefore, a part of the lower surface of the second contact electrode 262_1 can be in direct contact with the second insulating layer 520_1. In the display device 10_1 according to the present implementation mode, the third insulating layer 530 is omitted, and the first contact electrode 261_1 and the second contact electrode 262_1 are formed simultaneously in one process, so that the number of manufacturing processes of the display device 10_1 can be further reduced.

[0213] Figure 21 FIG. is a layout diagram showing a pixel of a display device according to another implementation mode. Figure 22 FIG. shows Figure 21 a cross-sectional view of a part of the display device of .

[0214] Referring to Figure 21 and Figure 22 , in the display device 10_2 according to the implementation mode, the outer bank layer 450 can be omitted. This implementation mode is different from the implementation modes of Figure 5 and Figure 6 in that the outer bank layer 450 is omitted. In the following, overlapping descriptions will be omitted, and the content different from the above will be mainly described.

[0215] In Figure 21 and Figure 22In the display device 10_2, the outer bank layer 450 can be omitted. As described above, the outer bank layer 450 can be used to prevent ink from overflowing into other sub-pixels PXn during the inkjet process of setting the light-emitting elements 300, while dividing the corresponding sub-pixels PXn. However, in some cases, when the ink can be positioned within the emission area EMA of the sub-pixel PXn, the outer bank layer 450 can be omitted. In addition, when it is not important for the ink to overflow into other sub-pixels PXn, for example, when multiple sub-pixels PXn include the same type of light-emitting element 300, the ink can be jetted to overflow into multiple sub-pixels PXn. In this case, the outer bank layer 450 can be omitted, and only the first planarization layer 180 can be provided on the non-emission area NEA.

[0216] Figure 23 is a layout diagram showing a pixel of a display device according to another embodiment.

[0217] Reference Figure 23 , in the display device 10_3 according to the embodiment, the second electrode main body portion 220S can be omitted, and the second electrode 220_3 can be electrically connected to the second voltage line VSSL through the electrode contact hole CNTS_3 formed for each sub-pixel PXn. The difference between this embodiment and Figure 5 's embodiment lies in the omission of the second electrode main body portion 220S. Hereinafter, overlapping descriptions will be omitted, and the differences from the above will be mainly described.

[0218] In Figure 23 's display device 10_3, the second electrode main body portion 220S can be omitted. Similar to the first electrode 210, the second electrode 220_3 can be provided for each sub-pixel PXn, and the second electrodes 220_3 provided in multiple sub-pixels PXn can be separated from each other. In this case, the second electrode 220_3 can extend in the second direction DR2 and can be electrically connected to the second voltage line VSSL, where the second voltage line VSSL is provided between sub-pixels PXn adjacent to each other in the first direction DR1.

[0219] Specifically, referring to Figure 5 , multiple pixels PX or sub-pixels PXn can be arranged in the first direction DR1 and the second direction DR2, and also in the case where wirings (such as the second voltage line VSSL) are provided in each of the multiple pixels PX or sub-pixels PXn, multiple wirings can extend in the first direction DR1. Therefore, it has been shown in Figure 5 that one second voltage line VSSL is provided on the upper side of the non-emission area NEA of one pixel PX or sub-pixel PXn, but the second voltage line VSSL can also be provided to extend on the lower side of the emission area EMA, as shown in Figure 23As shown. In this case, the second electrode 220_3 may extend in the second direction DR2 to partially overlap with the second voltage line VSSL, and may be electrically connected to the second voltage line VSSL through an electrode contact hole CNTS_3 in a region where the second electrode 220_3 overlaps with the second voltage line VSSL. In some embodiments, the second voltage line VSSL may overlap with a part of the outer bank layer 450 extending in the first direction DR1, and the electrode contact hole CNTS_3 through which the second electrode 220_3 and the second voltage line VSSL are connected to each other may be formed in a region where the second voltage line VSSL overlaps with the outer bank layer 450. However, the present disclosure is not limited thereto.

[0220] Meanwhile, as described above, the display device 10 may further include a larger number of bank structures 410 and 420 or a larger number of electrodes 210 and 220.

[0221] Figure 24 is a layout diagram showing a pixel of a display device according to another embodiment. Figure 25 is shown Figure 24 a cross-sectional view of a part of the display device.

[0222] Referring to Figure 24 and Figure 25 , the display device 10_4 according to an embodiment may further include a third bank structure 430_4 disposed between the first bank structure 410_4 and the second bank structure 420_4, a third electrode 230_4 disposed between the first electrode 210_4 and the second electrode 220_4 and disposed on the third bank structure 430_4, and a third contact electrode 263_4 disposed between the first contact electrode 261_4 and the second contact electrode 262_4 and disposed on the third electrode 230_4. The difference between this embodiment and the embodiments of Figure 5 and Figure 6 is that it further includes a third bank structure 430_4 and a third electrode 230_4. Hereinafter, overlapping descriptions will be omitted, and the content different from the above will be mainly described.

[0223] Figure 24 and Figure 25The display device 10_4 may further include a third bank structure 430_4. The third bank structure 430_4 may have substantially the same structure as the first bank structure 410_4 and the second bank structure 420_4. That is, the third bank structure 430_4 may include a third base layer 431_4 disposed on the first gate conductive layer, a third intermediate layer 437_4 disposed to cover the third base layer 431_4, and a third upper layer 432_4 disposed on the third intermediate layer 437_4 and at the first data conductive layer. The descriptions of the third base layer 431_4, the third intermediate layer 437_4, and the third upper layer 432_4 are the same as those of the first base layer 411, the first intermediate layer 417, and the first upper layer 412 above. The third bank structure 430_4 may be disposed to be spaced apart from and face the first bank structure 410_4 and the second bank structure 420_4 between the first bank structure 410_4 and the second bank structure 420_4, and may have a shape in which it extends in the second direction DR2 in the emission region EMA. Accordingly, a region in which the light-emitting element 300 is disposed may be formed between the first bank structure 410_4 and the third bank structure 430_4 and between the third bank structure 430_4 and the second bank structure 420_4, and a larger number of light-emitting elements 300 may be provided for each sub-pixel PXn.

[0224] The third electrode 230_4 is disposed on the third bank structure 430_4. The third electrode 230_4 may be formed such that its width measured in one direction is greater than the width of the third bank structure 430_4 measured in the one direction, and thus may be formed to surround the outer surface of the third bank structure 430_4. In addition, the third electrode 230_4 may be formed on the third bank structure 430_4 such that, similar to the first electrode 210_4, a part of its upper surface is exposed, may extend in the second direction DR2, and may be disposed to be spaced apart from and face the first electrode 210_4 and the second electrode 220_4 between the first electrode 210_4 and the second electrode 220_4.

[0225] However, different from the first electrode 210_4 and the second electrode 220_4, the third electrode 230_4 may not be electrically connected to the circuit elements or wirings provided in each pixel PX or sub-pixel PXn. The first electrode 210_4 may be electrically connected to the second source / drain electrode SDE2 of the first transistor TR1, and the second electrode 220_4 may be electrically connected to the second voltage line VSSL, but the third electrode 230_4 may be a floating electrode not electrically connected to the second source / drain electrode SDE2 of the first transistor TR1 and the second voltage line VSSL. The third electrode 230_4 may be an electrode to which an electrical signal applied from the circuit elements or wirings is not directly transmitted and to which the electrical signals flowing to the first electrode 210_4 and the second electrode 220_4 flow.

[0226] The third contact electrode 263_4 may also be provided on the third electrode 230_4. The third contact electrode 263_4 may contact each of the light-emitting elements 300 provided between the first bank structure 410_4 and the third bank structure 430_4 and the light-emitting elements 300 provided between the third bank structure 430_4 and the second bank structure 420_4. Each of the light-emitting elements 300 provided between the first bank structure 410_4 and the third bank structure 430_4 may have one end in contact with the first contact electrode 261_4 and the other end in contact with the third contact electrode 263_4, and each of the light-emitting elements 300 provided between the third bank structure 430_4 and the second bank structure 420_4 may have one end in contact with the third contact electrode 263_4 and the other end in contact with the second contact electrode 262_4. In addition, the third contact electrode 263_4 may also contact the exposed upper surface of the third electrode 230_4. Accordingly, the light-emitting elements 300 may be electrically connected to the third electrode 230_4 through the third contact electrode 263_4. One third bank structure 430_4, one third electrode 230_4, and one third contact electrode 263_4 have been shown in the drawings, but the present disclosure is not limited thereto, and the numbers of the third bank structure 430_4, the third electrode 230_4, and the third contact electrode 263_4 may be more than those shown in the drawings.

[0227] When an electrical signal is transmitted through the first electrode 210_4, the electrical signal can be transmitted to one end of the light-emitting element 300 disposed between the first bank structure 410_4 and the third bank structure 430_4. The electrical signal can be transmitted to the third contact electrode 263_4 and the third electrode 230_4, and can be transmitted to the light-emitting element 300 disposed between the third bank structure 430_4 and the second bank structure 420_4. The light-emitting element 300 disposed between the first bank structure 410_4 and the third bank structure 430_4 and the light-emitting element 300 disposed between the third bank structure 430_4 and the second bank structure 420_4 can receive the electrical signal only through the first electrode 210_4, respectively, and can be connected in series with each other. The display device 10_4 according to an embodiment can also improve the light-emitting efficiency by further including the third bank structure 430_4, the third electrode 230_4, and the third contact electrode 263_4 and thus connecting some of the plurality of light-emitting elements 300 in series with each other.

[0228] In addition, the display device 10 includes a larger number of first electrodes 210 and first bank structures 410 such that a larger number of light-emitting elements 300 can be provided for each sub-pixel PXn, but these light-emitting elements 300 can be connected in parallel with each other.

[0229] Figure 26 is a layout diagram showing a pixel of a display device according to another embodiment. Figure 27 is showing Figure 26 a cross-sectional view of a part of the display device.

[0230] Referring to Figure 26 and Figure 27 , the display device 10_5 according to an embodiment can include a plurality of first bank structures 410_5, and the second bank structure 420_5 can be disposed between the plurality of first bank structures 410_5. In addition, the first electrode 210_5 can include a first electrode main body part 210S_5 and a first electrode branch part 210B_5, and the second electrode 220_5 can include a second electrode branch part 220B_5 disposed between the first electrode branch parts 210B_5. This embodiment is different from the embodiments of Figure 5 and Figure 6 in that it further includes a plurality of first bank structures 410_5 and a part where the first electrode 210_5 has branches. Hereinafter, overlapping descriptions will be omitted, and the content different from the above will be mainly described.

[0231] Figure 26 and Figure 27The display device 10_5 may include a plurality of first bank structures 410_5, and a second bank structure 420_5 may be disposed between the plurality of first bank structures 410_5. That is, the first bank structures 410_5 and the second bank structure 420_5 may be alternately disposed in the emission region EMA of each sub-pixel PXn, and may be spaced apart from each other and face each other. A region in which the light-emitting element 300 is disposed is formed between the first bank structure 410_5 and the second bank structure 420_5 and between the second bank structure 420_5 and the first bank structure 410_5, so that a larger number of light-emitting elements 300 can be disposed. That is, in the present embodiment, it can be understood that the first bank structure 410_5 spaced apart from the second bank structure 420_5 is also disposed on Figure 5 and Figure 6 one side of the second bank structure 420 in the first direction DR1 in the embodiment of

[0232] The first electrode 210_5 may include a first electrode main body portion 210S_5 extending in the first direction DR1 and a plurality of first electrode branch portions 210B_5 branching from the first electrode main body portion 210S_5 in the second direction DR2. The first electrode branch portions 210B_5 may be respectively disposed on the first bank structures 410_5, and the first electrode main body portion 210S_5 may connect the first electrode branch portions 210B_5 to each other. The first electrode 210_5 may be electrically connected to the first transistor TR1 through a portion protruding from one side of the first electrode main body portion 210S_5, and may transmit an electrical signal to each of the first electrode branch portions 210B_5.

[0233] The second electrode 220_5 includes a second electrode main body portion 220S_5 and a second electrode branch portion 220B_5. The second electrode branch portion 220B_5 may be disposed on the second bank structure 420_5, and both sides of the second electrode branch portion 220B_5 may be respectively spaced apart from and face the first electrode branch portions 210B_5. That is, in the present embodiment, it can be understood that the first electrode branch portions 210B_5 spaced apart from the second electrode branch portion 220B_5 are also disposed on Figure 5 and Figure 6 one side of the second electrode branch portion 220B in the first direction DR1 in the embodiment of

[0234] In addition, a first contact electrode 261_5 may be disposed on the first electrode branch portion 210B_5, and a second contact electrode 262_5 may be disposed on the second electrode branch portion 220B_5. With Figure 5It is different and more first contact electrodes 261_5 can be provided.

[0235] The light-emitting elements 300 can be provided in each of the regions formed between the first bank structure 410_5 and the second bank structure 420_5, and at least one end of each of the light-emitting elements 300 can be electrically connected to the first electrode branch portion 210B_5 through the first contact electrode 261_5. Different from Figure 24 and Figure 25 the embodiment of, in this embodiment, the light-emitting elements 300 provided in different regions can have at least one end respectively electrically connected to the first electrode branch portion 210B_5, and thus, electrical signals can be received from the first transistor TR1 simultaneously. In addition, the light-emitting elements 300 provided in different regions can have the other end electrically connected to the second electrode branch portion 220B_5, and electrical signals can be received from the second voltage line VSSL simultaneously. That is, the light-emitting elements 300 according to this embodiment can be connected in parallel with each other. The description of other components is the same as the above description, and thus the detailed description of other components will be omitted.

[0236] At the end of the detailed description, those skilled in the art will understand that many changes and modifications can be made to the preferred embodiments without substantially departing from the principles of the present invention. Therefore, the preferred embodiments of the present invention disclosed are for general and descriptive purposes only and not for the purpose of limitation.

Claims

1. A display device, comprising: a substrate, in which an emission region and a non - emission region are defined; a first bank structure and a second bank structure, disposed in the emission region to be spaced apart from each other on the substrate; a first electrode and a second electrode, the first electrode being disposed on the first bank structure, and the second electrode being disposed on the second bank structure; and a light - emitting element, disposed between the first electrode and the second electrode in the emission region, wherein each of the first bank structure and the second bank structure includes a base layer, an upper layer disposed on the base layer, and an intermediate layer disposed between the base layer and the upper layer, the first electrode and the second electrode are disposed to respectively cover the first bank structure and the second bank structure, the display device further includes a first transistor, the first transistor is disposed in the non - emission region of the substrate, and includes a first active material layer, a first gate electrode disposed on the first active material layer, and source / drain electrodes in contact with at least a partial region of the first active material layer, and the first gate electrode is disposed at the same layer as the base layer of each of the first bank structure and the second bank structure.

2. The display device according to claim 1, wherein, The source / drain electrodes of the first transistor are disposed at the same layer as the upper layer of each of the first bank structure and the second bank structure.

3. The display device according to claim 2, wherein, The first electrode is at least partially disposed in the non - emission region, and a portion of the first electrode disposed in the non - emission region is in contact with the source / drain electrodes of the first transistor.

4. The display device according to claim 1, further comprising a third bank structure and a third electrode, the third bank structure is disposed in the emission region of the substrate and between the first bank structure and the second bank structure, and the third electrode is disposed on the third bank structure.

5. The display device according to claim 4, wherein, The light - emitting element includes a first light - emitting element disposed between the first bank structure and the third bank structure and a second light - emitting element disposed between the third bank structure and the second bank structure, the first light - emitting element has one end electrically connected to the first electrode, and the second light - emitting element has one end electrically connected to the second electrode.

6. The display device according to claim 1, further comprising a first planarization layer and an outer bank layer, the first planarization layer is disposed on the source / drain electrodes in the non - emission region, and the outer bank layer is disposed to surround the first bank structure and the second bank structure in the emission region.

7. The display device according to claim 6, wherein, The height from the upper surface of the substrate to the upper surface of the first planarization layer is the same as the height from the upper surface of the substrate to the upper surface of the outer bank layer.

8. The display device according to claim 1, wherein, The intermediate layer of each of the first bank structure and the second bank structure is disposed to surround the outer surface of the base layer.

9. The display device according to claim 8, wherein, The upper layer overlaps at least a partial region of the base layer in the thickness direction, and the intermediate layer is between the upper layer and the base layer.

10. The display device according to claim 1 further includes a first insulating layer disposed on at least a partial region of the first electrode and the second electrode, Among them, wherein the first insulating layer is disposed so as not to overlap at least a partial region of a part of the first electrode disposed on the first bank structure.

11. The display device according to claim 10 further includes a second insulating layer disposed on at least a partial region of the first insulating layer, Among them, wherein the second insulating layer is disposed such that a part of the first electrode that does not overlap with the first insulating layer is exposed.

12. The display device according to claim 11, wherein, The light-emitting element is disposed on the first insulating layer, and at least a part of the second insulating layer is disposed on the light-emitting element and is disposed such that both ends of the light-emitting element are exposed.

13. The display device according to claim 12 further includes a first contact electrode disposed on the first electrode and a second contact electrode disposed on the second electrode, Among them, wherein the first contact electrode is in direct contact with a part of the first electrode that does not overlap with the first insulating layer and the second insulating layer, and is in direct contact with one of the exposed both ends of the light-emitting element.

14. A display device includes: a substrate in which an emission region and a non-emission region are defined; a semiconductor layer disposed in the non-emission region of the substrate and including a first active material layer of a first transistor; a first gate insulating layer disposed on the substrate and the semiconductor layer; a first gate conductive layer disposed on the first gate insulating layer and including a first gate electrode of the first transistor disposed in the non-emission region and a plurality of base layers disposed in the emission region; an interlayer insulating layer including a first interlayer insulating layer disposed on the first gate electrode and a plurality of intermediate layers disposed to cover the plurality of base layers; a first data conductive layer including a source / drain electrode of the first transistor disposed on the first interlayer insulating layer and a plurality of upper layers disposed on the plurality of intermediate layers; a plurality of electrodes having at least a partial region disposed on the plurality of upper layers, spaced apart from each other, and facing each other; and at least one light-emitting element disposed between the plurality of electrodes.

15. The display device according to claim 14, wherein, The plurality of base layers include a first base layer and a second base layer disposed to be spaced apart from each other, the plurality of intermediate layers include a first intermediate layer disposed to cover the first base layer and a second intermediate layer disposed to cover the second base layer, and the plurality of upper layers include a first upper layer disposed on the first intermediate layer and a second upper layer disposed on the second intermediate layer.

16. The display device according to claim 15, wherein, The plurality of electrodes include a first electrode and a second electrode, the first electrode is disposed on the first upper layer and is disposed to cover the first base layer and the first intermediate layer, the second electrode is disposed on the second upper layer and is disposed to cover the second base layer and the second intermediate layer, and the light-emitting element is electrically connected to the first electrode and the second electrode.

17. The display device according to claim 16 further includes a first contact electrode provided on the first electrode and a second contact electrode provided on the second electrode, wherein the first contact electrode is in direct contact with the first electrode and one end of the light-emitting element, and the second contact electrode is in direct contact with the second electrode and the other end of the light-emitting element.

18. The display device according to claim 17, wherein, At least a part of the first electrode is provided in the non-emission region, and a part of the first electrode provided in the non-emission region is in contact with the source / drain electrode of the first transistor.

19. The display device according to claim 16 further includes a first insulating layer provided to cover at least a partial region of the first electrode and the second electrode, Among them, wherein the light-emitting element is provided on the first insulating layer.

20. The display device according to claim 19 further includes a second insulating layer provided on at least a partial region of the first insulating layer, Among them, wherein at least a part of the second insulating layer is provided on the light-emitting element and is provided such that both ends of the light-emitting element are exposed.

21. The display device according to claim 14 further includes a planarization layer provided on the first data conductive layer, Among them, wherein the planarization layer includes a first planarization layer provided to overlap with the non-emission region and an outer dike layer provided to surround the periphery of the emission region.

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