Radio frequency module, enabling method and electronic device thereof

Abstract

The present application discloses a radio frequency module, an enabling method and an electronic device thereof. The radio frequency module comprises a first register, a second register, a third register, a power amplifier, a distribution switch and an antenna switch, wherein: an output end of the first register is connected to a first multi-way AND gate; the multi-way output ends of the second register are respectively connected to a first multi-way NAND gate and a first multi-way OR gate; the third register is connected to the antenna switch for controlling the working state of the antenna switch, and the multi-way output ends of the third register are respectively connected to a second multi-way NAND gate and a second multi-way OR gate; the output end of the first multi-way NAND gate, the output end of the first multi-way OR gate, the output end of the second multi-way NAND gate and the output end of the second multi-way OR gate are respectively connected to the first multi-way AND gate; the output end of the first multi-way AND gate is connected to the power amplifier.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a radio frequency module, an enabling method and electronic equipment thereof. Background Art

[0002] At present, the application of RF front-end active devices often needs to comply with the corresponding power-on / power-off timing requirements, otherwise it may cause electrical stress (Electrical Over Stress, EOS) damage to the device and cause device failure. Taking the PA Module integrated Duplexer (PAMiD) as an example, Figure 1 The following is a functional block diagram of a typical PAMiD. Figure 1 In the embodiment, register A, register B and register C work independently, wherein register A independently controls the working state of the power amplifier (PA), register B independently controls the working state of the distribution switch (DSW), and register C independently controls the working state of the antenna switch (ASW).

[0003] Figure 2 The power-on / power-off sequence diagram of the PAMiD module is shown below: 1. VBAT is powered on before all other power supplies in the PAMiD module; 2. VIO is powered on to power the RFFE MIPI interface; 3. CMOS controller is initialized; 4. PA VCC is powered on; 5. PA Enable is turned on; 6. ASM antenna switch is turned on; 7. RF IN signal is loaded. Accordingly, the power-off sequence of the PAMiD module is opposite to its power-on sequence.

[0004] However, in the example of the functional block diagram of the PAMiD module above, when register A controls the PA to turn on and is in a large signal working state, it is impossible to determine from the hardware whether registers B and C are in a normal open state. In this case, if DSW or ASW is in a closed state due to incorrect instruction timing, it will cause electrical stress damage to the PA. Therefore, how to accurately determine the working status of PA, DSW and ASW still needs to provide further solutions. Summary of the invention

[0005] The embodiments of the present application provide a radio frequency module, an enabling method and an electronic device thereof to accurately determine the working status of a power amplifier, a distribution switch and an antenna switch.

[0006] In order to solve the above technical problems, the present application is implemented as follows: In a first aspect, an embodiment of the present application provides a radio frequency module, the radio frequency module comprising a first register, a second register, a third register, a power amplifier, a distribution switch and an antenna switch, wherein:

[0007] An output terminal of the first register is connected to a first multi-way AND gate;

[0008] The second register is connected to the distribution switch and is used to control the working state of the distribution switch, and the multi-way output terminals of the second register are respectively connected to the first multi-way NAND gate and the first multi-way OR gate;

[0009] The third register is connected to the antenna switch and is used to control the working state of the antenna switch, and the multi-way output end of the third register is respectively connected to the second multi-way NAND gate and the second multi-way OR gate;

[0010] The output end of the first multi-way NAND gate, the output end of the first multi-way OR gate, the output end of the second multi-way NAND gate and the output end of the second multi-way OR gate are respectively connected to the first multi-way AND gate;

[0011] The output end of the first multi-way AND gate is connected to the power amplifier.

[0012] In a second aspect, an embodiment of the present application provides an electronic device, wherein the electronic device includes the radio frequency module described in the first aspect.

[0013] In a third aspect, an embodiment of the present application provides an enabling method, which is applied to the radio frequency module described in the first aspect or the electronic device described in the second aspect, and the method includes:

[0014] Obtaining an output signal of the first multi-channel AND gate;

[0015] Based on the output signal of the first multi-AND gate, it is determined whether to enable the power amplifier.

[0016] In a fourth aspect, an embodiment of the present application provides an electronic device, including:

[0017] An acquisition unit, used for acquiring an output signal of the first multi-channel AND gate;

[0018] A determination unit is used to determine whether to enable the power amplifier based on the output signal of the first multi-path AND gate.

[0019] In a fifth aspect, an embodiment of the present application provides an electronic device, which includes a processor and a memory, wherein the memory stores programs or instructions that can be run on the processor, and when the program or instructions are executed by the processor, the steps of the method described in the third aspect are implemented.

[0020] In a sixth aspect, an embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the method of the third aspect are implemented.

[0021] In a seventh aspect, an embodiment of the present application provides a chip, comprising a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run a program or instruction to implement the method described in the third aspect.

[0022] In an eighth aspect, an embodiment of the present application provides a computer program product, which is stored in a storage medium and is executed by at least one processor to implement the method described in the third aspect.

[0023] The radio frequency module provided in the embodiment of the present application includes a first register, a second register, a third register, a power amplifier, a distribution switch and an antenna switch, wherein: an output end of the first register is connected to a first multi-way AND gate; the second register is connected to the distribution switch for controlling the working state of the distribution switch, and the multi-way output ends of the second register are respectively connected to the first multi-way NAND gate and the first multi-way OR gate; the third register is connected to the antenna switch for controlling the working state of the antenna switch, and the multi-way output ends of the third register are respectively connected to the second multi-way NAND gate and the second multi-way OR gate. Because an output end of the first register, the output end of the first multi-way NAND gate, the output end of the first multi-way OR gate, the output end of the second multi-way NAND gate and the output end of the second multi-way OR gate are respectively connected to the first multi-way AND gate, and the output end of the first multi-way AND gate is connected to the power amplifier.

[0024] Therefore, only when the signals outputted by an output terminal of the first register, the output terminal of the first multi-way NAND gate, the output terminal of the first multi-way OR gate, the output terminal of the second multi-way NAND gate and the output terminal of the second multi-way OR gate are all 1, the signal outputted by the output terminal of the first multi-way AND gate is 1, and the power amplifier is enabled at this time. That is, when the output signal of the first register controlling the power amplifier to be enabled is 1, the power amplifier is enabled only when the second register and the third register are both in the normally open state, thereby avoiding the problem of being unable to accurately judge the working states of the power amplifier, the distribution switch and the antenna switch from the hardware. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0026] Figure 1 It is a functional schematic block diagram of a typical PAMiD module in the prior art;

[0027] Figure 2 This is a schematic diagram of the power-on / power-off timing of the PAMiD module;

[0028] Figure 3 A schematic diagram of the structure of a radio frequency module provided in an embodiment of the present application;

[0029] Figure 4 A schematic diagram of an implementation flow of an enabling method provided in an embodiment of the present application;

[0030] Figure 5 A schematic diagram of the structure of an enabling device provided in an embodiment of the present application;

[0031] Figure 6 A schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present application;

[0032] Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0033] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0034] The technical solutions provided by various embodiments of the present application are described in detail below in conjunction with the accompanying drawings.

[0035] From 2G to 5G, due to the continuous increase in RF frequency bands, the emergence of new technologies such as diversity reception, multi-input-multi-output (MIMO) reception and transmission, sounding reference signal (SRS) antenna rotation, and NSA (None-Stand-Alone) networking, the architectural design of the RF front-end of mobile terminals has become more and more complex. This makes the PCB motherboard area occupied by RF front-end devices larger and larger. And with the increasing demand for terminal functions, such as the increase in the number of cameras, the addition of various sensors, and the increase in battery capacity, a large amount of motherboard layout space is also occupied. This results in a smaller and smaller layout area left for the RF front-end on the PCB motherboard.

[0036] To solve this problem, many manufacturers have chosen to continuously iterate and reduce the size of discrete components such as power amplifiers, filters, and switches, and integrate these discrete components into the same module to form PAMiD (PA Module integrated Duplexer), PAMiF (PA Module integrated Filter), L-PAMiD (LNA / PA Module integrated Duplexer) modules, etc. Since these modules are integrated at the die level (chip level), the area occupied by discrete component packaging, routing, matching devices, and device safety spacing is reduced, which can effectively reduce the layout area of ​​the entire RF front end.

[0037] by Figure 1 The PAMiD RF module shown in the figure is working in the LTE B1 band. The signal amplification and reception are used as an example to introduce the working process of the PAMiD RF module in detail, including:

[0038] Step 1: The RF input signal is input through the MB_IN port and amplified by the RF power amplifier (RF power amplifier tube made by CMOS, GaAs and other processes). The register A has 8 bits, which can control the working state of the RF power amplifier, including high gain mode, low gain mode, Enable / Disable of the power amplifier and other states.

[0039] Step 2: In step 1, the signal amplified by the RF power amplifier is input to the distribution switch, which distributes the RF signal to the corresponding branch. Figure 1The signal of B1 passes through the distribution switch and enters the filter of B1 / 4TX to filter out the out-of-band noise. In this process, the opening and closing of the distribution switch branch is controlled by register B. Register B has 8 bits, and different logical combinations of the 8 bits of register B control the distribution switch to switch to different branches. Generally, when the 8-bit value of register B is in the state of 0000 0000, all branches of the distribution switch are closed, and when the 8-bit value of register B is in the state of 1111 1111, all branches are closed and in a high isolation state.

[0040] Step 3: After passing through the B1 / 4TX filter, the signal is input to the corresponding branch of the antenna switch, and then reaches the antenna port MB_ANT of the device after passing through the power detection coupler (CPL shown in the figure). The branch to which the antenna switch is switched is controlled by register C, which also has 8 bits. Different logical combinations of the 8 bits of register C control the switch to different branches. Generally, when the 8-bit value of register C is in the state of 0000 0000, all branches of the antenna switch are closed, and when the 8-bit value of register C is in the state of 1111 1111, all branches are closed and in a high isolation state.

[0041] Step 4: The received signal of B1 is received by the antenna and input to the MB_ANT port of the device. After passing through the same antenna switch branch as in step 3, it enters the B1 / 4 / 66RX receive filter and reaches the B66 (1 / 4RX) pin of the device. It then enters the external LNA or the LNA built into the transceiver for the next demodulation.

[0042] Step 5: The state of each bit value in each register is controlled by the CMOS controller, which receives the control signal sent by the RFFE MIPI interface composed of CLK and DATA lines, and translates the control signal into high and low level signals that can be recognized by each module to control the operation of each module. The controlled party in the embodiment of the present application is not limited to the above-mentioned register A, register B and register C. The RFFE MIPI interface is usually provided with a stable power supply of 1.8V by VIO, the power supply of the distribution switch and the antenna switch is provided by VBAT, and the power supply of the power amplifier is provided by VCC1 and VCC2.

[0043] because Figure 1 The registers A, B, and C in the RF module shown in the figure work completely independently, and independently control the working status of the power amplifier, distribution switch, and antenna switch. If register A controls the power amplifier to turn on, and the power amplifier is in a large signal amplification state, it is impossible to determine from the hardware whether registers B and C are in a normal open state. This will lead to the following situations:

[0044] (1) Due to incorrect instruction timing, the power amplifier is already operating in the normal large signal amplification state, while the distribution switch or antenna switch has not yet been opened.

[0045] (2) Due to incorrect instruction timing, the power amplifier is still working in the normal large signal amplification state, and the distribution switch or antenna switch is turned off.

[0046] (3) Due to other reasons, when the power amplifier is working in the large signal amplification state, the distribution switch or antenna switch is abnormally closed.

[0047] In view of this, in order to accurately determine the working status of the power amplifier, the distribution switch and the antenna switch, the present application provides a radio frequency module, an enabling method and an electronic device thereof.

[0048] Specifically, the RF module provided in the present application includes: first, a first register, a second register, a third register, a power amplifier, a distribution switch and an antenna switch, wherein: an output end of the first register is connected to a first multi-way AND gate; the second register is connected to the distribution switch for controlling the working state of the distribution switch, and the multiple output ends of the second register are respectively connected to the first multi-way NAND gate and the first multi-way OR gate; the third register is connected to the antenna switch for controlling the working state of the antenna switch, and the multiple output ends of the third register are respectively connected to the second multi-way NAND gate and the second multi-way OR gate; the output end of the first multi-way NAND gate, the output end of the first multi-way OR gate, the output end of the second multi-way NAND gate and the output end of the second multi-way OR gate are respectively connected to the first multi-way AND gate; the output end of the first multi-way AND gate is connected to the power amplifier.

[0049] Since an output end of the first register, an output end of the first multi-way NAND gate, an output end of the first multi-way OR gate, an output end of the second multi-way NAND gate, and an output end of the second multi-way OR gate are respectively connected to the first multi-way AND gate, and the output end of the first multi-way AND gate is connected to the power amplifier. Therefore, only when the signals output by an output end of the first register, the output end of the first multi-way NAND gate, the output end of the first multi-way OR gate, the output end of the second multi-way NAND gate, and the output end of the second multi-way OR gate are all 1, the signal output by the output end of the first multi-way AND gate is 1, and the power amplifier is enabled at this time. That is, when the output signal of the first register controlling the power amplifier to be enabled is 1, the power amplifier is enabled only when the second register and the third register are both in the normal open state, thereby avoiding the problem of being unable to accurately judge the working status of the power amplifier, the distribution switch, and the antenna switch from the hardware.

[0050] Combine the following Figure 3 The structure diagram of the RF module shown in FIG. 1 is a detailed introduction to the structure of the RF module, including:

[0051] A first register 301, a second register 302, a third register 303, a power amplifier 309, a distribution switch 310 and an antenna switch 311, wherein:

[0052] An output terminal of the first register 301 is connected to a first multi-way AND gate 304;

[0053] The second register 302 is connected to the distribution switch 310 and is used to control the working state of the distribution switch. The multi-way output terminals of the second register 302 are respectively connected to the first multi-way NAND gate 305 and the first multi-way OR gate 306;

[0054] The third register 303 is connected to the antenna switch 311 and is used to control the working state of the antenna switch 311. The multi-way output terminals of the third register 303 are respectively connected to the second multi-way NAND gate 307 and the second multi-way OR gate 308.

[0055] The output end of the first multi-way NAND gate 305, the output end of the first multi-way OR gate 306, the output end of the second multi-way NAND gate 307 and the output end of the second multi-way OR gate 308 are respectively connected to the first multi-way AND gate 304;

[0056] An output terminal of the first multi-way AND gate 304 is connected to the power amplifier 309 .

[0057] As an example, an output terminal of the first register 301 may be Figure 3 The output of Q2 is shown.

[0058] Among them, the first register that directly controls the power amplifier is composed of 8 bits with parallel input and parallel output, and each bit is a latch composed of a basic digital logic circuit. D0, D1, D2, ..., D7 are the input signals of the register, and Q0, Q1, Q2, ..., Q7 are the output signals of the register. In an embodiment of the present application, the third bit output signal Q2 of the first register is the enable signal of the power amplifier. When Q2 is 0, the power amplifier enable signal is turned off, and when Q2 is 1, the power amplifier enable signal is turned on. The other bits of the first register control other working states of the power amplifier, including but not limited to adjusting the high and low gain modes of the power amplifier, and adjusting the inter-stage matching of the power amplifier to enable the power amplifier to obtain the best performance in the corresponding frequency band. The corresponding table of the true value of the first register and the state of the power amplifier it controls is as follows:

[0059] Table 1 Correspondence between the true value of the first register and the state of the power amplifier it controls

[0060]

[0061]

[0062] The second register directly controlling the distribution switch 310 (DistributionSwitch) is composed of 8 bits with parallel input and parallel output, each bit is a latch composed of a basic digital logic circuit, D0, D1, D2, ..., D7 are input signals of the second register, and Q0, Q1, Q2, ..., Q7 are output signals of the second register. In the embodiment of the present application, the logic state of the 8-bit combination of the second register can control the distribution switch 310 to switch to different switch states, as shown in Table 2.

[0063] Table 2 Correspondence between the true value of the second register and the distributed switch state it controls

[0064]

[0065] The third register directly controlling the antenna switch 311 (AntennaSwitch) is composed of 8 bits of parallel input and parallel output, each bit is a latch composed of a basic digital logic circuit, D0, D1, D2, ..., D7 are input signals of the third register, and Q0, Q1, Q2, ..., Q7 are output signals of the third register. In the embodiment of the present application, the logic state of the 8-bit combination of the third register can control the antenna switch 311 to switch to different switch states, as shown in Table 3.

[0066] Table 3 Correspondence between the true value of the third register and the antenna switch state it controls

[0067]

[0068] The signal outputted from the multi-channel output terminal of the second register passes through the first multi-channel NAND gate to obtain the first signal, and the signal outputted from the multi-channel output terminal of the second register passes through the first multi-channel OR gate to obtain the second signal.

[0069] The 8 inputs of the first multi-way NAND gate are respectively connected to the 8-bit output bits Q0-Q7 of the second register. The 8-way signals corresponding to the 8-bit output bits Q0-Q7 of the second register are inverted and output after passing through the AND gate in the first multi-way NAND gate. The output signal is the first signal. The truth table of the first multi-way NAND gate when working is:

[0070] Table 4 Correspondence between the true value of the first multi-way NAND gate and the output signal value of the second register

[0071]

[0072] The 8 inputs of the first multi-way OR gate are respectively connected to the 8-bit output bits Q0 to Q7 of the second register. The 8-way signals output by the 8-bit output bits Q0 to Q7 of the second register are output after the logic OR operation in the first multi-way OR gate. The output signal is the second signal. The truth table of the first multi-way OR gate when working is:

[0073] Table 5 Correspondence between the true value of the first multi-way OR gate and the output signal value of the second register

[0074]

[0075] The signal outputted from the multiple output end of the third register passes through the second multiple-way NAND gate to obtain a third signal, and the signal outputted from the multiple output end of the third register passes through the second multiple-way OR gate to obtain a fourth signal.

[0076] The 8 inputs of the second multi-way NAND gate are respectively connected to the 8-bit output bits Q0 to Q7 of the third register. The 8-way signals output by the 8-bit output bits Q0 to Q7 of the third register are inverted after passing through the AND gate in the second multi-way NAND gate. The output signal is the third signal. The truth table of the second multi-way NAND gate when working is:

[0077] Table 6 Correspondence between the true value of the second multi-way NAND gate and the output signal value of the third register

[0078]

[0079] The 8 inputs of the second multi-way OR gate are respectively connected to the 8-bit output bits Q0 to Q7 of the third register. The 8-way signals output by the 8-bit output bits Q0 to Q7 of the third register are output after the logic OR operation in the second multi-way OR gate. The output signal is the fourth signal. The truth table of the second multi-way OR gate when working is:

[0080] Table 7 Correspondence between the true value of the second multi-way OR gate and the output signal value of the third register

[0081]

[0082]

[0083] A signal output from an output end of the first register, the first signal, the second signal, the third signal and the fourth signal pass through a first multi-way AND gate to obtain an enable signal of the power amplifier, and the enable signal of the power amplifier is used to enable the power amplifier.

[0084] The signal output from an output end of the first register, the first signal, the second signal, the third signal and the fourth signal are output to the RF amplifier power amplifier after the logic AND operation of the first multi-way AND gate, and the output signal is the enable signal of the power amplifier. The truth table of the first multi-way AND gate when working is:

[0085] Table 8 Correspondence between the truth value of the first multi-way AND gate and the signals of each channel

[0086]

[0087] It can be seen from Table 8 that the enable signal of the power amplifier can be in a high level state and the power amplifier can be turned on normally only when and only when the signal outputted by an output terminal of the first register, the first signal, the second signal, the third signal and the fourth signal are all 1. Among them:

[0088] (1) If the first signal is 1, it indicates that the 8 output bits of the second register cannot be in the distributed switch closed state of all 1s, that is, the distributed switch is in a non-closed state.

[0089] (2) If the second signal is 1, it indicates that the 8 output bits of the second register cannot be in the distribution switch closed state of all 0s, that is, the distribution switch is in a non-closed state.

[0090] (3) If the third signal is 1, it indicates that the 8 output bits of the third register cannot be in the antenna switch off state of all 1s, that is, the antenna switch is not in the off state.

[0091] (4) If the fourth signal is 1, it indicates that the 8 output bits of the third register cannot be in the antenna switch off state of all 0s, that is, the antenna switch is in a non-off state.

[0092] (5) A signal outputted from an output terminal of the first register is 1, indicating that the system needs to turn on the power amplifier at this time.

[0093] Obviously, when and only when the above five conditions are met at the same time, the enable signal of the power amplifier can be high level, and the power amplifier can be turned on normally. Otherwise, at any time, when the distribution switch and the antenna switch are in the off state, the enable signal sent by the Q2 bit of the A register that controls the ENABLE state of the power amplifier will be blocked by the first multi-way AND gate, and the power amplifier will not be turned on. This can effectively avoid the problem of electrical stress damage to the power amplifier when the distribution switch or the antenna switch is in the off state due to an incorrect instruction timing.

[0094] The radio frequency module provided in the embodiment of the present application includes a first register, a second register, a third register, a power amplifier, a distribution switch and an antenna switch, wherein: an output end of the first register is connected to a first multi-way AND gate; the second register is connected to the distribution switch for controlling the working state of the distribution switch, and the multi-way output ends of the second register are respectively connected to the first multi-way NAND gate and the first multi-way OR gate; the third register is connected to the antenna switch for controlling the working state of the antenna switch, and the multi-way output ends of the third register are respectively connected to the second multi-way NAND gate and the second multi-way OR gate. Because an output end of the first register, the output end of the first multi-way NAND gate, the output end of the first multi-way OR gate, the output end of the second multi-way NAND gate and the output end of the second multi-way OR gate are respectively connected to the first multi-way AND gate, and the output end of the first multi-way AND gate is connected to the power amplifier.

[0095] Therefore, only when the signals outputted by an output terminal of the first register, the output terminal of the first multi-way NAND gate, the output terminal of the first multi-way OR gate, the output terminal of the second multi-way NAND gate and the output terminal of the second multi-way OR gate are all 1, the signal outputted by the output terminal of the first multi-way AND gate is 1, and the power amplifier is enabled at this time. That is, when the output signal of the first register controlling the power amplifier to be enabled is 1, the power amplifier is enabled only when the second register and the third register are both in the normally open state, thereby avoiding the problem of being unable to accurately judge the working states of the power amplifier, the distribution switch and the antenna switch from the hardware.

[0096] Figure 4 A flowchart of an enabling method provided in an embodiment of the present application, which is applied to Figure 3 The RF module shown includes:

[0097] S410, obtaining an output signal of a first multi-channel AND gate.

[0098] S420, determining whether to enable a power amplifier based on an output signal of the first multi-path AND gate.

[0099] Optionally, determining whether to enable the power amplifier based on the output signal of the first multi-path AND gate includes:

[0100] If the output signal of the first multi-way AND gate is 1, the power amplifier is enabled;

[0101] If the output signal of the first multi-way AND gate is 0, the power amplifier is disabled.

[0102] In the embodiment of the present application, since the output signal of the first multi-way AND gate is obtained by ANDing the signals outputted from an output terminal of the first register, the output terminal of the first multi-way NAND gate, the output terminal of the first multi-way OR gate, the output terminal of the second multi-way NAND gate, and the output terminal of the second multi-way OR gate, that is, only when the signals outputted from an output terminal of the first register, the output terminal of the first multi-way NAND gate, the output terminal of the first multi-way OR gate, the output terminal of the second multi-way NAND gate, and the output terminal of the second multi-way OR gate are all 1, the signal outputted from the output terminal of the first multi-way AND gate is 1, and the power amplifier is enabled at this time. In other words, when the output signal of the first register controlling the power amplifier to be enabled is 1, the power amplifier is enabled only when the second register and the third register are both in the normally open state, thereby avoiding the problem of being unable to accurately judge the working status of the power amplifier, the distribution switch, and the antenna switch from the hardware.

[0103] An embodiment of the present application also provides an electronic device, which may include the radio frequency module described above.

[0104] See also Figure 5 , is a schematic diagram of the structure of an electronic device 500 provided in an embodiment of the present application, such as Figure 5 As shown, including:

[0105] An acquisition unit 501 is used to acquire the output signal of the first multi-channel AND gate;

[0106] The determination unit 502 is configured to determine whether to enable the power amplifier based on the output signal of the first multi-path AND gate.

[0107] In the embodiment of the present application, since the output signal of the first multi-way AND gate is obtained by ANDing the signals outputted from an output terminal of the first register, the output terminal of the first multi-way NAND gate, the output terminal of the first multi-way OR gate, the output terminal of the second multi-way NAND gate, and the output terminal of the second multi-way OR gate, that is, only when the signals outputted from an output terminal of the first register, the output terminal of the first multi-way NAND gate, the output terminal of the first multi-way OR gate, the output terminal of the second multi-way NAND gate, and the output terminal of the second multi-way OR gate are all 1, the signal outputted from the output terminal of the first multi-way AND gate is 1, and the power amplifier is enabled at this time. In other words, when the output signal of the first register controlling the power amplifier to be enabled is 1, the power amplifier is enabled only when the second register and the third register are both in the normally open state, thereby avoiding the problem of being unable to accurately judge the working status of the power amplifier, the distribution switch, and the antenna switch from the hardware.

[0108] Optionally, in one implementation, the determining unit 502 is configured to:

[0109] If the output signal of the first multi-way AND gate is 1, enabling the power amplifier;

[0110] If the output signal of the first multi-way AND gate is 0, the power amplifier is disabled.

[0111] The electronic device 500 provided in the embodiment of the present application can achieve Figure 4 To avoid repetition, the various processes implemented by the electronic device in the method embodiment are not described here.

[0112] Alternatively, if Figure 6 As shown, an embodiment of the present application also provides an electronic device 600, including a processor 601 and a memory 602, wherein the memory 602 stores programs or instructions that can be executed on the processor 601, and when the program or instructions are executed by the processor 601, the various steps of the above-mentioned enabling method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, they are not repeated here.

[0113] It should be noted that the electronic devices in the embodiments of the present application include the mobile electronic devices and non-mobile electronic devices mentioned above.

[0114] Figure 7 A hardware structure diagram of an electronic device 700 for implementing various embodiments of the present application is shown below:

[0115] The electronic device 700 includes but is not limited to: a radio frequency unit 701, a network module 702, an audio output unit 703, an input unit 704, a sensor 705, a display unit 706, a user input unit 707, an interface unit 708, a memory 709, a processor 710, and a power supply 711.

[0116] Those skilled in the art will appreciate that the electronic device 700 may also include a power source (such as a battery) for supplying power to each component, and the power source may be logically connected to the processor 710 through a power management system, thereby implementing functions such as managing charging, discharging, and power consumption management through the power management system. Figure 7 The electronic device structure shown in the figure does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently, which will not be described in detail here.

[0117] The processor 710 is configured to obtain an output signal of the first multi-channel AND gate; and determine whether to enable the power amplifier based on the output signal of the first multi-channel AND gate.

[0118] In the embodiment of the present application, since the output signal of the first multi-way AND gate is obtained by ANDing the signals outputted from an output terminal of the first register, the output terminal of the first multi-way NAND gate, the output terminal of the first multi-way OR gate, the output terminal of the second multi-way NAND gate, and the output terminal of the second multi-way OR gate, that is, only when the signals outputted from an output terminal of the first register, the output terminal of the first multi-way NAND gate, the output terminal of the first multi-way OR gate, the output terminal of the second multi-way NAND gate, and the output terminal of the second multi-way OR gate are all 1, the signal outputted from the output terminal of the first multi-way AND gate is 1, and the power amplifier is enabled at this time. In other words, when the output signal of the first register controlling the power amplifier to be enabled is 1, the power amplifier is enabled only when the second register and the third register are both in the normally open state, thereby avoiding the problem of being unable to accurately judge the working status of the power amplifier, the distribution switch, and the antenna switch from the hardware.

[0119] It should be understood that in the embodiment of the present application, the input unit 704 may include a graphics processor (Graphics Processing Unit, GPU) 7041 and a microphone 7042, and the graphics processor 7041 processes the image data of the static picture or video obtained by the image capture device (such as a camera) in the video capture mode or the image capture mode. The display unit 706 may include a display panel 7061, and the display panel 7061 may be configured in the form of a liquid crystal display, an organic light emitting diode, etc. The user input unit 707 includes a touch panel 7071 and at least one of other input devices 7072. The touch panel 7071 is also called a touch screen. The touch panel 7071 may include two parts: a touch detection device and a touch controller. Other input devices 7072 may include, but are not limited to, a physical keyboard, function keys (such as volume control keys, switch keys, etc.), a trackball, a mouse, and a joystick, which will not be repeated here.

[0120] The memory 709 can be used to store software programs and various data. The memory 709 may mainly include a first storage area for storing programs or instructions and a second storage area for storing data, wherein the first storage area may store an operating system, an application program or instructions required for at least one function (such as a sound playback function, an image playback function, etc.), etc. In addition, the memory 709 may include a volatile memory or a non-volatile memory, or the memory 709 may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDRSDRAM), an enhanced synchronous dynamic random access memory (ESDRAM), a synchronous link dynamic random access memory (SLDRAM) and a direct memory bus random access memory (DRRAM). The memory 709 in the embodiment of the present application includes but is not limited to these and any other suitable types of memory.

[0121] The processor 710 may include one or more processing units; optionally, the processor 710 integrates an application processor and a modem processor, wherein the application processor mainly processes operations related to an operating system, a user interface, and application programs, and the modem processor mainly processes wireless communication signals, such as a baseband processor. It is understandable that the modem processor may not be integrated into the processor 710.

[0122] An embodiment of the present application also provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the various processes of the above-mentioned enabling method embodiment are implemented and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0123] The processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory ROM, a random access memory RAM, a magnetic disk or an optical disk.

[0124] An embodiment of the present application further provides a chip, which includes a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned enabling method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0125] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0126] An embodiment of the present application provides a computer program product, which is stored in a storage medium. The program product is executed by at least one processor to implement the various processes of the enabling method embodiment described above, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0127] It should be noted that, in this article, the term "comprises", "includes" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the method and device in the embodiment of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0128] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, a disk, or an optical disk), and includes a number of instructions for a terminal (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0129] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A radio frequency module, characterized in that: The radio frequency module includes a first register, a second register, a third register, a power amplifier, a distribution switch and an antenna switch, wherein: An output terminal of the first register is connected to a first multi-way AND gate; The second register is connected to the distribution switch and is used to control the working state of the distribution switch, and the multi-way output terminals of the second register are respectively connected to the first multi-way NAND gate and the first multi-way OR gate; The third register is connected to the antenna switch and is used to control the working state of the antenna switch, and the multi-way output end of the third register is respectively connected to the second multi-way NAND gate and the second multi-way OR gate; The output end of the first multi-way NAND gate, the output end of the first multi-way OR gate, the output end of the second multi-way NAND gate and the output end of the second multi-way OR gate are respectively connected to the first multi-way AND gate; The output end of the first multi-way AND gate is connected to the power amplifier.

2. The radio frequency module according to claim 1, characterized in that: The signal outputted from the multi-channel output terminal of the second register passes through the first multi-channel NAND gate to obtain a first signal, and the signal outputted from the multi-channel output terminal of the second register passes through the first multi-channel OR gate to obtain a second signal.

3. The radio frequency module according to claim 2, characterized in that: The signal outputted from the multi-channel output terminal of the third register passes through the second multi-channel NAND gate to obtain a third signal, and the signal outputted from the multi-channel output terminal of the third register passes through the second multi-channel OR gate to obtain a fourth signal.

4. The radio frequency module according to claim 3, characterized in that: A signal output from an output end of the first register, the first signal, the second signal, the third signal and the fourth signal pass through the first multi-way AND gate to obtain an enable signal of the power amplifier, and the enable signal of the power amplifier is used to enable the power amplifier.

5. An electronic device, characterized in that: The electronic device comprises the radio frequency module described in any one of claims 1 to 4.

6. An enabling method, characterized in that: The method is applied to the radio frequency module or electronic device according to any one of claims 1 to 5, and the method comprises: Obtaining an output signal of the first multi-channel AND gate; Based on the output signal of the first multi-AND gate, it is determined whether to enable the power amplifier.

7. The method according to claim 6, characterized in that Determining whether to enable the power amplifier based on the output signal of the first multi-path AND gate includes: If the output signal of the first multi-way AND gate is 1, enabling the power amplifier; If the output signal of the first multi-way AND gate is 0, the power amplifier is disabled.

8. An electronic device, characterized in that: The electronic device is applied to the radio frequency module described in any one of claims 1 to 4, and the electronic device includes: An acquisition unit, used for acquiring an output signal of the first multi-channel AND gate; A determination unit is used to determine whether to enable the power amplifier based on the output signal of the first multi-path AND gate.

9. An electronic device, characterized in that: It comprises a processor and a memory, wherein the memory stores a program or instruction that can be run on the processor, and when the program or instruction is executed by the processor, the steps of the enabling method as described in any one of claims 6 to 7 are implemented.

10. A readable storage medium, characterized in that: The readable storage medium stores a program or instruction, and when the program or instruction is executed by the processor, the steps of the enabling method according to any one of claims 6 to 7 are implemented.

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