Data driving circuit, its clock recovery method, and display driving device having the same.

Abstract

This disclosure relates to a data driving circuit, its clock recovery method, and a display driving device having the same. Specifically, it relates to a data driving circuit, its clock recovery method, and a display driving device having the same, capable of improving clock and data recovery stability by generating a clock synchronized with input data. According to one aspect, a data driving circuit includes a receiver comprising: a clock and data recovery unit configured to recover a test data pattern from input data using an internal clock; and a data comparator configured to compare the recovered test data pattern with a predetermined reference data pattern to generate a control signal based on the degree of asynchrony between the recovered test data pattern and the reference data pattern, wherein the clock and data recovery unit recovers a clock synchronized with the input data according to the control signal, and uses the recovered clock to recover control information and image data from the input data.

Description

Technical Field

[0001] This disclosure relates to a data drive circuit capable of improving clock and data recovery stability by generating a clock synchronized with the input data, a clock recovery method for the data drive circuit, and a display drive device having the data drive circuit. Background Technology

[0002] The display device includes a panel configured to display an image via a pixel matrix, a gating driver configured to drive gating lines of the panel, a data driver configured to provide data signals to data lines of the panel, and a timing controller configured to control the gating driver and the data driver. The data driver includes multiple data driver integrated circuits (ICs) configured to divide and drive data lines.

[0003] The timing controller can serialize parallel data and transmit the serialized data to multiple data driver ICs, and each of the multiple data driver ICs can recover and use the clock and data information from the transmitted signals.

[0004] In a system where the timing controller and data driver IC are used to transmit and receive N-bit data strings, multiple data driver ICs can generate clocks with N phases, resulting in signals with N different delays at different receivers. From a system perspective, controlling N different asynchronous signals presents difficulties, and when the input data is asynchronous with the clock, the receiver struggles to accurately recover the received information. Summary of the Invention

[0005] This disclosure aims to provide a data drive circuit capable of improving clock and data recovery stability by generating a clock synchronized with the input data, its clock recovery method, and a display drive device having the data drive circuit.

[0006] According to one aspect of this disclosure, a data driving circuit is provided, comprising a receiver including: a clock and data recovery unit configured to recover a test data pattern from input data using an internal clock; and a data comparator configured to compare the recovered test data pattern with a predetermined reference data pattern to generate a control signal based on the degree of asynchrony between the recovered test data pattern and the reference data pattern, wherein the clock and data recovery unit can recover a clock synchronized with the input data according to the control signal, and uses the recovered clock to recover control information and image data from the input data.

[0007] According to another aspect of this disclosure, a clock recovery method for a data driving circuit is provided, the method comprising: recovering a test data pattern from input data using an internal clock; comparing the recovered test data pattern with a predetermined reference data pattern to generate a control signal based on an offset between the recovered test data pattern and the reference data pattern; and recovering a clock synchronized with the input data by selecting any one of a plurality of clocks with different phases included in the internal clock according to the control signal.

[0008] The method may further include generating an internal clock comprising a first clock and a second clock before restoring the test data mode, wherein, when generating the internal clock, a first clock whose phase is locked synchronously with the clock training mode sent from the timing controller may be generated, the first clock may be divided into N frequency-divided clocks having the same period as the period of the N-bit image data string (where N is an integer equal to or greater than 2) to generate N frequency-divided clocks with different phases, and one of the frequency-divided clocks may be output as the second clock.

[0009] The steps for restoring the test data pattern may include: shifting the serial input test data pattern provided as input data according to a first clock; and restoring the test data pattern by latching the shifted test data pattern according to a second clock and outputting the latched test data pattern in parallel.

[0010] The steps of generating the control signal may include: comparing the recovered test data pattern with the reference data pattern and detecting the number of bits shifted by the recovered test data pattern compared with the reference data pattern as an offset; and generating a control signal for selecting a second clock from N divided clocks based on the detected offset.

[0011] According to another aspect of this disclosure, a display driving device is provided, comprising: a timing controller including a transmitter; and a plurality of data driving circuits, each of the data driving circuits including a receiver connected to the transmitter of the timing controller via each transmission channel, wherein the receiver may include: a clock and data recovery unit configured to recover a test data pattern from input data transmitted by the transmitter using an internal clock; and a data comparator configured to compare the recovered test data pattern with a predetermined reference data pattern to generate a control signal based on an offset between the recovered test data pattern and the reference data pattern, wherein the clock and data recovery unit may recover a clock synchronized with the input data based on the control signal, and recover control information and image data from the input data using the recovered clock.

[0012] The clock and data recovery unit may include: a clock generator configured to generate and output a first clock whose phase is locked synchronously with a clock training mode transmitted from the transmitter, divide the first clock into clocks with the same period as the period of an N-bit image data string (where N is an integer greater than or equal to 2), generate N divided clocks with different phases, and select and output a second clock from the divided clocks according to a control signal of a data comparator; and a deserializer configured to convert the serial input data into parallel data using the first and second clocks, and output the parallel data.

[0013] The deserializer can recover the test data pattern by shifting the serial input test data pattern provided as input data according to a first clock, latching the shifted test data pattern according to a second clock, and outputting the latched test data pattern in parallel.

[0014] The deserializer may include: a first register comprising N first flip-flops connected in series to the data input lines and configured to shift an input test data pattern input in units of N bit strings according to a first clock; and a second register comprising N second flip-flops connected in parallel to the N first flip-flops and configured to latch the N-bit test data pattern from the first register according to a second clock and output the latched test data pattern in parallel.

[0015] The data comparator compares the recovered test data pattern with the reference data pattern, detects the number of bits shifted between the recovered test data pattern and the reference data pattern as the degree of asynchrony, generates a control signal for selecting the second clock from N divided clocks based on the detected degree of asynchrony, and outputs the control signal to the clock generator.

[0016] The receiver can generate an internal clock using the serial form of the clock training mode sent from the transmitter during the first time period; using the internal clock, it can restore the serial form of the test data mode sent from the transmitter without a clock during the second time period to a parallel form of the test data mode, and use the restored test data mode to restore a clock synchronized with the input data; using the restored clock, it can restore the serial form of the control information sent from the transmitter without a clock during the third time period to a parallel form of the control information; and using the restored clock, it can restore the serial form of the image data sent from the transmitter without a clock during the fourth time period to a parallel form of the image data.

[0017] The first and second time periods may be included in the initial driving period before providing image data for each frame, the third time period may be included in the blanking period of each frame, and the fourth time period is included in the active period of each frame. The first and second time periods may also be included before the third time period of the blanking period of each frame.

[0018] The receiver may also include a receive buffer configured to receive the transmitted signal in differential signal form, convert the transmitted signal into input data, and output the input data to the clock and data recovery unit. Attached Figure Description

[0019] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the disclosure and, together with the description, serve to illustrate the principles of the disclosure. In the drawings:

[0020] Figure 1 This is a block diagram illustrating the construction of a display device according to one embodiment;

[0021] Figure 2 This is a block diagram illustrating a display driving device according to one embodiment of the present disclosure;

[0022] Figure 3 This is a block diagram illustrating the internal structure of each data-driven integrated circuit (IC) according to one implementation method;

[0023] Figure 4 This is a block diagram illustrating the construction of a transmitter and receiver of a display driving device according to one embodiment;

[0024] Figure 5 This is a block diagram illustrating the construction of a receiver for a data-driven IC according to one embodiment;

[0025] Figure 6 This is a flowchart illustrating a clock recovery method for a data driver IC according to one embodiment; and

[0026] Figure 7 This is a driving waveform diagram illustrating the clock recovery operation of the receiver of a data driver IC according to one embodiment. Detailed Implementation

[0027] The advantages and features of this disclosure, and its implementation methods, will become clear from the following embodiments described with reference to the accompanying drawings. However, this disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is limited only by the scope of the claims.

[0028] The shapes, dimensions, scales, angles, and quantities shown in the accompanying drawings to describe embodiments of this disclosure are merely examples, and therefore, this disclosure is not limited to the details shown. Throughout the specification, the same reference numerals denote the same elements. In the following description, detailed descriptions of relevant known functions or configurations will be omitted where it would unnecessarily obscure the focus of this disclosure.

[0029] When using the terms "comprising," "having," and "including" as described in this specification, another component may be added unless "only" is used. Unless otherwise stated, singular terms may include plural forms.

[0030] When interpreting a component, although it is not explicitly described, it is interpreted as including a range of error.

[0031] When describing positional relationships, for example, when the positional relationship between two components is described as “on,” “above,” “below,” and “next to,” one or more other components may be positioned between the two components unless more restrictive terms such as “adjacent” or “directly” are used.

[0032] When describing temporal relationships, such as when time sequence is described as “after,” “following,” “next,” and “before,” discontinuous situations may be included unless more restrictive terms such as “immediately,” “immediately,” or “directly” are used.

[0033] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0034] In describing the elements of this disclosure, the terms “first,” “second,” “A,” “B,” “(a),” “(b),” etc., may be used. These terms are intended to identify corresponding elements in relation to other elements, and the basis, order, or number of corresponding elements shall not be limited by these terms. The expression “connected,” “linked,” or “attached” to another element or layer, unless otherwise specified, indicates that the element or layer may be directly connected or attached to another element or layer, or indirectly connected or attached to another element or layer, and one or more intermediate elements or layers are “disposed” between these elements or layers.

[0035] The term "at least one" should be understood to include any and all combinations of one or more of the associated listed elements. For example, "at least one or more of the first element, the second element, and the third element" means a combination of all elements derived from two or more of the first element, the second element, and the third element, as well as the first element, the second element, or the third element.

[0036] As will be fully understood by those skilled in the art, the features of the various embodiments of this disclosure may be partially or wholly linked or combined with each other, and may be interoperable and technically driven differently. Embodiments of this disclosure may be implemented independently of each other, or may be implemented together in an interdependent manner.

[0037] In the following, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0038] Figure 1 This is a block diagram schematically illustrating the construction of a display device according to one embodiment, while Figure 2 This is a block diagram illustrating a display driving device including multiple data driver integrated circuits (ICs) and a timing controller according to one embodiment.

[0039] The display device according to one embodiment can be any of a variety of display devices, including liquid crystal display devices, electroluminescent display devices, and micro light-emitting diode (LED) display devices. The electroluminescent display device can be an organic light-emitting diode (OLED) display device, a quantum dot light-emitting diode display device, or an inorganic light-emitting diode display device.

[0040] Reference Figure 1 The display device may include a display panel 100, a gating driver 200, a data driver 300, a gamma voltage generator 500, a timing controller 400, etc. The gating driver 200 and the data driver 300 can be defined as panel drivers. The gating driver 200, the data driver 300, and the timing controller 400 can be defined as display drivers.

[0041] The display panel 100 displays images through a display area DA, in which sub-pixels P are arranged in a matrix. Each sub-pixel P is one of a red sub-pixel emitting red light, a green sub-pixel emitting green light, a blue sub-pixel emitting blue light, and a white sub-pixel emitting white light, and can be independently driven by at least one thin-film transistor (TFT). A unit pixel can be configured by a combination of two, three, or four sub-pixels with different colors.

[0042] The gate electrode of the TFT belonging to each sub-pixel P is connected to the gate driver 200 through a gate line provided on the display panel 100, and the input electrode of either the source electrode or the drain electrode of each TFT is connected to the data driver 300 through a data line provided on the display panel 100.

[0043] In other words, in each sub-pixel P, when the TFT is turned on in response to a scan pulse of the gate turn-on voltage provided from the gate driver 200 through the corresponding gate line, the pixel voltage (driving voltage) corresponding to the data signal is charged by receiving the data signal provided from the data driver 300 through the corresponding data line via the turned-on TFT, and light corresponding to the charged voltage is emitted, so that the gray level corresponding to the data signal can be represented.

[0044] The display panel 100 may also include a touch sensor screen that completely overlaps with the display area and is configured to sense the user's touch, and the touch sensor screen may be embedded in the panel 100 or disposed in the display area of ​​the panel 100.

[0045] The timing controller 400 can receive image data and synchronization signals from a host system (not shown). For example, the host system can be any system including a computer, a TV system, a set-top box, or a portable terminal such as a tablet or mobile phone. Synchronization signals can include a dot clock, a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, etc.

[0046] The timing controller 400 can use the received synchronization signal and the timing setting information (start timing, pulse width, etc.) stored in the internal register to generate multiple data control signals to provide multiple data control signals to multiple data drivers 300, and generate multiple gating control signals to provide multiple gating control signals to gating drivers 200.

[0047] The timing controller 400 can perform various types of image processing on the provided image data, such as brightness correction for reducing power consumption, image quality correction, etc., and provide the image-processed data to the data driver 300.

[0048] The gamma voltage generator 500 can generate a reference gamma voltage set including multiple reference gamma voltages with different voltage levels, and provide the reference gamma voltage set to the data driver 300. Under the control of the timing controller 400, the gamma voltage generator 500 can generate multiple reference gamma voltages corresponding to the gamma characteristics of the display device, and provide the reference gamma voltages to the data driver 300. The gamma voltage generator 500 may include a programmable gamma IC, and can receive gamma data from the timing controller 400, generate or adjust the reference gamma voltage level according to the gamma data, and output the reference gamma voltage level to the data driver 300.

[0049] The gating driver 200 is controlled by multiple gating control signals provided from the timing controller 400 to individually drive the gating lines of the display panel 100. The gating driver 200 can drive multiple gating lines sequentially. The gating driver 200 can provide a scan signal of the gate on voltage to the corresponding gating line during the driving period of each gating line, and provide a scan signal of the gate off voltage to the corresponding gating line during the non-driving period of each gating line.

[0050] The gate driver 200 may include at least one gate driver IC and may be mounted on a circuit film such as tape-on-film (TCP), chip-on-film (COF), or flexible printed circuit (FPC) to be attached to the display panel 100 in a tape-on-board (TAB) manner, or may be mounted on the display panel 100 in a chip-on-glass (COG) manner. Alternatively, the gate driver 200 may be formed on a TFT substrate together with the TFTs belonging to each sub-pixel P of the display panel 100 and embedded in the bezel area of ​​the display panel 100.

[0051] The data driver 300 can be controlled according to the data control signal provided from the timing controller 400, and can convert the digital image data provided from the timing controller 400 into analog data signals and provide the analog data signals to each data line of the display panel 100. The data driver 300 can convert digital image data into analog data signals using grayscale voltages obtained by subdividing multiple reference gamma voltages provided from the gamma voltage generator 500.

[0052] The data driver 300 may include at least one data driver IC and may be mounted on a circuit film such as TCP, COF, FPC, etc. to be attached to the display panel 100 in a TAB manner, or may be mounted in the bezel area of ​​the display panel 100 in a COG manner.

[0053] Reference Figure 2The data driver 300 may include multiple data driver ICs D-IC1 to D-ICn connected between the timing controller (TCON) 400 and the display panel 100 and configured to divide and drive multiple data lines of the display panel 100.

[0054] To reduce the number of transmission lines and electromagnetic interference (EMI), the timing controller 400 of the display driver and multiple data driver ICs D-IC1 to D-ICn can send and receive data via a high-speed serial interface method that converts parallel data into serial data and transmits the serial data in a point-to-point manner.

[0055] For a high-speed serial interface, the timing controller 400 may include a transmitter TX, and each of the multiple data driver ICs D-IC1 to D-ICn may include a receiver RX, and the transmitter TX and each of the multiple receivers RX may be connected in a point-to-point manner through multiple transmission channels TL1 to TLn.

[0056] The transmitter TX of the timing controller 400 can convert serial data into differential signals such as Low Voltage Differential Signaling (LVDS) or Mini LVDS, and can transmit the differential signals to the receiver RX of each of multiple data driver ICs D-IC1 to D-ICn through each of multiple transmission channels TL1 to TLn. Each of the transmission channels TL1 to TLn may include a pair of wires for transmitting the differential signal, or may include multiple pairs of wires, such as two pairs or four pairs of wires. The transmitter TX can transmit serial transmission data without a clock, or it can transmit serial transmission data with a clock embedded in it.

[0057] The serially transmitted data may include an N-bit image data string (where N is a positive integer) corresponding to each sub-pixel, and may include multiple data control signals. Additionally, the serially transmitted data may include a clock training mode for locking the clock generator in the receiver RX of each of the multiple data driver ICs D-IC1 to D-ICn, and may include a test data mode for accurately synchronizing the clock generated by each receiver RX with the input data.

[0058] For example, the transmitter TX can serially send a clock training mode to the receiver RX of each of the data driver ICs D-IC1 to D-ICn during a first time period, and each receiver RX can generate a lock signal when the clock generator uses the input clock training mode to lock and generate multiple clocks. Lock signals can be generated sequentially from the receiver RX of each of the multiple data driver ICs D-IC1 to D-ICn, and the lock signal generated from the receiver RX of the last data driver IC D-ICn can be transmitted to the transmitter TX of the given time controller 400.

[0059] During the second time period, the transmitter TX can serially send test data patterns to the receiver RX of each of the data driver ICs D-IC1 to D-ICn, and each receiver RX can recover the test data pattern from the input data using the output clock of the clock generator. Each receiver RX can detect the degree of asynchrony (offset) between the clock and the input data by comparing the recovered test data pattern with a predetermined reference data pattern. Each receiver RX can recover a clock that is accurately synchronized with the input data by controlling the output of the clock generator according to the detected degree of asynchrony (offset).

[0060] The transmitter TX can send control information to the receiver RX of each of the data driver ICs D-IC1 to D-ICn during the third time period, and send image data to each receiver RX during the fourth time period. Each receiver RX can accurately sample and recover the data control signal from the input data using a clock synchronized with the input data, and can also accurately sample and recover the image data.

[0061] The first time period of the transmit and receive clock training mode and the second time period of the transmit and receive test data mode can be included in the initial drive period before the display device is powered on and displays the image of each frame. The third time period of the transmit and receive data control signals can be included in the blanking period (vertical blanking period or horizontal blanking period) of each frame, and the fourth time period of the transmit and receive image data can be included in the active period of each frame. In addition, the first and second time periods can also be included before the third time period of the blanking period of each frame.

[0062] Figure 3 This is a block diagram illustrating the internal structure of various data driver ICs according to one implementation.

[0063] Reference Figure 3 Each data driver IC D-ICn may include a receiver (RX) 310, a shift register 362, latch units 364 and 366, a grayscale voltage generator 367, a digital-to-analog converter (DAC) unit 368, and an output buffer unit 370.

[0064] Each data driver IC D-ICn can provide corresponding data signals to m data lines among the data lines set in the display panel 100 through multiple (m) output channels CH1 to CHm (where m is a positive integer).

[0065] Each data driver IC D-ICn's receiver (RX) 310 can receive differential signal transmissions from the timing controller 400 via a high-speed serial interface, and can recover clock, image data, and control signals from the input transmissions to send the recovered clock, image data, and control signals to the logic controller 350.

[0066] Specifically, the receiver (RX) 310 can recover a clock that is accurately synchronized with the input data based on the comparison result between the test data pattern sent from the timing controller 400 and the predetermined reference data pattern, and can use the recovered clock to accurately sample and recover image data and control signals. The detailed clock recovery method of the receiver (RX) 310 will be described below.

[0067] The logic controller 350 can rearrange the image data of each sub-pixel unit provided from the receiver (RX) 310 according to the operation options, and output the rearranged image data to the first latch unit 364. The logic controller 350 can use the clock and data control signals provided from the receiver 310 to output a start pulse and shift clock to the shift register 362, and output load signals to the second latch unit 366, the output buffer unit 370, etc., and further generate and output control signals required for the operation of other components.

[0068] The shift register 362 can sequentially output multiple sampled signals to the first latch unit 364 while simultaneously shifting the start pulse according to the shift clock. The shift register 362 can include multiple channel stages, and while performing a shift operation to sequentially shift the start pulse according to the shift clock, it can sequentially output multiple channel sampled signals to the first latch unit 364. The shift register 362 can include m channel stages, equal to the number of output channels CH1 to CHm, and can also include fewer than m stages.

[0069] The first latch unit 364 can sequentially latch each data line from multiple channels transmitted sequentially from the receiver 310 via the data bus for each channel of each sub-pixel unit in response to the sampling signals of multiple channels sequentially input from the shift register 362. When all data lines of all channels are latched, the first latch unit 364 can simultaneously output the latched data of each channel to the second latch unit 366. The first latch unit 364 may include m first latches, the number of which is equal to the number of output channels CH1 to CHm.

[0070] The second latch unit 366 can simultaneously output data from each channel (sub-pixel) received from the first latch unit 364 to the DAC unit 368 in response to a load signal provided from the logic controller 350. The second latch unit 366 may include m second latches, the same number as the output channels CH1 to CHm.

[0071] The grayscale voltage generator 367 can divide the reference gamma voltage provided by the gamma voltage generator 500 into multiple grayscale voltages that correspond to the grayscale values ​​of the image data by dividing the reference gamma voltage through a resistor string, and then output the subdivided grayscale voltages to the DAC unit 368.

[0072] The DAC unit 368 can use the gray level voltage provided by the gray level voltage generator 367 to convert the data of each sub-pixel provided by the second latch unit 366 into an analog data signal for each channel, and output the analog data signal to the output buffer unit 370. The DAC unit 368 may include m channels equal to the number of channels CH1 to CHm.

[0073] The output buffer unit 370 can buffer the data signal of each sub-pixel provided from the DAC unit 368 for each channel, and output the buffered data signal to each of the plurality of output channels CH1 to CHm. The output buffer unit 370 may include m output buffers, the same number as the number of output channels CH1 to CHm.

[0074] Figure 4 This is a block diagram illustrating the construction of a transmitter of a timing controller and a receiver of a data driver IC in a display driving device according to one embodiment.

[0075] Reference Figure 4 Each data driver IC D-ICn receiver (RX) 310 may include an LVDS RX 320 as a receive buffer, a clock and data recovery (CDR) unit 330, and a data comparator 340.

[0076] The transmitter TX 410 of the timing controller 400 can convert serially transmitted data into differential signals in LVDS format and send the differential signals to the receiver (RX) 310 of each data driver IC D-ICn through each transmission channel TLn. The serially transmitted data can include clock training mode, test data mode, control information, image data, etc.

[0077] The LVDS RX 320, acting as a receive buffer, can receive differential signals in LVDS form sent from the transmitter TX 410 of the timing controller 400 through each transmission channel TLn, convert the received differential signals into serial data, and output the serial data.

[0078] The CDR unit 330 can generate and output a phase-locked first clock using the input clock training mode during a first time period, divide the first clock by N to generate a second clock with N different phases, and output any one of the N second clocks. The CDR unit 330 can use a phase-locked loop (PLL) or a delay-locked loop (DLL) as a clock generator to generate multiple clocks including the first clock and multiple second clocks.

[0079] The CDR unit 330 can use the first clock and the second clock during the second time period to recover the test data mode from the input data mode and output the recovered test data mode to the data comparator 340.

[0080] The data comparator 340 can compare the degree of asynchrony (offset) between the test data pattern recovered by the CDR unit 330 and the predetermined reference data pattern, generate a control signal based on the comparison result, and output the control signal to the CDR unit 330.

[0081] The CDR unit 330 can restore the second clock that is accurately synchronized with the input data by selecting and outputting any second clock that is synchronized with the input data from among the N phases of the second clock according to the control signal provided from the data comparator 340.

[0082] The CDR unit 330 can accurately sample and recover data control signals from the input data during the third time period using the first clock and the recovered second clock, and can accurately sample and recover image data from the input data during the fourth time period.

[0083] Figure 5 This is a block diagram illustrating the structure (mainly clock and data recovery unit) of a receiver of a data driver IC according to one embodiment.

[0084] Reference Figure 5The CDR unit 330 may include: a PLL 332, which is a clock generator configured to generate multiple clocks; and a deserializer 334, which is configured to convert an N-bit serial data string into parallel data.

[0085] The PLL 332 can receive the clock training mode via the LVDS RX 320 during the first time period and generate and output a phase-locked loop (PLL) first clock of x MHz synchronized with the clock training mode. Simultaneously, the PLL 332 can divide the first clock of x MHz by N to generate N phase-divided clocks. Each phase-divided clock has the same period as the N-bit data string, and its phase is sequentially delayed by one bit (the period of the first clock). The PLL 332 can select a second clock from the N phase-divided clocks and output the selected second clock. The PLL 332 can output the first clock of x MHz to the deserializer 334 and can output the second clock of x / N MHz to both the deserializer 334 and the data comparator 340.

[0086] The deserializer 334 can use the output clocks x MHz and x / N MHz of the PLL 332 to convert an N-bit serial data string input through the LVDS RX 320 into N-bit parallel data and output the parallel data. The deserializer 334 can output the recovered test data pattern to the data comparator 340 by converting the test data pattern input during the second time period into a parallel form.

[0087] Therefore, the deserializer 334 may include a first register 336 having N first D flip-flops (D-FFs) connected in series to the data input lines and a second register 338 having N second D flip-flops (D-FFs) connected in parallel to the N-bit output of the first register 336.

[0088] In the first register 336, the first D flip-flop D-FF connected in series can sequentially shift N bits of serial data according to the first clock x MHz output from PLL 332, and output the shifted parallel N bits of data to the second register 338.

[0089] In the second register 338, the second D flip-flop D-FF connected in parallel can simultaneously sample and latch N bits of data output in parallel from the first register 336 according to the second clock x / N MHz output from the PLL 332, and output the latched N bits of parallel data.

[0090] Data comparator 340 can compare the test data pattern recovered by deserializer 334 with a predetermined reference data pattern during the second time period, and detect the degree of asynchrony (offset) between the recovered test data pattern and the reference data pattern, thereby detecting the degree of asynchrony (offset) between the second clock output from PLL 332 and the input data. Data comparator 340 can generate a Mux selection signal as a control signal based on the detected degree of asynchrony, and output the Mux selection signal to PLL 332.

[0091] PLL 332 can select and output a second clock synchronized with the input reference data mode from the N-phase divided clock according to the Mux selection signal provided from the data comparator 340, thereby restoring the second clock x / NMHz synchronized with the input data.

[0092] The deserializer 334 can recover the data control signal, which was input as serial data, during the third time period by accurately sampling the data control signal using a first clock x MHz output from the PLL 332 and the recovered second clock x / N MHz, and converting the data control signal into parallel form. The recovered data control signal is then output to a reference. Figure 3 The logic controller 350 is described.

[0093] The deserializer 334 can accurately sample the image data using a first clock x MHz output from the PLL 332 and a recovered second clock x / N MHz, convert the image data into parallel form, recover the image data that was input as serial data during the fourth time period, and output the recovered image data to a reference. Figure 3 The logic controller 350 is described.

[0094] Figure 6 A flowchart illustrating a clock recovery method for a data driver IC according to one embodiment is provided, and Figure 7 This is a driving waveform diagram illustrating the clock recovery operation of the receiver of a data driver IC according to one embodiment.

[0095] Figure 6 The clock recovery method shown and Figure 7 The driving waveform shown can be derived from... Figure 5 The data driver IC shown operates in receiver RX mode, and therefore will be combined with Figures 5 to 7 Describe it.

[0096] Reference Figures 5 to 7The CDR unit 330 can receive a clock training mode as serial data input from the timing controller 400 via the LVDS RX320 during a first time period, and can receive multiple test data modes A0 to A3, B0 to B3, C0 to C3, and D0 to D3 as serial data input during a second time period. Each of the test data modes A0 to A3, B0 to B3, C0 to C3, and D0 to D3 sent from the timing controller 400 has an N-bit string consisting of N bits equal to the image data and has the same pattern as the predetermined reference data mode of the data comparator.

[0097] When the phase of the clock generated based on the input frequency is latched synchronously with the clock training mode input during the first time period, the PLL 332 can output a PLL latch signal (S602) in the active state (high logic state).

[0098] PLL 332 can generate and output a first clock x MHz synchronized with the clock training mode during the first time interval t10 (S604). Additionally, PLL 332 can divide the first clock x MHz by N to generate N phase-divided clocks x / N MHz_P0, x / N MHz_P1, x / N MHz_P2, and x / N MHz_P3. The period of each divided clock is equal to the period of the N bit string, and each divided clock has a different phase per bit (the period of the first clock). PLL 332 selects the first divided clock x / N MHz_P0 according to the initial Mux selection signal (0) and outputs the first divided clock x / N MHz_P0 as the second clock x / N MHz (S604). PLL 332 can output the first clock x MHz to the deserializer 334 and can output the second clock x / N MHz (=x / N MHz_P0) to both the deserializer 334 and the data comparator 340.

[0099] The deserializer 334 can start from the second timer t20 during the second time period, and sample each of the test data patterns A0 to A3, B0 to B3, C0 to C3 and D0 to D3 that are sequentially input as serial data in units of N-bit strings according to the first clock x MHz and the second clock x / N MHz (=x / N MHz_P0) output from the PLL 332. It can also convert each of the test data patterns A0 to A3, B0 to B3, C0 to C3 and D0 to D3 into N-bit parallel data, thereby recovering the test data pattern, and outputting the recovered test data pattern to the data comparator 340.

[0100] The data comparator 340 can receive the recovered test data pattern from the deserializer 334 in each cycle of the second clock x / N MHz (=x / N MHz_P0) output from the PLL 332, and compare the received test data pattern with a predetermined reference data pattern (S606). The reference data pattern can be preset to be the same as the test data pattern sent from the timing controller and stored in the data comparator 340. Figure 7 In this context, "reference data" refers to the predetermined reference data pattern in the data comparator 340, while "x / N D-FF output data" refers to the test data pattern recovered and output by the deserializer 334.

[0101] The data comparator 340 can compare the test data pattern recovered according to the second clock with the reference data pattern to detect the degree of asynchrony (offset), and determine whether the second clock x / N MHz output from the PLL 332 is synchronized with the test data pattern by comparing the recovered test data pattern with the predetermined reference data pattern (S606).

[0102] When it is determined that the second clock x / N MHz (=x / N MHz_P0) of PLL 332 is asynchronous with the test data mode (S606, No), the data comparator 340 can generate a Mux selection signal according to the degree of asynchrony (offset) between the test data mode and the reference data mode, and output the Mux selection signal to PLL 332 (S608).

[0103] For example, as a comparison result between the test data patterns X and A0 to A2, A3 and B0 to B2, and B3 and C0 to C2 recovered by the deserializer 334 in each cycle of the second clock x / N MHz (=x / N MHz_P0) of PLL 332 and the predetermined reference data patterns A0 to A3, B0 to B3, and C0 to C3, the data comparator 340 can detect that the recovered test data patterns X and A0 to A2, A3 and B0 to B2, and B3 and C0 to C2 are offset by one bit compared with the reference data patterns A0 to A3, B0 to B3, and C0 to C3, and generate a Mux selection signal (1) corresponding to the detected offset (the number of bits offset) and output the Mux selection signal (1) to PLL 332. Figure 7 In this context, "select data" refers to the Mux selection signal output from the data comparator 340.

[0104] PLL 332 can perform the operation of switching the phase of the second clock x / N MHz according to the Mux selection signal (1) provided from the data comparator 340 at the third time t30, and select the second divided clock x / N MHz_P1 with a phase delay of one bit from the N divided clocks x / N MHz_P0, x / N MHz_P1, x / N MHz_P2 and x / N MHz_P3 according to the Mux selection signal (1) at the fourth time t40, so as to output the second divided clock x / N MHz_P1 as the second clock x / N MHz (S604).

[0105] The deserializer 334 can use the first clock x MHz and the second clock x / N MHz (=x / NMHz_P1) output from the PLL 332 to convert the test data patterns A0 to A3, B0 to B3, C0 to C3 and D0 to D3, which are input as N-bit serial data strings, into parallel form, and output the test data patterns A0 to A3, B0 to B3, C0 to C3 and D0 to D3 to the data comparator 340 as the recovered test data patterns.

[0106] When the test data pattern output from the deserializer 334 is received in each cycle of the second clock x / N MHz (=x / N MHz_P1) output from the PLL 332 and the test data pattern is compared with the predetermined reference data pattern, and it is determined that the second clock x / N MHz (=x / N MHz_P1) of the PLL 332 is synchronized with the test data pattern (S606, Yes), the data comparator 340 can maintain the Mux selection signal (1) of the previous period.

[0107] Therefore, PLL 332 can maintain the output of a second clock x / N MHz (=x / N MHz_P1) by selecting and outputting a divided clock x / N MHz_P1 that is the same as the divided clock of the previous time period according to the held Mux selection signal (1). Therefore, PLL 332 can output a second clock x / N MHz (=x / N MHz_P1) that is accurately synchronized with the input data in the subsequent time period (S610).

[0108] Therefore, during the third and fourth time periods following the second time period, the deserializer 334 can use the first clock xMHz and the second clock x / N MHz output from the PLL332 to convert the data control signals and image data, which are serial data inputs, into parallel data and output the parallel data.

[0109] As described above, the data driving circuit, the clock recovery method of the data driving circuit, and the display driving device according to one embodiment can detect the degree of asynchrony (offset) by comparing a test data pattern recovered from the input data using any clock of the PLL with a predetermined reference data pattern, and recover a clock that is accurately synchronized with the input data by selecting the output clock in the PLL according to the detected degree of asynchrony (offset), and accurately recover the input data using the recovered clock, thereby improving the internal stability of the driving system.

[0110] The data driving circuit and display driving device including the data driving circuit according to the embodiments can be applied to various electronic devices. For example, the data driving circuit and display driving device including the data driving circuit according to the embodiments can be applied to mobile devices, video phones, smartwatches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, bending devices, electronic notebooks, e-books, portable multimedia players (PMPs), personal digital assistants (PDAs), MPEG audio layer 3 players, mobile medical devices, desktop personal computers (PCs), laptop PCs, netbooks, workstations, navigation devices, in-vehicle navigation devices, in-vehicle display devices, televisions, wallpaper display devices, signage devices, gaming devices, laptop computers, monitors, cameras, camcorders, home appliances, etc.

[0111] The features, structures, effects, etc., described above in the various examples of this disclosure are included in at least one example of this disclosure, and are not necessarily limited to one example. Furthermore, those skilled in the art to which the technical concept of this disclosure pertains can combine or modify the features, structures, effects, etc., shown in at least one example of this disclosure with respect to other examples. Therefore, the content relating to these combinations and modifications should be interpreted as being included within the technical spirit or scope of this disclosure.

[0112] While this disclosure is not limited to the embodiments and drawings described above, it will be apparent to those skilled in the art that various substitutions, modifications, and alterations can be made therein without departing from the scope of this disclosure. Therefore, the scope of this disclosure is defined by the appended claims, and all changes or modifications derived from the meaning, scope, and equivalents of the claims should be construed as being included within the scope of this disclosure.

[0113] Cross-reference to related applications

[0114] This application claims priority to Korean Patent Application No. 10-2020-0178114, filed on December 18, 2020, which is incorporated herein by reference as if fully set forth herein.

Claims

1. A data driving circuit, the data driving circuit including a receiver, the receiver comprising: A clock and data recovery unit configured to recover test data mode from input data using an internal clock; as well as A data comparator is configured to compare a recovered test data pattern with a predetermined reference data pattern to generate a control signal based on the degree of asynchrony between the recovered test data pattern and the reference data pattern. The clock and data recovery unit generates multiple clocks included in the internal clock through clock training, recovers a clock synchronized with the input data according to the control signal, and uses the recovered clock to recover control information and image data from subsequent input data received after the input data. The receiver is configured as follows: The internal clock is generated using a clock training pattern sent from the timing controller in serial form during the first time period; Using the internal clock, the serial test data pattern sent from the timing controller during the second time period without a clock is restored to a parallel test data pattern, and the restored test data pattern is used to restore a clock synchronized with the input data; Using the restored clock, the serial control information sent from the timing controller during the third time period without a clock will be restored to parallel control information; and Using the restored clock, the serial image data sent from the timing controller during the fourth time period without a clock will be restored to parallel image data.

2. The data driving circuit according to claim 1, wherein, The clock and data recovery unit includes: A clock generator configured to output a first clock based on an input frequency, select any one of a plurality of clocks with different phases generated by dividing the first clock for restoring the test data pattern, and output a second clock synchronized with the input data according to the control signal of the data comparator.

3. The data driving circuit according to claim 2, wherein, The clock generator is configured to: Generate and output a first clock whose phase is locked in sync with the clock training pattern provided as the input data; and The first clock is divided into N clocks with the same period as the N-bit image data string, generating N clocks with different phases. The second clock is selected and output from the N clocks according to the control signal of the data comparator, where N is an integer equal to or greater than 2.

4. The data driving circuit according to claim 3, further comprising a deserializer configured to convert the serial input data into parallel data using the first clock and the second clock, and output the parallel data. wherein The deserializer recovers the test data pattern by shifting the serial input test data pattern provided as input data according to the first clock, latching the shifted test data pattern according to the second clock, and outputting the latched test data pattern in parallel.

5. The data driving circuit according to claim 4, wherein, The deserializer includes: A first register, comprising N first flip-flops connected in series to the data input lines, and configured to shift an input test data pattern input in N-bit strings according to a first clock; and The second register includes N second flip-flops connected in parallel to the N first flip-flops and is configured to latch the test data pattern from the first register according to the second clock and output the latched test data pattern in parallel.

6. The data driving circuit according to claim 3, wherein, The data comparator compares the recovered test data pattern with the reference data pattern, detects the number of bits shifted by the recovered test data pattern compared with the reference data pattern as the degree of asynchrony, generates a control signal for selecting one of the N frequency division clocks based on the detected degree of asynchrony, and outputs the control signal to the clock generator.

7. The data driving circuit according to claim 1, wherein, The first and second time periods are included in the initial driving period prior to the provision of the image data for each frame. The third time period is included in the blanking time period of each frame, and, The fourth time period is included in the active time period of each frame.

8. The data driving circuit according to claim 7, wherein, The first and second time periods are also included before the third time period of the blanking period in each frame.

9. The data driving circuit according to claim 1, wherein, The receiver further includes a receive buffer configured to receive a transmission signal in differential signal form from the transmitter of the timing controller via a transmission channel, convert the transmission signal into the input data, and output the input data to the clock and data recovery unit.

10. A clock recovery method for a data driving circuit, the clock recovery method comprising the following steps: Multiple clocks with different phases are generated by clock training and included in the internal clock. The test data pattern is recovered from the input data using the internal clock; The recovered test data pattern is compared with a predetermined reference data pattern to generate a control signal based on the offset between the recovered test data pattern and the reference data pattern; as well as The clock synchronized with the input data is restored according to the control signal, and The clock recovery method further includes the following steps: The internal clock is generated using a clock training mode in serial form during the first time period; Using the internal clock, the serial test data pattern that was in the absence of a clock during the second time period is restored to a parallel test data pattern, and the restored test data pattern is used to restore a clock that is synchronized with the input data; Using the restored clock, the serial control information that was previously unavailable during the third time period will be restored to parallel control information; and Using the restored clock, the image data in serial form during the fourth time period, which was generated without a clock, will be restored to image data in parallel form.

11. The clock recovery method according to claim 10, further comprising the following steps: Before restoring the test data mode, an internal clock including a first clock and a second clock is generated. Specifically, when generating the internal clock, A first clock is generated and locked in phase with the clock training pattern sent from the timing controller. The first clock is divided into N clocks with the same period as the N-bit image data string to generate N clocks with different phases, where N is an integer equal to or greater than 2. One of the frequency-divided clocks is output as the second clock.

12. The clock recovery method according to claim 11, wherein, The steps to restore the test data mode include the following: The input test data pattern, provided as input data in serial form, is shifted according to the first clock; and The test data pattern is recovered by latching the shifted test data pattern according to the second clock and outputting the latched test data pattern in parallel.

13. The clock recovery method according to claim 11, wherein, The steps for generating the control signal include the following: The recovered test data pattern is compared with the reference data pattern, and the number of bits shifted by the recovered test data pattern compared with the reference data pattern is detected as the offset; and Based on the detected offset, a control signal is generated for selecting the second clock from the N divided clocks.

14. A display driving device, the display driving device comprising: A timing controller, which includes a transmitter; as well as Multiple data driving circuits, each including a receiver, are connected to the transmitter of the timing controller via each transmission channel. The receiver includes: A clock and data recovery unit configured to recover a test data pattern from input data transmitted by the transmitter using an internal clock; and A data comparator is configured to compare a recovered test data pattern with a predetermined reference data pattern to generate a control signal based on the offset between the recovered test data pattern and the reference data pattern. The clock and data recovery unit generates multiple clocks included in the internal clock through clock training, recovers a clock synchronized with the input data according to the control signal, and uses the recovered clock to recover control information and image data from subsequent input data received after the initial input data. The receiver is configured as follows: The internal clock is generated using a clock training pattern in serial form sent from the transmitter during the first time period; Using the internal clock, the serial test data pattern transmitted from the transmitter during the second time period without a clock is restored to a parallel test data pattern, and the restored test data pattern is used to restore a clock synchronized with the input data; Using the restored clock, the serial control information transmitted from the transmitter during the third time period without a clock will be restored to parallel control information; and Using the restored clock, the serial image data transmitted from the transmitter during the fourth time period without a clock will be restored to parallel image data.

15. The display driving device according to claim 14, wherein, The clock and data recovery unit includes: A clock generator configured to generate and output a first clock whose phase is locked synchronously with the clock training mode transmitted from the transmitter, divide the first clock into N divided clocks having the same period as the period of the N-bit image data string, generate N divided clocks with different phases, and select and output a second clock from the N divided clocks according to the control signal of the data comparator, wherein N is an integer equal to or greater than 2; and A deserializer, configured to convert serial input data into parallel data using the first clock and the second clock, and output the parallel data. The deserializer recovers the test data pattern by shifting the serial input test data pattern provided as input data according to the first clock, latching the shifted test data pattern according to the second clock, and outputting the latched test data pattern in parallel.

16. The display driving device according to claim 14, wherein, The data comparator compares the recovered test data pattern with the reference data pattern, detects the number of bits shifted by the recovered test data pattern compared with the reference data pattern as the offset, generates a control signal for selecting a second clock from N frequency-divided clocks based on the detected offset, and outputs the control signal to the clock generator.

17. The display driving device according to claim 14, wherein, The first and second time periods are included in the initial driving period prior to the provision of the image data for each frame. The third time period is included in the blanking period of each frame. The fourth time period is included in the active time period of each frame, and The first and second time periods are also included before the third time period of the blanking period in each frame.

18. The display driving device according to claim 14, wherein, The transmitter of the timing controller transmits a differential signal through each transmission channel, and The receiver receives the transmitted signal in differential signal form, converts the received signal into the input data, and outputs the input data to the clock and data recovery unit.

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