Memory device and operation method thereof

Abstract

The present invention discloses a memory device, including a data memory array, a reference memory array and a detection circuit. The reference memory array includes (N / 2+1) bit lines, (N / 2) source lines and a plurality of reference cells, where N is a positive even number. Each row of reference cells includes a (2n‑1)th reference cell and a (2n)th reference cell. The (2n‑1)th reference cell includes a first end coupled to the nth bit line among the (N / 2+1) bit lines; and a second end coupled to the nth source line among the (N / 2) source lines, where n is a positive integer less than N / 2+1. The (2n)th reference cell includes a first end coupled to the (n+1)th bit line among the (N / 2+1) bit lines; and a second end coupled to the nth source line among the (N / 2) source lines. The detection circuit compares the data current from the data memory array and the reference current from the reference memory array to determine the data state of the memory cells in the data memory array.

Description

Technical Field

[0001] The present invention relates to a non-volatile random access memory, and more particularly to a memory device having a reference memory array structure similar to a data memory array structure and an operation method thereof. Background Art

[0002] Resistive memory devices such as magnetoresistive random-access memory (MRAM) are a type of non-volatile random access memory that stores data by changing the resistance of memory cells. Resistive memory devices have attracted widespread attention for their high operating speed, high capacity, low power consumption, low manufacturing cost, and high reliability.

[0003] However, in the related art, the resistive memory device uses a data array and a reference array with inconsistent structures. Specifically, switches are used between cell rows in the reference array for read and write control, while switches are not included in the data array. Due to the different structures of the reference array and the data array, it is difficult for the reference array to simulate the characteristics of the data array. Summary of the invention

[0004] An embodiment of the present invention provides a memory device, including a first reference memory array, a data memory array, and a detection circuit. The first reference memory array includes a first reference cell and a second reference cell. The first reference cell includes a first end coupled to a first reference bit line; a second end coupled to a first reference source line; and a control end coupled to a first reference word line. The second reference cell includes a first end coupled to a second reference bit line; a second end coupled to a first reference source line; and a control end coupled to the first reference word line. The data memory array includes a first data cell and a second data cell. The first data cell includes a first end coupled to a first bit line; a second end coupled to a first source line; and a control end coupled to a first word line. The second data cell includes a first end coupled to a second bit line; a second end coupled to a second source line; and a control end coupled to a first word line. The detection circuit is used to compare a reference current from the reference memory array with a data current from the data memory array.

[0005] An embodiment of the present invention provides another memory device, including a data memory array, a reference memory array, and a detection circuit. The data memory array includes a plurality of memory cells for outputting data currents. The reference memory array is used to output reference currents and includes (N / 2+1) bit lines, (N / 2) source lines, and a plurality of reference cells, where N is a positive even number. The plurality of reference cells are arranged in rows and columns. Each reference cell includes a first end and a second end. Each row of reference cells includes a (2n-1)th reference cell and a (2n)th reference cell. The (2n-1)th reference cell includes a first end coupled to an nth bit line among the (N / 2+1) bit lines; and a second end coupled to an nth source line among the (N / 2) source lines, where n is a positive integer less than N / 2+1. The (2n)th reference cell includes a first end coupled to an (n+1)th bit line among the (N / 2+1) bit lines; and a second end coupled to an nth source line among the (N / 2) source lines. The detection circuit is coupled to the data memory array and the reference memory array and is used to compare the data current with the reference current to determine the data state of the memory cells in the data memory array.

[0006] An embodiment of the present invention provides another method for operating a memory device. The memory device includes a data memory array, a reference memory array, and a detection circuit. The reference memory array includes (N / 2+1) bit lines, (N / 2) source lines, and a plurality of reference cells, where N is a positive even number. The plurality of reference cells are arranged into a first reference array, a second reference array, and a third reference array. Each row of reference cells includes a (2n-1)th reference cell and a (2n)th reference cell. The (2n-1)th reference cell includes a first end coupled to the nth bit line and a second end coupled to the nth source line. The (2n)th reference cell includes a first end coupled to the (n+1)th bit line and a second end coupled to the nth source line. n is a positive integer less than N / 2+1. The detection circuit is coupled to the data memory array and the reference memory array. The method includes setting a plurality of memory cells in a data memory array to a first state to output respective data currents, setting a plurality of reference cells in a second reference array and a plurality of reference cells in a third reference array to a second state, setting a plurality of reference cells in a first reference array and a portion of reference cells in a second reference array to a first state, and selecting a first set of candidate selections having N rows from the first reference array, the second reference array, and the third reference array to output a first reference current. The method further includes comparing the first reference current with respective data currents from the data memory array by a detection circuit to determine respective data states of the plurality of memory cells, and determining whether to use the first set of candidate selections to determine the first state of the plurality of memory cells according to respective data states of the plurality of memory cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] FIG. 1 is a block diagram of a memory device according to an embodiment of the present invention.

[0008] FIG. 2 is a circuit diagram of a data storage array in FIG. 1 .

[0009] FIG. 3 is a circuit diagram of a reference memory array in FIG. 1 .

[0010] FIG. 4 is a flow chart of an operation method of the memory device in FIG. 1 .

[0011] FIG. 5 is a schematic circuit diagram of another reference memory array in FIG. 1 .

[0012] FIG. 6 shows reference currents generated by the reference memory array in FIG. 1 under various resistance modes.

[0013] FIG. 7 is a circuit diagram of another reference memory array in FIG. 1 .

[0014] FIG. 8 is a diagram showing the distribution of reference cells of the reference memory array in FIG. 1 .

[0015] 9A and 9B are flow charts of another method of operating the memory device in FIG. 8 .

[0016] The reference numerals are described as follows:

[0017] 10: Data memory array

[0018] 12: Reference memory array

[0019] 16: Controller

[0020] 50,52,54,70,72: Reference array

[0021] 80:P state distribution

[0022] 801: Slash area

[0023] 82:AP status distribution

[0024] 821: Dashed area

[0025] 400,900: Operation method

[0026] S402 to S412, S902 to S922: Steps

[0027] BLd(1) to BLd(P), BLr(1) to BLr(N / 2+1): bit lines

[0028] Do: Data status

[0029] idat: data current

[0030] iref: reference current

[0031] MC(1,1) to MC(P,Q): memory cells

[0032] RC(1,1) to RC(N,M): Reference cells

[0033] Rd(1,1) to Rd(P,Q), Rr(1,1) to Rr(N,M): variable resistor components

[0034] Rrp, Rr, Rrap: equivalent resistance

[0035] SLd(1) to SLd(P), SLr(1) to SLr(N / 2): Source lines

[0036] Td(1,1) to Td(P,Q), Tr(1,1) to Tr(N,M): Transistor

[0037] WLd(1) to WLd(Q), WLr(1) to WLr(M): word lines DETAILED DESCRIPTION

[0038] FIG. 1 is a block diagram of a memory device 1 according to an embodiment of the present invention. The memory device 1 may be a magnetoresistive random-access memory (MRAM) or other resistive memory devices. The memory device 1 includes a data memory array 10, a reference memory array 12, a detection circuit 14, and a controller 16. The controller 16 may be coupled to the data memory array 10 and the reference memory array 12. The detection circuit 14 may be coupled to the data memory array 10 and the reference memory array 12.

[0039] The data memory array 10 includes a plurality of memory cells for storing data. The reference memory array 12 includes a plurality of reference cells for generating a reference current iref. The circuit configuration and electrical connection of the reference cells of the reference memory array 12 may be similar to the memory cells in the data memory array 10, so that the circuit characteristic changes of the data memory array 10 can be closely tracked when the process, temperature, data retention and cycle endurance of the memory cells change. The circuit characteristics may include, but are not limited to, the resistance of the memory cells of the data memory array 10.

[0040] The controller 16 can control the data memory array 10 and the reference memory array 12 to perform a read operation and a write operation. In a read operation, the controller 16 can select a memory cell from the data memory array 10 to output a data current idat, and configure the reference memory array 12 to output a reference current iref. The detection circuit 14 can be a sense amplifier for comparing the data current idat from the data memory array 10 and the reference current iref from the reference memory array 12 to determine the data state Do of the memory cell in the data memory array 10. Therefore, the selection of the reference current iref is crucial for accurately determining the data state Do of the selected memory cell.

[0041] The reference memory array 12 can generate a plurality of levels of reference current iref in a linear manner. For example, the reference memory array 12 can generate 32 levels of reference current iref, and the range of the 32 levels can be between 0.5 mA and 0.2 mA, and each subsequent level differs from the previous level by about 0.01 mA. The adjustable linearity of the reference current iref is suitable for determining the appropriate level of the reference current iref used in the read operation. In addition, in the reference memory array 12, no switching device is set between adjacent columns of reference cells, so as to more closely simulate the circuit configuration and electrical connection of the memory cells in the data memory array 12. FIG. 2 is a circuit diagram of a data memory array 10. The data memory array 10 may include memory cells MC(1,1) to MC(P,Q), word lines WLd(1) to WLd(Q), bit lines BLd(1) to BLd(P), and source lines SLd(1) to SLd(P), where P and Q are positive integers greater than 1. The memory cells MC(1,1) to MC(P,Q) may be arranged in Q rows and P columns. Each memory cell MC(p,q) may include a transistor Td(p,q) and a variable resistance element Rd(p,q), wherein p is a positive integer between 1 and P, and q is a positive integer between 1 and Q. For example, FIG. 2 shows a memory cell MC(1,2) located at the intersection of the 1st column and the 2nd row, a transistor Td(2,Q-1) located at the intersection of the 2nd column and the (Q-1)th column, and a variable resistance element Rd(1,Q-1) located at the intersection of the 1st column and the (Q-1)th row. The qth row of memory cells MC(1,q) to MC(P,q) may be connected to a word line WLd(q), and the pth row of memory cells MC(p,1) to MC(p,Q) may be coupled to a bit line BLd(p) and a source line SLd(p).

[0042] Each transistor Td(p,q) may be an NMOS transistor. Each variable resistance element Rd(p,q) may be a magnetic tunnel junction and may be selectively set to a parallel state (P state) or an antiparallel state (AP state) to store one bit of data. The P state corresponds to a low resistance state and the AP state corresponds to a high resistance state. The high resistance and the low resistance may be determined by the characteristics of the magnetic tunnel junction material. For example, the high resistance may be 5.5k ohms and the low resistance may be 2k ohms. The controller 16 may select one or more memory cells MC(1,1) to MC(P,Q) from the data memory array 10 via word lines WLd(1) to WLd(Q), bit lines BLd(1) to BLd(P), and source lines SLd(1) to SLd(P) to write or read their data states Do.

[0043] In a read operation, the memory cell MC(p,q) may output a data current idat. In some embodiments, in a read operation, the controller 16 may apply a turn-on voltage of, for example, 1V to the word line WLd(q) and a read voltage of, for example, 1V to the source line SLd(p) to generate the data current idat. The magnitude of the data current idat may be determined by the resistance value of the variable resistance component Rd(p,q). If the variable resistance component Rd(p,q) is set to the P state, the variable resistance component Rd(p,q) may present a low resistance value, and the data current idat may be larger. If the variable resistance component Rd(p,q) is set to the AP state, the variable resistance component Rd(p,q) may present a high resistance value, and the data current idat may be smaller.

[0044] In a write operation, the controller 16 may select and write to the memory cell MC(p,q) by applying a turn-on voltage to the corresponding word line WLd(q), applying a first voltage to the bit line BLd(q), and applying a second voltage to the source line SLd(q). Specifically, when writing the P state to the memory cell MC(p,q), the controller 16 may apply a first voltage to the bit line BLd(q) and a second voltage to the source line SLd(q); when writing the AP state to the memory cell MC(p,q), the controller 16 may apply a first voltage to the source line SLd(q) and a second voltage to the bit line BLd(q). The voltage difference between the first voltage and the second voltage may vary based on the component characteristics of the memory cell MC(p,q). For example, the first voltage may be 1.4V and the second voltage may be 0V. In addition, the turn-on voltage for writing the AP state may be equal to or greater than the turn-on voltage for writing the P state. For example, the turn-on voltage for writing the AP state may be 1.6V and the turn-on voltage for writing the P state may be 1V. In some embodiments, the first voltage may be greater than the second voltage, but the disclosure is not limited thereto.

[0045] FIG. 3 is a circuit diagram of a reference memory array 12. The reference memory array 12 may include reference cells RC(1,1) to RC(N,M), word lines WLr(1) to WLr(M), bit lines BLr(1) to BLr(N / 2+1), and source lines SLr(1) to SLr(N / 2), where N is a positive integer and M is a positive integer greater than N. In some embodiments, N is an even number. The reference cells RC(1,1) to RC(N,M) may be arranged in M ​​rows and N columns. In the mth row, the reference cell RC(2n-1,m) may include a first terminal coupled to the bit line BLr(n); a second terminal coupled to the source line SLr(n); and a control terminal coupled to the word line WLr(m), where m and n are positive integers. The reference cell RC(2n,m) may include a first terminal coupled to the bit line BLr(n+1); a second terminal coupled to the source line SLr(n); and a control terminal coupled to the word line WLr(m). The reference cell RC(2n+1,m) may include a first terminal coupled to the bit line BLr(n+1); a second terminal coupled to the source line SLr(n+1); and a control terminal coupled to the word line WLr(m). The reference cells RC(2n-1,m) and RC(2n,m) share a common source line Slr(n), and the reference cells RC(2n,m) and RC(2n+1,m) share a common bit line BLr(n+1). For example, when n=1 and m=1, the reference cell RC(1,1) may include a first terminal coupled to the bit line BLr(1)(=n); a second terminal coupled to the source line SLr(1)(=n); and a control terminal coupled to the word line WLr(1)(=m). The reference cell RC(2,1) may include a first terminal coupled to the bit line BLr(2)(=n+1); a second terminal coupled to the source line SLr(1)(=n); and a control terminal coupled to the word line WLr(1)(=m). The reference cell RC(3,1) may include a first terminal coupled to the bit line BLr(2)(=n+1); a second terminal coupled to the source line SLr(2)(=n+1); and a control terminal coupled to the word line WLr(1)(=m).

[0046] Similarly, in the (m+1)th row, the reference cell RC(2n-1, m+1) may include a first terminal coupled to the bit line BLr(n); a second terminal coupled to the source line SLr(n); and a control terminal coupled to the word line WLr(m+1). The reference cell RC(2n, m+1) may include a first terminal coupled to the bit line BLr(n+1); a second terminal coupled to the source line SLr(n); and a control terminal coupled to the word line WLr(m+1). The reference cell RC(2n+1, m+1) may include a first terminal coupled to the bit line BLr(n+1); a second terminal coupled to the source line SLr(n+1); and a control terminal coupled to the word line WLr(m+1). Reference cells RC(2n-1,m+1) and RC(2n,m+1) share a common source line Slr(n), and reference cells RC(2n,m+1) and RC(2n+1),m+1) share a common bit line BLr(n+1).

[0047] Except for the electrical connection in one or more metal layers, each reference cell of the reference memory array 12 has substantially the same layout structure as each memory cell MC(P,Q) in the bottom layer. That is, the electrical connection of the reference cell RC(2n-1,m), the reference cell RC(2n,m), and the reference cell RC(2n+1,m) to each memory cell MC(p,q) in one or more metal layers may be different. In some embodiments, the first and second ends of the memory cell MC(P,Q) are separated from the first and second ends of the memory cell MC(p+1,q) and the first and second ends of the memory cell MC(p-1,q) in the layout structure, and may actually be coupled to each other through one or more metal layers. On the other hand, the second end of the reference cell RC(2n-1,m) is coupled to the second end of the reference cell RC(2n,m) in one or more metal layers. The first end of the reference cell RC(2n,m) and the first end of the (2n+1)th reference cell RC(2n+1,m) are coupled to each other in one or more metal layers. The reference cell RC(2n-1,m) may include a transistor Tr(2n-1,m) and a variable resistance element Rr(2n-1,m). The variable resistance element Rr(2n-1,m) includes a first terminal coupled to the first terminal of the reference cell RC(2n-1,m); and a second terminal. The transistor Tr(2n-1,m) includes a first terminal coupled to the second terminal of the variable resistance element Rr(2n-1,m); a second terminal coupled to the second terminal of the reference cell RC(2n-1,m); and a control terminal coupled to the word line WLr(m). Similarly, the reference cell RC(2n,m) may include a transistor Tr(2n,m) and a variable resistance element Rr(2n,m). The variable resistance element Rr(2n,m) includes a first terminal coupled to the first terminal of the reference cell RC(2n,m); and a second terminal. The transistor Tr(2n,m) includes a first terminal coupled to the second terminal of the variable resistor element Rr(2n,m); a second terminal coupled to the second terminal of the reference unit RC(2n,m); and a control terminal coupled to the word line WLr(m).

[0048] In some other embodiments, the data memory array 10 includes memory cells arranged in pairs, that is, by sharing the same area in the layout structure, the second end of the memory cell MC(p-1,q) is coupled to the second end of the memory cell MC(p,q), and the second end of the memory cell MC(p+1,q) is coupled to the second end of the memory cell MC(p+2,q). The first end of the memory cell MC(p,q) is disconnected from the first ends of the memory cell MC(p-1,q), the memory cell MC(p+1,q), and the memory cell MC(p+2,q). In this embodiment, the second end of the reference cell RC(2n-1,m) is coupled to the second end of the reference cell RC(2n,m), and the reference cell RC(2n-1,m) is coupled to the second end of the reference cell RC(2n+1,m) by sharing the same area in the layout structure. The first end of the reference cell RC(2n,m) and the first end of the reference cell RC(2n,m) are coupled to each other in one or more metal layers. It should be noted that the electrical connection and layout structure of the data storage array 10 are not limited thereto.

[0049] FIG. 3 shows that the reference cell RC(1,2) is located at the intersection of the 1st column and the 2nd row, the transistor Tr(2,M-1) is located at the intersection of the 2nd column and the (M-1)th row, and the variable resistance element Rr(1,M-1) is located at the intersection of the 1st column and the (M-1)th row. The transistors Tr(2n-1,m), Tr(2n,m) and the transistor Td(p,q) have the same circuit layout and electrical connection in the lower layer of one or more metal layers, and the variable resistance elements Rr(2n-1,m), Rr(2n,m) and the variable resistance element Rd(p,q) have the same circuit layout and electrical connection in the lower layer of one or more metal layers. In a write operation, each variable resistance element of the reference cells RC(1,1) to RC(N,M) can be selectively set to a P state or an AP state. Since the reference cells RC(2n-1,1) to RC(2n-1,M) and the reference cells RC(2n,1) to RC(2n,M) share the source line SLr(n), and the reference cells RC(2n,1) to RC(2n,M) and the reference cells RC(2n+1,1) to RC(2n+1,M) share the bit line BLr(n+1), the write control of the reference memory array 12 and the data memory array 10 can be different. The write control of the reference memory array 12 will be described in detail in FIG.

[0050] In a read operation, the reference memory array 12 may generate a reference current iref of at least one level to determine the P state and the AP state, and the detection circuit 14 may receive the reference current iref corresponding to the reference cells RC(1) to RC(N,M) in the reference memory array 12 to determine the data state Do of the data cell in the data memory array 10. In some embodiments, the reference memory array 12 may generate a reference current iref of a predetermined level to determine the P state and the AP state. The controller 16 may select a group of reference cells having N rows from the M rows of reference cells RC(1,1) to RC(N,M) by applying a turn-on voltage to N selected word lines to form a resistor grid of NxN variable resistor elements. In the resistor grid, the variable resistor elements of each column are coupled in parallel to each other, and the variable resistor elements of each row are coupled in series to each other. For example, the variable resistance elements Rr(n,1) to Rr(n,M) of the nth row are connected in parallel, and the variable resistance elements Rr(1,m) to Rr(N,m) of the mth row are connected in series. The equivalent resistance of the parallel and series resistance network can be equal to the average resistance of the variable resistance elements in the group of reference cells. The variable resistance elements in the group of reference cells can be defaulted to generate an average resistance, and the average resistance is between the correctable lower limit of the resistance of the P state and the correctable upper limit of the resistance of the AP state. The controller 16 can apply a read voltage to the bit line BLr(N / 2+1) of the group of reference cells to generate a reference current iref.

[0051] In other embodiments, the reference memory array 12 may generate two independent reference current iref levels, one for determining the P state and the other for determining the AP state. The controller 16 may select a first group of reference cells having N rows from the M rows of reference cells RC(1,1) to RC(N,M), and apply a read voltage to the bit line BLr(N / 2+1) of the first group of reference cells to generate a first level reference current iref for determining the P state. The first level of the reference current iref for determining the P state may be higher than or equal to a correctable lower limit of the resistance value of the P state. Similarly, the reference memory array 12 may select a second group of reference cells from the M rows of reference cells RC(1,1) to RC(N,M), and apply a read voltage to the bit line BLr(N / 2+1) of the second group of reference cells to generate a second level reference current iref for determining the AP state. The second level of the reference current iref for determining the P state may be lower than or equal to a correctable upper limit of the resistance value of the AP state.

[0052] FIG. 4 is a flow chart of an operation method 400 of the memory device 1. The method 400 includes steps S402 to S412. Any reasonable technical changes or step adjustments fall within the scope of the present invention. Steps S402 to S412 are as follows:

[0053] Step S402: the data memory array 10 outputs a data current idat;

[0054] Step S404: setting the reference cells RC(1,1) to RC(N,M) to the AP state;

[0055] Step S406: applying a second voltage to the source lines SLr(1) to SLr(N / 2);

[0056] Step S408: setting bit lines BLr(1) to BLr(N / 2+1) according to the number of reference cells to be set to the P state;

[0057] Step S410: refer to the memory array 12 outputting a reference current iref;

[0058] Step S412 : The detection circuit 14 compares the data current idat with the reference current iref to determine the data state Do of the memory cell in the data memory array 10 .

[0059] In step S402, the controller 16 selects a memory cell MC(p,q) from the data memory array 10 to output a data current idat. In step S404, the controller 16 applies a turn-on voltage to the word lines WLr(1) to WLr(M), applies a first voltage to the source lines SLr(1) to SLr(N / 2), and applies a second voltage to the bit lines BLr(1) to BLr(N / 2+1), thereby applying voltages to all reference cells RC(1,1) to RC(N,M) in the reference memory array 12 to set them to the AP state.

[0060] In steps S406 and S408, the controller 16 sets a predetermined number of reference cells in the selected row to the P state without changing the AP state of the remaining reference cells. The number of reference cells can be a non-negative integer less than N+1. For setting an odd number of reference cells to the P state, the controller 16 applies a first voltage to the bit line BLr(1); for setting a non-zero even number of reference cells to the P state, the controller 16 applies a second voltage to the bit line BLr(1). The bit line BLr(1) is coupled to an odd number (e.g., one) of the reference cells in the selected row. When (2*S-1) reference cells in the selected row are set to the P state, the controller 16 applies a first voltage to the first S bit lines and a second voltage to the remaining bit lines, where S is a positive integer less than N / 2+1. When S is equal to 1, the controller 16 applies a first voltage to the bit line BLr(1) and a second voltage to the remaining bit lines BLr(2) to BLr(N / 2+1). When S is between 2 and N / 2, the controller 16 applies a first voltage to the bit lines BLr(1) to BLr(S), and applies a second voltage to the bit lines BLr(S+1) to BLr(N / 2+1).

[0061] In steps S410 and S412, for example, the reference memory array 12 outputs the reference current iref to the detection circuit 14 by coupling the detection circuit 14 to the bit line BLr(1) and grounding the bit line BLr(N / 2+1), or by coupling the detection circuit 14 to the bit line BLr(N / 2+1) and grounding the bit line BLr(1).

[0062] Table 1 shows the bit line settings for setting various numbers of reference cells from the AP state to the P state. When three reference cells are set to the P state, the first voltage V1 is applied to the bit lines BL(1) and BL(2), and the second voltage V2 is applied to the remaining bit lines BL(3) to BL(5).

[0063] Table 1

[0064]

[0065] When (2S) reference cells in the selected row are set to the P state, the controller 16 applies the first voltage to the first S bit lines and the second voltage to the remaining bit lines, where S is a positive integer less than N / 2+1. When S is equal to 1, the controller 16 applies the first voltage to the bit line BLr(2) and the second voltage to the remaining bit lines BLr(1), BLr(3) to BLr(N / 2+1). When S is between 2 and N / 2-1, the controller 16 applies the first voltage to the bit lines BLr(2) to BLr(S+1), and the second voltage to the bit lines BLr(S+2) to BLr(N / 2+1). Table 1 shows that when 4 reference cells are to be set to the P state, the first voltage V1 is applied to the bit lines BL(2) and BL(3), and the second voltage V2 is applied to the remaining bit lines BL(1), BL(4) and BL(5).

[0066] In step S410, the controller 16 selects N rows of reference cells from the M rows of the reference memory array 12 as the reference memory array 12 to generate the reference current iref. The method of selecting N rows of reference cells is described in detail in FIGS. 9A and 9B. In step S412, the data state Do of the selected memory cell MC(P,Q) is determined.

[0067] Although the reference memory array 12 in FIG. 3 provides a specific configuration of (N / 2+1) bit lines and (N / 2) source lines, it will be appreciated by those skilled in the art that the reference memory array 12 may also be implemented using an alternative configuration of (N / 2) bit lines and (N / 2+1) source lines. If an alternative configuration of (N / 2) bit lines and (N / 2+1) source lines is used, in step S404, the reference cells RC(1,1) to RC(N,M) are set to the P state, in step S406, a second voltage is applied to the bit lines BLr(1) to BLr(N / 2), and in step S408, the source lines SLr(1) to SLr(N / 2+1) are set according to the number of reference cells to be set to the AP state. When an odd number of reference cells in each row of the reference memory array 12 are to be set to the AP state, a first voltage V1 is applied to the source line SL(1). When an even number of reference cells in each row of the reference memory array 12 are to be set to the AP state, the second voltage V2 is applied to the source line SL(1). Table 2 shows the source line settings for setting various numbers of reference cells from the P state to the AP state.

[0068] Table 2

[0069]

[0070]

[0071] FIG. 5 is a circuit diagram of another reference memory array 12. The difference between the reference memory array 12 in FIG. 5 and FIG. 3 is that the reference cells RC(1,1) to RC(N,M) in FIG. 3 are configured to form a first reference array 50, a second reference array 52, and a third reference array 54. The first reference array 50, the second reference array 52, and the third reference array 54 are coupled to each other through bit lines BLr(1) to BLr(N / 2+1) and source lines SLr(1) to SLr(N / 2). The reference cells in the first reference array 50 may be arranged into N columns and I rows, and the reference cells in the I row may be coupled to respective word lines WLr(1) to WLr(I), where I is a positive integer. The reference cells in the second reference array 52 may be arranged into N columns and J rows, and the reference cells in the J row may be coupled to respective word lines WLr(I+1) to WLr(I+J), where J is a positive integer and is equal to or less than N. The reference cells in the third reference array 54 may be arranged in N columns and K rows, and the K rows of reference cells may be coupled to respective word lines WLr(I+J+1) to WLr(M), where K is a positive integer less than N+1. In some embodiments, I and K are equal to N, J is equal to N / 2, and I+J+K=M. For example, I, K, and N are equal to 16, and J is equal to 8. The configuration of the reference cells in the first reference array 50, the second reference array 52, and the third reference array 54 is similar to that in FIG. 3. For the sake of brevity, the description will be omitted here.

[0072] The reference cells of the first reference array 50 and a portion of the reference cells of the second reference array 52 may be set to a P state. The reference cells of the remaining portion of the second reference array 52 and the reference cells of the third reference array 54 may be set to an AP state.

[0073] For example, the reference cells in the first reference array 50 may be set to the P state to generate a 16x16 P matrix, half of the reference cells in each row in the second reference array 52 may be set to the P state and the other half of the reference cells in each row in the second reference array 52 may be set to the AP state to generate an 8x16 half-P and half-AP matrix, and the reference cells in the third reference array 54 may be set to the AP state to generate a 16x16 AP matrix. When 16 rows are selected from the first reference array 50, the equivalent resistance of the selected 16 rows is equal to the average resistance of the memory cells in the P state. When 16 rows are selected from the third reference array 54, the equivalent resistance of the selected 16 rows is equal to the average resistance of the memory cells in the AP state. When 16 rows are selected from the first reference array 50 and the second reference array 52, or 16 rows are selected from the third reference array 54 and the second reference array 52, the equivalent resistance of the selected 16 rows is between the average resistance of the memory cells in the P state and the average resistance of the memory cells in the AP state.

[0074] In some embodiments, each row of reference cells in the second reference array 52 includes a first number (e.g., L) of reference cells set to the P state and a second number (e.g., NL) of reference cells set to the AP state. The ratio of the P state to the AP state of each row of reference cells in the second reference array 52 may be determined by the low resistance value of the P state and the high resistance value of the AP state. In one example, the ratio of the P state to the AP state may be 5:11. In other embodiments, a subsequent row of the second reference array 52 may have a smaller number of reference cells in the P state than a previous row of the second reference array 52. ​​For example, 12 reference cells in the first row of the second reference array 52 are set to the P state, 11 reference cells in the second row of the second reference array 52 are set to the P state, and 10 reference cells in the third row of the second reference array 52 are set to the P state. In other embodiments, a subsequent row of the second reference array 52 may have a larger number of reference cells in the P state than a previous row of the second reference array 52. For example, 10 reference cells in the first row of the second reference array 52 are set to the P state, 11 reference cells in the second row of the second reference array 52 are set to the P state, and 12 reference cells in the third row of the second reference array 52 are set to the P state. The falling ratio or rising ratio between the P state and the AP state in the second reference array 52 can potentially enhance the linearity of the reference current iref.

[0075] The controller 16 may select a plurality of candidate selections having N rows from the first reference array 50, the second reference array 52, and the third reference array 54. For example, N may be 16, and the controller 16 may select one of 32 candidate selections from the first reference array 50, the second reference array 52, and the third reference array 54, each candidate selection including 16 rows of reference cells. For example, the first candidate selection may be selected only from the first reference array 50 and may include only reference cells in the P state. The second candidate selection may include 15 rows of reference cells from the first reference array 50 and 1 row of reference cells from the second reference array 52. ​​The eighth candidate selection may include 8 rows of reference cells from the first reference array 50 and 8 rows of reference cells from the second reference array 52. ​​The ninth candidate selection may include 8 rows of reference cells from the first reference array 50, 1 row of reference cells from the second reference array 52, and 7 rows of reference cells from the third reference array 54. The 16th candidate selection may include 8 rows of reference cells from the first reference array 50 and 8 rows of reference cells from the third reference array 54. The 17th set of candidate selections may include 7 rows of reference cells from the first reference array 50, 1 row of reference cells from the second reference array 52, and 8 rows of reference cells from the third reference array 54. The 24th set of candidate selections may include 8 rows of reference cells from the second reference array 52 and 8 rows of reference cells from the third reference array 54. The 25th set of candidate selections may include 7 rows of reference cells from the second reference array 52 and 9 rows of reference cells from the third reference array 54. The 32nd set of candidate selections may include 16 rows of reference cells from the third reference array 54.

[0076] Therefore, since all rows of reference cells in the first reference array 50 include only P-state cells, all rows of reference cells in the second reference array 52 include P-state cells and AP-state cells, and all rows of reference cells in the third reference array 54 include only AP-state cells, the equivalent resistance values ​​of the 32nd group of candidate selections to the 1st group of candidate selections have a linear decreasing order. The 32nd group of candidate selections can provide the highest equivalent resistance value, the 1st group of candidate selections can provide the lowest equivalent resistance value, and the 16th group of candidate selections and the 17th group of candidate selections can provide intermediate equivalent resistance values. Therefore, the reference memory array 12 can generate 32 levels of reference current iref in a linear manner, as shown in FIG. 6 .

[0077] FIG. 6 shows the reference current iref generated by various candidate selections of the reference memory array 12, wherein the horizontal axis represents the equivalent resistance of each candidate selection of the reference memory array 12, and the vertical axis represents the level of the reference current iref. FIG. 6 shows the results of 32 candidate selections of the reference memory array 12. As described in the previous paragraphs, the equivalent resistance values ​​for the first candidate selection to the 32nd candidate selection increase in a linear order, and the corresponding level of the reference current IREF decreases in a linear order. The controller 16 can select an appropriate reference current iref level based on the resistance distribution of the data memory array 10 and other requirements to determine the P state and / or AP state. FIGS. 9A and 9B will explain in detail the method of selecting the reference current iref of the appropriate level.

[0078] FIG. 7 is a circuit diagram of another reference memory array 12. The difference between the reference memory array 12 in FIG. 7 and FIG. 5 is that the reference cells RC(1,1) to RC(N,M) in FIG. 7 are configured as a first reference array 70 and a second reference array 72. The reference cells in the first reference array 70 may be arranged in N columns and N rows, and the N rows of reference cells in the first reference array 70 may be coupled to respective word lines WLr(1) to WLr(N), and the reference cells in the second reference array 72 may be arranged in N columns and N rows, and the N rows of reference cells in the second reference array 72 may be coupled to respective word lines WLr(N+1) to WLr(M), where M is equal to 2N. For example, N is equal to 16, and both the first reference array 70 and the second reference array 72 are 16x16 arrays.

[0079] The reference cells of the first reference array 70 may be set to a P state, and the reference cells of the second reference array 72 may be set to an AP state. The controller 16 may select 16 sets of candidate selections having N rows from the first reference array 70 and the second reference array 72, wherein the first set of candidate selections may provide the lowest equivalent resistance value and the 16th set of candidate selections may provide the highest equivalent resistance value. The configuration and operation of the first reference array 70 and the second reference array 72 are similar to the first reference array 50 and the third reference array 54, and explanations thereof may be found in the previous paragraphs and will not be repeated here.

[0080] FIG. 8 shows a distribution diagram of reference cells MC(1,1) to MC(P,Q) in the reference memory array 10, wherein the horizontal axis represents resistance and the vertical axis represents the number of reference cells. Since the electrical characteristics of reference cells MC(1,1) to MC(P,Q) may be slightly different from each other, reference cells MC(1,1) to MC(P,Q) may show a distribution of resistance changes when programmed to a P state or an AP state. P state distribution 80 represents the distribution of reference cells MC(1,1) to MC(P,Q) in the P state, and AP state distribution 82 represents the distribution of reference cells MC(1,1) to MC(P,Q) in the AP state. The shapes of P state distribution 80 and AP state distribution 82 may be similar or different. In addition, P state distribution 80 and AP state distribution 82 may be completely separated from each other or partially overlap. In FIG. 8, P state distribution 80 is wider than AP state distribution 82, and P state distribution 80 and AP state distribution 82 partially overlap. The equivalent resistance Rrp is the correctable lower limit of the resistance in the P state, and can be selected based on the acceptable error rate of the P state. For example, when up to 20 error bits that are misjudged as the AP state can be corrected back to the P state by an error correction code (ECC) or other error correction mechanisms, the equivalent resistance Rrp can be selected to form a slash area 801 corresponding to 20 bits. Similarly, the equivalent resistance Rrap is the correctable upper limit of the resistance in the AP state, and the dashed area 821 corresponds to the number of bits in the error bits that are misjudged as the P state that can be corrected back to the AP state by an error correction code or other error correction mechanisms.

[0081] The reference equivalent resistance Rr between the equivalent resistance Rrp and the equivalent resistance Rrap is located in the area overlapped by the oblique line area 801 and the dotted line area 821 in FIG. 8, and the reference equivalent resistance Rr can be determined by the method shown in FIGS. 9A and 9B. Please refer to the following paragraphs for detailed operations.

[0082] Figures 9A and 9B are flow charts of another operation method 900 of the memory device 1. The method 900 includes steps S902 to S922. Steps S902 to S906 are used to initialize the data memory array 10 and the reference memory array 12. Steps S908 to S922 are used to select a first group of N rows of reference cells from the reference memory array 12 to provide an equivalent resistance Rrp for determining the P state, and select a second group of N rows of reference cells from the reference memory array 12 to provide an equivalent resistance Rrp for determining the AP state. Any reasonable technical changes or step adjustments fall within the scope of the present invention. Steps S902 to S922 are as follows:

[0083] Step S902: setting the memory cells MC(1,1) to MC(P,Q) in the data memory array 10 to the P state to output respective data currents;

[0084] Step S904: setting the reference units in the second reference array 52 and the reference units in the third reference array 54 to AP state;

[0085] Step S906: setting the reference cells in the first reference array 50 and some reference cells in the second reference array 52 to a P state;

[0086] Step S908: Selecting an initial candidate selection having N rows from the first reference array 50 , the second reference array 52 , and the third reference array 54 to output a first reference current;

[0087] Step S910: the detection circuit 14 compares each data current from the data memory array 10 with the first reference current to determine the data states of the memory cells MC(1,1) to MC(P,Q);

[0088] Step S912: Determine whether to use the initial candidate selection to determine the P state of memory cells MC(1,1) to MC(P,Q)? If yes, proceed to step S914; if no, proceed to step S916;

[0089] Step S914: Set the initial candidate selection to be used to determine memory cells MC(1,1) to MC(P,Q)

[0090] P status;

[0091] Step S916: Select a next set of candidate selections with N rows from the first reference array 50, the second reference array 52 and the third reference array 54 to output a next reference current;

[0092] Step S918: the detection circuit 14 compares each data current from the data memory array 10 with the next reference current to determine the updated data states of the memory cells MC(1,1) to MC(P,Q);

[0093] Step S920: Determine whether to use the next set of candidate selections to determine the P state of memory cells MC(1,1) to MC(P,Q)? If yes, proceed to step S922; if no, proceed to step S916;

[0094] Step S922: Set the next set of candidate selections to be used to determine the P state of memory cells MC(1,1) to MC(P,Q).

[0095] Method 900 will be explained with reference to memory device 1 in FIG. 1 and reference memory array 12 in FIG. 5. In step S902, data memory array 10 is initialized to select a first set of reference cells having N rows for determining a P state. Therefore, all memory cells MC(1,1) to MC(P,Q) are set to a P state. In steps S904 and S906, reference cells in first reference array 50, second reference array 52, and third reference array 54 are initialized to a setting similar to that of reference memory array 12 in FIG. 5. That is, reference cells in first reference array 50 are set to a P state, reference cells in third reference array 54 are set to an AP state, and reference cells in each row of second reference array 52 are set to a predetermined ratio of a P state to an AP state, for example, 5:11.

[0096] In step S908, the initial candidate selection may include reference cells of mixed P state and AP state. For example, the 16th group of candidate selection or the 17th group of candidate selection may provide a good starting point because both produce intermediate equivalent resistance values. In the present embodiment, the 16th group of candidate selection is selected to generate a first reference current. In step S910, since all memory cells MC(1,1) to MC(P,Q) have been set to the P state, if the respective data currents exceed the first reference current, the selected reference cell is determined to be not in the P state, and the controller 16 identifies a detection error. The controller 16 accumulates the detection errors to generate the number of error cells. In step S912, if the number of error cells is less than the predetermined error amount, the controller 16 determines that the 16th group of candidate selection can be used to determine the P state. Therefore, the controller 16 sets the 16th group of candidate selection as the 1st group of reference cells for determining the P state (S914). Otherwise, the controller 16 determines that the 16th group of candidate selection cannot be used to determine the P state. The predetermined error amount may be the number of error bits that can be recovered using an error correction mechanism or a memory redundancy mechanism. For example, the predetermined error amount may be 20. In step S916, since the 16th group of candidate selections fails to provide the expected error rate, the controller 16 selects the next candidate selection. The next candidate selection may generate an equivalent resistance value higher than the 16th group of candidate selections. For example, the 17th group of candidate selections may be selected to generate the next reference current. In some other embodiments, the candidate selection selected after the 16th group of selections may not be the next candidate selection, for example, the 18th group of candidate selections. In step S918, if the respective data currents exceed the next reference current, it is determined that the selected reference cell is not in the P state, and the controller 16 recognizes a detection error. The controller 16 accumulates the detection errors again to generate a new number of error cells. In step S920, if the new number of error cells is less than the predetermined error amount, the controller 16 determines that the 17th group of candidate selections can be used to determine the P state. Therefore, the controller 16 sets the 17th group of candidate selections as the 1st group of reference cells for determining the P state (S922). Otherwise, the controller 16 determines that the 17th group of candidate selections cannot be used to determine the P state, and the method 900 returns to step S916 to select the next candidate selection. Steps S916 to S920 are repeated until the number of new error cells is less than the predetermined error amount, and the controller 16 sets the next candidate selection as the 1st group of reference cells for determining the P state (S922).

[0097] After the first set of reference cells with N rows for determining the P state is set, the controller 16 may set another set of candidate selections with N rows as the second set of reference cells for determining the AP state. The second set of reference cells may generate a reference current iref that is smaller than the first set of reference cells by a predetermined current difference. For example, the predetermined current difference may be 5 microamperes, the first set of reference cells may generate 0.35 mA, and the second set of reference cells may generate 0.345 mA. In this way, the method 900 may determine the first set of reference cells for determining the P state and the second set of reference cells for determining the AP state.

[0098] In method 900, the first group of reference cells for determining the P state is first determined, and then the second group of reference cells for determining the AP state is determined according to the equivalent resistance of the first group of reference cells. The present invention is also applicable to first determining the second group of reference cells for determining the AP state, and then determining the first group of reference cells for determining the P state through a similar principle outline in method 900. In addition, although the reference memory array 12 in FIG. 5 is used in the embodiment to explain the steps of method 900, the method 900 can also be applied to the reference memory array 12 in FIG. 7 according to a similar principle.

[0099] The embodiments of FIGS. 1, 3, 5 and 7 provide a structure of a reference memory array 12 similar to the data memory array 10, closely tracking the changes in circuit characteristics such as the process, temperature, data retention and cycle endurance of the data memory array 10, while providing linear control of the reference current iref, thereby improving the accuracy of data state judgment. In addition, the embodiments of FIGS. 7, 9A and 9B provide methods for operating the reference memory array 12 of the memory device 1, writing reference cells and selecting reference cells to generate appropriate reference current iref, thereby accurately judging the data state.

[0100] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A memory device, comprising: A first reference memory array comprising: A first reference unit includes a first terminal coupled to a first reference bit line; a second terminal coupled to a first reference source line; and a control terminal coupled to a first reference word line; A second reference unit includes a first terminal coupled to a second reference bit line; a second terminal coupled to the first reference source line; and a control terminal coupled to the first reference word line; a third reference unit, comprising a first terminal coupled to the first reference bit line; a second terminal coupled to the first reference source line; and a control terminal coupled to a second reference word line; and a fourth reference unit, comprising a first terminal coupled to the second reference bit line; a second terminal coupled to the first reference source line; and a control terminal coupled to the second reference word line; A data storage array comprising: A first data unit includes a first terminal coupled to a first bit line; a second terminal coupled to a first source line; and a control terminal coupled to a first word line; and a second data unit, comprising a first terminal coupled to a second bit line; a second terminal coupled to a second source line; and a control terminal coupled to the first word line; and a detection circuit for comparing a reference current from the reference memory array and a data current from the data memory array; The detection circuit is coupled to the first bit line to receive the data current corresponding to the first data unit, and is coupled to the first reference bit line to receive the reference current corresponding to the first reference unit, the second reference unit, the third reference unit and the fourth reference unit to determine a data state of the first data unit coupled to the first bit line in the data storage array.

2. The memory device of claim 1, wherein: The first reference memory array further includes: a third reference unit including a first terminal coupled to the second reference bit line; a second terminal coupled to a second reference source line; and a control terminal coupled to the first reference word line.

3. The memory device of claim 1, wherein: The first reference unit and the first data unit have the same structure. 4 . The memory device as claimed in claim 1 , wherein the first reference cell is coupled to the second reference cell through a metal layer.

5. The memory device of claim 1 , further comprising: A second reference array is coupled to the first reference bit line, wherein the first reference array is set to a first state and the second reference array is set to a second state.

6. The memory device of claim 5, wherein: The first reference array is an N×N array; and The second reference array is an N×N array, where N is a positive integer.

7. The memory device of claim 5, further comprising: a third reference array, coupled to the first reference bit line, comprising a plurality of rows of reference cells; wherein a row of the plurality of rows of reference cells coupled to a third reference word line comprises a first portion and a second portion; in, Before the first portion is set to the first state by receiving a first voltage, the row is set to the second state by receiving a second voltage, wherein the first voltage is greater than the second voltage.

8. The memory device of claim 7, wherein when the first portion has a first odd number of reference cells, the first reference bit line coupled to a second odd number of reference cells in the row is configured to receive the first voltage.

9. The memory device of claim 7, wherein when the first portion has an even number of reference cells, the first reference bit line coupled to an odd number of reference cells in the row is used to receive the second voltage.

10. The memory device of claim 1, wherein each data cell and each reference cell each comprises a magnetoresistive random-access memory (MRRAM) cell.

11. The memory device of claim 1, wherein: The first source line is coupled to the second source line.

12. A memory device comprising: A data memory array includes a plurality of memory cells for outputting a data current; A reference memory array, used to output a reference current, comprises: (N / 2+1) bit lines, N is a positive even number; (N / 2) source lines; and A plurality of reference units are arranged in rows and columns, each reference unit includes a first end and a second end, and each row of reference units includes: a (2n-1)th reference unit, comprising a first terminal coupled to an nth bit line among the (N / 2+1) bit lines; and a second terminal coupled to an nth source line among the (N / 2) source lines, where n is a positive integer less than N / 2+1; and a (2n)th reference unit, comprising a first terminal coupled to an (n+1)th bit line among the (N / 2+1) bit lines; and a second terminal coupled to the nth source line among the (N / 2) source lines; and a detection circuit coupled to the data memory array and the reference memory array and used to compare the data current with the reference current to determine a data state of a memory cell in the data memory array; The multiple reference cells are arranged into a first reference array, a second reference array and a third reference array, the multiple reference cells of the first reference array and a portion of the reference cells of the second reference array are set to a first state, and the reference cells of a remaining portion of the second reference array and the multiple reference cells of the third reference array are set to a second state.

13. The memory device of claim 12, wherein: A first number of reference cells set to the first state in a subsequent row of the second reference array is less than a second number of reference cells set to the first state in a previous row of the second reference array.

14. A memory device comprising: A data memory array includes a plurality of memory cells for outputting a data current; A reference memory array, used to output a reference current, comprises: (N / 2+1) bit lines, N is a positive even number; (N / 2) source lines; and A plurality of reference units are arranged in rows and columns, each reference unit includes a first end and a second end, and each row of reference units includes: a (2n-1)th reference unit, comprising a first terminal coupled to an nth bit line among the (N / 2+1) bit lines; and a second terminal coupled to an nth source line among the (N / 2) source lines, where n is a positive integer less than N / 2+1; and a (2n)th reference unit, comprising a first terminal coupled to an (n+1)th bit line among the (N / 2+1) bit lines; and a second terminal coupled to the nth source line among the (N / 2) source lines; and a detection circuit coupled to the data memory array and the reference memory array and used to compare the data current with the reference current to determine a data state of a memory cell in the data memory array; When (2*S-1) reference cells in a row of reference cells are set to a first state, a first bit line to an S bit line among the (N / 2+1) bit lines are used to receive a first voltage, and a remaining bit line of the (N / 2+1) bit lines is used to receive a second voltage, where S is a positive integer.

15. A memory device comprising: A data memory array includes a plurality of memory cells for outputting a data current; A reference memory array, used to output a reference current, comprises: (N / 2+1) bit lines, N is a positive even number; (N / 2) source lines; and A plurality of reference units are arranged in rows and columns, each reference unit includes a first end and a second end, and each row of reference units includes: a (2n-1)th reference unit, comprising a first terminal coupled to an nth bit line among the (N / 2+1) bit lines; and a second terminal coupled to an nth source line among the (N / 2) source lines, where n is a positive integer less than N / 2+1; and a (2n)th reference unit, comprising a first terminal coupled to an (n+1)th bit line among the (N / 2+1) bit lines; and a second terminal coupled to the nth source line among the (N / 2) source lines; and a detection circuit coupled to the data memory array and the reference memory array and used to compare the data current with the reference current to determine a data state of a memory cell in the data memory array; When (2S) reference cells in a row of reference cells are set to a second state, a second bit line to an (S+1)th bit line among the (N / 2+1) bit lines are used to receive a first voltage, and a remaining bit line of the (N / 2+1) bit lines is used to receive a second voltage, where S is a positive integer.

16. A method for operating a memory device, the memory device comprising a data memory array, a reference memory array and a detection circuit, the reference memory array comprising (N / 2+1) bit lines, (N / 2) source lines, and a plurality of reference cells, N being a positive even number, the plurality of reference cells being arranged into a first reference array, a second reference array and a third reference array, each row of reference cells comprising a (2n-1)th reference cell and a (2n)th reference cell, the (2n-1)th reference cell comprising a first terminal coupled to an nth bit line and a second terminal coupled to an nth source line, the (2n)th reference cell comprising a first terminal coupled to an (n+1)th bit line and a second terminal coupled to the nth source line, n being a positive integer less than N / 2+1, the detection circuit being coupled to the data memory array and the reference memory array, the method comprising: Setting a plurality of memory cells in the data memory array to a first state to output respective data currents; Setting the plurality of reference cells in the second reference array and the plurality of reference cells in the third reference array to a second state; Setting a plurality of reference cells in the first reference array and a portion of reference cells in the second reference array to the first state; Selecting a first set of candidate selections having N rows from the first reference array, the second reference array, and the third reference array to output a first reference current; The detection circuit compares the first reference current with the respective data currents from the data memory array to determine the respective data states of the plurality of memory cells; and According to the respective data states of the plurality of memory cells, it is determined whether to use the first set of candidate selections to determine the first state of the plurality of memory cells.

17. The method of claim 16, wherein determining whether to use the first set of candidate selections to determine the first state of the plurality of memory cells comprises: If a portion of the memory cells are determined not to be in the first state, and a cell number of the portion of the memory cells is less than a predetermined error amount, the first set of candidate selections is used to determine the first state of the plurality of memory cells.

18. The method of claim 16, further comprising: If a portion of the memory cells is determined to be not in the first state, and a number of the memory cells in the portion is not less than a predetermined error amount, a second set of candidate selections having N rows is selected from the first reference array, the second reference array, and the third reference array, to output a second reference current, the second group of candidate selections including more reference cells in the second state than the first group of candidate selections; The detection circuit compares the second reference current with the respective data currents from the data memory array to determine the respective updated data states of the plurality of memory cells; and According to the respective updated data states of the plurality of memory cells, it is determined whether to use the second set of candidate selections to determine the first states of the plurality of memory cells.

Images