Manufacturing process of vertical channel silicon field-effect transistors
A novel process for fabricating vertical gate transistors in wide trenches has solved the problem of large device size in existing technologies, enabling transistors with small cell size and minimized pixel area, suitable for image sensor circuits, and improving device integration density and performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- OMNIVISION TECHNOLOGIES INC
- Filing Date
- 2021-11-30
- Publication Date
- 2026-06-30
AI Technical Summary
In the prior art, non-coplanar source/drain diffused silicon field-effect transistors cannot be effectively coupled using vertical channels when applied in high-power switching devices and selection transistors, resulting in large device sizes that cannot meet the requirements for small cell sizes and minimized pixel area.
A novel manufacturing process is employed to form vertical gate transistors in wide trenches. Wide trenches are formed through masking and etching, dielectric and flowable materials are deposited, semiconductor strips are epitaxially grown to form gate oxide and gate conductors, and source and drain regions are injected to realize a vertical channel transistor structure.
Transistors with small cell size and minimized pixel area are realized, suitable for source followers and reset transistors in image sensor circuits, improving device integration density and performance.
Smart Images
Figure CN114649210B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a method for manufacturing a transistor having a vertical gate in a wide trench and a vertical gate transistor. Background Technology
[0002] Silicon field-effect transistors with non-coplanar source / drain diffusions (typically where one of the source and drain regions is on top of the other) are commonly used in high-power switching devices and are also used as select transistors to couple buried photodiodes to overlying circuitry. However, these devices do not use vertical channels for coupling between coplanar but horizontally separated source / drain diffusions. Summary of the Invention
[0003] A novel fabrication process for small vertical-channel insulated-gate field-effect transistors (IGFETs) is proposed. In one embodiment, these transistors are used as source followers and reset transistors in embedded photodiode image sensor circuits to achieve small cell size and minimize pixel area.
[0004] The present invention provides a method for manufacturing a transistor having a vertical gate in a wide trench and a vertical gate transistor.
[0005] In one aspect, a method for fabricating a transistor with a vertical gate in a wide trench includes masking and etching the wide trench; forming a dielectric within and around the wide trench; depositing a flowable material into the wide trench; masking and etching to form an inner narrow trench within the wide trench, thereby exposing a well or substrate. The method continues by epitaxially growing semiconductor strips seeded from the well or substrate inside and outside the inner narrow trench; removing the flowable material from the wide trench; growing a gate oxide on the semiconductor strips; forming a gate conductor over the gate oxide and in the gap between the epitaxially grown semiconductor strips and the dielectric; masking and etching the gate conductor; and implanting source and drain regions.
[0006] In some implementations, the depth of the wide trench is 50 to 400 nanometers.
[0007] In some implementations, the semiconductor strip primarily comprises silicon.
[0008] In some implementations, the trap or substrate primarily comprises silicon.
[0009] In some implementations, the gate conductor primarily comprises polycrystalline silicon.
[0010] In some embodiments, the medium comprises a flowable chemical vapor deposition (CVD) oxide.
[0011] In some embodiments, the semiconductor strip has P-type silicon and the source and drain have N-type silicon.
[0012] In some implementations, the flowable material includes silicon, nitrogen, and hydrogen.
[0013] On the other hand, a vertical gate transistor includes a semiconductor strip of a first conductivity type extending from a source region of a second conductivity type to a drain region of a second conductivity type, the semiconductor strip being formed in a trench with the trench walls insulated by a dielectric; a gate oxide formed on two vertical walls of the semiconductor strip; and a gate material between the dielectric and the gate oxide.
[0014] In some implementations, the semiconductor strip primarily comprises silicon.
[0015] In some implementations, the gate material primarily comprises polycrystalline silicon.
[0016] In some implementations, the depth of the trench is between 50 and 400 nanometers. Attached Figure Description
[0017] Figure 1 This is a top plan view of a transistor configured for a vertical channel between coplanar source / drain regions.
[0018] Figure 2 It is along Figure 1 The image shows a cross-sectional view of a transistor configured for a vertical channel, taken from line AA, with the vertical channel running along the sidewall of an epitaxial semiconductor strip in the trench.
[0019] Figure 3 This is a schematic diagram of a four-embedded photodiode and a seven-transistor pixel unit used in image sensor integrated circuits.
[0020] Figure 4 It is manufacturing Figure 1 and Figure 2 The flowchart of the method for using transistors.
[0021] Figure 5 , 6 Numbers 7, 8, 9, 10, 11, 12, and 13 are diagrams. Figure 1 and 2 A cross-sectional view of a partially manufactured transistor, each of which may appear in... Figure 4 In specific steps of the method. Detailed Implementation
[0022] exist Figure 1The top plan view illustrates a novel transistor 120 having an epitaxial semiconductor strip in a trench. The transistor has source 122 and drain 126 diffusion regions of a first diffusion type (such as N-type) within a well or substrate 127 of a second diffusion type semiconductor (such as silicon). In alternative embodiments, the semiconductor is another group IV material (such as germanium), a compound semiconductor (such as an alloy of silicon with carbon or germanium), or a group III-V semiconductor (such as gallium arsenide, gallium indium arsenide). The transistor 120 has a gate formed directly over a second diffusion type semiconductor strip or filler 124 by a conductor (such as polysilicon), extending to the gate of first and second sides 130 including the semiconductor strip or filler 124, and the gate conductor may overlap the transistor in an overlap region 128. The gate conductor material may extend 129 over other portions of the device for use as an interconnect.
[0023] In cross-section, the new transistor 100 is fabricated within and on top of a trench 102 cut in a second conductor type well or substrate 104, 127. An epitaxially grown semiconductor strip 106 is located approximately at the center of the trench 102, with a thin gate insulator 108 along its sides. A gate conductor 110 is formed on the semiconductor strip 106, filling the vertical gate portions 112 of the trench 102 on both sides of the semiconductor strip 106. The remaining portion of the trench 102 is filled with a thick dielectric 114, which also extends across the well or substrate surface below the overlapping portions 116 and interconnect portions 118 of the gate conductor 110.
[0024] In a particular embodiment, the well or substrate 104, 127 is P-type silicon, the semiconductor filler 124 is epitaxially grown P-type silicon, the gate insulator 108 is thermally grown silicon oxide, the gate conductor materials 130, 110 are polycrystalline silicon, and the inversion region formed when the gate conductor materials 130, 110 are appropriately biased is N-type, and the transistor having the epitaxial bands 124, 106 operates as an N-channel metal-oxide-semiconductor (MOS) transistor. In this embodiment, the thick dielectric 114 is silicon oxide, such as a thermally grown oxide or CVD oxide film, but other dielectrics may also be used.
[0025] When the gate conductor 110 is properly biased, an inversion region is formed along the top and sidewalls of the epitaxially grown semiconductor strips 106, 124, thereby operating with an effective gate width that is twice the sum of the depth of trench 102 and the width of semiconductor strips 106, 124.
[0026] Compared to existing MOS transistors, transistor 120 with epitaxial semiconductor strips in the trench has advantages because the effective gate width of the transistor can be greater than the effective gate width of conventionally manufactured planar transistors made using semiconductor wafers of the same surface area.
[0027] In one embodiment, the transistor 100 having epitaxial strip 106 serves as a reduced-physical-width source follower transistor 202 in the 4-buried photodiode pixel unit 200 of the image sensor in the image sensor integrated circuit. Figure 3 The pixel unit of the image sensor includes a unit selection transistor 204 and a reset transistor 206. In this pixel unit, the photodiode transmission gate transistors 208, 210, 212, and 214 can be vertical transistors used to select embedded photodiodes 216, 218, 220, and 222.
[0028] In one implementation scheme Figure 1 and Figure 2 The transistor 100 with epitaxial stripes is based on Figure 4 The wafer is manufactured using method 250; note that prior to the steps of method 250, the wafer needs to be prepared in earlier steps of the process, and intermediate steps such as cleaning and photoresist stripping may be performed in addition to the steps described herein, and the following steps are required to complete the integrated circuit.
[0029] Perform masking and etching operations 252 to create trenches 402 with a depth of 50 to 400 nanometers. Figure 5 Etching is performed into the well or substrate 404. In addition to the deposition, exposure, development, etching, and removal of photomask materials, the masking and etching operations described herein may also include the deposition and removal of hard mask materials (such as silicon nitride SiN). Replanarization operations, such as chemical mechanical polishing, may also be interspersed within... Figure 4 Between the steps recorded in the document.
[0030] After etching trenches 402 and 102, the formed medium 406 is then lined in and around trenches 402 and 102. Figure 6 In the implementation, the medium is a thermal oxide grown on a semiconductor well or substrate surrounding the trench.
[0031] After forming medium 254, a flowable CVD material 407 is deposited and flowed 255. Figure 7 After the oxide flows, the flowable CVD material can be planarized. Figure 8 To flatten the wafer surface, a flowable CVD material 407 is left in the space 402A within each trench not occupied by the dielectric 406. In one embodiment, the flowable CVD material 407 is silicon nitride or a film containing silicon, nitrogen, and hydrogen.
[0032] Once the medium 406 and the flowable CVD material 407 are formed, a masking and etching operation 256 is performed to form internal narrow trenches 408 in the medium 406 and the flowable CVD material 407. Figure 9 ), forming the shape of the remaining medium 406A ( Figure 9 The remaining flowable CVD material is shaped 407A, and the substrate or well 404 is exposed at the bottom of the narrow trench 408. After the inner trench 408 is formed, a semiconductor strip 410 is formed at the bottom of the inner trench 408 and centered within the trench 402. Figure 10 The semiconductor strip 410 is formed by epitaxial growth 258 through a well or substrate 404. After the semiconductor strip 410 is grown, the remaining flowable material 407 is removed from 259. Figure 11 ) and a 260 gate oxide 412 is grown on semiconductor strip 410. Figure 12 Before that, the device being formed can be optionally re-planarized.
[0033] After the gate oxide 412 is grown for 260°, the gate conductor 414 ( Figure 13 ) Deposit 262 on gate oxide 412 and into the gap between epitaxially grown semiconductor strip 410 and dielectric 406A. In one embodiment, gate conductor 414 is polysilicon silicided with molybdenum.
[0034] After depositing gate conductor 414 262, the gate conductor is masked and etched 264 to accommodate gate regions 130, 124 as required by a specific integrated circuit design. Figure 1 The conductor is patterned with overlapping regions (if any) 128 and extended interconnect regions 129.
[0035] After the gate conductor 414 is masked and etched 264, the source and drain regions 122 and 126 are implanted 266, and then the 268 integrated circuit is completed using conventional metal, via and contact deposition, masking and etching steps.
[0036] In the implementation, hundreds of thousands or millions of lateral and vertical gate transistors as described herein are formed on each wafer, and each megapixel image sensor has one or more pixel units.
[0037] combination
[0038] A method, designated A, for manufacturing a transistor having a vertical gate in a wide trench includes masking and etching the wide trench; forming a dielectric in and around the wide trench; filling the wide trench with a flowable material; masking and etching to form an inner narrow trench in the wide trench, thereby exposing a well or substrate. The method continues by epitaxially growing a semiconductor strip led from the well or substrate on top of the well or substrate exposed by the inner narrow trench; removing the flowable material from the wide trench; growing a gate oxide on the semiconductor strip; forming a gate conductor over the gate oxide and in the gap between the epitaxially grown semiconductor strip and the dielectric; masking and etching the gate conductor; and implanting source and drain regions.
[0039] Methods designated as AA, including methods designated as A, wherein the depth of the wide trench is 50 to 400 nanometers.
[0040] The method designated as AB includes the method designated as A or AA, wherein the semiconductor strip primarily comprises silicon.
[0041] The method designated as AC includes methods designated as A, AA, or AB, wherein the well or substrate primarily comprises silicon.
[0042] The method designated as AD includes methods designated as A, AA, AB, or AC, wherein the gate conductor primarily comprises polysilicon.
[0043] Methods designated as AE, including methods designated as A, AA, AB, AC, or AD, wherein the medium includes silicon dioxide.
[0044] The method designated as AF includes methods designated as A, AA, AB, AC, AD, or AE, wherein the semiconductor strip has P-type silicon and the source and drain have N-type silicon.
[0045] Methods designated as AG, including methods designated as A, AA, AB, AC, AD, AE, or AF, wherein the flowable material includes silicon, nitrogen, and hydrogen.
[0046] A vertical gate transistor designated as B includes a semiconductor strip of a first conductivity type extending from a source region of a second conductivity type to a drain region of a second conductivity type, the semiconductor strip being formed in a trench with the trench walls insulated by a dielectric; a gate oxide formed on two vertical walls of the semiconductor strip; and a gate material between the dielectric and the gate oxide.
[0047] Vertical gate transistors designated as BA include vertical gate transistors designated as B, wherein the semiconductor strip primarily comprises silicon.
[0048] Vertical gate transistors designated as BB, including vertical gate transistors designated as B or BA, wherein the gate material primarily comprises polysilicon.
[0049] Vertical gate transistors designated as BC, including vertical gate transistors designated as B, BA, or BC, wherein the trench has a depth between 50 and 400 nanometers.
[0050] While the invention has been specifically shown and described with reference to preferred embodiments thereof, those skilled in the art will understand that various other changes in form and detail may be made without departing from the spirit and scope of the invention. It should be understood that various changes may be made in adapting the invention to different embodiments without departing from the broader inventive concept disclosed herein and as understood by the appended claims.
Claims
1. A method for manufacturing a transistor having a vertical gate in a wide trench, comprising: Masking and etching to form the wide trenches; A lining medium is formed in and around the wide groove; The wide trench is filled with a first flowable material; Masking and etching are used to form internal narrow trenches in the wide trenches, thereby exposing the trap or substrate; A semiconductor strip, driven by the well or substrate, is epitaxially grown on top of the well or substrate exposed by the internal narrow trench; Remove the first flowable material from the wide groove; A gate oxide is grown on the epitaxially grown semiconductor strip; A gate conductor is formed above the gate oxide and in the gap between the epitaxially grown semiconductor strip and the liner dielectric; Masking and etching the gate conductor; as well as Inject into the source and drain regions.
2. The method according to claim 1, wherein the depth of the wide trench is 50 to 400 nanometers.
3. The method of claim 2, wherein the semiconductor strip comprises silicon.
4. The method of claim 2, wherein the well or substrate comprises silicon.
5. The method of claim 3, wherein the gate conductor comprises polysilicon.
6. The method of claim 5, wherein the lining medium comprises a second flowable material consisting of chemical vapor deposition (CVD) oxides.
7. The method of claim 6, wherein the semiconductor strip is P-type silicon and the source and drain are N-type silicon.
8. The method of claim 6, wherein the first flowable material comprises silicon, nitrogen, and hydrogen.
9. A vertical gate transistor, fabricated by the method according to any one of claims 1 to 8, and comprising: A semiconductor strip of a first conductivity type extends from a source region of a second conductivity type to a drain region of the second conductivity type, the semiconductor strip being formed in a trench, the walls of the trench being insulated with a dielectric. Gate oxide formed on the two vertical walls of the semiconductor strip; as well as Gate material between the dielectric and the gate oxide.
10. The vertical gate transistor of claim 9, wherein the semiconductor strip comprises silicon.
11. The vertical gate transistor of claim 9, wherein the gate material comprises polysilicon.
12. The vertical gate transistor according to any one of claims 9 to 11, wherein the depth of the trench is between 50 and 400 nanometers.