Method, device and equipment for detecting IP core calls

Abstract

The present invention provides a method, apparatus, and device for detecting IP core invocations, belonging to the field of communications technology. The method includes: determining, based on first information, whether an IP core is invoked and / or suspected of being invoked in a target chip and / or information about the target chip; and / or, based on second information, determining whether an IP core is invoked and / or suspected of being invoked in the target chip and / or information about the target chip; wherein the target chip information can be one or more types of information. The present invention improves the accuracy and reliability of IP core invocation detection.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a method, device and equipment for detecting IP core calls. Background Art

[0002] Chip design is the core and source of the chip industry chain, and its autonomy and controllability plays a vital role in the autonomy and controllability of the entire chip.

[0003] As chip design scales, mature intellectual property cores (IP cores) are increasingly integrated into chip designs to reduce design time and improve efficiency. Therefore, the autonomy of IP cores is a key indicator of the controllability of chip design.

[0004] However, current IP core detection methods have limited accuracy and reliability. Summary of the Invention

[0005] In view of this, the present invention provides a method, apparatus and device for detecting IP core calls, which are used to solve the problem of limited accuracy and reliability of current chip IP core inspection methods.

[0006] To solve the above technical problems, in a first aspect, the present invention provides a method for detecting IP core calls, comprising:

[0007] Determining, based on the first information, whether an IP core is called and / or suspected of being called in the target chip and / or in the information of the target chip; and / or,

[0008] Determine the target chip and / or information of the target chip according to the second information, and call and / or suspected call IP core;

[0009] The information of the target chip is one type of information or multiple types of information.

[0010] In a second aspect, the present invention further provides an IP core call detection device, comprising:

[0011] An IP core calling judgment module is configured to determine, based on the first information, whether an IP core is called in a target chip and / or in the information of the target chip and / or whether an IP core is suspected of being called; and / or,

[0012] An IP core calling determination module is configured to determine the target chip and / or the information of the target chip according to the second information, and to call and / or suspect to call the IP core;

[0013] The information of the target chip is one type of information or multiple types of information.

[0014] Optionally, the target chip is a whole or partial chip, and the types of the chip include but are not limited to one or more of the following: a packaged chip, an unpackaged bare chip, a module in a bare chip, and a unit in a bare chip.

[0015] Optionally, the first information is the same as or different from the second information.

[0016] Optionally, the first information includes a chip design layout and / or a design layout and / or a design layout and wiring and / or a design layout and wiring diagram, and / or a physical chip and / or a physical layout and / or a physical layout and / or a physical layout and wiring and / or a physical layout and wiring diagram;

[0017] The IP core call judgment module includes but is not limited to one or more of the following:

[0018] A first judgment submodule is configured to determine that an IP core has been called and / or is suspected of being called in the target chip and / or in the information of the target chip if, in a chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, there is a blank area and / or the area of ​​the blank area is greater than or equal to a first preset threshold and / or the proportion of the blank area occupied is greater than or equal to a second preset threshold and / or the blank area is a regular geometric shape; the blank area occupancy ratio refers to the proportion of the blank area occupied by the design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, and the regular geometric shape includes but is not limited to one or more of the following: square, rectangle, rhombus, trapezoid, parallelogram, circle, ellipse, triangle, polygon, bow, and arc;

[0019] The second judgment submodule is used to compare the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram with the corresponding physical chip and / or physical layout and / or physical layout and / or physical layout wiring and / or physical layout wiring diagram. If the comparison is inconsistent, it is determined that the IP core is called and / or suspected to be called in the target chip and / or the information of the target chip. The inconsistent comparison includes but is not limited to one or more of the following: inconsistent comparison of all layers and / or part of the layers and / or one layer; inconsistent comparison of the entire area and / or multiple local areas and / or one local area in all layers and / or part of the layers and / or one layer;

[0020] A third judgment submodule is configured to determine that an IP core has been called and / or is suspected of being called in the target chip and / or in the information of the target chip if a first identifier exists in the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, and / or in the physical chip and / or physical layout and / or physical layout wiring and / or physical layout wiring diagram; the first identifier is an identifier of a company other than the design company of the target chip, and / or an identifier representing a company other than the design company of the target chip;

[0021] a fourth judgment submodule, configured to determine that an IP core has been called and / or is suspected of being called in the target chip and / or in the information of the target chip if a second identifier is present in the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, and / or in the physical chip and / or physical layout and / or physical layout wiring and / or physical layout wiring and / or physical layout wiring diagram; the second identifier being an identifier of a design company of the target chip and / or an identifier representing a design company of the target chip;

[0022] a fifth judgment submodule, configured to compare the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram with the layout and / or layout and / or layout wiring and / or layout wiring diagram in the first preset library; if a first area in the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram is identical and / or similar to a second area in the layout and / or layout and / or layout wiring and / or layout wiring diagram in the first preset library, and / or the degree of similarity is greater than or equal to a third preset threshold, then it is determined that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core; and the first preset library does not contain the layout and / or layout and / or layout wiring and / or layout wiring diagram designed by the design company of the target chip;

[0023] a sixth judgment submodule, configured to compare the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram with the layout and / or layout and / or layout wiring and / or layout wiring diagram in the second preset library; if the third area of ​​the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram is identical and / or similar to the fourth area of ​​the layout and / or layout and / or layout wiring and / or layout wiring diagram in the second preset library, and / or the similarity is greater than or equal to a fourth preset threshold, then it is determined that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core; the layout and / or layout and / or layout wiring and / or layout wiring diagram designed by the design company of the target chip in the second preset library, and / or the layout and / or layout and / or layout wiring and / or layout wiring diagram IP core library of the design company of the target chip, and / or the IP core library of the design company of the target chip;

[0024] a seventh judgment submodule, configured to compare the physical chip and / or the physical layout ...

[0025] an eighth judgment submodule, for comparing the physical chip and / or the physical layout and / or the physical layout and / or the physical layout wiring and / or the physical layout wiring diagram with the layout and / or the layout and / or the layout wiring and / or the layout wiring diagram in the fourth preset library; if the seventh area of ​​the physical chip and / or the physical layout and / or the physical layout and / or the physical layout wiring and / or the physical layout wiring diagram is consistent with the eighth area of ​​the layout and / or the layout and / or the layout wiring and / or the layout wiring diagram in the fourth preset library, If the information of the target chip and / or the target chip is the same and / or similar and / or the degree of similarity is greater than or equal to the sixth preset threshold, it is determined that the target chip and / or the information of the target chip has called the IP core and / or is suspected of calling the IP core; the fourth preset library includes the layout and / or layout and / or layout wiring and / or layout wiring diagram designed by the design company of the target chip, and / or the layout and / or layout and / or layout wiring and / or layout wiring diagram IP core library of the design company of the target chip, and / or the IP core library of the design company of the target chip.

[0026] Optionally, the first information includes a schematic diagram of the chip, and / or a chip design layout and / or a design layout and / or a design layout and wiring and / or a design layout and wiring diagram;

[0027] The IP core call judgment module includes but is not limited to one or more of the following:

[0028] a ninth judgment submodule, configured to determine that an IP core is called and / or is suspected of being called in the target chip and / or in the information of the target chip if a third identifier is present in the schematic diagram of the chip; the third identifier being an identifier of a company other than the design company of the target chip and / or an identifier representing a company other than the design company of the target chip;

[0029] a tenth judgment submodule, configured to determine that an IP core is called and / or is suspected of being called in the target chip and / or in the information of the target chip if a fourth identifier is present in the schematic diagram of the chip; the fourth identifier being an identifier of a design company of the target chip and / or an identifier representing a design company of the target chip;

[0030] an eleventh judgment submodule, configured to compare the schematic diagram of the chip with the schematic diagrams in a fifth preset library; if a ninth region in the chip schematic diagram is identical and / or similar to a tenth region in the schematic diagram in the fifth preset library and / or the degree of similarity is greater than or equal to a seventh preset threshold, then determining that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core; and the fifth preset library does not contain a schematic diagram designed by the design company of the target chip;

[0031] A twelfth judgment submodule is configured to compare the schematic diagram of the chip with the schematic diagram in the sixth preset library, and if the eleventh area in the chip schematic diagram is identical and / or similar to the twelfth area in the schematic diagram in the sixth preset library and / or the similarity is greater than or equal to an eighth preset threshold, then it is determined that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core; the schematic diagram designed by the design company of the target chip in the sixth preset library, and / or the schematic IP core library of the design company of the target chip, and / or the IP core library of the design company of the target chip;

[0032] a thirteenth judgment submodule, configured to perform one or more LVS verifications on the schematic diagram of the chip and the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram using one or more LVS verification software and / or tools and / or environments; if one or more LVS verifications fail, determining that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core;

[0033] The fourteenth judgment submodule is used to modify the names of one or part of or all of the modules and / or units in the schematic diagram of the chip and the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, and use one or more LVS verification software and / or tools and / or environments to perform one or more LVS verifications after the modification. If one or more LVS verifications fail, it is determined that the target chip and / or the information of the target chip has called the IP core and / or is suspected of calling the IP core.

[0034] Optionally, the first information includes a chip transistor-level netlist, and / or a chip design layout and / or a design layout and / or a design layout wiring and / or a design layout wiring diagram; the transistor-level netlist includes but is not limited to one or more of the following: a netlist described as transistor-level, a transistor-level netlist corresponding to a chip schematic diagram, a transistor-level netlist corresponding to a gate-level netlist of a final design of the chip, a transistor-level netlist corresponding to the chip design layout and / or a design layout and / or a design layout wiring and / or a design layout wiring diagram, a transistor-level netlist in an analog-digital hybrid chip composed of a transistor-level netlist corresponding to a transistor-level netlist corresponding to a schematic diagram of an analog module and / or a transistor-level netlist corresponding to a gate-level netlist of a final design of a digital module;

[0035] The IP core call judgment module includes but is not limited to one or more of the following:

[0036] A fifteenth judgment submodule is configured to determine that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core if a fifth identifier exists in the chip transistor-level netlist; the fifth identifier being an identifier of a company other than the design company of the target chip and / or an identifier representing a company other than the design company of the target chip;

[0037] A sixteenth judgment submodule is configured to determine that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core if a sixth identifier exists in the chip transistor-level netlist; the sixth identifier being an identifier of a design company of the target chip and / or an identifier representing a design company of the target chip;

[0038] A seventeenth judgment submodule is configured to compare the transistor-level netlist of the chip with the transistor-level netlist in a seventh preset library; if a first portion of the transistor-level netlist of the chip is identical and / or similar to a second portion of the transistor-level netlist in the seventh preset library and / or the degree of similarity is greater than or equal to a ninth preset threshold, then it is determined that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core; and the seventh preset library does not contain a transistor-level netlist designed by the design company of the target chip;

[0039] An eighteenth judgment submodule is configured to compare the transistor-level netlist of the chip with the transistor-level netlist in an eighth preset library; if the third portion of the transistor-level netlist of the chip is identical and / or similar and / or the similarity is greater than or equal to a tenth preset threshold, then it is determined that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core; the transistor-level netlist designed by the design company of the target chip in the eighth preset library, and / or the transistor-level netlist IP core library of the design company of the target chip, and / or the IP core library of the design company of the target chip;

[0040] a nineteenth judgment submodule, configured to perform one or more LVS verifications on the chip transistor-level netlist and the chip design layout and / or design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram using one or more LVS verification software and / or tools and / or environments; if one or more LVS verifications fail, determining that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core;

[0041] The twentieth judgment submodule is used to modify the names of one or part of or all of the modules and / or units with respect to the chip transistor-level netlist and the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, and perform one or more LVS verifications in one or more LVS verification software and / or tools and / or environments after the modification. If one or more of the LVS verifications fails, it is determined that the target chip and / or the information of the target chip has called the IP core and / or is suspected of calling the IP core.

[0042] Optionally, the first information includes a gate-level netlist of the chip, and / or a chip design layout and / or a design layout and / or a design layout and wiring and / or a design layout and wiring diagram; the gate-level netlist of the chip includes but is not limited to one or more of the following: a gate-level netlist for completing the final design, a gate-level netlist corresponding to the chip design layout and / or design layout and / or design layout and wiring and / or a design layout and wiring diagram, a gate-level netlist formed by synthesizing the chip register transfer-level RTL code, a front-end gate-level netlist, a back-end gate-level netlist, and a gate-level netlist during the chip design process; the front-end gate-level netlist and / or the back-end gate-level netlist and / or the gate-level netlist during the chip design process include but are not limited to one or more gate-level netlists;

[0043] The IP core call judgment module includes but is not limited to one or more of the following:

[0044] A twenty-first judgment submodule is configured to determine that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core if a seventh identifier exists in the gate-level netlist of the chip; the seventh identifier being an identifier of a company other than the design company of the target chip and / or an identifier representing a company other than the design company of the target chip;

[0045] A twenty-second judgment submodule is configured to determine that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core if an eighth identifier exists in the gate-level netlist of the chip; the eighth identifier being an identifier of a design company of the target chip and / or an identifier representing a design company of the target chip;

[0046] a twenty-third judgment submodule, configured to compare the gate-level netlist of the chip with the gate-level netlist in a ninth preset library; if the fifth portion of the gate-level netlist of the chip is identical and / or similar to the sixth portion of the gate-level netlist in the ninth preset library and / or the degree of similarity is greater than or equal to an eleventh preset threshold, then determining that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core; and the ninth preset library does not contain a gate-level netlist designed by the design company of the target chip;

[0047] a twenty-fourth judgment submodule, configured to compare the gate-level netlist of the chip with the gate-level netlist in the tenth preset library; if the seventh portion of the gate-level netlist of the chip is identical and / or similar and / or the similarity is greater than or equal to a twelfth preset threshold to the eighth portion of the gate-level netlist in the tenth preset library, then determining that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core; the gate-level netlist designed by the design company of the target chip in the tenth preset library, and / or the gate-level netlist IP core library of the design company of the target chip, and / or the IP core library of the design company of the target chip;

[0048] a twenty-fifth judgment submodule, configured to perform one or more LVS verifications on the gate-level netlist of the chip and the chip design layout and / or design layout and / or design layout and / or design layout and wiring and / or design layout and wiring diagram using one or more LVS verification software and / or tools and / or environments; if one or more of the LVS verifications fail, determining that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core;

[0049] a twenty-sixth judgment submodule, configured to modify the names of one, a portion of, or all of the modules and / or units of the gate-level netlist of the chip and the chip design layout and / or design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, and perform one or more LVS verifications in one or more LVS verification software and / or tools and / or environments after the modification; if one or more LVS verifications fail, determining that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core;

[0050] a twenty-seventh judgment submodule, configured to convert the gate-level netlist of the chip into a chip transistor-level netlist, and then, using one or more LVS verification software and / or tools and / or environments, perform one or more LVS verifications on the converted chip transistor-level netlist and the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram; if one or more of the LVS verifications fail, determining that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core;

[0051] a twenty-eighth judgment submodule, configured to convert the gate-level netlist of the chip into a chip transistor-level netlist, and then, for the converted chip transistor-level netlist and the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, modify the names of one, a portion of, or all of the modules and / or units, and perform one or more LVS verifications in one or more LVS verification software and / or tools and / or environments after the modification; if one or more LVS verifications fail, determining that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core;

[0052] a twenty-ninth judgment submodule, configured to modify the names of one, part of, or all of the modules and / or units of the chip's gate-level netlist and the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, and then convert the modified gate-level netlist into a chip transistor-level netlist; and perform one or more LVS verifications on the converted chip transistor-level netlist and the modified chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram using one or more LVS verification software and / or tools and / or environments; if one or more of the LVS verifications fail, it is determined that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core;

[0053] a 30th judgment submodule, configured to perform one or more formal verifications on two gate-level netlists of the chip using one or more formal verification software and / or tools and / or environments, and if one or more of the formal verifications fail, determining that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core;

[0054] a thirty-first judgment submodule, configured to modify the names of one, a portion of, or all of the modules and / or units of the two gate-level netlists of the chip, and perform one or more formal verifications using one or more formal verification software and / or tools and / or environments after the modifications; if one or more of the formal verifications fail, determining that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core;

[0055] Among them, when carrying out formal verification, if there are differences in the functions and / or logic of auxiliary design and / or auxiliary testing between the two gate-level netlists, the functions and / or logic corresponding to the differences are not verified or verified; wherein, the functions and / or logic corresponding to the differences are not verified, including but not limited to: when setting constants, prohibiting the functions and / or logic and / or pins and / or pins of auxiliary design and / or auxiliary testing, and / or setting the functions and / or logic and / or pins and / or pins of auxiliary design and / or auxiliary testing to be invalid; the functions and / or logic and / or pins and / or pins of the auxiliary design and / or auxiliary testing include but are not limited to one or more of the following: scanning the SCAN chain and / or the enable pins and / or enable pins corresponding to the SCAN chain, the JTAG chain and / or the enable pins and / or enable pins corresponding to the JTAG chain, and the pins and / or pins corresponding to the chip testability design and / or the testability design.

[0056] Optionally, the first information includes chip RTL code, and / or a gate-level netlist of the chip; the gate-level netlist of the chip includes but is not limited to one or more of the following: a gate-level netlist for completing the final design, a gate-level netlist corresponding to the chip design layout and / or design layout and / or design layout and wiring and / or design layout and wiring diagram, a gate-level netlist formed by synthesizing the chip RTL code, a front-end gate-level netlist, a back-end gate-level netlist, and a gate-level netlist during the chip design process; the front-end gate-level netlist and / or back-end gate-level netlist and / or gate-level netlist during the chip design process include but are not limited to one or more gate-level netlists;

[0057] The IP core call judgment module includes but is not limited to one or more of the following:

[0058] A thirty-second judgment submodule is configured to determine, if a ninth identifier is present in the chip RTL code, that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core; the ninth identifier being an identifier of a company other than the design company of the target chip and / or an identifier representing a company other than the design company of the target chip;

[0059] A thirty-third judgment submodule is configured to determine that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core if a tenth identifier exists in the chip RTL code; the tenth identifier is an identifier of a design company of the target chip and / or an identifier representing a design company of the target chip;

[0060] The thirty-fourth judgment submodule is used to determine whether the target chip and / or the information of the target chip has called the IP core and / or is suspected of calling the IP core if there are other level descriptions except the register transfer level description in the chip RTL code; the other level descriptions except the register transfer level description include but are not limited to gate level descriptions; wherein, the thirty-fourth judgment submodule is also used to check whether there are other level descriptions except the register transfer level description in the chip RTL code, and the thirty-fourth judgment submodule includes but is not limited to one or more of the following: a first retrieval unit, used to perform keyword retrieval on the chip RTL code; a first comparison unit, used to compare the chip RTL code with the gate-level netlist of the chip, if the ninth part in the chip RTL code is the same and / or similar to the tenth part of the gate-level netlist of the chip and / or the similarity is greater than or equal to the thirteenth preset threshold, then it is determined that there are other level descriptions except the register transfer level description in the chip RTL code; wherein, the first retrieval unit includes but is not limited to one or more of the following: a first retrieval submodule, used to use a keyword representing other level descriptions except the register transfer level description The RTL code is searched using one or more keywords, and if it is found that one or more keywords exist in the RTL code and / or the total number of one or more keywords in the RTL code is greater than or equal to a fourteenth preset threshold and / or the proportion of the total number of one or more keywords in the RTL code to the total number of RTL code words is greater than or equal to a fifteenth preset threshold, it is determined that other levels of description except the register transfer level description exist in the chip RTL code; a second retrieval subunit is used to search the RTL code using one or more keywords representing the register transfer level description, and if it is found that various keywords do not exist in the RTL code and / or one or more keywords do not exist in the RTL code, it is determined that other levels of description except the register transfer level description exist in the chip RTL code; the types of keywords include but are not limited to one or more of the following: code at the representation description level, vocabulary and / or phrases at the representation description level, script at the representation description level, program at the representation description level, RTL code at the representation description level, netlist at the representation description level, wherein the netlist includes but is not limited to a gate-level netlist;

[0061] a thirty-fifth judgment submodule, configured to compare the chip RTL code with the RTL code in an eleventh preset library; if an eleventh portion of the chip RTL code is identical and / or similar to a twelfth portion of the RTL code in the eleventh preset library and / or the degree of similarity is greater than or equal to a sixteenth preset threshold, then determining that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core; and the eleventh preset library does not contain the RTL code designed by the design company of the target chip;

[0062] A thirty-sixth judgment submodule is configured to compare the chip RTL code with the RTL code in a twelfth preset library. If a thirteenth part of the chip RTL code is identical and / or similar to a fourteenth part of the RTL code in the twelfth preset library and / or the similarity is greater than or equal to a seventeenth preset threshold, it is determined that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core; the RTL code designed by the design company of the target chip in the twelfth preset library, and / or the RTL code IP core library of the design company of the target chip, and / or the IP core library of the design company of the target chip;

[0063] A thirty-seventh judgment submodule is configured to perform one or more formal verifications on the chip RTL code and the gate-level netlist of the chip using one or more formal verification software and / or tools and / or environments; if one or more of the formal verifications fail, determining that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core;

[0064] A thirty-eighth judgment submodule is configured to modify the names of one, a portion of, or all of the modules and / or units in the chip RTL code and the gate-level netlist of the chip, and perform one or more formal verifications using one or more formal verification software and / or tools and / or environments after the modification; if any one or more formal verifications fail, it is determined that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core;

[0065] Among them, when carrying out formal verification, if there are differences between the RTL code and the gate-level netlist in the functions and / or logic of auxiliary design and / or auxiliary testing, the functions and / or logic corresponding to the differences are not verified or verified; wherein, the functions and / or logic corresponding to the differences are not verified, including but not limited to: when setting constants, prohibiting the functions and / or logic and / or pins and / or pins of auxiliary design and / or auxiliary testing, and / or setting the functions and / or logic and / or pins and / or pins of auxiliary design and / or auxiliary testing to be invalid; the functions and / or logic and / or pins and / or pins of the auxiliary design and / or auxiliary testing include but are not limited to one or more of the following: scanning the SCAN chain and / or the enable pin and / or enable pin corresponding to the SCAN chain, the JTAG chain and / or the enable pin and / or enable pin corresponding to the JTAG chain, and the chip testability design and / or the pins and / or pins corresponding to the testability design.

[0066] Optionally, the second information includes a chip design layout and / or a design layout and / or a design layout and wiring and / or a design layout and wiring diagram, and / or a physical chip and / or a physical layout and / or a physical layout and / or a physical layout and wiring and / or a physical layout and wiring diagram;

[0067] The IP core call determination module includes but is not limited to one or more of the following:

[0068] a first determining submodule, configured to determine a blank area in a chip design layout and / or a design layout and / or a design layout wiring and / or a design layout wiring diagram, and / or a blank area with an area greater than or equal to an eighteenth preset threshold, and / or a blank area with an occupancy ratio greater than or equal to a nineteenth preset threshold, and / or a blank area of ​​a regular geometric figure, and determine the blank area, and / or the design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram corresponding to the blank area, and / or the module and / or unit and / or design information corresponding to the blank area as the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; the occupancy ratio refers to the ratio of the blank area to the design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram; the regular geometric figure includes but is not limited to one or more of the following: square, rectangle, rhombus, trapezoid, parallelogram, circle, ellipse, triangle, polygon, arc, and arc; the blank area includes but is not limited to one or more areas;

[0069] The second determination submodule is used to determine the inconsistencies when comparing the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram with the corresponding chip physical object and / or physical layout and / or physical layout and / or physical layout wiring and / or physical layout wiring diagram, and to compare the inconsistencies, and / or the design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram corresponding to the inconsistencies, and / or the chip physical object and / or physical layout and / or physical layout and / or physical layout wiring and / or physical layout wiring diagram corresponding to the inconsistencies. , and / or the modules and / or units and / or design information corresponding to the inconsistencies are determined to be the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; wherein the inconsistencies include but are not limited to one or more of the following situations: inconsistencies in comparison of all layers and / or part of the layers and / or one layer; inconsistencies in comparison of the entire area and / or multiple local areas and / or one local area in all layers and / or part of the layers and / or one layer; the inconsistencies include but are not limited to one or more layouts and / or layout drawings and / or layout and wiring and / or layout and wiring diagrams;

[0070] A third determination submodule is used to determine that the position of the eleventh identifier in the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, and / or the physical chip and / or physical layout and / or physical layout wiring and / or physical layout wiring and / or physical layout wiring diagram is located, and / or the area where the eleventh identifier is located and / or the area whose distance from the eleventh identifier is less than or equal to the twentieth preset threshold, and / or the module and / or unit and / or design information corresponding to the position and / or area and / or the eleventh identifier is the target chip and / or the information call of the target chip and / or the IP core suspected of being called;

[0071] A fourth determination submodule is configured to determine the position of the eleventh identifier in the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, and / or the physical chip and / or physical layout and / or physical layout wiring and / or physical layout wiring and / or physical layout wiring diagram, and / or the area where the eleventh identifier is located and / or an area whose distance from the eleventh identifier is less than or equal to a twenty-first preset threshold, and / or the module and / or unit and / or design information corresponding to the position and / or area and / or the eleventh identifier, and then determine the position and / or area of ​​one or more layers, and / or the modules and / or units and / or design information corresponding to the position and / or area of ​​the one or more layers as the target chip and / or the information call and / or suspected call of the IP core of the target chip; wherein the twenty-first preset threshold is the same as or different from the twenty-first preset threshold;

[0072] The eleventh identifier is an identifier of a company other than the design company of the target chip, and / or an identifier representing a company other than the design company of the target chip;

[0073] A fifth determination submodule is used to determine that the position of the twelfth identifier in the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, and / or the physical chip and / or physical layout and / or physical layout wiring and / or physical layout wiring and / or physical layout wiring diagram is located, and / or the area where the twelfth identifier is located and / or the area whose distance from the twelfth identifier is less than or equal to the twenty-second preset threshold, and / or the module and / or unit and / or design information corresponding to the position and / or area and / or the twelfth identifier is the target chip and / or the information call of the target chip and / or the IP core suspected of being called;

[0074] A sixth determination submodule is used to determine the position of the twelfth identifier in the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, and / or the physical chip and / or physical layout and / or physical layout wiring and / or physical layout wiring and / or physical layout wiring diagram, and / or the position of the twelfth identifier and / or the area where the twelfth identifier is located and / or the area whose distance from the twelfth identifier is less than or equal to the twenty-third preset threshold, and / or the module and / or unit and / or design information corresponding to the position and / or area and / or the twelfth identifier, and then determine the position and / or area of ​​one or more layers, and / or the modules and / or units and / or design information corresponding to the position and / or area of ​​the one or more layers as the target chip and / or the information call and / or suspected call of the IP core of the target chip; wherein the twenty-third preset threshold is the same as or different from the twenty-second preset threshold;

[0075] The twelfth identifier is an identifier of a design company of the target chip and / or an identifier representing a design company of the target chip;

[0076] a seventh determination submodule, for determining the fourteenth region in the chip design layout and / or design layout and / or design layout and / or design layout and / or design layout diagram, and / or the module and / or unit and / or design information corresponding to the fourteenth region, which is identical and / or similar and / or has a similarity greater than or equal to a twenty-fourth preset threshold, as the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; the thirteenth preset library does not contain the layout and / or layout and / or layout and / or layout diagram designed by the design company of the target chip;

[0077] an eighth determination submodule, for determining the sixteenth region in the chip design layout and / or design layout and / or design layout and / or design layout and / or design layout and / or design layout, which is identical and / or similar and / or has a similarity greater than or equal to the twenty-fifth preset threshold to be the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; the layout and / or layout and / or layout and / or layout and / or layout diagram designed by the design company of the target chip in the fourteenth preset library, and / or the layout and / or layout and / or layout and / or layout diagram IP core library of the design company of the target chip, and / or the IP core library of the design company of the target chip;

[0078] a ninth determination submodule, configured to determine the eighteenth region of the physical chip and / or the physical layout and / or the physical layout and / or the physical layout and / or the physical layout and / or the design information corresponding to the eighteenth region, which is identical and / or similar and / or has a similarity greater than or equal to the seventeenth region of the layout and / or the layout and / or the layout and wiring and / or the layout and wiring diagram in the fifteenth preset library, as the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; the fifteenth preset library does not contain the layout and / or the layout and / or the layout and wiring and / or the layout and wiring diagram designed by the design company of the target chip;

[0079] a tenth determining submodule, configured to determine the twentieth region of the physical chip and / or the physical layout and / or the physical layout and / or the physical layout and / or the physical layout and / or the design information corresponding to the twentieth region, which is identical and / or similar and / or has a similarity greater than or equal to a twenty-seventh preset threshold to the nineteenth region of the layout and / or the layout and / or the layout and wiring and / or the layout and wiring diagram in the sixteenth preset library, as the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; the layout and / or the layout and / or the layout and wiring and / or the layout and wiring diagram designed by the design company of the target chip in the sixteenth preset library, and / or the IP core library of the layout and / or the layout and / or the layout and / or the layout and / or the layout and wiring and / or the layout and wiring diagram IP core library of the design company of the target chip, and / or the IP core library of the design company of the target chip;

[0080] The eleventh determination submodule is used to determine the position and / or area of ​​the physical chip and / or physical layout and / or physical layout and / or physical layout wiring and / or physical layout wiring diagram of the target chip and / or the IP core called by the information and / or suspected call of the target chip, and / or the module and / or unit and / or design information corresponding to the position and / or area, the corresponding chip design layout and / or design layout and / or design layout wiring and / or the position and / or area, and / or the module and / or unit and / or design information corresponding to the position and / or area as the target chip and / or the IP core called by the information and / or suspected call of the target chip.

[0081] Optionally, the second information includes a schematic diagram of the chip, and / or a chip design layout and / or a design layout and / or a design layout and wiring and / or a design layout and wiring diagram;

[0082] The IP core call determination module includes but is not limited to one or more of the following:

[0083] A twelfth determination submodule is used to determine that the position of the thirteenth identifier in the schematic diagram of the chip and / or the area where the thirteenth identifier is located and / or the area whose distance from the thirteenth identifier is less than or equal to the twenty-eighth preset threshold, and / or the module and / or unit and / or design information corresponding to the position and / or area and / or the thirteenth identifier is the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; the thirteenth identifier is an identifier of a company other than the design company of the target chip, and / or an identifier representing a company other than the design company of the target chip;

[0084] A fourteenth determination submodule is used to determine that the position of the fourteenth identifier in the schematic diagram of the chip and / or the area where the fourteenth identifier is located and / or the area whose distance from the fourteenth identifier is less than or equal to the twenty-ninth preset threshold, and / or the module and / or unit and / or design information corresponding to the position and / or area and / or the fourteenth identifier is the target chip and / or the IP core called by the information of the target chip and / or suspected of being called; the fourteenth identifier is the identifier of the design company of the target chip and / or the identifier representing the design company of the target chip;

[0085] a fifteenth determining submodule, for determining the twenty-second region in the schematic diagram of the chip, and / or the module and / or unit and / or design information corresponding to the twenty-second region, which is identical and / or similar and / or has a similarity greater than or equal to a thirtieth preset threshold to be the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; the seventeenth preset library does not contain a schematic designed by the design company of the target chip;

[0086] A sixteenth determination submodule is configured to determine the twenty-fourth area in the schematic diagram of the chip, which is identical and / or similar and / or has a similarity greater than or equal to a thirty-first preset threshold, and / or the module and / or unit and / or design information corresponding to the twenty-fourth area as the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; the schematics designed by the design company of the target chip in the eighteenth preset library, and / or the schematic IP core library of the design company of the target chip, and / or the IP core library of the design company of the target chip;

[0087] The seventeenth determination submodule is used to determine the target chip and / or the information call and / or suspected call IP core of the target chip based on the chip schematic and chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, and the results and / or reports of the failed LVS verification using one or more LVS verification software and / or tools and / or environments; the seventeenth determination submodule includes but is not limited to one or more of the following: a first determination unit is used to determine the schematic area that failed in the verification, and / or the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram area that failed, and / or the failed The module and / or unit and / or design information corresponding to the area is the target chip and / or the IP core called and / or suspected to be called by the information of the target chip; a second determining unit is used to determine that the devices and / or connection relationships in the schematic diagram found in the verification, the differences between the devices and / or connection relationships in the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, and / or the schematic diagram area, and / or chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram area, and / or module, and / or unit, and / or design information corresponding to the differences are the target chip and / or the IP core called and / or suspected to be called by the information of the target chip;

[0088] An eighteenth determination submodule is used to determine the target chip and / or the information call and / or suspected call IP core of the target chip based on the chip schematic and chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, after modifying the names of one or part of or all of the modules and / or units, and using one or more LVS verification software and / or tools and / or environments to perform one or more LVS verifications, and the results and / or reports of the failed LVS verifications; the eighteenth determination submodule includes but is not limited to one or more of the following: a third determination unit is used to determine the schematic area that failed the verification, and / or the chip design layout and / or design layout and / or design layout wiring and / or the failed LVS verification. or the design layout wiring diagram area, and / or the module and / or unit and / or design information corresponding to the failed area is the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; a fourth determination unit is used to determine that the devices and / or connection relationships in the schematic diagram found in the verification, the differences with the devices and / or connection relationships in the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, and / or the schematic diagram area, and / or chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram area, and / or module, and / or unit, and / or design information corresponding to the differences are the target chip and / or the IP core called and / or suspected of being called by the information of the target chip.

[0089] Optionally, the second information includes a chip transistor-level netlist, and / or a chip design layout and / or a design layout and / or a design layout wiring and / or a design layout wiring diagram; the transistor-level netlist includes but is not limited to one or more of the following: a netlist described as transistor-level, a transistor-level netlist corresponding to a chip schematic diagram, a transistor-level netlist corresponding to a gate-level netlist of a final chip design, a transistor-level netlist corresponding to a chip design layout and / or a design layout and / or a design layout wiring and / or a design layout wiring diagram, a transistor-level netlist in an analog-digital hybrid chip composed of a transistor-level netlist corresponding to a transistor-level netlist corresponding to a schematic diagram of an analog module and / or a transistor-level netlist corresponding to a gate-level netlist of a final digital module design;

[0090] The IP core call determination module includes but is not limited to one or more of the following:

[0091] A nineteenth determination submodule is used to determine that the position of the fifteenth identifier in the chip transistor-level netlist and / or the part where the fifteenth identifier is located and / or the part where the code length between the fifteenth identifier and the fifteenth identifier is less than or equal to the thirty-second preset threshold and / or the part where the code length between the fifteenth identifier and the fifteenth identifier accounts for less than or equal to the first proportion threshold in the chip transistor-level netlist, and / or the module and / or unit and / or design information corresponding to the position and / or part and / or the fifteenth identifier is the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; the fifteenth identifier is an identifier of a company other than the design company of the target chip, and / or an identifier representing a company other than the design company of the target chip;

[0092] A twentieth determination submodule is used to determine that the position of the sixteenth identifier in the chip transistor-level netlist and / or the part where the sixteenth identifier is located and / or the part where the code length between the sixteenth identifier and the sixteenth identifier is less than or equal to the thirty-third preset threshold and / or the part where the code length between the sixteenth identifier and the sixteenth identifier accounts for less than or equal to the second proportion threshold in the chip transistor-level netlist, and / or the module and / or unit and / or design information corresponding to the position and / or part and / or the sixteenth identifier is the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; the sixteenth identifier is the identifier of the design company of the target chip and / or the identifier representing the design company of the target chip;

[0093] a twenty-first determining submodule, configured to determine the sixteenth part of the transistor-level netlist of the chip, which is identical and / or similar and / or has a similarity greater than or equal to a thirty-fourth preset threshold, and / or the module and / or unit and / or design information corresponding to the sixteenth part, as the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; the nineteenth preset library does not contain a transistor-level netlist designed by the design company of the target chip;

[0094] a twenty-second determining submodule, configured to determine the eighteenth part in the transistor-level netlist of the chip, which is identical and / or similar and / or has a similarity greater than or equal to a thirty-fifth preset threshold, and / or the module and / or unit and / or design information corresponding to the eighteenth part, as the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; the transistor-level netlist designed by the design company of the target chip in the twenty-first preset library, and / or the transistor-level netlist IP core library of the design company of the target chip, and / or the IP core library of the design company of the target chip;

[0095] The twenty-third determination submodule is used to determine the target chip and / or the information call and / or suspected call IP core of the target chip based on the chip transistor-level netlist and the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, and the results and / or reports of the failed LVS verification performed one or more times using one or more LVS verification software and / or tools and / or environments; the twenty-third determination submodule includes but is not limited to one or more of the following: a fifth determination unit, used to determine the transistor-level netlist portion that failed in the verification, and / or the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram area that failed, and / or the failed portion and / or the module and / or unit and / or design information corresponding to the failed area is the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; a sixth determining unit, used to determine that the devices and / or connection relationships in the transistor-level netlist found in the verification, the differences between the devices and / or connection relationships in the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, and / or the transistor-level netlist part, and / or chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram area, and / or module, and / or unit, and / or design information corresponding to the differences are the target chip and / or the IP core called and / or suspected of being called by the information of the target chip;

[0096] The twenty-fourth determination submodule is used to determine the target chip and / or the information call and / or suspected call IP core of the target chip based on the chip transistor-level netlist and the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, after modifying the names of one or part of or all of the modules and / or units, and using one or more LVS verification software and / or tools and / or environments to perform one or more LVS verifications, and the results and / or reports of the LVS verifications that failed; the twenty-fourth determination submodule includes but is not limited to one or more of the following: a seventh determination unit, used to determine the transistor-level netlist portion that failed in the verification, and / or the chip design layout and / or design layout and / or design layout wiring and / or design that failed The modules and / or units and / or design information corresponding to the layout and wiring diagram area, and / or the failed part and / or the failed area are the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; the eighth determination unit is used to determine that the devices and / or connection relationships in the transistor-level netlist found in the verification, the differences with the devices and / or connection relationships in the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, and / or the transistor-level netlist part, and / or chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram area, and / or module, and / or unit, and / or design information corresponding to the differences are the target chip and / or the IP core called and / or suspected of being called by the information of the target chip.

[0097] Optionally, the second information includes a gate-level netlist of the chip, and / or a chip design layout and / or a design layout and / or a design layout and wiring and / or a design layout and wiring diagram; the gate-level netlist of the chip includes but is not limited to one or more of the following: a gate-level netlist for completing the final design, a gate-level netlist corresponding to the chip design layout and / or design layout and / or design layout and wiring and / or the design layout and wiring diagram, a gate-level netlist synthesized from the chip RTL code, a front-end gate-level netlist, a back-end gate-level netlist, and a gate-level netlist during the chip design process; the front-end gate-level netlist and / or the back-end gate-level netlist and / or the gate-level netlist during the chip design process include but are not limited to one or more gate-level netlists;

[0098] The IP core call determination module includes but is not limited to one or more of the following:

[0099] The twenty-fifth determination submodule is used to determine that the position of the seventeenth identifier in the gate-level netlist of the chip and / or the part where the seventeenth identifier is located and / or the part where the code length between the seventeenth identifier and the seventeenth identifier is less than or equal to the thirty-sixth preset threshold and / or the part where the code length between the seventeenth identifier and the seventeenth identifier accounts for less than or equal to the third proportion threshold in the gate-level netlist of the chip, and / or the module and / or unit and / or design information corresponding to the position and / or part and / or the seventeenth identifier is the target chip and / or the information call and / or suspected call of the IP core of the target chip; the seventeenth identifier is an identifier of a company other than the design company of the target chip, and / or an identifier representing a company other than the design company of the target chip;

[0100] The twenty-sixth determination submodule is used to determine that the position of the eighteenth identifier in the gate-level netlist of the chip and / or the part where the eighteenth identifier is located and / or the part where the code length between the eighteenth identifier and the eighteenth identifier is less than or equal to the thirty-seventh preset threshold and / or the part where the code length between the eighteenth identifier and the eighteenth identifier accounts for less than or equal to the fourth proportion threshold in the gate-level netlist of the chip, and / or the module and / or unit and / or design information corresponding to the position and / or part and / or the eighteenth identifier is the target chip and / or the IP core called by the information of the target chip and / or suspected of being called; the eighteenth identifier is the identifier of the design company of the target chip, and / or the identifier representing the design company of the target chip;

[0101] a twenty-seventh determining submodule, configured to determine the twentieth part in the gate-level netlist of the chip, and / or the module and / or unit and / or design information corresponding to the twentieth part, which is identical and / or similar and / or has a similarity greater than or equal to a thirty-eighth preset threshold to the nineteenth part of the gate-level netlist in the twenty-first preset library, as the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; the twenty-first preset library does not contain a gate-level netlist designed by the design company of the target chip;

[0102] a twenty-eighth determination submodule, configured to determine the twenty-second part in the gate-level netlist of the chip, which is identical and / or similar and / or has a similarity greater than or equal to a thirty-ninth preset threshold, and / or the module and / or unit and / or design information corresponding to the twenty-second part, as the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; the gate-level netlist designed by the design company of the target chip in the twenty-second preset library, and / or the gate-level netlist IP core library of the design company of the target chip, and / or the IP core library of the design company of the target chip;

[0103] The twenty-ninth determination submodule is used to determine the target chip and / or the information call and / or suspected call IP core of the target chip based on the gate-level netlist of the chip and the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, and the results and / or reports of the failed LVS verification using one or more LVS verification software and / or tools and / or environments; the twenty-ninth determination submodule includes but is not limited to one or more of the following: the ninth determination unit is used to determine the gate-level netlist part that failed in the verification, and / or the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram area that failed, and / or the failed part and / or the module and / or unit and / or design information corresponding to the failed area is the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; a tenth determining unit, used to determine that the devices and / or connection relationships in the gate-level netlist found in the verification, the differences between the devices and / or connection relationships in the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, and / or the gate-level netlist parts, and / or chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram areas, and / or modules, and / or units, and / or design information corresponding to the differences are the target chip and / or the IP core called and / or suspected of being called by the information of the target chip;

[0104] The 30th determination submodule is used to determine the target chip and / or the information call and / or suspected call IP core of the target chip based on the gate-level netlist of the chip and the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, after modifying the names of one or part of or all of the modules and / or units, and using one or more LVS verification software and / or tools and / or environments to perform one or more LVS verifications, and the results and / or reports of the LVS verifications that failed; the 30th determination submodule includes but is not limited to one or more of the following: an eleventh determination unit is used to determine the gate-level netlist part that failed in the verification, and / or the chip design layout and / or design layout and / or design layout wiring and / or design layout diagram that failed. The module and / or unit and / or design information corresponding to the local wiring diagram area, and / or the failed part and / or the failed area are the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; a twelfth determining unit, used to determine that the devices and / or connection relationships in the gate-level netlist found in the verification, the differences between the devices and / or connection relationships in the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, and / or the gate-level netlist part, and / or chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram area, and / or module, and / or unit, and / or design information corresponding to the differences are the target chip and / or the IP core called and / or suspected of being called by the information of the target chip;

[0105] The thirty-first determination submodule is used to determine the target chip and / or the information call and / or suspected call of the target chip IP core based on the converted chip transistor-level netlist and the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram after the chip gate-level netlist is converted into the chip transistor-level netlist, and the results and / or reports of the failed LVS verification performed one or more times using one or more LVS verification software and / or tools and / or environments; the thirty-first determination submodule includes but is not limited to one or more of the following: a thirteenth determination unit is used to determine the transistor-level netlist portion that failed in the verification, and / or the gate-level netlist portion corresponding to the failed transistor-level netlist portion, and / or the failed chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram The area, and / or the module and / or unit and / or design information corresponding to the failed part and / or the failed area are the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; a fourteenth determining unit, used to determine that the devices and / or connection relationships in the transistor-level netlist found in the verification, the differences between the devices and / or connection relationships in the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, and / or the transistor-level netlist part corresponding to the difference, and / or the gate-level netlist part corresponding to the corresponding transistor-level netlist part, and / or the corresponding chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram area, and / or module, and / or unit, and / or design information are the target chip and / or the IP core called and / or suspected of being called by the information of the target chip;

[0106] The thirty-second determination submodule is used to determine the target chip and / or the target chip's information call and / or suspected call IP core based on the converted chip transistor-level netlist and the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram after converting the chip's gate-level netlist into the chip transistor-level netlist and modifying the names of one or part of or all of the modules and / or units, and performing one or more LVS verifications using one or more LVS verification software and / or tools and / or environments, and the results and / or reports of the failed LVS verifications; the thirty-second determination submodule includes but is not limited to one or more of the following: a fifteenth determination unit, used to determine the transistor-level netlist portion that failed in the verification, and / or the gate-level netlist portion corresponding to the failed transistor-level netlist portion, and / or the failed chip design layout and / or design layout and / or The module and / or unit and / or design information corresponding to the design layout and / or design layout and wiring diagram area, and / or the failed part and / or the failed area are the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; a sixteenth determining unit, used to determine that the devices and / or connection relationships in the transistor-level netlist discovered during the verification, the differences between the devices and / or connection relationships in the chip design layout and / or design layout and / or design layout and / or design layout and wiring and / or design layout and wiring diagram, and / or the transistor-level netlist part corresponding to the difference, and / or the gate-level netlist part corresponding to the corresponding transistor-level netlist part, and / or the corresponding chip design layout and / or design layout and / or design layout and / or design layout and wiring and / or design layout and wiring diagram area, and / or module, and / or unit, and / or design information are the target chip and / or the IP core called and / or suspected of being called by the information of the target chip;

[0107] The thirty-third determination submodule is used to determine the target chip and / or the target chip's information call and / or suspected call IP core by comparing the converted chip transistor-level netlist with the modified chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram based on the gate-level netlist of the chip and the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, modifying the names of one or part of or all of the modules and / or units, and then determining the target chip and / or the target chip's information call and / or suspected call IP core by comparing the failed LVS verification results and / or reports of the failed LVS verification using one or more LVS verification software and / or tools and / or environments; the thirty-third determination submodule includes but is not limited to one or more of the following: a seventeenth determination unit is used to determine the transistor-level netlist portion that failed the verification, and / or the gate-level netlist portion corresponding to the failed transistor-level netlist portion , and / or failed chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram area, and / or the module and / or unit and / or design information corresponding to the failed part and / or failed area are the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; an eighteenth determining unit, used to determine that the devices and / or connection relationships in the transistor-level netlist found in the verification, the differences between the devices and / or connection relationships in the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, and / or the transistor-level netlist part corresponding to the differences, and / or the gate-level netlist part corresponding to the corresponding transistor-level netlist part, and / or the corresponding chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram area, and / or the module, and / or the unit, and / or the design information are the target chip and / or the IP core called and / or suspected of being called by the information of the target chip;

[0108] The thirty-fourth determination submodule is used to determine the target chip and / or the information call and / or the suspected call IP core of the target chip based on the two gate-level netlists of the chip, the results and / or reports of the formal verification performed one or more times using one or more formal verification software and / or tools and / or environments; the thirty-fourth determination submodule includes but is not limited to one or more of the following: a nineteenth determination unit is used to determine that the gate-level netlist portion that failed the verification, and / or the module and / or unit and / or design information corresponding to the failed portion is the target chip and / or the information call and / or the suspected call IP core of the target chip; a twentieth determination unit is used to determine the gate-level netlist portion corresponding to the mismatch point found in the verification, and / or the portion and / or or the module and / or unit and / or design information corresponding to the mismatch point is the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; a twenty-first determining unit, for determining the inequivalent part found in the verification, and / or the gate-level netlist part corresponding to the inequivalent part, and / or the module and / or unit and / or design information corresponding to the inequivalent part is the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; a twenty-second determining unit, for determining the difference in logic and / or function between two gate-level netlists found in the verification, and / or the gate-level netlist part corresponding to the difference, and / or the module and / or unit and / or design information is the target chip and / or the IP core called and / or suspected of being called by the information of the target chip;

[0109] The thirty-fifth determination submodule is used to determine the target chip and / or the information call and / or suspected call IP core of the target chip based on the two gate-level netlists of the chip, after modifying the names of one or part of the modules and / or units or all of the modules and / or units, and using one or more formal verification software and / or tools and / or environments to perform one or more formal verifications and / or the results and / or reports of the formal verifications that failed; the thirty-fifth determination submodule includes but is not limited to one or more of the following: a twenty-third determination unit is used to determine that the gate-level netlist part that failed the verification, and / or the module and / or unit and / or design information corresponding to the failed part is the target chip and / or the information call and / or suspected call IP core of the target chip; a twenty-fourth determination unit is used to determine the mismatch found in the verification The gate-level netlist portion corresponding to the matching point, and / or the module and / or unit and / or design information corresponding to the portion and / or mismatching point is the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; a twenty-fifth determining unit, used to determine the inequivalent portion found in the verification, and / or the gate-level netlist portion, and / or the module and / or unit and / or design information corresponding to the inequivalent portion is the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; a twenty-sixth determining unit, used to determine the difference in logic and / or function between the two gate-level netlists found in the verification, and / or the gate-level netlist portion, and / or the module and / or unit and / or design information corresponding to the difference is the target chip and / or the IP core called and / or suspected of being called by the information of the target chip;

[0110] Among them, when carrying out formal verification, if there are differences in the functions and / or logic of auxiliary design and / or auxiliary testing between the two gate-level netlists, the functions and / or logic corresponding to the differences are not verified or verified; wherein, the functions and / or logic corresponding to the differences are not verified, including but not limited to: when setting constants, prohibiting the functions and / or logic and / or pins and / or pins of auxiliary design and / or auxiliary testing, and / or setting the functions and / or logic and / or pins and / or pins of auxiliary design and / or auxiliary testing to be invalid; the functions and / or logic and / or pins and / or pins of the auxiliary design and / or auxiliary testing include but are not limited to one or more of the following: scanning the SCAN chain and / or the enable pins and / or enable pins corresponding to the SCAN chain, the JTAG chain and / or the enable pins and / or enable pins corresponding to the JTAG chain, and the pins and / or pins corresponding to the chip testability design and / or the testability design.

[0111] Optionally, the second information includes chip RTL code, and / or a gate-level netlist of the chip; the gate-level netlist of the chip includes but is not limited to one or more of the following: a gate-level netlist for completing the final design, a gate-level netlist corresponding to the chip design layout and / or design layout and / or design layout and wiring and / or design layout and wiring diagram, a gate-level netlist formed by synthesizing the chip RTL code, a front-end gate-level netlist, a back-end gate-level netlist, and a gate-level netlist during the chip design process; the front-end gate-level netlist and / or back-end gate-level netlist and / or gate-level netlist during the chip design process include but are not limited to one or more gate-level netlists;

[0112] The IP core call determination module includes but is not limited to one or more of the following:

[0113] The thirty-sixth determination submodule is used to determine that the position of the nineteenth identifier in the chip RTL code and / or the part where the nineteenth identifier is located and / or the part between the nineteenth identifier and the nineteenth identifier has a code length less than or equal to the fortieth preset threshold and / or the part whose code length between the nineteenth identifier and the nineteenth identifier accounts for less than or equal to the fifth proportion threshold in the chip RTL code, and / or the module and / or unit and / or design information corresponding to the position and / or part and / or the nineteenth identifier is the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; the nineteenth identifier is an identifier of a company other than the design company of the target chip, and / or an identifier representing a company other than the design company of the target chip;

[0114] The thirty-seventh determination submodule is used to determine that the position of the twentieth identifier in the chip RTL code and / or the part where the twentieth identifier is located and / or the part with the code length between the twentieth identifier and the twentieth identifier is less than or equal to the forty-first preset threshold and / or the part with the code length between the twentieth identifier and the twentieth identifier accounts for less than or equal to the sixth proportion threshold in the chip RTL code, and / or the module and / or unit and / or design information corresponding to the position and / or part and / or the twentieth identifier is the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; the twentieth identifier is the identifier of the design company of the target chip, and / or the identifier representing the design company of the target chip;

[0115] The thirty-eighth determination submodule is used to determine the target chip and / or the information call and / or suspected call IP core of the target chip based on the part of the chip RTL code where the description of other levels except the register transfer level description is located; the description of other levels except the register transfer level description includes but is not limited to gate level description; wherein, the thirty-eighth determination submodule includes but is not limited to one or more of the following: a twenty-seventh determination unit is used to determine that one or more keywords existing in the chip RTL code, and / or the total number of one or more keywords existing in the chip RTL code is greater than or equal to the keyword corresponding to the forty-second preset threshold, and / or the proportion of the total number of one or more keywords in the chip RTL code in the entire chip RTL code is greater than or equal to the keyword corresponding to the forty-third preset threshold, and the position and / or part where the keyword is located and / or the code length between the keyword and the part where ... The part whose proportion is less than or equal to the seventh proportion threshold, and / or the module and / or unit and / or design information corresponding to the position and / or part and / or the keyword are determined as the target chip and / or the IP core called by information and / or suspected of being called by the target chip, wherein the keyword is a keyword representing descriptions at other levels except the register transfer level description, and the types of the keyword include but are not limited to one or more of the following: code at the representation description level, vocabulary and / or phrases at the representation description level, script at the representation description level, program at the representation description level, netlist at the representation description level, wherein the netlist includes but is not limited to a gate-level netlist; a twenty-eighth determining unit, used to determine the twenty-fourth part in the RTL code of the chip, which is identical and / or similar to the twenty-third part of the gate-level netlist of the chip and / or the module and / or unit and / or design information corresponding to the twenty-fourth part, which is identical and / or similar to the twenty-third part and / or has a similarity greater than or equal to the forty-fifth preset threshold, as the target chip and / or the IP core called by information and / or suspected of being called by the target chip;

[0116] a thirty-ninth determining submodule, configured to determine the twenty-sixth portion of the chip RTL code, and / or the module and / or unit and / or design information corresponding to the twenty-sixth portion, which is identical and / or similar and / or has a similarity greater than or equal to a forty-sixth preset threshold, as the target chip and / or an IP core called and / or suspected of being called by the information of the target chip; the twenty-third preset library does not contain the RTL code designed by the design company of the target chip;

[0117] The fortieth determination submodule is used to determine the twenty-eighth part of the chip RTL code, which is identical and / or similar and / or has a similarity greater than or equal to the forty-seventh preset threshold, and / or the module and / or unit and / or design information corresponding to the twenty-eighth part as the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; the RTL code designed by the design company of the target chip in the twenty-fourth preset library, and / or the RTL code IP core library of the design company of the target chip, and / or the IP core library of the design company of the target chip;

[0118] The forty-first determination submodule is used to determine the target chip and / or the information call and / or suspected call IP core of the target chip based on the chip RTL code and the chip's gate-level netlist, the results and / or reports of the formal verification performed one or more times using one or more formal verification software and / or tools and / or environments; the forty-first determination submodule includes but is not limited to one or more of the following: a twenty-ninth determination unit is used to determine that the RTL code portion that failed in the verification, and / or the gate-level netlist portion that failed, and / or the module and / or unit and / or design information corresponding to the failed portion is the target chip and / or the information call and / or suspected call IP core of the target chip; a thirtieth determination unit is used to determine the RTL code portion, and / or the gate-level netlist portion, and / or the portion corresponding to the mismatch point found in the verification the module and / or unit and / or design information corresponding to the points and / or mismatch points are the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; a thirty-first determining unit, used to determine the inequivalent parts found in the verification, and / or the RTL code parts, and / or gate-level netlist parts, and / or the modules and / or units and / or design information corresponding to the inequivalent parts are the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; a thirty-second determining unit, used to determine the differences between the logic and / or functions in the RTL code found in the verification and the logic and / or functions in the gate-level netlist, and / or the RTL code parts, and / or gate-level netlist parts, and / or the modules and / or units and / or design information corresponding to the differences are the target chip and / or the IP core called and / or suspected of being called by the information of the target chip;

[0119] The forty-second determination submodule is used to determine the target chip and / or the information call and / or suspected call IP core of the target chip based on the chip RTL code and the chip gate-level netlist, after modifying the names of one or part of the modules and / or units, and using one or more formal verification software and / or tools and / or environments to perform one or more formal verifications, and the results and / or reports of the formal verifications that failed; the forty-second determination submodule includes but is not limited to one or more of the following: a thirty-third determination unit, used to determine that the RTL code portion that failed the verification, and / or the gate-level netlist portion that failed, and / or the module and / or unit and / or design information corresponding to the failed portion is the target chip and / or the information call and / or suspected call IP core of the target chip; determine the RTL code portion, and / or gate-level netlist portion that failed the verification, and / or the module and / or unit and / or design information corresponding to the failed portion is the target chip and / or the information call and / or suspected call IP core of the target chip; determine the RTL code portion, and / or gate-level netlist portion that failed the verification, and / or the gate-level netlist portion that failed the verification The netlist part, and / or the module and / or unit and / or design information corresponding to the part and / or the mismatch point are the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; a thirty-fourth determining unit, used to determine the inequivalent part found in the verification, and / or the RTL code part, and / or the gate-level netlist part, and / or the module and / or unit and / or design information corresponding to the inequivalent part are the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; a thirty-fifth determining unit, used to determine the difference between the logic and / or function in the RTL code found in the verification and the logic and / or function in the gate-level netlist, and / or the RTL code part, and / or the gate-level netlist part, and / or the module and / or unit and / or design information corresponding to the difference are the target chip and / or the IP core called and / or suspected of being called by the information of the target chip;

[0120] Among them, when carrying out formal verification, if there are differences between the RTL code and the gate-level netlist in the functions and / or logic of auxiliary design and / or auxiliary testing, the functions and / or logic corresponding to the differences are not verified or verified; wherein, the functions and / or logic corresponding to the differences are not verified, including but not limited to: when setting constants, prohibiting the functions and / or logic and / or pins and / or pins of auxiliary design and / or auxiliary testing, and / or setting the functions and / or logic and / or pins and / or pins of auxiliary design and / or auxiliary testing to be invalid; the functions and / or logic and / or pins and / or pins of the auxiliary design and / or auxiliary testing include but are not limited to one or more of the following: scanning the SCAN chain and / or the enable pin and / or enable pin corresponding to the SCAN chain, the JTAG chain and / or the enable pin and / or enable pin corresponding to the JTAG chain, and the chip testability design and / or the pins and / or pins corresponding to the testability design.

[0121] Optionally, when determining, based on the first information, whether an IP core is called and / or whether an IP core is suspected to be called in a target chip and / or information of the target chip, a preset threshold and / or identifier and / or preset library and / or an area and / or part thereof, and when determining, based on the second information, the target chip and / or information of the target chip, an IP core to be called and / or suspected to be called, a preset threshold and / or identifier and / or preset library and / or an area and / or part thereof;

[0122] When determining, based on the first information, in the target chip and / or in the information of the target chip, whether the IP core is called and / or whether the IP core is suspected of being called, the preset thresholds and / or identifiers and / or preset libraries and / or the regions and / or parts thereof used, whether the preset thresholds and / or identifiers and / or preset libraries and / or the regions and / or parts thereof of the same type are the same or different;

[0123] According to the second information, determine the target chip and / or the information of the target chip, the IP core called and / or suspected of being called, the preset thresholds and / or identifiers and / or preset libraries used and / or the areas and / or parts therein, and whether the preset thresholds and / or identifiers and / or preset libraries and / or the areas and / or parts therein of the same type are the same or different.

[0124] Optionally, the IP core includes but is not limited to a non-self-developed IP core and / or a self-developed IP core;

[0125] Among them, the non-self-developed IP core includes but is not limited to one or more of the following: an IP core that is not designed by the design company of the target chip, an IP core purchased by the design company of the target chip from other companies, an IP core called by the design company of the target chip from a non-self-developed IP core library, and an IP core whose intellectual property rights do not belong to the design company of the target chip;

[0126] Among them, the self-developed IP core includes but is not limited to one or more of the following: the IP core designed by the design company of the target chip, the IP core independently developed by the design company of the target chip, the IP core owned by the design company of the target chip, the IP core accumulated by the design company of the target chip itself, and the IP core whose intellectual property rights belong to the design company of the target chip.

[0127] Optionally, the device further includes: an IP core classification module, configured to determine, based on the first information and / or the second information and / or the information of the target chip and / or the design file of the target chip and / or the authorization information of the target chip, whether the target chip and / or the information, the called and / or the suspected called IP core is a non-self-developed IP core and / or whether it is a self-developed IP core; and / or

[0128] The IP core classification module is configured to determine, based on the second information, the target chip and / or the information of the target chip, and determine whether the IP core is a non-self-developed IP core and / or whether it is a self-developed IP core while calling and / or suspected of calling the IP core;

[0129] The IP core classification module includes: a first classification submodule for determining whether the target chip and / or the target chip's information, the called and / or suspected called IP core is a non-self-developed IP core; the first classification submodule includes but is not limited to one or more of the following:

[0130] A first classification unit is used to determine that an IP core determined by a chip design layout and / or a design layout and / or a design layout and / or a blank area in a design layout and / or a content corresponding to the blank area is a non-self-developed IP core;

[0131] A second classification unit is used to determine that an IP core is a non-self-developed IP core determined by comparing the chip design layout and / or design layout and / or design layout and wiring and / or design layout and wiring diagram with the corresponding physical chip and / or physical layout and / or physical layout and / or physical layout and wiring and / or physical layout and wiring diagram, and / or the content corresponding to the inconsistency.

[0132] A third classification unit is configured to determine that the IP core identified by the twenty-first identifier in the third information of the target chip is a non-self-developed IP core; the twenty-first identifier is an identifier of a company other than the design company of the target chip, and / or an identifier representing a company other than the design company of the target chip;

[0133] a fourth classification unit, configured to determine that an IP core determined by the 26th region in the third information of the target chip, which is identical and / or similar to the 25th region of the information in the 25th preset library and / or whose similarity is greater than or equal to a 48th preset threshold, and / or the content corresponding to the 26th region, is a non-self-developed IP core; and the 25th preset library does not contain information designed by the design company of the target chip;

[0134] a fifth classification unit, configured to determine that an IP core determined by the thirtieth part of the third information of the target chip, which is identical and / or similar to the twenty-ninth part of the information in the twenty-sixth preset library and / or whose similarity is greater than or equal to a forty-ninth preset threshold, and / or the content corresponding to the thirtieth part, is a non-self-developed IP core; and the twenty-sixth preset library does not contain information about the design company of the target chip;

[0135] A sixth classification unit is used to determine that the IP core determined as a non-self-developed IP core is a non-self-developed IP core by determining the position and / or area of ​​the chip and / or physical layout and / or physical layout and / or physical layout wiring and / or physical layout wiring diagram, and / or the modules and / or units and / or design information corresponding to the position and / or area, and / or the position and / or area of ​​the corresponding chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, and / or the modules and / or units and / or design information corresponding to the position and / or area;

[0136] A seventh classification unit is used to determine that an IP core determined by one or more LVS verifications performed one or more times and the results and / or reports of failed LVS verifications are non-self-developed IP cores;

[0137] The eighth classification unit is used to determine that an IP core determined by the results and / or reports of one or more formal verifications performed one or more times and failing the formal verifications is a non-self-developed IP core;

[0138] The ninth classification unit is used to determine whether the IP core determined by the portion of the chip RTL code where the description of the level other than the register transfer level is located is a non-self-developed IP core;

[0139] a tenth classification unit, for determining, for the target chip and / or the IP core called and / or suspected of being called by the information of the target chip, that the IP core is not a self-developed IP core called and / or suspected of being called by the information of the target chip and / or the target chip, that the IP core is a non-self-developed IP core called and / or suspected of being called by the information of the target chip and / or the target chip;

[0140] The IP core classification module includes: a second classification submodule for determining whether the target chip and / or the target chip's information, the called and / or suspected called IP core is a self-developed IP core, and the second classification submodule includes but is not limited to one or more of the following:

[0141] an eleventh classification unit, configured to determine that the IP core identified by the twenty-second identifier in the third information of the target chip is a self-developed IP core; the twenty-second identifier is an identifier of a design company of the target chip and / or an identifier representing a design company of the target chip;

[0142] A twelfth classification unit is configured to determine that an IP core determined by the twenty-eighth region in the third information of the target chip, which is identical and / or similar to the twenty-seventh region of the information in the twenty-seventh preset library and / or has a similarity greater than or equal to a fiftieth preset threshold, and / or the content corresponding to the twenty-eighth region is a self-developed IP core; information designed by a design company of the target chip in the twenty-seventh preset library, and / or an IP core library of the design company of the target chip, and / or an IP core library of the design company of the target chip;

[0143] A thirteenth classification unit is configured to determine that an IP core determined by the thirty-second part of the third information of the target chip, which is identical and / or similar to the thirty-first part of the information in the twenty-eighth preset library and / or the content corresponding to the thirty-second part, is a self-developed IP core; information designed by a design company of the target chip in the twenty-eighth preset library, and / or an IP core library of the information of the design company of the target chip, and / or an IP core library of the design company of the target chip;

[0144] A fourteenth classification unit is used to determine that the IP core is a self-developed IP core by determining the position and / or area of ​​the physical chip and / or physical layout and / or physical layout and / or physical layout wiring and / or physical layout wiring diagram, and / or the modules and / or units and / or design information corresponding to the position and / or area of ​​the corresponding chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, and / or the modules and / or units and / or design information corresponding to the position and / or area;

[0145] A fifteenth classification unit is configured to, for the target chip and / or the IP core called and / or suspected of being called by the information of the target chip, if it is determined that the IP core is not a non-self-developed IP core called by the information, called and / or suspected of being called by the target chip and / or the target chip, determine that the IP core is a self-developed IP core called and / or suspected of being called by the information of the target chip and / or the target chip;

[0146] The third information of the target chip includes but is not limited to one or more of the following: chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, chip physical and / or physical layout and / or physical layout and / or physical layout wiring and / or physical layout wiring diagram, chip schematic, chip transistor-level netlist, chip gate-level netlist, chip RTL code, all or part of one or more of the first information, and all or part of one or more of the second information;

[0147] Among them, the types of information in the 25th preset library and / or the 26th preset library and / or the 27th preset library and / or the 28th preset library and / or the information designed by the design company of the target chip, and / or the information in the IP core library of the design company of the target chip, include but are not limited to one or more of the following: layout and / or layout and / or layout and wiring and / or layout and wiring diagram, schematic diagram, transistor-level netlist, gate-level netlist, RTL code.

[0148] Optionally, the apparatus further includes: a determination module, configured to determine the degree of autonomy and / or controllability of the chip; the determination module includes but is not limited to one or more of the following:

[0149] a first requirement determination unit, configured to determine one or more fourth information required to determine the autonomy and / or controllability of the chip, the fourth information including but not limited to one or more of the following: a chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, a physical chip and / or physical layout and / or physical layout and / or physical layout wiring and / or physical layout wiring diagram, a chip schematic, a chip transistor-level netlist, a chip gate-level netlist, a chip RTL code, all or part of one or more of the first information, all or part of one or more of the second information, and other information of the chip other than the first information and the second information;

[0150] a first score allocating unit, configured to allocate, for each type of the one or more required fourth information, a score corresponding to the fourth information; wherein the first score allocating unit includes but is not limited to: a first allocating sub-unit, configured to allocate a score based on the difficulty and / or criticality of implementation and / or design of each type of fourth information;

[0151] A first score determination unit is configured to, for each type of required fourth information, determine a score obtained for the chip as follows: the score corresponding to the fourth information minus the portion of the information of the chip to be determined that is missing in the fourth information and / or the missing functions and / or logic and / or modules and / or units of the chip to be determined, and / or if the fourth information obtained calls a non-self-developed IP core and / or is suspected of calling a non-self-developed IP core. or the score corresponding to the missing logic and / or the missing module and / or the missing unit, minus the score corresponding to the non-self-developed IP core called and / or suspected to be called in the obtained fourth information, the remaining score; and / or, determining the score obtained by the chip is: the score corresponding to the fourth information, minus the first proportion of the score corresponding to the missing information part of the chip to be determined and / or the missing function and / or the missing logic and / or the missing module and / or the missing unit, minus the score corresponding to the called and / or suspected called in the fourth information. / or suspected of calling the non-self-developed IP core, the remaining score after the second proportion of the score corresponding to the non-self-developed IP core; wherein, if the information part of the chip to be determined and / or the missing function and / or the missing logic and / or the missing module and / or the missing unit that are missing in the fourth information obtained are repeated and / or overlapped with the non-self-developed IP core called and / or suspected of being called in the fourth information obtained, then for the repeated and / or overlapping content, only one point is deducted, and / or no repeated points are deducted; wherein, the first score determination unit includes: a first proportion determination sub Unit, the first ratio determination subunit is used to determine the first ratio and / or the second ratio. The conditions that the first ratio and / or the second ratio must meet include but are not limited to one or more of the following: the ratio is less than or equal to 1, the ratio is greater than or equal to 0, the ratio of the missing information part of the chip to be determined and / or the missing function and / or the missing logic and / or the missing module and / or the missing unit when they are domestically produced is less than or equal to the ratio when they are non-domestic produced, and the ratio of the non-self-developed IP core called and / or suspected of being called when they are domestically produced is less than or equal to the ratio when the non-self-developed IP core is non-domestic produced;

[0152] a second score determining unit, configured to, for each type of required fourth information, determine a score obtained for the chip as: a score corresponding to the fourth information if the fourth information obtained includes all such information of the chip to be determined and / or includes all functions and / or all logic and / or all modules and / or all units of the chip to be determined, and the fourth information obtained does not call a non-self-developed IP core and does not suspect calling a non-self-developed IP core;

[0153] a third score determining unit, configured to, for each type of required fourth information, determine that the chip does not receive a score for the fourth information if the fourth information is not obtained and / or it cannot be confirmed that the obtained fourth information is the fourth information of the chip;

[0154] a first determination unit, configured to sum actual scores obtained by the chip for each of the one or more required fourth information as a total score of the chip, and determine the degree of autonomy and / or controllability of the chip based on the total score;

[0155] Among them, one situation in which the fourth information obtained does not include all such information of the chip to be determined and / or does not include all functions and / or all logics and / or all modules and / or all units of the chip to be determined is that a non-self-developed IP core is called in other information after the design of the fourth information is completed, and the functions and / or logics and / or modules and / or units corresponding to the IP core have not yet been designed in the fourth information;

[0156] In assigning scores corresponding to the required one or more types of fourth information, it is necessary to ensure that the scores corresponding to the same degree of autonomy and / or controllability for a chip with a given function are the same under different solutions. The premise for ensuring the same scores corresponding to the same degree of autonomy and / or controllability includes but is not limited to: the sum of the scores corresponding to the required types of fourth information for a chip with a given function is the same under different solutions.

[0157] A second requirement determination unit, configured to determine various functions and / or logics and / or modules and / or units required to determine the degree of autonomy and / or controllability of the chip;

[0158] a second score allocation unit, configured to allocate, for each of the various required functions and / or logics and / or modules and / or units, a score corresponding to the function and / or logic and / or module and / or unit; wherein the second score allocation unit includes but is not limited to: a second allocation sub-unit, configured to allocate a score based on the difficulty and / or criticality of implementation and / or design of each function and / or logic and / or module and / or unit;

[0159] a fourth score determination unit, configured to, for each of the required functions and / or logics and / or modules and / or units, determine a score corresponding to the chip obtaining the function and / or logic and / or module and / or unit if no non-self-developed IP core is called and no non-self-developed IP core is suspected of being called in the function and / or logic and / or module and / or unit of the chip to be determined;

[0160] A fifth score determination unit is configured to determine, for each of the required functions and / or logics and / or modules and / or units, if a non-self-developed IP core is called and / or a non-self-developed IP core is suspected to be called in the function and / or logic and / or module and / or unit of the chip to be determined, determine that the chip does not obtain the score corresponding to the function and / or logic and / or module and / or unit, and / or determine the score of a third ratio of the scores corresponding to the function and / or logic and / or module and / or unit obtained by the chip; wherein the conditions that the third ratio needs to meet include but are not limited to one or more of the following: the ratio is less than or equal to 1, the ratio is greater than or equal to 0, and the ratio of the non-self-developed IP core called and / or suspected of being called is greater than or equal to the ratio of the non-self-developed IP core when it is non-domestic;

[0161] a sixth score determination unit, configured to, for each of the required functions and / or logics and / or modules and / or units, determine that the chip does not obtain a score for the required functions and / or logics and / or modules and / or units if the chip to be determined lacks the required functions and / or logics and / or modules and / or units;

[0162] a second determination unit, configured to sum the actual scores obtained by the chip for each of the required functions and / or logics and / or modules and / or units to obtain a total score for the chip, and determine the degree of autonomy and / or controllability of the chip based on the total score;

[0163] Among them, when allocating scores corresponding to the various functions and / or logics and / or modules and / or units required, it is necessary to ensure that the scores corresponding to the same degree of autonomy and / or controllability of a chip with a given function are the same under different schemes; the premise of ensuring that the scores corresponding to the same degree of autonomy and / or controllability are the same includes but is not limited to: the sum of the scores corresponding to the various functions and / or logics and / or modules and / or units required under different schemes of a chip with a given function is the same.

[0164] Optionally, the first score determination unit is further used to calculate the score corresponding to the information portion of the chip to be determined that is missing in the obtained fourth information and / or the missing function and / or the missing logic and / or the missing module and / or the missing unit, and / or the score corresponding to the non-self-developed IP core called and / or suspected of being called in the obtained fourth information. The first score determination unit also includes but is not limited to one or more of the following:

[0165] a first score allocation subunit, configured to allocate scores corresponding to various functions and / or logics and / or modules and / or units in the required fourth information, with the sum of the scores corresponding to the various functions and / or logics and / or modules and / or units being the score corresponding to the fourth information; wherein the first score allocation subunit is configured to, but is not limited to, allocate scores based on the difficulty and / or criticality of implementation and / or design of each function and / or logic and / or module and / or unit;

[0166] a first score determination subunit, configured to locate, among various functions and / or logics and / or modules and / or units in the required fourth information, information portions and / or functions and / or logics and / or modules and / or units of the chip to be determined that are missing from the acquired fourth information, and determine the scores assigned to these portions of functions and / or logics and / or modules and / or units, or the sum of the scores, as the scores corresponding to the information portions of the chip to be determined that are missing from the acquired fourth information, and / or the missing functions and / or logics and / or modules and / or units;

[0167] The second score determination sub-unit is used to find the functions and / or logic and / or modules and / or units corresponding to the non-self-developed IP core called and / or suspected to be called in the obtained fourth information among the various functions and / or logic and / or modules and / or units in the required fourth information, and determine that the score or the sum of the scores assigned to this part of the functions and / or logic and / or modules and / or units is the score corresponding to the non-self-developed IP core called and / or suspected to be called in the obtained fourth information.

[0168] Optionally, the device further includes a confirmation module for confirming that the acquired information is information of the target chip; the information includes but is not limited to one or more of the following: chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, physical chip and / or physical layout and / or physical layout and / or physical layout wiring and / or physical layout wiring diagram, chip schematic, chip transistor-level netlist, chip gate-level netlist, chip RTL code, all or part of one or more of the first information, all or part of one or more of the second information; other information of the chip other than the first information and the second information; the confirmation module includes but is not limited to one or more of the following:

[0169] A first confirmation submodule is used to confirm whether the acquired information has been declared or identified as information of the target chip;

[0170] A second confirmation submodule is configured to determine the acquired physical chip and / or physical layout and / or physical layout and / or physical layout and wiring and / or physical layout and wiring diagram as information of the target chip;

[0171] a third confirmation submodule, configured to compare and / or verify the acquired information to confirm whether it is the information of the target chip, the third confirmation submodule including but not limited to one or more of the following: a first confirmation unit, configured to compare and / or verify the acquired information with information that has been declared or identified as the target chip one or more times, and if the comparison and / or verification passes, confirm that the acquired information is the information of the target chip; a second confirmation unit, configured to compare and / or verify the acquired information with a physical chip and / or a physical layout and / or a physical layout and / or a physical layout wiring and / or a physical layout wiring diagram one or more times, and if the comparison and / or verification passes, confirm that the acquired information is the information of the target chip;

[0172] The fourth confirmation submodule is used to compare and / or verify the acquired information with the information of the target chip confirmed through comparison and / or verification once or more. If the comparison and / or verification passes, the acquired information is the information of the target chip.

[0173] Optionally, the first confirmation unit and / or the second confirmation unit and / or the fourth confirmation submodule include but are not limited to one or more of the following:

[0174] A first comparison subunit is configured to compare the chip design layout and / or design layout and / or design layout and wiring and / or design layout and wiring diagram with the physical chip and / or physical layout and / or physical layout and / or physical layout and wiring and / or physical layout and wiring diagram;

[0175] a second comparison subunit, configured to compare the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram with the physical chip and / or physical layout and / or physical layout and / or physical layout wiring and / or physical layout wiring diagram, excluding portions and / or regions and / or modules and / or units of non-self-developed IP cores that have been confirmed to be called or suspected of being called by the target chip, and then compare the remaining chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram with the remaining physical chip and / or physical layout and / or physical layout and / or physical layout wiring and / or physical layout wiring diagram;

[0176] A first verification subunit is configured to perform LVS verification on the chip schematic, the chip design layout, and / or the design layout and / or the design layout and wiring, and / or the design layout and wiring diagram;

[0177] a second verification subunit, configured to perform LVS verification on the chip schematic, the chip design layout, and / or the design layout and / or the design layout and / or the design layout and / or the design layout and wiring diagram, after removing the portion and / or the region and / or the module and / or the unit and / or the design information of the non-self-developed IP core that has been confirmed to be called or suspected to be called by the target chip;

[0178] A third verification subunit is configured to perform LVS verification on the chip transistor-level netlist and the chip design layout and / or the design layout and / or the design layout and wiring and / or the design layout and wiring diagram;

[0179] a fourth verification subunit, configured to perform LVS verification on the chip transistor-level netlist, the chip design layout and / or design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, after removing the portion and / or region and / or module and / or unit and / or design information of the non-self-developed IP core that has been confirmed to be called or suspected of being called by the target chip;

[0180] a fifth verification subunit, configured to perform LVS verification on the gate-level netlist of the chip, the chip design layout and / or the design layout and / or the design layout and wiring and / or the design layout and wiring diagram;

[0181] a sixth verification subunit, configured to perform LVS verification on the gate-level netlist of the chip, and the chip design layout and / or design layout and / or design layout and / or design layout and wiring and / or design layout and wiring diagram, after removing the portion and / or region and / or module and / or unit and / or design information of the non-self-developed IP core that has been confirmed to be called or suspected of being called by the target chip;

[0182] a seventh verification subunit, configured to convert the gate-level netlist of the chip into a chip transistor-level netlist, and then perform LVS verification on the converted chip transistor-level netlist and the chip design layout and / or design layout and / or design layout and wiring and / or design layout and wiring diagram;

[0183] an eighth verification subunit, configured to convert the gate-level netlist of the chip into a chip transistor-level netlist, and then compare the converted chip transistor-level netlist with the chip design layout and / or design layout and / or design layout and wiring and / or design layout wiring diagram, removing the portion and / or region and / or module and / or unit and / or design information of the non-self-developed IP core that has been confirmed to be called or suspected of being called by the target chip, and then perform LVS verification on the remaining chip transistor-level netlist and the remaining chip design layout and / or design layout and / or design layout and wiring and / or design layout wiring diagram;

[0184] a ninth verification subunit, configured to convert the gate-level netlist of the chip, and the chip design layout and / or design layout and / or design layout and wiring and / or design layout wiring diagram, into a transistor-level netlist after removing portions and / or regions and / or modules and / or units and / or design information of non-self-developed IP cores that have been confirmed to be called or suspected of being called by the target chip, and perform LVS verification on the converted transistor-level netlist and the remaining chip design layout and / or design layout and / or design layout and wiring and / or design layout wiring diagram;

[0185] a tenth verification subunit, configured to perform formal verification on a gate-level netlist of the chip and another gate-level netlist of the chip;

[0186] an eleventh verification sub-unit, configured to perform formal verification on a gate-level netlist of a chip and another gate-level netlist of a chip, after removing portions and / or regions and / or modules and / or units and / or design information of non-self-developed IP cores that have been confirmed to be called or suspected of being called by the target chip;

[0187] a twelfth verification subunit, for performing formal verification on the chip RTL code and the chip's gate-level netlist;

[0188] A thirteenth verification subunit is configured to perform formal verification on the chip RTL code and the gate-level netlist of the chip after removing the portion and / or region and / or module and / or unit and / or design information of the non-self-developed IP core that has been confirmed to be called or suspected to be called by the target chip;

[0189] Among them, when carrying out formal verification, if there are differences in the functions and / or logic of auxiliary design and / or auxiliary test between the two gate-level netlists being verified, and / or between the verified RTL code and the gate-level netlist, the functions and / or logic corresponding to the differences are not verified or verified; wherein, the functions and / or logic corresponding to the differences are not verified and include but are not limited to: when setting constants, prohibiting the functions and / or logic and / or pins and / or pins of auxiliary design and / or auxiliary test, and / or setting the functions and / or logic and / or pins and / or pins of auxiliary design and / or auxiliary test to be invalid; the functions and / or logic and / or pins and / or pins of the auxiliary design and / or auxiliary test include but are not limited to one or more of the following: scanning the SCAN chain and / or the enable pin and / or enable pin corresponding to the SCAN chain, the JTAG chain and / or the enable pin and / or enable pin corresponding to the JTAG chain, and the chip testability design and / or the pins and / or pins corresponding to the testability design.

[0190] Optionally, the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, and / or the area in the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, includes but is not limited to the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram of all layers and / or partial layers and / or one layer, and for one layer, the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram includes but is not limited to the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram of the entire area and / or multiple local areas and / or one local area; wherein the positions and / or ranges of the entire area and / or multiple local areas and / or one local area of ​​different layers are the same or different; and / or,

[0191] The physical chip and / or physical layout and / or physical layout and / or physical layout wiring and / or physical layout wiring diagram, and / or the physical chip and / or physical layout and / or physical layout and / or physical layout wiring and / or the area in the physical layout wiring diagram, include but are not limited to the physical chip and / or physical layout and / or physical layout and / or physical layout wiring and / or physical layout wiring diagram of all layers and / or partial layers and / or one layer. For one layer, the physical chip and / or physical layout and / or physical layout and / or physical layout wiring and / or physical layout wiring diagram include but are not limited to the physical chip and / or physical layout and / or physical layout and / or physical layout wiring and / or physical layout wiring diagram of the entire area and / or multiple local areas and / or one local area; wherein the positions and / or ranges of the entire area and / or multiple local areas and / or one local area of ​​different layers are the same or different; and / or,

[0192] The layout and / or layout and / or layout wiring and / or layout wiring diagram, and / or the areas in the layout and / or layout and / or layout and / or layout wiring and / or layout wiring diagram in the preset library include but are not limited to the layout and / or layout and / or layout wiring and / or layout wiring and / or layout wiring diagram of all layers and / or partial layers and / or one layer, and for one layer, the layout and / or layout and / or layout and / or layout wiring and / or layout wiring diagram include but are not limited to the layout and / or layout and / or layout wiring and / or layout wiring diagram of the entire area and / or multiple local areas and / or one local area; wherein the positions and / or ranges of the entire area and / or multiple local areas and / or one local area of ​​different layers are the same or different; and / or,

[0193] The schematic diagram of the chip, and / or a region in the schematic diagram of the chip, including but not limited to a schematic diagram of the chip for the entire region and / or multiple local regions and / or a local region; and / or,

[0194] The schematic diagrams in the preset library, and / or the regions in the schematic diagrams, include but are not limited to the schematic diagrams of the entire region and / or multiple local regions and / or one local region; and / or,

[0195] The chip transistor-level netlist, and / or part of the transistor-level netlist, including but not limited to: the entire transistor-level netlist, a partial transistor-level netlist; and / or,

[0196] The transistor-level netlist in the preset library, and / or part of the transistor-level netlist, including but not limited to: the entire transistor-level netlist, a part of the transistor-level netlist; and / or,

[0197] The gate-level netlist of the chip, and / or part of the gate-level netlist, including but not limited to: the entire gate-level netlist, a part of the gate-level netlist; and / or,

[0198] The gate-level netlist in the preset library, and / or part of the gate-level netlist, including but not limited to: the entire gate-level netlist, part of the gate-level netlist; and / or,

[0199] The chip RTL code, and / or part of the RTL code, includes but is not limited to one or more of the following: the entire RTL code, part of the RTL code, the RTL code claimed by the design company of the target chip, and the code designed by the design company of the target chip during the RTL design stage; and / or,

[0200] The RTL code in the preset library, and / or part of the RTL code, including but not limited to: the entire RTL code, part of the RTL code; and / or,

[0201] The chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram includes but is not limited to one or more of the following: chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, notes and / or descriptions in the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram; and / or,

[0202] The physical chip and / or physical layout and / or physical layout and / or physical layout wiring and / or physical layout wiring diagram includes but is not limited to one or more of the following: physical chip and / or physical layout and / or physical layout and / or physical layout wiring and / or physical layout wiring diagram, notes and / or descriptions in the physical chip and / or physical layout and / or physical layout and / or physical layout wiring and / or physical layout wiring diagram; and / or,

[0203] The schematic diagram of the chip includes, but is not limited to, one or more of the following: a schematic diagram of the chip, annotations and / or descriptions in the schematic diagram of the chip; and / or,

[0204] The chip transistor level netlist includes but is not limited to one or more of the following: a chip transistor level netlist, comments and / or descriptions in the chip transistor level netlist; and / or,

[0205] The gate-level netlist of the chip includes but is not limited to one or more of the following: the gate-level netlist of the chip, the annotations and / or descriptions in the gate-level netlist of the chip; and / or,

[0206] The chip RTL code includes but is not limited to one or more of the following: chip RTL code, comments and / or instructions in the chip RTL code; and / or,

[0207] The identification includes one or more of the following: text, graphics, trademarks, names, logos, marks, and watermarks.

[0208] In a third aspect, the present invention also provides an electronic device comprising a memory, a processor, and a program stored in the memory and executable on the processor; when the processor executes the program, the steps in the detection method for any of the above-mentioned IP core calls are implemented.

[0209] In a fourth aspect, the present invention further provides a readable storage medium having a program stored thereon, which, when executed by a processor, implements the steps in any of the above-mentioned IP core call detection methods.

[0210] The beneficial effects of the above technical solution of the present invention are as follows:

[0211] The embodiments of the present invention improve the accuracy and reliability of IP core call situation detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0212] Figure 1 This is a flow chart of a method for detecting an IP core call in the first embodiment of the present invention;

[0213] Figure 2 This is a schematic diagram of the structure of a detection device for IP core call in the second embodiment of the present invention;

[0214] Figure 3 This is a schematic structural diagram of an electronic device in Embodiment 3 of the present invention. DETAILED DESCRIPTION

[0215] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the described embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present invention.

[0216] See also Figure 1 , Figure 1 A flowchart of a method for detecting an IP core call provided in the first embodiment of the present invention includes the following steps:

[0217] Step 11: Determine, based on the first information, whether an IP core is called (also referred to as used, borrowed, embedded, nested, etc., the same below) in the target chip and / or in the information of the target chip and / or whether an IP core is suspected of being called;

[0218] Step 12: Determine the target chip and / or information of the target chip based on the second information, and call and / or suspect the IP core to be called;

[0219] The information of the target chip is one type of information or multiple types of information.

[0220] It should be noted that the first information and the second information may be physical information and / or design information of the target chip, and the first information and the second information may be the same or different. The information of the target chip may be physical information and / or design information of the target chip. For details, please refer to the following.

[0221] The embodiments of the present invention can improve the accuracy and credibility of IP core call situation detection.

[0222] In other optional specific implementations, only step 11 may be performed, that is, based only on the first information, determining whether an IP core is called and / or suspected to be called in the target chip and / or the information of the target chip, without performing step 12. Alternatively, only step 12 may be performed, that is, based only on the second information, determining whether the target chip and / or the information of the target chip is called and / or suspected to be called, without performing step 11.

[0223] Optionally, the target chip is a whole or partial chip, and the types of chips include but are not limited to one or more of the following: packaged chips, unpackaged bare chips (bare chips are also called bare crystals or grains), modules in bare chips (including functional modules in bare chips), and units in bare chips (including functional units in bare chips).

[0224] It should be noted that from the perspective of classification, the chip here is a general term, including but not limited to integrated circuits IC, microsystems MEMS, microelectromechanical systems, semiconductor devices, discrete devices, sensors, actuators and other categories.

[0225] Optionally, the first information is the same as or different from the second information.

[0226] Optionally, determining whether an IP core is called and / or suspected to be called in the target chip and / or the information of the target chip and determining whether an IP core is called and / or suspected to be called by the target chip and / or the information of the target chip are performed in two steps or combined into one step;

[0227] Optionally, determining the IP core called and / or suspected of being called by the target chip and / or the information of the target chip is also a method for determining whether an IP core is called and / or suspected of being called in the target chip and / or the information of the target chip.

[0228] Optionally, the first information includes a chip design layout and / or a design layout and / or a design layout and wiring and / or a design layout and wiring diagram, and / or a physical chip and / or a physical layout and / or a physical layout and / or a physical layout and wiring and / or a physical layout and wiring diagram;

[0229] Optionally, determining, based on the first information, whether an IP core is called in the target chip and / or in the information of the target chip and / or whether an IP core is suspected of being called includes, but is not limited to, one or more of the following 5.1-5.8:

[0230] 5.1. If, in the chip design layout and / or design layout and / or design layout and wiring and / or design layout and wiring diagram, there is a blank area and / or the area of ​​the blank area is greater than or equal to a first preset threshold and / or the proportion of the blank area is greater than or equal to a second preset threshold and / or the blank area is a regular geometric shape, it is determined that the IP core has been invoked and / or is suspected of being invoked in the target chip and / or in the target chip information;

[0231] Optionally, the blank area occupancy ratio refers to the ratio of the blank area to the design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram;

[0232] Optionally, the regular geometric shapes include, but are not limited to, one or more of the following: square, rectangle, rhombus, trapezoid, parallelogram, circle, ellipse, triangle, polygon, arc, and arc;

[0233] 5.2. Compare the chip design layout and / or design layout and / or design layout and wiring and / or design layout and wiring diagram with the corresponding physical chip and / or physical layout and / or physical layout and wiring and / or physical layout and wiring diagram. If the comparison is inconsistent, it is determined that the IP core is called and / or is suspected of being called in the target chip and / or in the target chip information;

[0234] Optionally, the situations of the inconsistency in the comparison include but are not limited to one or more of the following: inconsistency in the comparison of all layers and / or part of the layers and / or one layer; inconsistency in the comparison of the entire region and / or multiple local regions and / or one local region in all layers and / or part of the layers and / or one layer;

[0235] 5.3. If a first identifier is present in the chip design layout and / or design layout and / or design layout and / or design layout and / or design layout diagram, and / or in the physical chip and / or physical layout and / or physical layout and / or physical layout and / or physical layout and / or physical layout diagram, it is determined that an IP core has been invoked and / or is suspected of being invoked in the target chip and / or in the target chip information; the first identifier is an identifier of a company other than the design company of the target chip, and / or an identifier representing a company other than the design company of the target chip;

[0236] 5.4. If a second identifier is present in the chip design layout and / or design layout and / or design layout and / or design layout and / or design layout diagram, and / or in the physical chip and / or physical layout and / or physical layout and / or physical layout and / or physical layout and / or physical layout diagram, it is determined that an IP core has been invoked and / or is suspected of being invoked in the target chip and / or in the target chip information; the second identifier is an identifier of the design company of the target chip and / or an identifier representing the design company of the target chip;

[0237] 5.5. Comparing the chip design layout and / or design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram with the layout and / or layout and / or layout and / or layout wiring and / or layout wiring diagram in a first preset library; if a first region in the chip design layout and / or design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram is identical and / or similar to a second region in the layout and / or layout and / or layout and / or layout wiring and / or layout wiring diagram in the first preset library, and / or the degree of similarity is greater than or equal to a third preset threshold, then determining that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core; the first preset library does not contain the layout and / or layout and / or layout and / or layout wiring and / or layout wiring diagram designed by the design company of the target chip;

[0238] 5.6. Compare the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram with the layout and / or layout and / or layout wiring and / or layout wiring diagram in the second preset library. If the third area of ​​the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram is identical and / or similar to the fourth area of ​​the layout and / or layout and / or layout wiring and / or layout wiring diagram in the second preset library, and / or the similarity is greater than or equal to a fourth preset threshold, then it is determined that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core; the layout and / or layout and / or layout wiring and / or layout wiring diagram designed by the design company of the target chip in the second preset library, and / or the layout and / or layout and / or layout wiring and / or layout wiring diagram IP core library of the design company of the target chip, and / or the IP core library of the design company of the target chip.

[0239] 5.7. Comparing the physical chip and / or the physical layout and / or the physical layout and / or the physical layout and / or the physical layout and / or the physical layout and / or the physical layout and / or the layout diagram with the layout and / or the layout and / or the layout and / or the layout diagram in the third preset library; if the fifth region of the physical chip and / or the physical layout and / or the physical layout and / or the physical layout and / or the physical layout and / or the physical layout and / or the physical layout and / or the layout diagram is identical and / or similar to the sixth region of the layout and / or the layout and / or the layout and / or the layout diagram in the third preset library, and / or the degree of similarity is greater than or equal to a fifth preset threshold, then determining that the target chip and / or the information of the target chip has invoked an IP core and / or is suspected of invoking an IP core; and the third preset library does not contain the layout and / or the layout and / or the layout and / or the layout diagram designed by the design company of the target chip;

[0240] 5.8. Compare the physical chip and / or the physical layout and / or the physical layout and / or the physical layout and / or the physical layout and / or the physical layout and / or the physical layout and / or the physical layout and / or the physical layout and / or the layout diagram with the layout and / or the layout and / or the layout and / or the layout diagram in the fourth preset library. If the seventh region of the physical chip and / or the physical layout and / or the physical layout and / or the physical layout and / or the physical layout and / or the layout diagram is the same as the eighth region of the layout and / or the layout and / or the layout and / or the layout diagram in the fourth preset library, Or similarity and / or similarity is greater than or equal to a sixth preset threshold, it is determined that the target chip and / or the information of the target chip has called the IP core and / or is suspected of calling the IP core; the fourth preset library is the layout and / or layout and / or layout wiring and / or layout wiring diagram designed by the design company of the target chip, and / or the layout and / or layout and / or layout wiring and / or layout wiring diagram IP core library of the design company of the target chip, and / or the IP core library of the design company of the target chip.

[0241] Optionally, the first information includes a schematic diagram of the chip, and / or a chip design layout and / or a design layout and / or a design layout and wiring and / or a design layout and wiring diagram;

[0242] Optionally, determining, based on the first information, whether an IP core is called in the target chip and / or in the information of the target chip and / or whether an IP core is suspected of being called includes, but is not limited to, one or more of the following 6.1-6.6:

[0243] 6.1. If a third identifier is present in the schematic diagram of the chip, it is determined that an IP core is invoked and / or is suspected of being invoked in the target chip and / or in the target chip information; the third identifier is an identifier of a company other than the design company of the target chip and / or an identifier representing a company other than the design company of the target chip;

[0244] 6.2. If a fourth identifier is present in the schematic diagram of the chip, it is determined that an IP core is invoked and / or is suspected of being invoked in the target chip and / or in the information of the target chip; the fourth identifier is an identifier of the design company of the target chip and / or an identifier representing the design company of the target chip;

[0245] 6.3. Comparing the schematic diagram of the chip with schematic diagrams in a fifth preset library; if the ninth region of the chip schematic diagram is identical and / or similar to the tenth region of the schematic diagram in the fifth preset library, and / or the degree of similarity is greater than or equal to a seventh preset threshold, determining that the target chip and / or the information of the target chip invokes an IP core and / or is suspected of invoking an IP core; and the fifth preset library does not contain a schematic diagram designed by the design company of the target chip;

[0246] 6.4. Comparing the schematic diagram of the chip with the schematic diagrams in a sixth preset library; if an eleventh region in the chip schematic diagram is identical and / or similar to a twelfth region in the schematic diagram in the sixth preset library, and / or the degree of similarity is greater than or equal to an eighth preset threshold, then determining that the target chip and / or the information of the target chip has invoked an IP core and / or is suspected of invoking an IP core; the schematic diagrams designed by the design company of the target chip in the sixth preset library, and / or the schematic IP core library of the design company of the target chip, and / or the IP core library of the design company of the target chip;

[0247] 6.5. Perform one or more LVS verifications on the chip's schematics and the chip's design layout and / or design layout and / or design layout and / or design layout and wiring diagram using one or more LVS verification software and / or tools and / or environments. If one or more LVS verifications fail, it is determined that the target chip and / or the target chip's information invokes an IP core and / or is suspected of invoking an IP core.

[0248] It should be noted that the LVS verification environment can be an electronic design automation (EDA) environment that includes LVS verification, such as an EDA software environment that can perform design, simulation, and verification. LVS verification can be performed directly in this complete environment. For example, if the verification object passes verification in one LVS verification environment but fails in another LVS verification environment, it is determined that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core.

[0249] 6.6. With respect to the chip schematic and the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, modify the names of one, part, or all of the modules (which may be the module itself, or an instantiated module, etc.) and / or units, and after the modification, perform one or more LVS verifications using one or more LVS verification software and / or tools and / or environments. If one or more of the LVS verifications fails, it is determined that the target chip and / or the target chip information has called an IP core and / or is suspected of calling an IP core.

[0250] It should be noted that the LVS verification environment can be an EDA environment that includes LVS verification, such as an EDA software environment capable of design, simulation, and verification. LVS verification can be performed directly within this complete environment. For example, if the verification target passes verification in one LVS verification environment but fails in another LVS verification environment, it is determined that the target chip and / or its information has invoked an IP core and / or is suspected of invoking an IP core.

[0251] Optionally, the first information includes a chip transistor-level netlist, and / or a chip design layout and / or a design layout and / or a design layout and wiring and / or a design layout and wiring diagram;

[0252] Optionally, the transistor-level netlist includes but is not limited to one or more of the following: a netlist described as transistor-level, a transistor-level netlist corresponding to a chip schematic, a transistor-level netlist corresponding to a gate-level netlist of a chip that completes a final design, a transistor-level netlist corresponding to a chip design layout and / or design layout and / or design layout wiring and / or a transistor-level netlist corresponding to a design layout wiring diagram, a transistor-level netlist composed of a transistor-level netlist corresponding to a transistor-level netlist corresponding to an analog module schematic and / or a transistor-level netlist corresponding to a gate-level netlist of a digital module that completes a final design in an analog-to-digital hybrid chip; it should be noted that the transistor-level netlist refers to a description of the transistor level (including transistors, capacitors, resistors and other devices), and comes in various forms, such as a CDL netlist, an SCS netlist, a SPICE netlist, etc.

[0253] Optionally, determining, based on the first information, whether an IP core is called and / or whether an IP core is suspected of being called in the target chip and / or the information of the target chip includes, but is not limited to, one or more of the following 7.1-7.6:

[0254] 7.1. If a fifth identifier is present in the transistor-level netlist of the chip, it is determined that the target chip and / or the information of the target chip has invoked an IP core and / or is suspected of invoking an IP core; the fifth identifier is an identifier of a company other than the design company of the target chip, and / or an identifier representing a company other than the design company of the target chip;

[0255] 7.2. If a sixth identifier is present in the transistor-level netlist of the chip, it is determined that the target chip and / or the information of the target chip has invoked an IP core and / or is suspected of invoking an IP core; the sixth identifier is an identifier of the design company of the target chip and / or an identifier representing the design company of the target chip;

[0256] 7.3. Comparing the transistor-level netlist of the chip with a transistor-level netlist in a seventh preset library; if a first portion of the transistor-level netlist of the chip is identical and / or similar to a second portion of the transistor-level netlist in the seventh preset library, and / or the degree of similarity is greater than or equal to a ninth preset threshold, determining that the target chip and / or the information of the target chip invokes an IP core and / or is suspected of invoking an IP core; and the seventh preset library does not contain a transistor-level netlist designed by the design company of the target chip.

[0257] 7.4. Comparing the transistor-level netlist of the chip with the transistor-level netlist in an eighth preset library; if the third portion of the transistor-level netlist of the chip is identical and / or similar to the fourth portion of the transistor-level netlist in the eighth preset library, and / or the degree of similarity is greater than or equal to a tenth preset threshold, determining that the target chip and / or the information of the target chip has invoked an IP core and / or is suspected of invoking an IP core; the transistor-level netlist designed by the design company of the target chip in the eighth preset library, and / or the transistor-level netlist IP core library of the design company of the target chip, and / or the IP core library of the design company of the target chip;

[0258] 7.5. Perform one or more LVS verifications on the chip's transistor-level netlist and the chip's design layout and / or design layout and / or design layout and / or design layout and / or design layout and wiring diagram using one or more LVS verification software and / or tools and / or environments. If one or more LVS verifications fail, it is determined that the target chip and / or the target chip's information has invoked an IP core and / or is suspected of invoking an IP core.

[0259] It should be noted that the LVS verification environment can be an EDA environment that includes LVS verification, such as an EDA software environment capable of design, simulation, and verification. LVS verification can be performed directly within this complete environment. For example, if the verification target passes verification in one LVS verification environment but fails in another LVS verification environment, it is determined that the target chip and / or its information has invoked an IP core and / or is suspected of invoking an IP core.

[0260] 7.6. With respect to the chip transistor-level netlist and the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, modify the names of one, part, or all of the modules and / or units, and perform one or more LVS verifications using one or more LVS verification software and / or tools and / or environments after the modification. If one or more of the LVS verifications fails, it is determined that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core.

[0261] It should be noted that the LVS verification environment can be an EDA environment that includes LVS verification, such as an EDA software environment capable of design, simulation, and verification. LVS verification can be performed directly within this complete environment. For example, if the verification target passes verification in one LVS verification environment but fails in another LVS verification environment, it is determined that the target chip and / or its information has invoked an IP core and / or is suspected of invoking an IP core.

[0262] Optionally, the first information includes a gate-level netlist of the chip, and / or a chip design layout and / or a design layout and / or a design layout and wiring and / or a design layout and wiring diagram;

[0263] Optionally, the gate-level netlist of the chip includes but is not limited to one or more of the following: a gate-level netlist for completing the final design, a gate-level netlist corresponding to the chip design layout and / or design layout and / or design layout and wiring and / or design layout and wiring diagram, a gate-level netlist synthesized from the chip register transfer level RTL code, a front-end gate-level netlist, a back-end gate-level netlist, and a gate-level netlist during the chip design process; the front-end gate-level netlist and / or back-end gate-level netlist and / or gate-level netlist during the chip design process include but are not limited to one or more gate-level netlists;

[0264] Optionally, determining, based on the first information, whether an IP core is called and / or whether an IP core is suspected of being called in the target chip and / or the information of the target chip includes, but is not limited to, one or more of the following 8.1-8.11:

[0265] 8.1. If a seventh identifier is present in the gate-level netlist of the chip, it is determined that the target chip and / or the information of the target chip has invoked an IP core and / or is suspected of invoking an IP core; the seventh identifier is an identifier of a company other than the design company of the target chip, and / or an identifier representing a company other than the design company of the target chip;

[0266] 8.2. If an eighth identifier is present in the gate-level netlist of the chip, it is determined that the target chip and / or the information of the target chip has invoked an IP core and / or is suspected of invoking an IP core; the eighth identifier is an identifier of the design company of the target chip and / or an identifier representing the design company of the target chip;

[0267] 8.3. Comparing the gate-level netlist of the chip with the gate-level netlist in a ninth preset library; if the fifth portion of the gate-level netlist of the chip is identical and / or similar to the sixth portion of the gate-level netlist in the ninth preset library, and / or the degree of similarity is greater than or equal to an eleventh preset threshold, then determining that the target chip and / or the information of the target chip invokes an IP core and / or is suspected of invoking an IP core; and the ninth preset library does not contain a gate-level netlist designed by the design company of the target chip;

[0268] 8.4. Comparing the gate-level netlist of the chip with the gate-level netlist in the tenth preset library. If the seventh portion of the gate-level netlist of the chip is identical and / or similar to the eighth portion of the gate-level netlist in the tenth preset library, and / or the degree of similarity is greater than or equal to a twelfth preset threshold, then determining that the target chip and / or the information of the target chip has invoked an IP core and / or is suspected of invoking an IP core; the gate-level netlist designed by the design company of the target chip in the tenth preset library, and / or the gate-level netlist IP core library of the design company of the target chip, and / or the IP core library of the design company of the target chip;

[0269] 8.5. Perform one or more LVS verifications on the gate-level netlist of the chip and the chip design layout and / or design layout and / or design layout and / or design layout and / or design layout and wiring diagram using one or more LVS verification software and / or tools and / or environments. If one or more LVS verifications fail, it is determined that the target chip and / or the target chip information has invoked an IP core and / or is suspected of invoking an IP core.

[0270] It should be noted that the LVS verification environment can be an EDA environment that includes LVS verification, such as an EDA software environment capable of design, simulation, and verification. LVS verification can be performed directly within this complete environment. For example, if the verification target passes verification in one LVS verification environment but fails in another LVS verification environment, it is determined that the target chip and / or its information has invoked an IP core and / or is suspected of invoking an IP core.

[0271] 8.6. Modify the names of one, some, or all of the modules and / or units in the gate-level netlist and the chip design layout and / or design layout and / or design layout and / or design layout and wiring diagram of the chip, and perform one or more LVS verifications after the modifications using one or more LVS verification software and / or tools and / or environments. If one or more LVS verifications fail, it is determined that the target chip and / or the target chip information has invoked an IP core and / or is suspected of invoking an IP core.

[0272] It should be noted that the LVS verification environment can be an EDA environment that includes LVS verification, such as an EDA software environment capable of design, simulation, and verification. LVS verification can be performed directly within this complete environment. For example, if the verification target passes verification in one LVS verification environment but fails in another LVS verification environment, it is determined that the target chip and / or its information has invoked an IP core and / or is suspected of invoking an IP core.

[0273] 8.7. After converting the chip's gate-level netlist to a chip transistor-level netlist, perform one or more LVS verifications on the converted chip transistor-level netlist and the chip design layout and / or design layout and / or design layout and / or design layout and wiring diagram using one or more LVS verification software and / or tools and / or environments. If one or more LVS verifications fail, it is determined that the target chip and / or the target chip information has invoked an IP core and / or is suspected of invoking an IP core.

[0274] It should be noted that the LVS verification environment can be an EDA environment that includes LVS verification, such as an EDA software environment capable of design, simulation, and verification. LVS verification can be performed directly within this complete environment. For example, if the verification target passes verification in one LVS verification environment but fails in another LVS verification environment, it is determined that the target chip and / or its information has invoked an IP core and / or is suspected of invoking an IP core.

[0275] 8.8. After converting the chip's gate-level netlist to a chip-transistor-level netlist, modify the names of one, some, or all of the modules and / or units in the converted chip-transistor-level netlist and the chip design layout and / or design layout and / or design layout and / or design layout and wiring diagram, and perform one or more LVS verifications after the modifications using one or more LVS verification software and / or tools and / or environments. If one or more LVS verifications fail, it is determined that the target chip and / or the target chip's information has invoked an IP core and / or is suspected of invoking an IP core.

[0276] It should be noted that the LVS verification environment can be an EDA environment that includes LVS verification, such as an EDA software environment capable of design, simulation, and verification. LVS verification can be performed directly within this complete environment. For example, if the verification target passes verification in one LVS verification environment but fails in another LVS verification environment, it is determined that the target chip and / or its information has invoked an IP core and / or is suspected of invoking an IP core.

[0277] 8.9. Modify the names of one, some, or all of the modules and / or units in the chip's gate-level netlist and the chip's design layout and / or design layout and / or design layout and wiring and / or design layout wiring diagram, then convert the modified gate-level netlist into a chip transistor-level netlist. Perform one or more LVS verifications on the converted chip transistor-level netlist and the modified chip design layout and / or design layout and wiring and / or design layout and wiring diagram using one or more LVS verification software and / or tools and / or environments. If one or more LVS verifications fail, it is determined that the target chip and / or the target chip's information invokes an IP core and / or is suspected of invoking an IP core.

[0278] It should be noted that the LVS verification environment can be an EDA environment that includes LVS verification, such as an EDA software environment capable of design, simulation, and verification. LVS verification can be performed directly within this complete environment. For example, if the verification target passes verification in one LVS verification environment but fails in another LVS verification environment, it is determined that the target chip and / or its information has invoked an IP core and / or is suspected of invoking an IP core.

[0279] 8.10. Perform one or more formal verifications on the two gate-level netlists of the chip using one or more formal verification (FV) software and / or tools and / or environments. If one or more of the formal verifications fail, it is determined that the target chip and / or the information of the target chip has invoked an IP core and / or is suspected of invoking an IP core.

[0280] It should be noted that the two gate-level netlists may be any two of one or more of the following, and / or two of one: a gate-level netlist to complete the final design, a gate-level netlist corresponding to the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, a gate-level netlist formed by synthesizing the chip register transfer level RTL code, a front-end gate-level netlist, a back-end gate-level netlist, and a gate-level netlist in the chip design process. The front-end gate-level netlist and / or back-end gate-level netlist and / or gate-level netlist in the chip design process include but are not limited to one or more gate-level netlists.

[0281] It should also be noted that the formal verification environment can be an EDA environment that includes formal verification, such as an EDA software environment that can perform design, simulation, and verification. Formal verification can be performed directly within this complete environment. For example, if the verification target passes verification in one formal verification environment but fails in another formal verification environment, it is determined that the target chip and / or its information has invoked an IP core and / or is suspected of invoking an IP core.

[0282] 8.11. For two gate-level netlists of a chip, modify the names of one, some, or all modules and / or units, and perform one or more formal verifications using one or more formal verification software and / or tools and / or environments after the modifications. If one or more formal verifications fail, it is determined that the target chip and / or the target chip information invokes an IP core and / or is suspected of invoking an IP core.

[0283] It should be noted that the two gate-level netlists may be any two of one or more of the following, and / or two of one: a gate-level netlist to complete the final design, a gate-level netlist corresponding to the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, a gate-level netlist formed by synthesizing the chip register transfer level RTL code, a front-end gate-level netlist, a back-end gate-level netlist, and a gate-level netlist in the chip design process. The front-end gate-level netlist and / or back-end gate-level netlist and / or gate-level netlist in the chip design process include but are not limited to one or more gate-level netlists. It should be noted that the two gate-level netlists may include but are not limited to any two of one or more of the following, and / or two of one: a gate-level netlist for the final design, a gate-level netlist corresponding to the chip design layout and / or design layout and / or design layout and wiring and / or design layout and wiring diagram, a gate-level netlist formed by synthesizing the chip register transfer level RTL code, a front-end gate-level netlist, a back-end gate-level netlist, a gate-level netlist during the chip design process, and the front-end gate-level netlist and / or back-end gate-level netlist and / or gate-level netlist during the chip design process include but are not limited to one or more gate-level netlists. It should be noted that the formal verification environment may be: a set of EDA environments that include formal verification, such as an EDA software environment that can perform design, simulation, and verification, and formal verification is performed directly in this complete environment. For example, if the verification object passes verification in one formal verification environment but fails in another formal verification environment, it is determined that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core.

[0284] Optionally, when performing formal verification, if there are differences in the auxiliary design and / or auxiliary test functions and / or logic between the two gate-level netlists, the functions and / or logic corresponding to the differences are not verified or verified;

[0285] For example, a gate-level netlist is the front-end, a gate-level netlist is the back-end, and the back-end netlist adds a scan chain for testability design. If it is considered that this is a function that facilitates subsequent chip testing and is not a focus of IP core testing, it can be not verified; on the contrary, if it is considered that IP core testing is also necessary, then verification is performed; similarly, for other functions and / or logic, whether to verify can also be determined based on whether they are the focus of IP core testing.

[0286] Optionally, the method of not verifying the function and / or logic corresponding to the difference includes but is not limited to: when setting constants, prohibiting the auxiliary design and / or auxiliary test function and / or logic and / or pin and / or pin, and / or setting the auxiliary design and / or auxiliary test function and / or logic and / or pin and / or pin to be invalid;

[0287] Optionally, the functions and / or logic and / or pins and / or pins of the auxiliary design and / or auxiliary test include but are not limited to one or more of the following: scanning the SCAN chain and / or scanning the enable pin and / or enable pin corresponding to the SCAN chain, the JTAG chain and / or the enable pin and / or enable pin corresponding to the JTAG chain, the chip testability design and / or the pins and / or pins corresponding to the testability design.

[0288] Optionally, the first information includes chip RTL code and / or a gate-level netlist of the chip;

[0289] Optionally, the gate-level netlist of the chip includes but is not limited to one or more of the following: a gate-level netlist for completing the final design, a gate-level netlist corresponding to the chip design layout and / or design layout and / or design layout and wiring and / or design layout and wiring diagram, a gate-level netlist synthesized from the chip RTL code, a front-end gate-level netlist, a back-end gate-level netlist, and a gate-level netlist during the chip design process; the front-end gate-level netlist and / or back-end gate-level netlist and / or gate-level netlist during the chip design process include but are not limited to one or more gate-level netlists;

[0290] Optionally, determining, based on the first information, whether an IP core is called and / or whether an IP core is suspected of being called in the target chip and / or the information of the target chip includes, but is not limited to, one or more of the following 9.1-9.7:

[0291] 9.1. If a ninth identifier is present in the chip RTL code, it is determined that the target chip and / or the target chip information invokes an IP core and / or is suspected of invoking an IP core; the ninth identifier is an identifier of a company other than the design company of the target chip, and / or an identifier representing a company other than the design company of the target chip;

[0292] 9.2. If a tenth identifier is present in the chip RTL code, it is determined that the target chip and / or the information of the target chip has invoked an IP core and / or is suspected of invoking an IP core; the tenth identifier is an identifier of the design company of the target chip and / or an identifier representing the design company of the target chip;

[0293] 9.3. If the chip RTL code contains descriptions at levels other than register transfer level descriptions, it is determined that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core;

[0294] Optionally, the other level descriptions except the register transfer level description include but are not limited to gate level description;

[0295] Optionally, the method for checking whether there is any level description other than register transfer level description in the chip RTL code includes, but is not limited to, one or more of the following:

[0296] Optionally, perform keyword search on the chip RTL code;

[0297] Optionally, the chip RTL code is compared with the gate-level netlist of the chip. If a ninth portion of the chip RTL code is identical to and / or similar to a tenth portion of the gate-level netlist of the chip and / or the degree of similarity is greater than or equal to a thirteenth preset threshold, it is determined that descriptions at levels other than the register transfer level description exist in the chip RTL code.

[0298] Optionally, the method for keyword searching the chip RTL code includes but is not limited to one or more of the following: using one or more keywords representing descriptions at levels other than register transfer level descriptions to search the RTL code, and if it is found that one or more of the keywords exist in the RTL code and / or the total number of the one or more keywords in the RTL code is greater than or equal to a fourteenth preset threshold and / or the proportion of the total number of the one or more keywords in the RTL code to the total number of RTL code words is greater than or equal to a fifteenth preset threshold, then it is determined that descriptions at levels other than register transfer level descriptions exist in the chip RTL code; using one or more keywords representing register transfer level descriptions to search the RTL code, and if it is found that various keywords do not exist in the RTL code and / or one or more keywords do not exist in the RTL code, then it is determined that descriptions at levels other than register transfer level descriptions exist in the chip RTL code; the types of keywords include but are not limited to one or more of the following: code representing a description level, vocabulary and / or phrases representing a description level, script representing a description level, program representing a description level, RTL code representing a description level, netlist representing a description level, and netlist representing a description level, wherein the netlist includes but is not limited to a gate-level netlist;

[0299] 9.4. Comparing the chip RTL code with the RTL code in an eleventh preset library; if an eleventh portion of the chip RTL code is identical and / or similar to a twelfth portion of the RTL code in the eleventh preset library, and / or the degree of similarity is greater than or equal to a sixteenth preset threshold, then determining that the target chip and / or the target chip information invokes an IP core and / or is suspected of invoking an IP core; and the eleventh preset library does not contain the RTL code designed by the design company of the target chip;

[0300] 9.5. Compare the chip RTL code with the RTL code in a twelfth preset library. If the thirteenth portion of the chip RTL code is identical and / or similar to the fourteenth portion of the RTL code in the twelfth preset library and / or the similarity is greater than or equal to a seventeenth preset threshold, then determine that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core; the RTL code designed by the design company of the target chip in the twelfth preset library, and / or the RTL code IP core library of the design company of the target chip, and / or the IP core library of the design company of the target chip;

[0301] 9.6. Perform one or more formal verifications on the chip RTL code and the chip's gate-level netlist using one or more formal verification software and / or tools and / or environments. If one or more of the formal verifications fail, it is determined that the target chip and / or the target chip's information invokes an IP core and / or is suspected of invoking an IP core.

[0302] It should be noted that the formal verification environment can be an EDA environment that includes formal verification, such as an EDA software environment that can perform design, simulation, and verification. Formal verification can be performed directly within this complete environment. For example, if the verification target passes verification in one formal verification environment but fails in another, it is determined that the target chip and / or its information invokes an IP core and / or is suspected of invoking an IP core.

[0303] 9.7. Modify the names of one, some, or all modules and / or units in the chip RTL code and gate-level netlist, and perform one or more formal verifications using one or more formal verification software and / or tools and / or environments after the modifications. If any one or more formal verifications fail, it is determined that the target chip and / or its information has invoked an IP core and / or is suspected of invoking an IP core.

[0304] It should be noted that the formal verification environment can be an EDA environment that includes formal verification, such as an EDA software environment that can perform design, simulation, and verification. Formal verification can be performed directly within this complete environment. For example, if the verification target passes verification in one formal verification environment but fails in another, it is determined that the target chip and / or its information invokes an IP core and / or is suspected of invoking an IP core.

[0305] Optionally, when performing formal verification, if there are differences between the RTL code and the gate-level netlist in the functions and / or logics of the auxiliary design and / or auxiliary test, the functions and / or logic corresponding to the differences are not verified or verified;

[0306] For example, the gate-level netlist is the back-end, and compared to the RTL code, it adds a scan chain for testability design. If it is considered that this is a function that facilitates subsequent chip testing and is not a focus of IP core testing, it can be not verified; on the contrary, if it is considered that IP core testing is also necessary, then it is verified; similarly, for other functions and / or logic, whether to verify can also be determined based on whether they are the focus of IP core testing.

[0307] Optionally, the method of not verifying the function and / or logic corresponding to the difference includes but is not limited to: when setting constants, prohibiting the auxiliary design and / or auxiliary test function and / or logic and / or pin and / or pin, and / or setting the auxiliary design and / or auxiliary test function and / or logic and / or pin and / or pin to be invalid;

[0308] Optionally, the functions and / or logic and / or pins and / or pins of the auxiliary design and / or auxiliary test include but are not limited to one or more of the following: scanning the SCAN chain and / or scanning the enable pin and / or enable pin corresponding to the SCAN chain, the JTAG chain and / or the enable pin and / or enable pin corresponding to the JTAG chain, the chip testability design and / or the pins and / or pins corresponding to the testability design.

[0309] Optionally, the second information includes a chip design layout and / or a design layout and / or a design layout and wiring and / or a design layout and wiring diagram, and / or a physical chip and / or a physical layout and / or a physical layout and / or a physical layout and wiring and / or a physical layout and wiring diagram;

[0310] Optionally, determining the target chip and / or information of the target chip based on the second information, and calling and / or suspected calling of an IP core, includes but is not limited to one or more of the following 10.1-10.11:

[0311] 10.1. Determine the blank areas in the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, and / or the blank areas with an area greater than or equal to the eighteenth preset threshold, and / or the blank areas with an occupation ratio greater than or equal to the nineteenth preset threshold, and / or the blank areas of regular geometric figures, and convert the blank areas and / or the blank areas (referring to the above: the blank areas in the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, and / or the blank areas with an area greater than or equal to the eighteenth preset threshold, and / or the blank areas with an occupation ratio greater than or equal to the nineteenth preset threshold, and / or the blank areas of regular geometric figures) corresponding to the design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, and / or the blank areas The module (which may be the layout itself, or a series of information such as the layout / schematic diagram / gate-level netlist / RTL code corresponding to the module, and the same applies to the unit; the "corresponding module" in many places in the text has this meaning, which may be the information itself, or a series of information such as the layout / schematic diagram / gate-level netlist / RTL code corresponding to the module) and / or the unit and / or the design information corresponding to the white area (referring to the blank area in the preceding: the chip design layout and / or the design layout and / or the blank area with an area greater than or equal to the eighteenth preset threshold, and / or the blank area with an occupation ratio greater than or equal to the nineteenth preset threshold, and / or the blank area of ​​the regular geometric figure) is determined to be the target chip and / or the IP core called and / or suspected of being called by the information of the target chip;

[0312] Optionally, the occupation ratio refers to the ratio of the blank area to the design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram;

[0313] Optionally, the regular geometric shapes include but are not limited to one or more of the following: square, rectangle, rhombus, trapezoid, parallelogram, circle, ellipse, triangle, polygon, arc, and arc; the blank area includes but is not limited to one or more areas;

[0314] 10.2. Determine inconsistencies when comparing the chip design layout and / or design layout and / or design layout and wiring and / or design layout and wiring diagram with the corresponding physical chip and / or physical layout and / or physical layout and / or physical layout and wiring and / or physical layout and wiring diagram, and determine the inconsistencies, and / or the design layout and / or design layout and wiring and / or design layout and wiring diagram corresponding to the inconsistencies, and / or the physical chip and / or physical layout and / or physical layout and wiring and / or physical layout and wiring diagram corresponding to the inconsistencies, and / or the modules and / or units and / or design information corresponding to the inconsistencies as the target chip and / or the IP core invoked and / or suspected of being invoked by the information of the target chip;

[0315] Optionally, the inconsistencies include but are not limited to one or more of the following: inconsistencies in comparison of all layers and / or part of layers and / or one layer; inconsistencies in comparison of the entire region and / or multiple local regions and / or one local region in all layers and / or part of layers and / or one layer; the inconsistencies include but are not limited to one or more layouts and / or layout patterns and / or layout wiring and / or layout wiring diagrams;

[0316] 10.3. Determine that the location of the eleventh identifier in the chip design layout and / or design layout and / or design layout and wiring and / or design layout and wiring diagram, and / or the physical chip and / or physical layout and / or physical layout and wiring and / or physical layout and wiring diagram, and / or the location of the eleventh identifier and / or the area where the eleventh identifier is located, and / or the area whose distance from the eleventh identifier is less than or equal to the twentieth preset threshold, and / or the location and / or area (referring to the location of the eleventh identifier in the chip design layout and / or design layout and / or design layout and wiring and / or the design layout and wiring diagram, and / or the physical chip and / or physical layout and / or physical layout and wiring and / or physical layout and wiring diagram, and / or the physical layout and / or physical layout and wiring diagram, and / or the module and / or unit and / or design information corresponding to the eleventh identifier is the target chip and / or the IP core called and / or suspected of being called by the information of the target chip;

[0317] 10.4. Determine the position of the eleventh marker in the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, and / or the physical chip and / or physical layout and / or physical layout wiring and / or physical layout wiring and / or physical layout wiring diagram, and / or the area where the eleventh marker is located and / or the area whose distance from the eleventh marker is less than or equal to the twenty-first preset threshold, and / or the position and / or area (referring to the previous chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, and / or the physical chip and / or physical layout and / or physical layout and / or physical layout wiring and / or physical layout wiring diagram) After determining the position of the eleventh identifier in the physical layout and wiring diagram and / or the area where the eleventh identifier is located and / or the area whose distance from the eleventh identifier is less than or equal to a twenty-first preset threshold) and / or the module and / or unit and / or design information corresponding to the eleventh identifier, determine the position and / or area of ​​one or more layers, and / or the modules and / or units and / or design information corresponding to the position and / or area of ​​the one or more layers as the target chip and / or the information call and / or suspected call of the IP core of the target chip; wherein the twenty-first preset threshold is the same as or different from the twenty-first preset threshold;

[0318] Optionally, the eleventh identifier is an identifier of a company other than the design company of the target chip, and / or an identifier representing a company other than the design company of the target chip;

[0319] 10.5. Determine that the location of the twelfth identifier in the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, and / or the physical chip and / or physical layout and / or physical layout and / or physical layout wiring and / or physical layout wiring diagram, and / or the location of the twelfth identifier and / or the area where the twelfth identifier is located, and / or the area whose distance from the twelfth identifier is less than or equal to the 22nd preset threshold, and / or the location and / or area (referring to the aforementioned: the location of the twelfth identifier in the chip design layout and / or design layout and / or design layout wiring and / or the area where the twelfth identifier is located, and / or the area whose distance from the twelfth identifier is less than or equal to the 22nd preset threshold, and / or the module and / or unit and / or design information corresponding to the twelfth identifier is the target chip and / or the IP core called and / or suspected of being called by the information of the target chip;

[0320] 10.6. Determine the position of the twelfth marker in the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, and / or the physical chip and / or physical layout and / or physical layout and / or physical layout wiring and / or physical layout wiring diagram, and / or the location of the twelfth marker and / or the area where the twelfth marker is located and / or the area whose distance from the twelfth marker is less than or equal to the twenty-third preset threshold, and / or the position and / or area (referring to the preceding: chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, and / or the physical chip and / or physical layout and / or physical layout and / or physical layout wiring and / or physical layout wiring diagram) After determining the position of the twelfth identifier and / or the area where the twelfth identifier is located in the physical layout and / or physical layout and / or the area whose distance from the twelfth identifier is less than or equal to a twenty-third preset threshold) and / or the module and / or unit and / or design information corresponding to the twelfth identifier, the position and / or area of ​​one or more layers, and / or the modules and / or units and / or design information corresponding to the position and / or area of ​​the one or more layers are determined as the target chip and / or the information call and / or suspected call of the IP core of the target chip; wherein the twenty-third preset threshold is the same as or different from the twenty-second preset threshold;

[0321] Optionally, the twelfth identifier is an identifier of a design company of the target chip, and / or an identifier representing a design company of the target chip;

[0322] 10.7. Determine a fourteenth region in the chip design layout and / or design layout and / or design layout and / or design layout and / or design layout diagram, and / or the module and / or unit and / or design information corresponding to the fourteenth region, which is identical and / or similar and / or has a similarity greater than or equal to a twenty-fourth preset threshold to the thirteenth region of the layout and / or layout and / or layout and wiring diagram in the thirteenth preset library, as the target chip and / or the IP core invoked and / or suspected of being invoked by the target chip's information; the thirteenth preset library does not contain the layout and / or layout and / or layout and wiring diagram designed by the design company of the target chip;

[0323] 10.8. Determine the sixteenth region in the chip design layout and / or design layout and / or design layout and / or design layout and / or design layout diagram, and / or the module and / or unit and / or design information corresponding to the sixteenth region, which is identical and / or similar and / or has a similarity greater than or equal to the twenty-fifth preset threshold to the fifteenth region in the layout and / or layout and / or layout and wiring and / or layout diagram in the fourteenth preset library, as the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; the layout and / or layout and / or layout and wiring and / or layout diagram designed by the design company of the target chip in the fourteenth preset library, and / or the IP core library of the layout and / or layout and / or layout and wiring and / or layout diagram of the design company of the target chip, and / or the IP core library of the design company of the target chip;

[0324] 10.9. Determine the target chip and / or the IP core invoked and / or suspected of being invoked by the target chip's information as the eighteenth region of the physical chip and / or physical layout and / or physical layout and / or physical layout and / or physical layout and / or layout diagram, and / or the module and / or unit and / or design information corresponding to the eighteenth region, which is identical and / or similar and / or has a similarity greater than or equal to the twenty-sixth preset threshold to the seventeenth region of the layout and / or layout and / or layout and / or layout diagram in the fifteenth preset library; the fifteenth preset library does not contain the layout and / or layout and / or layout and / or layout diagram designed by the design company of the target chip;

[0325] 10.10. Determine the twentieth region of the physical chip and / or the physical layout and / or the physical layout and / or the physical layout and / or the physical layout and / or the physical layout and / or the design information corresponding to the twentieth region, which is identical and / or similar and / or has a similarity greater than or equal to the twenty-seventh preset threshold to the nineteenth region of the layout and / or the layout and / or the layout and / or the layout and / or the layout diagram in the sixteenth preset library, as the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; the layout and / or the layout and / or the layout and / or the layout and / or the layout diagram designed by the design company of the target chip in the sixteenth preset library, and / or the IP core library of the layout and / or the layout and / or the layout and / or the layout and / or the layout diagram of the design company of the target chip, and / or the IP core library of the design company of the target chip;

[0326] 10.11. The physical chip and / or physical layout and / or physical layout and / or physical layout and / or physical layout wiring and / or physical layout wiring diagram position and / or area of ​​the target chip and / or the IP core called by information and / or suspected of being called by the target chip, and / or the module and / or unit and / or design information corresponding to the position and / or area, the corresponding chip design layout and / or design layout and / or design layout wiring and / or the position and / or area of ​​the design layout wiring diagram, and / or the module and / or unit and / or design information corresponding to the position and / or area are determined as the target chip and / or the IP core called by information and / or suspected of being called by the target chip.

[0327] Optionally, the second information includes a schematic diagram of the chip, and / or a chip design layout and / or a design layout and / or a design layout and wiring and / or a design layout and wiring diagram;

[0328] Optionally, determining the target chip and / or information of the target chip based on the second information, and calling and / or suspected calling of an IP core, includes but is not limited to one or more of the following 11.1-11.6:

[0329] 11.1. Determine whether the location of the thirteenth identifier in the chip schematic diagram and / or the area where the thirteenth identifier is located and / or the area whose distance from the thirteenth identifier is less than or equal to the twenty-eighth preset threshold, and / or the module and / or unit and / or design information corresponding to the location and / or area (referring to the aforementioned: the location of the thirteenth identifier in the chip schematic diagram and / or the area where the thirteenth identifier is located and / or the area whose distance from the thirteenth identifier is less than or equal to the twenty-eighth preset threshold) and / or the thirteenth identifier is the target chip and / or an IP core invoked and / or suspected of being invoked by the target chip information; the thirteenth identifier is the identifier of a company other than the design company of the target chip and / or an identifier representing a company other than the design company of the target chip;

[0330] 11.2. Determine whether the location of the fourteenth marker in the chip schematic diagram and / or the area where the fourteenth marker is located and / or the area whose distance from the fourteenth marker is less than or equal to the twenty-ninth preset threshold, and / or the module and / or unit and / or design information corresponding to the location and / or area (referring to the aforementioned: the location of the fourteenth marker in the chip schematic diagram and / or the area where the fourteenth marker is located and / or the area whose distance from the fourteenth marker is less than or equal to the twenty-ninth preset threshold) and / or the fourteenth marker is the target chip and / or the IP core invoked and / or suspected of being invoked by the target chip information; the fourteenth marker is the identifier of the design company of the target chip and / or an identifier representing the design company of the target chip;

[0331] 11.3. Determine the 22nd region in the schematic diagram of the chip, and / or the module and / or unit and / or design information corresponding to the 22nd region, which is identical and / or similar to the 21st region in the schematic diagram in the 17th preset library and / or has a similarity greater than or equal to a 30th preset threshold, as the target chip and / or an IP core invoked and / or suspected of being invoked by the information of the target chip; the 17th preset library does not contain schematics designed by the design company of the target chip;

[0332] 11.4. Determine the 24th region in the schematic diagram of the chip, and / or the module and / or unit and / or design information corresponding to the 24th region, which is identical and / or similar and / or has a similarity greater than or equal to a 31st preset threshold, as the target chip and / or an IP core invoked and / or suspected of being invoked by the target chip's information; the schematics designed by the design company of the target chip in the 18th preset library, and / or the schematic IP core library of the design company of the target chip, and / or the IP core library of the design company of the target chip;

[0333] 11.5. Determine the target chip and / or the IP core invoked and / or suspected of being invoked by the target chip based on the chip schematic and chip design layout and / or design layout and / or design layout and wiring and / or design layout and wiring diagram, and the results and / or reports of failed LVS verifications conducted one or more times using one or more LVS verification software and / or tools and / or environments;

[0334] It should be noted that the LVS verification environment can be an EDA environment that includes LVS verification, such as an EDA software environment that can perform design, simulation, and verification. LVS verification can be performed directly within this complete environment. For example, if the verification object passes verification in one LVS verification environment but fails in another, the IP core can be determined based on the latter.

[0335] Optionally, the determination method includes but is not limited to one or more of the following: determining that the module and / or unit and / or design information corresponding to the schematic area that failed the verification, and / or the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram area that failed, and / or the failed area (referring to the previous: failed schematic area, and / or failed chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram area) is the target chip and / or the information call and / or the target chip or an IP core suspected of being called; determining that the devices and / or connection relationships in the schematic diagram discovered during verification, the differences between the devices and / or connection relationships in the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, and / or the schematic diagram area, and / or chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram area, and / or module, and / or unit, and / or design information corresponding to the differences are the target chip and / or the IP core called and / or suspected of being called by the information of the target chip;

[0336] 11.6. Based on the chip schematic and chip design layout and / or design layout and / or design layout and / or design layout and wiring and / or design layout and wiring diagram, after modifying the names of one, some, or all modules and / or units, and using one or more LVS verification software and / or tools and / or environments to perform one or more LVS verifications, and the results and / or reports of failed LVS verifications, determine the target chip and / or the IP core that the target chip calls and / or is suspected of calling;

[0337] It should be noted that the LVS verification environment can be: a set of EDA environments that include LVS verification, such as an EDA software environment that can perform design, simulation, and verification, and LVS verification can be performed directly in this complete environment. For example, for the verification object, if verification passes in one LVS verification environment but fails in another LVS verification environment, the IP core can be determined based on the latter. (It should be noted that if the determined IP core happens to be a module and / or unit whose name is modified during verification, the module and / or unit will remain IP both before and after the name modification.

[0338] Optionally, the determination method includes but is not limited to one or more of the following: determining that the module and / or unit and / or design information corresponding to the schematic area that failed the verification, and / or the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram area that failed, and / or the failed area (referring to the previous: failed schematic area, and / or failed chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram area) is the target chip and / or the information call and / or the target chip or suspected IP core called; determine the devices and / or connection relationships in the schematic diagram discovered during verification, the differences between the devices and / or connection relationships in the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, and / or the schematic diagram area, and / or chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram area, and / or module, and / or unit, and / or design information corresponding to the differences, as the target chip and / or the information call of the target chip and / or the IP core suspected to be called.

[0339] Optionally, the second information includes a chip transistor-level netlist, and / or a chip design layout and / or a design layout and / or a design layout and wiring and / or a design layout and wiring diagram;

[0340] Optionally, the transistor-level netlist includes but is not limited to one or more of the following: a netlist described as transistor-level, a transistor-level netlist corresponding to a chip schematic, a transistor-level netlist corresponding to a gate-level netlist of a chip that has completed a final design, a transistor-level netlist corresponding to a chip design layout and / or a design layout and / or a design layout and wiring and / or a design layout and wiring diagram, a transistor-level netlist in an analog-digital hybrid chip composed of a transistor-level netlist corresponding to a transistor-level netlist corresponding to an analog module schematic and / or a transistor-level netlist corresponding to a gate-level netlist of a digital module that has completed a final design;

[0341] It should be noted that the transistor-level netlist refers to the description of the transistor level (including transistors, capacitors, resistors and other devices), and there are various forms, such as CDL netlist, SCS netlist, SPICE netlist, etc.

[0342] Optionally, determining the target chip and / or information of the target chip based on the second information, and calling and / or suspected calling of an IP core, includes but is not limited to one or more of the following 12.1-12.6:

[0343] 12.1. Determine in a chip-transistor-level netlist whether the position of the fifteenth identifier and / or the portion of the fifteenth identifier and / or the portion where the code length between the fifteenth identifier and the fifteenth identifier is less than or equal to a thirty-second preset threshold and / or the portion where the code length between the fifteenth identifier and the fifteenth identifier accounts for less than or equal to a first proportion threshold in the chip-transistor-level netlist, and / or the position and / or portion (referring to the preceding: the position of the fifteenth identifier and / or the portion of the fifteenth identifier and / or the portion where the code length between the fifteenth identifier and the fifteenth identifier is less than or equal to the thirty-second preset threshold and / or the portion where the code length between the fifteenth identifier and the fifteenth identifier accounts for less than or equal to the first proportion threshold in the chip-transistor-level netlist) and / or the module and / or unit and / or design information corresponding to the fifteenth identifier is the target chip and / or an IP core called and / or suspected of being called by the information of the target chip; the fifteenth identifier is an identifier of a company other than the design company of the target chip, and / or an identifier representing a company other than the design company of the target chip;

[0344] 12.2. Determine in a chip-transistor-level netlist the position where the sixteenth identifier is located and / or the portion where the sixteenth identifier is located and / or the portion between the sixteenth identifier and the sixteenth identifier whose code length is less than or equal to a thirty-third preset threshold and / or the portion where the code length between the sixteenth identifier and the sixteenth identifier is less than or equal to a second proportion threshold, and / or the position and / or portion (referring to the preceding: the position where the sixteenth identifier is located and / or the portion where the sixteenth identifier is located and / or the portion between the sixteenth identifier and the sixteenth identifier whose code length is less than or equal to the thirty-third preset threshold and / or the portion where the code length between the sixteenth identifier and the sixteenth identifier is less than or equal to the second proportion threshold in the chip-transistor-level netlist) and / or the module and / or unit and / or design information corresponding to the sixteenth identifier is the target chip and / or an IP core called and / or suspected of being called by the information of the target chip; the sixteenth identifier is the identifier of the design company of the target chip and / or an identifier representing the design company of the target chip;

[0345] 12.3. Determine the sixteenth portion of the transistor-level netlist of the chip, and / or the module and / or unit and / or design information corresponding to the sixteenth portion, which is identical and / or similar and / or has a similarity greater than or equal to a thirty-fourth preset threshold, as the target chip and / or an IP core invoked and / or suspected of being invoked by the target chip's information; the nineteenth preset library does not contain a transistor-level netlist designed by the design company of the target chip;

[0346] 12.4. Determine the eighteenth part of the transistor-level netlist of the chip, which is identical and / or similar and / or has a similarity greater than or equal to the thirty-fifth preset threshold, and / or the module and / or unit and / or design information corresponding to the eighteenth part, as the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; the transistor-level netlist designed by the design company of the target chip in the 20th preset library, and / or the transistor-level netlist IP core library of the design company of the target chip, and / or the IP core library of the design company of the target chip;

[0347] 12.5. Determine the target chip and / or the IP cores invoked and / or suspected of being invoked by the target chip based on the chip transistor-level netlist and chip design layout and / or design layout and / or design layout and wiring and / or design layout and wiring diagram, and the results and / or reports of failed LVS verifications performed one or more times using one or more LVS verification software and / or tools and / or environments;

[0348] It should be noted that the LVS verification environment can be an EDA environment that includes LVS verification, such as an EDA software environment that can perform design, simulation, and verification. LVS verification can be performed directly within this complete environment. For example, if the verification object passes verification in one LVS verification environment but fails in another, the IP core can be determined based on the latter.

[0349] Optionally, the determination method includes but is not limited to one or more of the following: determining that the module and / or unit and / or design information corresponding to the transistor-level netlist portion that failed the verification, and / or the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring area that failed, and / or the failed portion and / or failed area (referring to the previous: the failed transistor-level netlist portion, and / or the failed chip design layout and / or design layout and / or design layout wiring and / or design layout wiring area) is the target chip and / or the information of the target chip The IP core that is called and / or suspected of being called is determined; the devices and / or connection relationships in the transistor-level netlist discovered during the verification, the differences between the devices and / or connection relationships in the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, and / or the transistor-level netlist portion, and / or chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram area, and / or module, and / or unit, and / or design information corresponding to the differences are determined to be the target chip and / or the IP core that is called and / or suspected of being called by the information of the target chip;

[0350] 12.6. Determine the target chip and / or the IP cores invoked and / or suspected of being invoked by the target chip based on the chip transistor-level netlist and chip design layout and / or design layout and / or design layout and / or design layout and wiring diagram, after modifying the names of one, some, or all modules and / or units, and performing one or more LVS verifications using one or more LVS verification software and / or tools and / or environments, and the results and / or reports of failed LVS verifications;

[0351] It should be noted that the LVS verification environment can be: a set of EDA environments that include LVS verification, such as an EDA software environment that can perform design, simulation, and verification, and LVS verification can be performed directly in this complete environment. For example, for the verification object, if verification passes in one LVS verification environment but fails in another LVS verification environment, the IP core can be determined based on the latter. (It should be noted that if the determined IP core happens to be a module and / or unit whose name is modified during verification, the module and / or unit will remain IP both before and after the name modification.

[0352] Optionally, the determination method includes but is not limited to one or more of the following: determining that the module and / or unit and / or design information corresponding to the transistor-level netlist portion that failed the verification, and / or the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring area that failed, and / or the failed portion and / or failed area (referring to the previous: the failed transistor-level netlist portion, and / or the failed chip design layout and / or design layout and / or design layout wiring and / or design layout wiring area) is the target chip and / or the information of the target chip An IP core that is called and / or suspected of being called; determining the devices and / or connection relationships in the transistor-level netlist discovered during verification, the differences between the devices and / or connection relationships in the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, and / or the transistor-level netlist parts corresponding to the differences, and / or the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram areas, and / or modules, and / or units, and / or design information, as the target chip and / or the information of the target chip that is called and / or suspected of being called the IP core.

[0353] Optionally, the second information includes a gate-level netlist of the chip, and / or a chip design layout and / or a design layout and / or a design layout and wiring and / or a design layout and wiring diagram;

[0354] Optionally, the gate-level netlist of the chip includes but is not limited to one or more of the following: a gate-level netlist for completing the final design, a gate-level netlist corresponding to the chip design layout and / or design layout and / or design layout and wiring and / or design layout and wiring diagram, a gate-level netlist synthesized from the chip RTL code, a front-end gate-level netlist, a back-end gate-level netlist, and a gate-level netlist during the chip design process; the front-end gate-level netlist and / or back-end gate-level netlist and / or gate-level netlist during the chip design process include but are not limited to one or more gate-level netlists;

[0355] Optionally, determining the target chip and / or information of the target chip based on the second information, and calling and / or suspected calling of an IP core, includes but is not limited to one or more of the following 13.1-13.11:

[0356] 13.1. Determine whether the position of the seventeenth identifier in the gate-level netlist of the chip and / or the portion where the seventeenth identifier is located and / or the portion between the seventeenth identifier and the seventeenth identifier has a code length less than or equal to a thirty-sixth preset threshold and / or the portion where the code length between the seventeenth identifier and the seventeenth identifier accounts for less than or equal to a third proportion threshold in the gate-level netlist of the chip, and / or the position and / or portion (referring to the preceding: the position of the seventeenth identifier in the gate-level netlist of the chip and / or the portion where the seventeenth identifier is located and / or the portion between the seventeenth identifier and the seventeenth identifier has a code length less than or equal to the thirty-sixth preset threshold and / or the portion where the code length between the seventeenth identifier and the seventeenth identifier accounts for less than or equal to the third proportion threshold in the gate-level netlist of the chip) and / or the module and / or unit and / or design information corresponding to the seventeenth identifier is the target chip and / or an IP core called and / or suspected of being called by the information of the target chip; the seventeenth identifier is an identifier of a company other than the design company of the target chip, and / or an identifier representing a company other than the design company of the target chip;

[0357] 13.2. Determine that the position of the eighteenth identifier in the gate-level netlist of the chip and / or the portion where the eighteenth identifier is located and / or the portion where the code length between the eighteenth identifier and the eighteenth identifier is less than or equal to the thirty-seventh preset threshold and / or the portion where the code length between the eighteenth identifier and the eighteenth identifier is less than or equal to the fourth proportion threshold, and / or the position and / or portion (referring to the preceding: the position of the eighteenth identifier in the gate-level netlist of the chip and / or the portion where the code length between the eighteenth identifier and the eighteenth identifier is less than or equal to the thirty-seventh preset threshold and / or the portion where the code length between the eighteenth identifier and the eighteenth identifier is less than or equal to the fourth proportion threshold) and / or the module and / or unit and / or design information corresponding to the eighteenth identifier is the target chip and / or an IP core called and / or suspected of being called by the information of the target chip; the eighteenth identifier is the identifier of the design company of the target chip and / or an identifier representing the design company of the target chip;

[0358] 13.3. Determine the twentieth portion of the gate-level netlist of the chip, and / or the module and / or unit and / or design information corresponding to the twentieth portion, which is identical and / or similar and / or has a similarity greater than or equal to a thirty-eighth preset threshold to the nineteenth portion of the gate-level netlist in the twenty-first preset library, as the target chip and / or an IP core invoked and / or suspected of being invoked by the information of the target chip; the twenty-first preset library does not contain a gate-level netlist designed by the design company of the target chip;

[0359] 13.4. Determine the 22nd portion of the gate-level netlist of the chip, and / or the module and / or unit and / or design information corresponding to the 22nd portion, which is identical and / or similar and / or has a similarity greater than or equal to the 39th preset threshold, as the target chip and / or an IP core called and / or suspected of being called by the information of the target chip; the gate-level netlist designed by the design company of the target chip, and / or the gate-level netlist IP core library of the design company of the target chip, and / or the IP core library of the design company of the target chip in the 22nd preset library;

[0360] 13.5. Determine the target chip and / or the IP cores invoked and / or suspected of being invoked by the target chip based on the chip's gate-level netlist and chip design layout and / or design layout and / or design layout and routing and / or design layout and routing diagram, and the results and / or reports of failed LVS verifications conducted one or more times using one or more LVS verification software and / or tools and / or environments;

[0361] It should be noted that the LVS verification environment can be an EDA environment that includes LVS verification, such as an EDA software environment that can perform design, simulation, and verification. LVS verification can be performed directly within this complete environment. For example, if the verification object passes verification in one LVS verification environment but fails in another, the IP core can be determined based on the latter.

[0362] Optionally, the determination method includes but is not limited to one or more of the following: determining that the module and / or unit and / or design information corresponding to the gate-level netlist portion that failed the verification, and / or the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram area that failed, and / or the failed portion and / or failed area (referring to the previous: the failed gate-level netlist portion, and / or the failed chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram area) is the target chip and / or the information of the target chip The IP core that is called and / or suspected of being called is determined; the devices and / or connection relationships in the gate-level netlist discovered during the verification, the differences between the devices and / or connection relationships in the chip design layout and / or design layout and / or design layout and wiring and / or design layout and wiring diagram, and / or the gate-level netlist portion, and / or chip design layout and / or design layout and / or design layout and wiring and / or design layout and wiring diagram area, and / or module, and / or unit, and / or design information corresponding to the differences are the target chip and / or the IP core that is called and / or suspected of being called by the information of the target chip;

[0363] 13.6. Determine the target chip and / or the IP core that is called and / or suspected of being called by the target chip based on the chip's gate-level netlist and chip design layout and / or design layout and / or design layout and / or design layout and wiring diagram, after modifying the names of one, some, or all of the modules and / or units, and performing one or more LVS verifications using one or more LVS verification software and / or tools and / or environments, and the results and / or reports of any failed LVS verifications;

[0364] It should be noted that the LVS verification environment can be: a set of EDA environments that include LVS verification, such as an EDA software environment that can perform design, simulation, and verification, and LVS verification can be performed directly in this complete environment. For example, for the verification object, if verification passes in one LVS verification environment but fails in another LVS verification environment, the IP core can be determined based on the latter. (It should be noted that if the determined IP core happens to be a module and / or unit whose name is modified during verification, the module and / or unit will remain IP both before and after the name modification.

[0365] Optionally, the determination method includes but is not limited to one or more of the following: determining that the module and / or unit and / or design information corresponding to the gate-level netlist portion that failed the verification, and / or the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram area that failed, and / or the failed portion and / or failed area (referring to the previous: the failed gate-level netlist portion, and / or the failed chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram area) is the target chip and / or the information of the target chip The IP core that is called and / or suspected of being called is determined; the devices and / or connection relationships in the gate-level netlist discovered during the verification, the differences between the devices and / or connection relationships in the chip design layout and / or design layout and / or design layout and wiring and / or design layout and wiring diagram, and / or the gate-level netlist portion, and / or chip design layout and / or design layout and / or design layout and wiring and / or design layout and wiring diagram area, and / or module, and / or unit, and / or design information corresponding to the differences are the target chip and / or the IP core that is called and / or suspected of being called by the information of the target chip;

[0366] 13.7. After converting the chip's gate-level netlist to a chip transistor-level netlist, determine the target chip and / or the IP cores invoked and / or suspected of being invoked by the target chip by comparing the converted chip transistor-level netlist with the chip design layout and / or design layout and / or design layout and wiring and / or design layout and wiring diagram, and the results and / or reports of failed LVS verifications performed one or more times using one or more LVS verification software and / or tools and / or environments;

[0367] It should be noted that the LVS verification environment can be an EDA environment that includes LVS verification, such as an EDA software environment that can perform design, simulation, and verification. LVS verification can be performed directly in this complete environment. For example, if the verification object passes verification in one LVS verification environment but fails in another, the IP core will be determined based on the latter.

[0368] Optionally, the determination method includes but is not limited to one or more of the following: determining that the transistor-level netlist portion that failed the verification, and / or the gate-level netlist portion corresponding to the failed transistor-level netlist portion, and / or the failed chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram area, and / or the failed portion and / or the failed area (referring to the previous: the failed transistor-level netlist portion, and / or the gate-level netlist portion corresponding to the failed transistor-level netlist portion, and / or the failed chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram area) corresponds to the module and / or unit and / or design information as the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; determining the devices and / or connection relationships in the transistor-level netlist found in the verification, the differences between the devices and / or connection relationships in the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, and / or the transistor-level netlist part corresponding to the difference, and / or the gate-level netlist part corresponding to the corresponding transistor-level netlist part, and / or the corresponding chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram area, and / or module, and / or unit, and / or design information, as the target chip and / or the IP core called and / or suspected of being called by the information of the target chip;

[0369] 13.8. After converting the chip's gate-level netlist to a chip transistor-level netlist, determine the target chip and / or the IP cores invoked and / or suspected of being invoked by the target chip by comparing the converted chip transistor-level netlist with the chip design layout and / or design layout and / or design layout and wiring and / or design layout and wiring diagram, after modifying the names of one, some, or all modules and / or units, and performing one or more LVS verifications using one or more LVS verification software and / or tools and / or environments, and the results and / or reports of any failed LVS verifications;

[0370] It should be noted that the LVS verification environment can be: a set of EDA environments that include LVS verification, such as an EDA software environment that can perform design, simulation, and verification, and LVS verification can be performed directly in this complete environment. For example, for the verification object, if verification passes in one LVS verification environment but fails in another LVS verification environment, the IP core can be determined based on the latter. (It should be noted that if the determined IP core happens to be a module and / or unit whose name is modified during verification, the module and / or unit will remain IP both before and after the name modification.

[0371] Optionally, the determination method includes but is not limited to one or more of the following: determining that the transistor-level netlist portion that failed the verification, and / or the gate-level netlist portion corresponding to the failed transistor-level netlist portion, and / or the failed chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram area, and / or the failed portion and / or the failed area (referring to the previous: the failed transistor-level netlist portion, and / or the gate-level netlist portion corresponding to the failed transistor-level netlist portion, and / or the failed chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram area) corresponds to the module and / or unit and / or design information as the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; determining the devices and / or connection relationships in the transistor-level netlist found in the verification, the differences between the devices and / or connection relationships in the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, and / or the transistor-level netlist part corresponding to the difference, and / or the gate-level netlist part corresponding to the corresponding transistor-level netlist part, and / or the corresponding chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram area, and / or module, and / or unit, and / or design information, as the target chip and / or the IP core called and / or suspected of being called by the information of the target chip;

[0372] 13.9. Based on the chip's gate-level netlist and the chip design layout and / or design layout and / or design layout and wiring and / or design layout wiring diagram, after modifying the names of one, some, or all of the modules and / or units, convert the modified gate-level netlist into a chip transistor-level netlist, and perform one or more LVS verifications on the converted chip transistor-level netlist and the modified chip design layout and / or design layout and wiring and / or design layout wiring diagram using one or more LVS verification software and / or tools and / or environments, and determine the target chip and / or the IP cores called and / or suspected of being called by the target chip information, and / or the IP cores that are suspected of being called by the target chip information;

[0373] It should be noted that the LVS verification environment can be: a set of EDA environments that include LVS verification, such as an EDA software environment that can perform design, simulation, and verification, and LVS verification can be performed directly in this complete environment. For example, for the verification object, if verification passes in one LVS verification environment but fails in another LVS verification environment, the IP core can be determined based on the latter. (It should be noted that if the determined IP core happens to be a module and / or unit whose name is modified during verification, the module and / or unit will remain IP both before and after the name modification.

[0374] Optionally, the determination method includes but is not limited to one or more of the following: determining that the transistor-level netlist portion that failed the verification, and / or the gate-level netlist portion corresponding to the failed transistor-level netlist portion, and / or the failed chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram area, and / or the failed portion and / or the failed area (referring to the previous: the failed transistor-level netlist portion, and / or the gate-level netlist portion corresponding to the failed transistor-level netlist portion, and / or the failed chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram area) corresponds to the module and / or unit and / or design information as the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; determining the devices and / or connection relationships in the transistor-level netlist found in the verification, the differences between the devices and / or connection relationships in the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, and / or the transistor-level netlist part corresponding to the difference, and / or the gate-level netlist part corresponding to the corresponding transistor-level netlist part, and / or the corresponding chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram area, and / or module, and / or unit, and / or design information, as the target chip and / or the IP core called and / or suspected of being called by the information of the target chip;

[0375] 13.10. Determine the target chip and / or the IP cores invoked and / or suspected of being invoked by the target chip based on two gate-level netlists of the chip, one or more formal verifications conducted using one or more formal verification software and / or tools and / or environments, and the results and / or reports of failed formal verifications;

[0376] It should be noted that the two gate-level netlists may be any two of one or more of the following, and / or two of one: a gate-level netlist to complete the final design, a gate-level netlist corresponding to the chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, a gate-level netlist formed by synthesizing the chip register transfer level RTL code, a front-end gate-level netlist, a back-end gate-level netlist, and a gate-level netlist in the chip design process. The front-end gate-level netlist and / or back-end gate-level netlist and / or gate-level netlist in the chip design process include but are not limited to one or more gate-level netlists.

[0377] It should also be noted that a formal verification environment can be an EDA environment that includes formal verification, such as an EDA software environment that can perform design, simulation, and verification. Formal verification can be performed directly within this complete environment. For example, if the verification object passes verification in one formal verification environment but fails in another, the IP core can be determined based on the latter.

[0378] Optionally, the determination method includes but is not limited to one or more of the following: determining that the gate-level netlist portion that failed in the verification, and / or the module and / or unit and / or design information corresponding to the failed portion (referring to the preceding: the gate-level netlist portion that failed) is the target chip and / or the information call of the target chip and / or the IP core suspected of calling; determining that the gate-level netlist portion corresponding to the mismatch point found in the verification, and / or the portion (referring to the preceding: the gate-level netlist portion corresponding to the mismatch point found in the verification) and / or the module and / or unit and / or design information corresponding to the mismatch point is the target chip and / or the IP core suspected of calling. the target chip's information call and / or suspected IP core called; determining that the inequivalent portion found in the verification, and / or the gate-level netlist portion corresponding to the inequivalent portion, and / or the module and / or unit and / or design information corresponding to the inequivalent portion are the target chip and / or the IP core called by the information of the target chip and / or suspected IP core called; determining that the difference in logic and / or function between two gate-level netlists found in the verification, and / or the gate-level netlist portion corresponding to the difference, and / or the module and / or unit and / or design information are the target chip and / or the IP core called by the information of the target chip and / or suspected IP core called;

[0379] 13.11. Determine the target chip and / or the IP cores invoked and / or suspected of being invoked by the target chip based on two gate-level netlists of the chip, after modifying the names of one, some, or all of the modules and / or units, and using one or more formal verification software and / or tools and / or environments to conduct one or more formal verifications, and the results and / or reports of the formal verifications that failed;

[0380] It should be noted that the two gate-level netlists may include but are not limited to any two of one or more of the following, and / or two of one: a gate-level netlist for completing the final design, a gate-level netlist corresponding to the chip design layout and / or design layout and / or design layout and wiring and / or design layout and wiring diagram, a gate-level netlist formed by synthesizing the chip register transfer level RTL code, a front-end gate-level netlist, a back-end gate-level netlist, a gate-level netlist during the chip design process, and the front-end gate-level netlist and / or back-end gate-level netlist and / or the gate-level netlist during the chip design process include but are not limited to one or more gate-level netlists. It should be noted that the formal verification environment may be: a set of EDA environments that include formal verification, such as an EDA software environment that can perform design, simulation, and verification, and formal verification is performed directly in this complete environment. For example, for the verification object, if it passes verification in one formal verification environment but fails in another formal verification environment, the IP core can be determined based on the latter. It should be noted that if the determined IP core happens to be a module and / or unit whose name is modified during verification, the module and / or unit is still an IP before and after the name is modified.

[0381] Optionally, the determination method includes but is not limited to one or more of the following: determining that the gate-level netlist portion that failed the verification, and / or the module and / or unit and / or design information corresponding to the failed portion (referring to the previous: the gate-level netlist portion that failed the verification) is the target chip and / or the information call of the target chip and / or the IP core suspected of calling; determining that the gate-level netlist portion corresponding to the mismatch point found in the verification, and / or the portion (referring to the previous: the gate-level netlist portion corresponding to the mismatch point found in the verification) and / or the module and / or unit and / or design information corresponding to the mismatch point is the target chip and / or The information call and / or suspected call of the target chip; determining that the inequivalent part found in the verification, and / or the gate-level netlist part corresponding to the inequivalent part, and / or the module and / or unit and / or design information corresponding to the inequivalent part are the target chip and / or the IP core called by the information of the target chip and / or suspected call; determining that the difference in logic and / or function between two gate-level netlists found in the verification, and / or the gate-level netlist part, and / or the module and / or unit and / or design information corresponding to the difference are the target chip and / or the IP core called by the information of the target chip and / or suspected call;

[0382] Optionally, when conducting formal verification, if there are differences between the two gate-level netlists in the functions and / or logic of auxiliary design and / or auxiliary testing, the functions and / or logic corresponding to the differences are verified or not verified; for example, one gate-level netlist is front-end, and the other gate-level netlist is back-end, and the back-end netlist adds a scan chain of testability design. If it is considered that this is a function that facilitates subsequent chip testing and is not a focus of IP core testing, it can be not verified; on the contrary, if it is considered that IP core testing is also necessary, it is verified; similarly, for other functions and / or logic, whether to verify can also be determined based on whether they are the focus of IP core testing.

[0383] Optionally, the method of not verifying the function and / or logic corresponding to the difference includes but is not limited to: when setting constants, prohibiting the auxiliary design and / or auxiliary test function and / or logic and / or pin and / or pin, and / or setting the auxiliary design and / or auxiliary test function and / or logic and / or pin and / or pin to be invalid;

[0384] Optionally, the functions and / or logic and / or pins and / or pins of the auxiliary design and / or auxiliary test include but are not limited to one or more of the following: scanning the SCAN chain and / or scanning the enable pin and / or enable pin corresponding to the SCAN chain, the JTAG chain and / or the enable pin and / or enable pin corresponding to the JTAG chain, the chip testability design and / or the pins and / or pins corresponding to the testability design.

[0385] Optionally, the second information includes chip RTL code and / or a gate-level netlist of the chip;

[0386] Optionally, the gate-level netlist of the chip includes but is not limited to one or more of the following: a gate-level netlist for completing the final design, a gate-level netlist corresponding to the chip design layout and / or design layout and / or design layout and wiring and / or design layout and wiring diagram, a gate-level netlist synthesized from the chip RTL code, a front-end gate-level netlist, a back-end gate-level netlist, and a gate-level netlist during the chip design process; the front-end gate-level netlist and / or back-end gate-level netlist and / or gate-level netlist during the chip design process include but are not limited to one or more gate-level netlists;

[0387] Optionally, determining the target chip and / or information of the target chip based on the second information, and calling and / or suspected calling of an IP core, includes but is not limited to one or more of the following 14.1-14.7:

[0388] 14.1. Determine whether the position of the nineteenth identifier in the chip RTL code and / or the portion of the nineteenth identifier and / or the portion between the nineteenth identifier and the nineteenth identifier has a code length less than or equal to the fortieth preset threshold and / or the portion of the code length between the nineteenth identifier and the nineteenth identifier in the chip RTL code is less than or equal to the fifth ratio threshold, and / or the position and / or portion (referring to the preceding: the position of the nineteenth identifier in the chip RTL code and / or the portion of the nineteenth identifier and / or the portion between the nineteenth identifier and the nineteenth identifier has a code length less than or equal to the fortieth preset threshold and / or the portion of the code length between the nineteenth identifier and the nineteenth identifier in the chip RTL code is less than or equal to the fifth ratio threshold) and / or the module and / or unit and / or design information corresponding to the nineteenth identifier is the target chip and / or an IP core called and / or suspected of being called by the information of the target chip; the nineteenth identifier is an identifier of a company other than the design company of the target chip, and / or an identifier representing a company other than the design company of the target chip;

[0389] 14.2. Determine whether the position of the 20th identifier in the chip RTL code and / or the portion of the 20th identifier and / or the portion between the 20th identifier and the portion whose code length is less than or equal to the 41st preset threshold and / or the portion whose code length between the 20th identifier and the portion in the chip RTL code is less than or equal to the 6th proportion threshold, and / or the position and / or portion (referring to the preceding: the position of the 20th identifier in the chip RTL code and / or the portion of the 20th identifier and / or the portion between the 20th identifier and the portion whose code length is less than or equal to the 41st preset threshold and / or the portion whose code length between the 20th identifier and the portion in the chip RTL code is less than or equal to the 6th proportion threshold) and / or the module and / or unit and / or design information corresponding to the 20th identifier is the target chip and / or an IP core called and / or suspected of being called by the information of the target chip; and whether the 20th identifier is the identifier of the design company of the target chip and / or an identifier representing the design company of the target chip.

[0390] 14.3. Determine the target chip and / or the IP core called and / or suspected of being called by the target chip's information based on the portion of the chip RTL code containing descriptions at levels other than the register transfer level;

[0391] Optionally, the other level descriptions except the register transfer level description include but are not limited to gate level description;

[0392] Optionally, the determination method includes but is not limited to one or more of the following: determining that one or more keywords existing in the chip RTL code, and / or the total number of one or more keywords existing in the chip RTL code is greater than or equal to the keyword corresponding to the forty-second preset threshold, and / or the proportion of the total number of one or more keywords existing in the chip RTL code in the entire chip RTL code is greater than or equal to the keyword corresponding to the forty-third preset threshold, and the position and / or the part where the keyword is located and / or the part where the code length between the keyword and the keyword is less than or equal to the forty-fourth preset threshold and / or the part where the code length between the keyword and the keyword is less than or equal to the seventh proportion threshold in the chip RTL code, and / or the position and / or the part (referring to the previous: the position and / or the part where the keyword is located and / or the part where the code length between the keyword and the keyword is less than or equal to the forty-fourth preset threshold and / or the part where the code length between the keyword and the keyword is less than or equal to the forty-fourth preset threshold in the chip RTL code. The method further comprises: determining the target chip and / or the IP core of the target chip by information calling and / or suspected calling thereof, wherein the keyword is a keyword representing descriptions at other levels except register transfer level description, and the types of the keyword include but are not limited to one or more of the following: code at the representation description level, vocabulary and / or phrases at the representation description level, script at the representation description level, program at the representation description level, netlist at the representation description level, wherein the netlist includes but is not limited to a gate-level netlist; determining the twenty-fourth part of the chip RTL code, which is identical and / or similar to the twenty-third part of the gate-level netlist of the chip and / or the module and / or unit and / or design information corresponding to the twenty-fourth part, and / or the module and / or unit and / or design information corresponding to the twenty-fourth part, as the target chip and / or the IP core of the target chip by information calling and / or suspected calling thereof;

[0393] 14.4. Determine the 26th portion of the chip RTL code, and / or the module and / or unit and / or design information corresponding to the 26th portion, which is identical and / or similar to the 25th portion of the RTL code in the 23rd preset library and / or has a similarity greater than or equal to a 46th preset threshold, as the target chip and / or an IP core invoked and / or suspected of being invoked by the target chip's information; the 23rd preset library does not contain RTL code designed by the design company of the target chip;

[0394] 14.5. Determine the 28th portion of the chip RTL code, and / or the module and / or unit and / or design information corresponding to the 28th portion, which is identical and / or similar and / or has a similarity greater than or equal to the 47th preset threshold, as the target chip and / or an IP core called and / or suspected of being called by the target chip's information; the RTL code designed by the design company of the target chip in the 24th preset library, and / or the RTL code IP core library of the design company of the target chip, and / or the IP core library of the design company of the target chip;

[0395] 14.6. Determine the target chip and / or the IP cores invoked and / or suspected of being invoked by the target chip based on the chip RTL code and the chip's gate-level netlist, and the results and / or reports of one or more formal verifications performed using one or more formal verification software and / or tools and / or environments, including any formal verifications that failed;

[0396] It should be noted that a formal verification environment can be an EDA environment that includes formal verification, such as an EDA software environment that can perform design, simulation, and verification. Formal verification can be performed directly within this complete environment. For example, if the verification object passes verification in one formal verification environment but fails in another, the IP core can be determined based on the latter.

[0397] Optionally, the determination method includes but is not limited to one or more of the following: determining that the RTL code portion and / or the gate-level netlist portion that failed in the verification, and / or the module and / or unit and / or design information corresponding to the failed portion (referring to the preceding: the failed RTL code portion and / or the failed gate-level netlist portion) are the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; determining that the RTL code portion and / or the gate-level netlist portion corresponding to the mismatch point found in the verification, and / or the portion (referring to the preceding: the RTL code portion and / or the gate-level netlist portion corresponding to the mismatch point) and / or the module and / or unit and / or design information corresponding to the mismatch point are the target chip and / or the IP core. the target chip and / or the IP core called and / or suspected to be called by the information of the target chip; determining that the inequivalent part found in the verification, and / or the RTL code part corresponding to the inequivalent part, and / or the gate-level netlist part corresponding to the inequivalent part, and / or the module and / or unit and / or design information corresponding to the inequivalent part are the target chip and / or the IP core called and / or suspected to be called by the information of the target chip; determining that the logic and / or function in the RTL code found in the verification and the difference between the logic and / or function in the gate-level netlist, and / or the RTL code part, and / or the gate-level netlist part, and / or the module and / or unit and / or design information corresponding to the difference are the target chip and / or the IP core called and / or suspected to be called by the information of the target chip;

[0398] 14.7. Determine the target chip and / or the IP cores invoked and / or suspected of being invoked by the target chip based on the chip RTL code and the chip's gate-level netlist, after modifying the names of one, some, or all modules and / or units, and using one or more formal verification software and / or tools and / or environments to conduct one or more formal verifications, and the results and / or reports of the formal verifications that failed;

[0399] It should be noted that the formal verification environment can be: a set of EDA environments that include formal verification, such as an EDA software environment that can perform design, simulation, and verification, and formal verification can be performed directly in this complete environment. For example, for the verification object, if verification passes in one formal verification environment but fails in another formal verification environment, the IP core can be determined based on the latter. (It should be noted that if the determined IP core happens to be a module and / or unit whose name is modified during verification, the module and / or unit remains IP before and after the name modification.

[0400] Optionally, the determination method includes but is not limited to one or more of the following: determining that the RTL code portion and / or the gate-level netlist portion that failed in the verification, and / or the module and / or unit and / or design information corresponding to the failed portion (referring to the preceding: the failed RTL code portion and / or the failed gate-level netlist portion) are the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; determining that the RTL code portion and / or the gate-level netlist portion corresponding to the mismatch point found in the verification, and / or the portion (referring to the preceding: the RTL code portion and / or the gate-level netlist portion corresponding to the mismatch point) and / or the module and / or unit and / or design information corresponding to the mismatch point are the target chip and / or or the IP core called by the information of the target chip and / or suspected of being called; determining that the inequivalent part found in the verification, and / or the RTL code part and / or the gate-level netlist part corresponding to the inequivalent part, and / or the module and / or unit and / or design information corresponding to the inequivalent part are the target chip and / or the IP core called by the information of the target chip and / or suspected of being called; determining that the logic and / or function in the RTL code found in the verification and the difference between the logic and / or function in the gate-level netlist, and / or the RTL code part and / or the gate-level netlist part and / or the module and / or unit and / or design information corresponding to the difference are the target chip and / or the IP core called by the information of the target chip and / or suspected of being called;

[0401] Optionally, when conducting formal verification, if there are differences between the RTL code and the gate-level netlist in the functions and / or logic of auxiliary design and / or auxiliary testing, the functions and / or logic corresponding to the differences are verified or not verified; for example, the gate-level netlist is the back-end, and a scan chain of testability design is added compared to the RTL code. If it is considered that this is a function that facilitates subsequent chip testing and is not a focus of IP core detection, it can be not verified; on the contrary, if it is considered that IP core detection is also necessary, it is verified; similarly, for other functions and / or logic, whether to verify can also be determined based on whether they are the focus of IP core detection.

[0402] Optionally, the method of not verifying the function and / or logic corresponding to the difference includes but is not limited to: when setting constants, prohibiting the auxiliary design and / or auxiliary test function and / or logic and / or pin and / or pin, and / or setting the auxiliary design and / or auxiliary test function and / or logic and / or pin and / or pin to be invalid;

[0403] Optionally, the functions and / or logic and / or pins and / or pins of the auxiliary design and / or auxiliary test include but are not limited to one or more of the following: scanning the SCAN chain and / or scanning the enable pin and / or enable pin corresponding to the SCAN chain, the JTAG chain and / or the enable pin and / or enable pin corresponding to the JTAG chain, the chip testability design and / or the pins and / or pins corresponding to the testability design.

[0404] Optionally, when determining, based on the first information, whether an IP core is called and / or whether an IP core is suspected to be called in a target chip and / or information of the target chip, a preset threshold and / or identifier and / or preset library and / or an area and / or part thereof, and when determining, based on the second information, the target chip and / or information of the target chip, an IP core to be called and / or suspected to be called, a preset threshold and / or identifier and / or preset library and / or an area and / or part thereof;

[0405] Optionally, when determining, based on the first information, in the target chip and / or in the information of the target chip, whether to call the IP core and / or whether it is suspected to call the IP core, the preset thresholds and / or identifiers and / or preset libraries and / or the areas and / or parts thereof used, the preset thresholds and / or identifiers and / or preset libraries and / or the areas and / or parts thereof of the same type are the same or different;

[0406] Optionally, based on the second information, determine the target chip and / or the information of the target chip, the IP core called and / or suspected of being called, the preset thresholds and / or identifiers and / or preset libraries used and / or the areas and / or parts therein, and whether the preset thresholds and / or identifiers and / or preset libraries and / or the areas and / or parts therein of the same type are the same or different.

[0407] Optionally, the IP core includes but is not limited to a non-self-developed IP core and / or a self-developed IP core;

[0408] Optionally, the non-self-developed IP core includes but is not limited to one or more of the following: an IP core not designed by the design company of the target chip, an IP core purchased by the design company of the target chip from other companies, an IP core called by the design company of the target chip from a non-self-developed IP core library, and an IP core whose intellectual property rights do not belong to the design company of the target chip;

[0409] Optionally, the self-developed IP core includes but is not limited to one or more of the following: the IP core designed by the design company of the target chip, the IP core independently developed by the design company of the target chip, the IP core owned by the design company of the target chip, the IP core accumulated by the design company of the target chip itself, and the IP core whose intellectual property rights belong to the design company of the target chip.

[0410] Optionally, the method further includes: determining, based on the first information and / or the second information and / or the information of the target chip and / or the design file of the target chip and / or the authorization information of the target chip (including but not limited to: IP core authorization information, chip own authorization information, chip design company's authorization information, etc.), whether the information of the target chip and / or the IP core called and / or suspected of being called is a non-self-developed IP core and / or whether it is a self-developed IP core; and / or

[0411] Optionally, while determining the target chip and / or information of the target chip based on the second information, and calling and / or suspected calling the IP core, determining whether the IP core is a non-self-developed IP core and / or whether it is a self-developed IP core;

[0412] Optionally, the method for determining whether the target chip and / or the target chip information, the called and / or suspected called IP core is a non-self-developed IP core includes but is not limited to one or more of the following 17.1.1-17.1.10:

[0413] 17.1.1. An IP core identified by the chip design layout and / or design layout and / or design layout and / or blank areas in the design layout and / or the content corresponding to the blank areas is a non-self-developed IP core; (For example, the IP core identified in 10.1 is considered a non-self-developed IP core)

[0414] 17.1.2. The IP cores identified as non-self-developed IP cores are determined by comparing the chip design layout and / or design layout and / or design layout and / or design layout and wiring diagrams with the corresponding physical chip and / or physical layout and / or physical layout and wiring diagrams, and / or the content corresponding to the inconsistencies. (For example, the IP cores identified in 10.2 are considered non-self-developed IP cores.)

[0415] 17.1.3. The IP core determined by the twenty-first identifier in the third information of the target chip is a non-self-developed IP core; the twenty-first identifier is an identifier of a company other than the design company of the target chip, and / or an identifier representing a company other than the design company of the target chip; (For example, the IP core determined in 10.3 is considered a non-self-developed IP core, the IP core determined in 10.4 is considered a non-self-developed IP core, the IP core determined in 11.1 is considered a non-self-developed IP core, the IP core determined in 12.1 is considered a non-self-developed IP core, the IP core determined in 13.1 is considered a non-self-developed IP core, and the IP core determined in 14.1 is considered a non-self-developed IP core)

[0416] 17.1.4. The IP core determined by the 26th region in the third information of the target chip, and / or the content corresponding to the 26th region, being identical and / or similar to the 25th region in the information in the 25th preset library, and / or having a similarity greater than or equal to the 48th preset threshold, is a non-self-developed IP core; the 25th preset library does not contain information designed by the design company of the target chip; (For example, the IP core determined in 10.7 is considered a non-self-developed IP core, the IP core determined in 10.9 is considered a non-self-developed IP core, and the IP core determined in 11.3 is considered a non-self-developed IP core)

[0417] 17.1.5. The IP core determined to be a non-self-developed IP core is determined by the 30th part of the third information of the target chip, and / or the content corresponding to the 30th part, being identical and / or similar to the 29th part of the information in the 26th preset library, and / or having a similarity greater than or equal to the 49th preset threshold. The 26th preset library does not contain information designed by the design company of the target chip. (For example, the IP core determined in 12.3 is considered a non-self-developed IP core, the IP core determined in 13.3 is considered a non-self-developed IP core, and the IP core determined in 14.4 is considered a non-self-developed IP core.)

[0418] 17.1.6. By determining the location and / or area of ​​the physical chip and / or physical layout and / or physical layout and / or physical layout and / or physical layout and / or physical layout and / or layout diagram, and / or the modules and / or units and / or design information corresponding to such locations and / or areas, the IP core is determined to be a non-self-developed IP core based on the location and / or area of ​​the corresponding chip design layout and / or design layout and / or design layout and / or design layout and / or the modules and / or units and / or design information corresponding to such locations and / or areas.

[0419] For example, in 10.11, the physical chip and / or physical layout and / or physical layout and / or physical layout wiring and / or physical layout wiring diagram position and / or area of ​​the target chip and / or the non-self-developed IP core called and / or suspected by the information of the target chip, and / or the module and / or unit and / or design information corresponding to the position and / or area, the corresponding chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram position and / or area, and / or the module and / or unit and / or design information corresponding to the position and / or area are determined as the non-self-developed IP core called and / or suspected by the information of the target chip.

[0420] 17.1.7. IP cores determined as non-self-developed IP cores by the results and / or reports of LVS verification that failed one or more times using one or more LVS verification software and / or tools and / or environments; (For example, the IP cores determined in 11.5 are considered non-self-developed IP cores, the IP cores determined in 11.6 are considered non-self-developed IP cores, the IP cores determined in 12.5 are considered non-self-developed IP cores, the IP cores determined in 12.6 are considered non-self-developed IP cores, the IP cores determined in 13.5 are considered non-self-developed IP cores, the IP cores determined in 13.6 are considered non-self-developed IP cores, the IP cores determined in 13.7 are considered non-self-developed IP cores, the IP cores determined in 13.8 are considered non-self-developed IP cores, and the IP cores determined in 13.9 are considered non-self-developed IP cores)

[0421] 17.1.8. IP cores determined by the results and / or reports of one or more formal verifications conducted using one or more formal verification software and / or tools and / or environments that fail to pass the formal verification are considered non-self-developed IP cores. (For example, the IP cores determined in 13.10 are considered non-self-developed IP cores, the IP cores determined in 13.11 are considered non-self-developed IP cores, the IP cores determined in 14.6 are considered non-self-developed IP cores, and the IP cores determined in 14.7 are considered non-self-developed IP cores.)

[0422] 17.1.9. IP cores identified as non-self-developed IP cores based on the descriptions at levels other than register transfer level in the chip RTL code. (For example, the IP cores identified in 14.3 are considered non-self-developed IP cores.)

[0423] 17.1.10. If, with respect to the target chip and / or the IP core invoked and / or suspected of being invoked by the target chip's information, it is determined that the IP core is not a self-developed IP core invoked and / or suspected of being invoked by the target chip and / or the target chip's information, the IP core is a non-self-developed IP core invoked and / or suspected of being invoked by the target chip and / or the target chip's information;

[0424] Optionally, the method for determining whether the target chip and / or the target chip information, the called and / or suspected called IP core is a self-developed IP core includes but is not limited to one or more of the following 17.2.1-17.2.5:

[0425] 17.2.1. The IP core determined by the twenty-second identifier in the third information of the target chip is a self-developed IP core; the twenty-second identifier is the identifier of the design company of the target chip and / or the identifier representing the design company of the target chip; (For example, the IP core determined in 10.5 is considered a self-developed IP core, the IP core determined in 10.6 is considered a self-developed IP core, the IP core determined in 11.2 is considered a self-developed IP core, the IP core determined in 12.2 is considered a self-developed IP core, the IP core determined in 13.2 is considered a self-developed IP core, and the IP core determined in 14.2 is considered a self-developed IP core)

[0426] 17.2.2. The IP core determined to be a self-developed IP core is the 28th region in the third information of the target chip, and / or the content corresponding to the 28th region, which is identical and / or similar to the 27th region in the information in the 27th preset library, and / or whose similarity is greater than or equal to the 50th preset threshold; the IP core determined to be a self-developed IP core is the 28th region in the third information of the target chip, and / or the content corresponding to the 28th region; the IP core determined to be a self-developed IP core is the 27th preset library, and / or the IP core library of the design company of the target chip; (For example, the IP core determined in 10.8 is considered a self-developed IP core, the IP core determined in 10.10 is considered a self-developed IP core, the IP core determined in 11.4 is considered a self-developed IP core, and the IP core determined in 14.5 is considered a self-developed IP core).

[0427] 17.2.3. The IP core determined to be a self-developed IP core is determined by the 32nd portion of the third information of the target chip, and / or the content corresponding to the 32nd portion, being identical and / or similar to the 31st portion of the information in the 28th preset library, and / or having a similarity greater than or equal to the 51st preset threshold. The IP core determined to be a self-developed IP core is determined by the 28th preset library, including the design information of the design company of the target chip, and / or the IP core library of the design company of the target chip. (For example, the IP core determined in 12.4 is considered a self-developed IP core, and the IP core determined in 13.4 is considered a self-developed IP core.)

[0428] 17.2.4. By determining the physical chip and / or physical layout and / or physical layout and / or physical layout and / or physical layout and / or physical layout and / or layout diagram location and / or area, and / or the modules and / or units and / or design information corresponding to such locations and / or areas, and / or the corresponding chip design layout and / or design layout and / or design layout and / or design layout diagram location and / or area, and / or the modules and / or units and / or design information corresponding to such locations and / or areas, the IP core is determined to be a self-developed IP core;

[0429] For example, in 10.11, the physical chip and / or physical layout and / or physical layout and / or physical layout wiring and / or physical layout wiring diagram of the target chip and / or the self-developed IP core called and / or suspected by the information of the target chip, and / or the position and / or area, and / or the module and / or unit and / or design information corresponding to the position and / or area, the corresponding chip design layout and / or design layout and / or design layout wiring and / or the position and / or area, and / or the module and / or unit and / or design information corresponding to the position and / or area are determined to be the self-developed IP core called and / or suspected by the information of the target chip.

[0430] 17.2.5. For the target chip and / or the IP core invoked and / or suspected of being invoked by the target chip's information, if it is determined that the IP core is not a non-self-developed IP core invoked, invoked, and / or suspected of being invoked by the target chip and / or the target chip's information, then the IP core is a self-developed IP core invoked and / or suspected of being invoked by the target chip and / or the target chip's information;

[0431] Optionally, the third information of the target chip includes but is not limited to one or more of the following: chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, physical chip and / or physical layout and / or physical layout wiring and / or physical layout wiring diagram, chip schematic, chip transistor-level netlist, chip gate-level netlist, chip RTL code, all or part of one or more of the first information, and all or part of one or more of the second information;

[0432] Optionally, the types of information in the 25th preset library and / or the 26th preset library and / or the 27th preset library and / or the 28th preset library and / or the information designed by the design company of the target chip and / or the information IP core library of the design company of the target chip include but are not limited to one or more of the following: layout and / or layout and / or layout and wiring and / or layout and wiring diagram, schematic diagram, transistor-level netlist, gate-level netlist, RTL code.

[0433] Optionally, the method further includes: determining the degree of autonomy and / or controllability of the chip; the determination method includes but is not limited to one or more of the following 18.1-18.15:

[0434] 18.1. Determine one or more types of fourth information required to determine the autonomy and / or controllability of the chip, including but not limited to one or more of the following: chip design layout and / or design layout and / or design layout and wiring and / or design layout wiring diagram, physical chip and / or physical layout and / or physical layout and wiring and / or physical layout and wiring diagram, chip schematic, chip transistor-level netlist, chip gate-level netlist, chip RTL code, all or part of one or more types of the first information, all or part of one or more types of the second information, and other chip information other than the first and second information;

[0435] 18.2. For each of the one or more required fourth information, assign a score corresponding to the fourth information;

[0436] Optionally, the method of assigning scores includes but is not limited to: assigning scores according to the difficulty and / or criticality of each type of fourth information implementation and / or design;

[0437] 18.3. For each type of required fourth information, if the fourth information obtained does not contain all of the information of the chip to be determined, and / or does not contain all functions and / or all logic and / or all modules and / or all units of the chip to be determined, and / or if the fourth information obtained calls a non-self-developed IP core and / or is suspected of calling a non-self-developed IP core, the score obtained by the chip is: the score corresponding to the fourth information, minus the part of the information of the chip to be determined that is missing in the fourth information and / or the missing functions and / or missing logic and / or missing modules and / or missing units. The score corresponding to the missing unit is deducted from the score corresponding to the non-self-developed IP core called and / or suspected to be called in the obtained fourth information, and the remaining score is obtained; and / or, the score obtained by the chip is: the score corresponding to the fourth information, deducted from the first proportion of the scores corresponding to the missing information part of the chip to be determined and / or the missing function and / or the missing logic and / or the missing module and / or the missing unit in the obtained fourth information, and the remaining score is obtained after deducting the second proportion of the scores corresponding to the non-self-developed IP core called and / or suspected to be called in the obtained fourth information;

[0438] Optionally, if the portion of the information of the chip to be determined that is missing in the obtained fourth information and / or the missing function and / or the missing logic and / or the missing module and / or the missing unit are repeated and / or overlapped with the non-self-developed IP core called and / or suspected of being called in the obtained fourth information, then only one point will be deducted for the repeated and / or overlapping content, and / or no points will be deducted repeatedly;

[0439] Optionally, the method for determining the first ratio and / or the second ratio includes but is not limited to one or more of the following: the ratio is less than or equal to 1, the ratio is greater than or equal to 0, the ratio of the missing information portion of the chip to be determined and / or the missing function and / or the missing logic and / or the missing module and / or the missing unit when they are domestically produced is less than or equal to the ratio when they are non-domestic produced, and the ratio of the non-self-developed IP core called and / or suspected of being called when they are domestically produced is less than or equal to the ratio when the non-self-developed IP core is non-domestic produced;

[0440] 18.4. For each type of required fourth information, if the acquired fourth information contains all such information of the chip to be evaluated and / or contains all functions and / or all logic and / or all modules and / or all units of the chip to be evaluated, and the acquired fourth information does not call or is suspected of calling non-independent IP cores, then the score assigned to the chip is: the score corresponding to that type of fourth information;

[0441] 18.5. For each required fourth information, if such fourth information is not obtained and / or it cannot be confirmed that the obtained fourth information is the fourth information of the chip, the chip will not receive any points for such fourth information.

[0442] 18.6. Sum the actual scores obtained by the chip for each of the one or more required fourth information to obtain the total score of the chip. The chip's autonomy and / or controllability is determined based on the total score.

[0443] 18.7. One case where the obtained fourth information does not include all such information of the chip to be determined and / or does not include all functions and / or all logic and / or all modules and / or all units of the chip to be determined is that other information after the fourth information is designed calls for a non-self-developed IP core, and the fourth information has not yet designed the functions and / or logic and / or modules and / or units corresponding to the IP core;

[0444] 18.8. When assigning scores corresponding to the required one or more types of fourth information, it is necessary to ensure that a chip with a given function, under different solutions, has the same score corresponding to the same degree of autonomy and / or controllability. Methods for achieving this include, but are not limited to, ensuring that the sum of the scores corresponding to the required fourth information is the same for a chip with a given function under different solutions.

[0445] For example 1, the fourth information required is determined to be the physical chip, chip design layout, chip gate-level netlist, and chip RTL code. Each type of fourth information is worth 25 points.

[0446] If the function of module A is missing from the obtained chip gate-level netlist, the score of the chip in the gate-level netlist is 25 points of the RTL code - the score of module A (assuming it is 5 points) = 20 points.

[0447] If the obtained chip design layout calls non-self-developed IP core B, the score obtained by the chip in the design layout is 25 points of the design layout - the score of non-self-developed IP core B (assuming it is 5 points) = 20 points;

[0448] If the chip contains all the information and / or all the functions and / or all the logic and / or all the modules and / or all the units of the chip to be tested, and does not call or suspect the use of non-self-developed IP cores, the chip will be scored 25 points in the chip physical area.

[0449] If the RTL code is not obtained, the chip will not get any points in the RTL code.

[0450] Then the final total score of the chip is 20 points + 20 points + 25 points = 65.

[0451] Example 2: The fourth information required is determined to be the physical chip, chip design layout, chip gate-level netlist, and chip RTL code. Each type of fourth information is worth 25 points.

[0452] If the function of module A is missing from the obtained chip gate-level netlist, the score of the chip in the gate-level netlist is 25 points of the RTL code - the score of module A (assuming 5 points) * the first ratio (assuming 0.6) = 22 points.

[0453] If the obtained chip design layout calls non-self-developed IP core B, the score obtained by the chip in the design layout is 25 points of the design layout - the score of non-self-developed IP core B (assuming it is 5 points) * the second ratio (assuming it is 0.4) = 23 points;

[0454] If the chip contains all the information and / or all the functions and / or all the logic and / or all the modules and / or all the units of the chip to be tested, and does not call or suspect the use of non-self-developed IP cores, the chip will be scored 25 points in the chip physical area.

[0455] If the RTL code is not obtained, the chip will not get any points in the RTL code.

[0456] Then the total score of the chip is 22 points + 23 points + 25 points = 70.

[0457] Example 3: For a certain required fourth information, if there is more than one missing information part of the chip to be determined and / or the missing function and / or the missing logic and / or the missing module and / or the missing unit, and / or the non-self-developed IP core that is called and / or suspected of being called, then you can just remove them one by one.

[0458] For example 4, for a certain required fourth information, if there is more than one missing chip information portion and / or missing function and / or missing logic and / or missing module and / or missing unit, and / or non-self-developed IP core called or suspected of being called, and there are duplicates, then the duplicate portion will be deducted only once to avoid repeated deductions. For different required fourth information, if there are duplicates, this restriction does not apply.

[0459] For example 5, the second ratios of different IP cores, such as IP core C, IP core D, IP core E, etc., may be the same or different; similarly, the first ratios of different modules may be the same or different.

[0460] 18.9. Determine the various functions and / or logic and / or modules and / or units required to determine the chip's autonomy and / or controllability;

[0461] 18.10. For each of the various required functions and / or logics and / or modules and / or units, assign a score corresponding to that function and / or logic and / or module and / or unit;

[0462] Optionally, the method of assigning scores includes but is not limited to: assigning scores based on the difficulty and / or criticality of each function and / or logic and / or module and / or unit, implementation and / or design;

[0463] 18.11. For each required function and / or logic and / or module and / or unit, if the chip to be evaluated does not call a non-in-house developed IP core and is not suspected of calling a non-in-house developed IP core in that function and / or logic and / or module and / or unit, the chip will receive a score corresponding to that function and / or logic and / or module and / or unit.

[0464] 18.12. For each required function and / or logic and / or module and / or unit, if a non-in-house developed IP core is called or suspected of being called in that function and / or logic and / or module and / or unit of the chip to be evaluated, the chip will not receive the score corresponding to that function and / or logic and / or module and / or unit, and / or the chip will receive a score that is a third proportion of the score corresponding to that function and / or logic and / or module and / or unit.

[0465] Optionally, a method for determining the third ratio includes but is not limited to one or more of the following: a ratio less than or equal to 1, a ratio greater than or equal to 0, a ratio when the called and / or suspected called non-self-developed IP core is domestically produced is greater than or equal to a ratio when the non-self-developed IP core is non-domestic produced;

[0466] 18.13. For each required function and / or logic and / or module and / or unit, if the chip to be evaluated lacks that function and / or logic and / or module and / or unit, the chip will not receive a score for that function and / or logic and / or module and / or unit.

[0467] 18.14. Sum the actual scores obtained by the chip for each of the various required functions and / or logics and / or modules and / or units to form the chip's total score. The chip's degree of autonomy and / or controllability is determined based on this total score.

[0468] 18.15. In particular, when assigning scores corresponding to the various functions and / or logics and / or modules and / or units required, it is necessary to ensure that the scores corresponding to the same degree of autonomy and / or controllability of a chip with a given function are the same under different schemes; the implementation method for ensuring that the scores corresponding to the same degree of autonomy and / or controllability are the same includes but is not limited to: the sum of the scores corresponding to the various functions and / or logics and / or modules and / or units required under different schemes of a chip with a given function is the same.

[0469] For example 1, the various functions and / or logics and / or modules and / or units required to determine the autonomy and / or controllability of a chip are determined to be module 1, module 2, module 3, and module 3, and the points allocated to each of the three are 25 points;

[0470] It was found that in module 1 of the chip, no non-self-developed IP cores were called and no non-self-developed IP cores were suspected of being called. The chip received a score of 25 points corresponding to module 1.

[0471] If it is found that non-self-developed IP core a is called in module 2 of the chip, the chip will obtain the score of the third ratio of the score corresponding to module 2 (assuming that the third ratio is 0.6 when a is domestically produced and 0 when it is not domestically produced, and in this example, a is domestically produced), that is, 25 points * 0.6 = 15 points;

[0472] If it is found that non-self-developed IP core b is called in module 3 of the chip, the chip will obtain a score equal to the third ratio of the score corresponding to module 3 (assuming that the third ratio is 0.4 when b is domestically produced and 0 when it is not domestically produced, and in this example, b is not domestically produced), that is, 25 points * 0 = 0 points;

[0473] If a chip is found to be missing module 4, the chip will not receive a score under module 4;

[0474] The total score of the chip is 25 points + 15 points + 0 points = 40 points.

[0475] For example 2, different IP cores, such as IP core c, IP core d, IP core e, etc., may have the same or different third ratios.

[0476] Optionally, the scores corresponding to the missing information portion of the chip to be determined and / or the missing functions and / or missing logic and / or missing modules and / or missing units in the obtained fourth information, and / or the calculation method for the scores corresponding to the non-self-developed IP cores called and / or suspected of being called in the obtained fourth information, include but are not limited to one or more of the following 19.1-19.3:

[0477] 19.1. For the required fourth information, assign scores corresponding to various functions and / or logics and / or modules and / or units therein, with the sum of the scores corresponding to the various functions and / or logics and / or modules and / or units being the score corresponding to the fourth information;

[0478] Optionally, the method of assigning scores includes but is not limited to: assigning scores based on the difficulty and / or criticality of each function and / or logic and / or module and / or unit, implementation and / or design;

[0479] 19.2. Among the various functions and / or logics and / or modules and / or units in the required fourth information, identify the portion of information on the chip to be determined that is missing from the acquired fourth information and / or ...

[0480] 19.3. Among the various functions and / or logics and / or modules and / or units in the required fourth information, find the functions and / or logics and / or modules and / or units corresponding to the non-self-developed IP core called and / or suspected to be called in the obtained fourth information. The score or the sum of the scores assigned to this part of the functions and / or logics and / or modules and / or units is the score corresponding to the non-self-developed IP core called and / or suspected to be called in the obtained fourth information.

[0481] Optionally, the method further includes: confirming that the acquired information is information of the target chip;

[0482] Optionally, the information includes but is not limited to one or more of the following: chip design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, physical chip and / or physical layout and / or physical layout wiring and / or physical layout wiring and / or physical layout wiring diagram, chip schematic, chip transistor-level netlist, chip gate-level netlist, chip RTL code, all or part of one or more of the first information, all or part of one or more of the second information; other information of the chip other than the first information and the second information;

[0483] Optionally, the confirmation method includes but is not limited to one or more of the following 20.1-20.4:

[0484] 20.1. The information obtained has been declared or identified as the information of the target chip;

[0485] 20.2. Determine the acquired physical chip and / or physical layout and / or physical layout and / or physical layout and wiring and / or physical layout and wiring diagram as the target chip information;

[0486] 20.3. Comparing and / or verifying the acquired information to confirm whether it is the information of the target chip, including but not limited to one or more of the following: comparing and / or verifying the acquired information one or more times with information that has been declared or identified as the target chip; if the comparison and / or verification passes, the acquired information is the information of the target chip; comparing and / or verifying the acquired information one or more times with the physical chip and / or its physical layout and / or physical layout and / or physical layout and wiring diagram; if the comparison and / or verification passes, the acquired information is the information of the target chip;

[0487] 20.4. Perform one or more comparisons and / or verifications on the acquired information with the information of the target chip that has been compared and / or verified. If the comparison and / or verification passes, the acquired information is the information of the target chip.

[0488] Optionally, the comparison and / or verification includes, but is not limited to, one or more of the following 21.1-21.16:

[0489] 21.1. Compare the chip design layout and / or design layout and / or design layout and wiring and / or design layout and wiring diagram with the physical chip and / or physical layout and / or physical layout and / or physical layout and wiring and / or physical layout and wiring diagram;

[0490] 21.2. Compare the chip design layout and / or design layout and / or design layout and wiring and / or design layout and wiring diagrams with the physical chip and / or physical layout and / or physical layout and wiring and / or physical layout and wiring diagrams, excluding the portions and / or regions and / or modules and / or units that have been confirmed to be non-in-house developed IP cores that are used or suspected to be used by the target chip. Then, compare the remaining chip design layout and / or design layout and / or design layout and wiring and / or design layout and wiring diagrams with the remaining physical chip and / or physical layout and / or physical layout and / or physical layout and wiring and / or physical layout and wiring diagrams;

[0491] 21.3. Perform LVS verification on the chip schematic, chip design layout, and / or design layout and / or design layout and / or design layout and / or design layout diagram;

[0492] 21.4. After removing the portions and / or regions and / or modules and / or units and / or design information of the chip schematics, chip design layouts and / or design layout and / or design layout and wiring and / or design layout and wiring diagrams that have been confirmed to be used or suspected to be used by the target chip and that are not self-developed IP cores, perform LVS verification on the remaining chip schematics, chip design layouts and / or design layouts and / or design layout and wiring and / or design layout and wiring diagrams;

[0493] 21.5. Perform LVS verification on the chip transistor-level netlist, the chip design layout, and / or the design layout and / or the design layout and / or the design layout and / or the design layout and wiring diagram;

[0494] 21.6. After removing the portions and / or regions and / or modules and / or units and / or design information of the non-self-developed IP cores that have been confirmed or suspected to be used by the target chip, perform LVS verification on the remaining chip transistor-level netlist and the remaining chip design layout and / or design layout and / or design layout and / or design layout;

[0495] 21.7. Perform LVS verification on the chip's gate-level netlist, the chip design layout, and / or the design layout and / or the design layout and routing, and / or the design layout and routing diagram;

[0496] 21.8. After removing the portion and / or region and / or module and / or unit and / or design information of the non-self-developed IP core that has been confirmed or suspected to be used by the target chip from the chip's gate-level netlist and the chip design layout and / or design layout and / or design layout and / or design layout and / or design layout diagram, perform LVS verification on the remaining chip's gate-level netlist and the remaining chip design layout and / or design layout and / or design layout and / or design layout diagram;

[0497] 21.9. After converting the chip's gate-level netlist to a chip transistor-level netlist, perform LVS verification on the converted chip transistor-level netlist and the chip design layout and / or design layout and / or design layout and / or design layout and / or design layout diagram;

[0498] 21.10. After converting the chip's gate-level netlist to a chip transistor-level netlist, compare the converted chip transistor-level netlist with the chip design layout and / or design layout and / or design layout and routing and / or design layout and routing diagram, excluding the portions and / or regions and / or modules and / or units and / or design information of non-self-developed IP cores that have been confirmed or suspected to be called by the target chip. Perform LVS verification on the remaining chip transistor-level netlist and the remaining chip design layout and / or design layout and / or design layout and routing and / or design layout and routing diagram;

[0499] 21.11. After removing the portions and / or regions and / or modules and / or units and / or design information of the chip's gate-level netlist and the chip design layout and / or design layout and / or design layout and routing and / or design layout and routing diagram that have been confirmed to be used or suspected to be used by the target chip and that are not self-developed IP cores, convert the remaining gate-level netlist into a transistor-level netlist and perform LVS verification on the converted transistor-level netlist and the remaining chip design layout and / or design layout and / or design layout and routing and / or design layout and routing diagram;

[0500] 21.12. Perform formal verification on one gate-level netlist of a chip and another gate-level netlist of the chip;

[0501] 21.13. After removing the portions and / or regions and / or modules and / or units and / or design information of non-self-developed IP cores that have been confirmed or suspected to be called by the target chip, perform formal verification on one gate-level netlist of the chip and another gate-level netlist of the chip;

[0502] 21.14. Perform formal verification on the chip RTL code and the chip gate-level netlist;

[0503] 21.15. After removing the portions and / or regions and / or modules and / or units and / or design information of the chip RTL code and the chip gate-level netlist that have been confirmed to be called or suspected to be called by the target chip and that are not self-developed IP cores, formal verification shall be performed on the remaining chip RTL code and the remaining chip gate-level netlist;

[0504] 21.16. When conducting formal verification, if there are differences in the functions and / or logic of auxiliary design and / or auxiliary testing between the two gate-level netlists being verified, and / or between the RTL code being verified and the gate-level netlist, the functions and / or logic c...

Claims

1. A method for detecting IP core calls, characterized in that: include: determining, based on the first information, whether an IP core is called and / or suspected of being called in a target chip and / or in the information of the target chip; in: The first information includes a chip schematic and a chip design layout; The determining, based on the first information, whether the IP core is called and / or whether the IP core is suspected of being called in the target chip and / or in the information of the target chip includes: Modifying the names of the modules in the schematic diagram and the chip design layout of the chip, and performing LVS verification using an LVS verification tool after the modification; if the LVS verification fails, determining that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core; and / or The first information includes a chip transistor-level netlist and a chip design layout; The determining, based on the first information, whether the IP core is called and / or whether the IP core is suspected of being called in the target chip and / or in the information of the target chip includes: Modifying the module names in the chip transistor-level netlist and the chip design layout, and performing LVS verification using an LVS verification tool after the modification; if the LVS verification fails, determining that the target chip and / or the target chip information has called an IP core and / or is suspected of calling an IP core; and / or The first information includes a gate-level netlist of the chip and / or a chip design layout; Determining, based on the first information, whether the IP core is called and / or whether the IP core is suspected of being called in the target chip and / or the information of the target chip includes one or more of the following: Modifying the names of modules in the gate-level netlist and the chip design layout of the chip, and performing LVS verification using an LVS verification tool after the modification; if the LVS verification fails, determining that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core; After converting the gate-level netlist of the chip into a chip transistor-level netlist, modifying the names of the modules in the converted chip transistor-level netlist and the chip design layout, and performing LVS verification using an LVS verification tool after the modification; if the LVS verification fails, it is determined that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core; Modifying the names of the modules in the gate-level netlist of the chip and the chip design layout, converting the modified gate-level netlist into a chip transistor-level netlist, and performing LVS verification on the converted chip transistor-level netlist and the modified chip design layout using an LVS verification tool. If the LVS verification fails, it is determined that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core. For two gate-level netlists of the chip, modify the names of the modules therein, and perform formal verification using a formal verification tool after the modification. If the formal verification fails, it is determined that the target chip and / or the information of the target chip calls the IP core and / or is suspected of calling the IP core; and / or The first information includes chip RTL code and / or chip gate-level netlist; Determining, based on the first information, whether the IP core is called and / or whether the IP core is suspected of being called in the target chip and / or the information of the target chip includes one or more of the following: If other level descriptions except register transfer level descriptions exist in the chip RTL code, it is determined that the target chip and / or the information of the target chip calls an IP core and / or is suspected of calling an IP core; For the chip RTL code and the gate-level netlist of the chip, the names of the modules therein are modified, and formal verification is performed using a formal verification tool after the modification. If the formal verification fails, it is determined that the target chip and / or the information of the target chip has called the IP core and / or is suspected of calling the IP core.

2. The method according to claim 1, characterized in that The target chip is a whole or part of a chip, and the types of the chip include but are not limited to one or more of the following: a packaged chip, an unpackaged die, a module in a die, and a unit in a die.

3. The method according to claim 1, characterized in that Also includes: Determine the target chip and / or information of the target chip according to the second information, and call and / or suspected call IP core; in: The second information includes a schematic diagram of the chip and a chip design layout; The step of determining the target chip and / or information of the target chip according to the second information, and calling and / or suspected calling an IP core, includes: Determine the target chip and / or the IP core called and / or suspected called by the target chip based on the chip schematic and chip design layout, after modifying the module names therein, performing LVS verification using an LVS verification tool, and the results and / or report of the failed LVS verification; and / or The second information includes a chip transistor-level netlist and a chip design layout; The step of determining the target chip and / or information of the target chip according to the second information, and calling and / or suspected calling an IP core, includes: Determine the target chip and / or the IP core called and / or suspected of being called by the target chip based on the chip transistor-level netlist and chip design layout, after modifying the module names therein, and the results and / or report of LVS verification performed using an LVS verification tool; and / or The second information includes a gate-level netlist of the chip and / or a chip design layout; Determining the target chip and / or information of the target chip based on the second information, and calling and / or suspected calling an IP core, includes one or more of the following: Determine the target chip and / or the IP core called and / or suspected of being called by the target chip based on the gate-level netlist and chip design layout of the chip, after modifying the names of the modules therein, and the results and / or report of the failed LVS verification performed using an LVS verification tool; Determine the target chip and / or the IP core called and / or suspected called by the target chip based on the converted chip transistor-level netlist and the chip design layout after converting the chip gate-level netlist to the chip transistor-level netlist, modifying the module names therein, performing LVS verification using an LVS verification tool, and the results and / or report of the failed LVS verification; According to the gate-level netlist of the chip and the chip design layout, after modifying the names of the modules therein, converting the modified gate-level netlist into a chip transistor-level netlist, performing LVS verification on the converted chip transistor-level netlist and the modified chip design layout using an LVS verification tool, and determining the target chip and / or the information call and / or suspected call of the IP core of the target chip according to the results and / or report of the failed LVS verification; Determine the target chip and / or the IP core called and / or suspected of being called by the information of the target chip based on the two gate-level netlists of the chip, after modifying the names of the modules therein, and the results and / or reports of the formal verification performed using a formal verification tool; and / or The second information includes chip RTL code and / or a gate-level netlist of the chip; Determining the target chip and / or information of the target chip based on the second information, and calling and / or suspected calling an IP core, includes one or more of the following: Determine the target chip and / or the IP core called and / or suspected of being called by the information of the target chip according to the portion of the chip RTL code where the descriptions at other levels except the register transfer level description are located; According to the chip RTL code and the chip's gate-level netlist, after modifying the module names therein, using a formal verification tool for formal verification, and the results and / or reports of failed formal verification, the target chip and / or the information call and / or suspected call of the IP core of the target chip are determined.

4. The method according to claim 3, characterized in that The first information is the same as or different from the second information.

5. The method according to claim 1, wherein The determination of whether the IP core is called and / or whether the IP core is suspected to be called in the target chip and / or the information of the target chip, and the determination of whether the IP core is called and / or suspected to be called by the target chip and / or the information of the target chip are divided into two steps or combined into one step; the determination of whether the IP core is called and / or suspected to be called by the target chip and / or the information of the target chip is also a method for determining whether the IP core is called and / or whether the IP core is suspected to be called in the target chip and / or the information of the target chip.

6. The method according to claim 1, wherein The first information includes a chip design layout, and / or a physical chip and / or a physical layout and / or a physical layout and / or a physical layout and / or a physical layout and wiring and / or a physical layout and wiring diagram; The determining, based on the first information, whether an IP core is called and / or whether an IP core is suspected of being called in the target chip and / or the information of the target chip includes, but is not limited to, one or more of the following: In the chip design layout, if there is a blank area and / or the area of ​​the blank area is greater than or equal to a first preset threshold and / or the blank area occupancy ratio is greater than or equal to a second preset threshold and / or the blank area is a regular geometric shape, it is determined that the IP core has been called and / or is suspected of being called in the target chip and / or in the information of the target chip; the blank area occupancy ratio refers to the ratio of the blank area to the design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, and the regular geometric shape includes but is not limited to one or more of the following: square, rectangle, rhombus, trapezoid, parallelogram, circle, ellipse, triangle, polygon, arc, and arc; Comparing the chip design layout with the corresponding physical chip and / or physical layout and / or physical layout and / or physical layout and / or physical layout and / or physical layout and / or physical layout and wiring diagram. If the comparison is inconsistent, it is determined that the IP core is called and / or suspected of being called in the target chip and / or the information of the target chip. The inconsistent comparison includes but is not limited to one or more of the following: inconsistent comparison of all layers and / or part of the layers and / or one layer; inconsistent comparison of the entire area and / or multiple local areas and / or one local area in all layers and / or part of the layers and / or one layer; If a first identifier exists in the chip design layout, and / or in the physical chip and / or the physical layout and / or the physical layout and / or the physical layout and / or the physical layout and wiring and / or the physical layout and wiring diagram, it is determined that the IP core is called and / or is suspected of being called in the target chip and / or in the information of the target chip; the first identifier is an identifier of a company other than the design company of the target chip, and / or an identifier representing a company other than the design company of the target chip; If a second identifier is present in the chip design layout, and / or the physical chip and / or the physical layout and / or the physical layout and / or the physical layout and / or the physical layout and wiring and / or the physical layout and wiring diagram, it is determined that an IP core is called and / or is suspected of being called in the target chip and / or in the information of the target chip; The second identifier is an identifier of a design company of the target chip and / or an identifier representing a design company of the target chip; Comparing the chip design layout with a layout and / or layout and / or layout-wiring and / or layout-wiring diagram in a first preset library; if a first region in the chip design layout is identical and / or similar to a second region in the layout and / or layout and / or layout and / or layout-wiring diagram in the first preset library, and / or the degree of similarity is greater than or equal to a third preset threshold, determining that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core; The first preset library does not contain the layout and / or layout and / or layout-wiring and / or layout-wiring diagram designed by the design company of the target chip; Comparing the chip design layout with a layout and / or layout and / or layout-wiring and / or layout-wiring diagram in a second preset library; if a third region in the chip design layout is identical and / or similar to a fourth region in the layout and / or layout and / or layout-wiring and / or layout-wiring diagram in the second preset library, and / or the degree of similarity is greater than or equal to a fourth preset threshold, determining that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core; The second preset library contains the layout and / or layout and / or layout-wiring and / or layout-wiring diagram designed by the design company of the target chip, and / or the layout and / or layout and / or layout-wiring and / or layout-wiring diagram IP core library of the design company of the target chip, and / or the IP core library of the design company of the target chip; Comparing the physical chip and / or the physical layout and / or the physical layout and / or the physical layout wiring and / or the physical layout wiring diagram with the layout and / or the layout and / or the layout wiring and / or the layout wiring diagram in the third preset library; if the fifth area of ​​the physical chip and / or the physical layout and / or the physical layout and / or the physical layout wiring and / or the physical layout wiring diagram is identical and / or similar to the sixth area of ​​the layout and / or the layout and / or the layout wiring and / or the layout wiring diagram in the third preset library, and / or the similarity is greater than or equal to a fifth preset threshold, it is determined that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core; the third preset library does not contain the layout and / or the layout and / or the layout wiring and / or the layout wiring diagram designed by the design company of the target chip; Comparing the physical chip and / or the physical layout and / or the physical layout and / or the physical layout and / or the physical layout and / or the physical layout and / or the physical layout diagram with the layout and / or the layout and / or the layout and / or the layout diagram in the fourth preset library; if the seventh region of the physical chip and / or the physical layout and / or the physical layout and / or the physical layout and / or the physical layout diagram is identical and / or similar to the eighth region of the layout and / or the layout and / or the layout and / or the layout diagram in the fourth preset library, and / or the similarity is greater than or equal to a sixth preset threshold, then determining that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core; The fourth preset library contains the layout and / or layout and / or layout wiring and / or layout wiring diagram designed by the design company of the target chip, and / or the layout and / or layout and / or layout wiring and / or layout wiring diagram IP core library of the design company of the target chip, and / or the IP core library of the design company of the target chip.

7. The method according to claim 1, characterized in that The first information includes a schematic diagram of the chip and / or a chip design layout; The determining, based on the first information, whether an IP core is called and / or whether an IP core is suspected of being called in the target chip and / or the information of the target chip includes, but is not limited to, one or more of the following: If a third identifier exists in the schematic diagram of the chip, it is determined that an IP core is called and / or suspected to be called in the target chip and / or in the information of the target chip; the third identifier is an identifier of a company other than the design company of the target chip, and / or an identifier representing a company other than the design company of the target chip; If a fourth identifier exists in the schematic diagram of the chip, it is determined that an IP core is called and / or suspected to be called in the target chip and / or in the information of the target chip; the fourth identifier is an identifier of a design company of the target chip and / or an identifier representing a design company of the target chip; Comparing the schematic diagram of the chip with the schematic diagrams in a fifth preset library, and if a ninth region in the schematic diagram of the chip is identical and / or similar to a tenth region in the schematic diagram in the fifth preset library and / or the degree of similarity is greater than or equal to a seventh preset threshold, determining that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core; The fifth preset library does not include the schematic diagram designed by the design company of the target chip; comparing the schematic diagram of the chip with the schematic diagrams in a sixth preset library, and if an eleventh region in the schematic diagram of the chip is identical and / or similar to a twelfth region in the schematic diagram in the sixth preset library and / or the degree of similarity is greater than or equal to an eighth preset threshold, determining that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core; The sixth preset library contains the schematics designed by the design company of the target chip, and / or the schematic IP core library of the design company of the target chip, and / or the IP core library of the design company of the target chip; An LVS verification tool is used to perform LVS verification on the schematic diagram and the chip design layout of the chip. If the LVS verification fails, it is determined that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core.

8. The method according to claim 1, characterized in that The first information includes a chip transistor-level netlist and / or a chip design layout; the transistor-level netlist includes but is not limited to one or more of the following: a netlist described as transistor-level, a transistor-level netlist corresponding to a chip schematic, a transistor-level netlist corresponding to a gate-level netlist of a final chip design, a transistor-level netlist corresponding to a chip design layout, and a transistor-level netlist in a mixed analog-digital chip composed of a transistor-level netlist corresponding to an analog module schematic and / or a transistor-level netlist corresponding to a gate-level netlist of a final digital module design; The determining, based on the first information, whether an IP core is called and / or whether an IP core is suspected of being called in the target chip and / or the information of the target chip includes, but is not limited to, one or more of the following: If a fifth identifier exists in the chip transistor-level netlist, it is determined that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core; the fifth identifier is an identifier of a company other than the design company of the target chip, and / or an identifier representing a company other than the design company of the target chip; If a sixth identifier exists in the chip transistor-level netlist, it is determined that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core; the sixth identifier is an identifier of a design company of the target chip and / or an identifier representing a design company of the target chip; comparing the transistor-level netlist of the chip with the transistor-level netlist in a seventh preset library; if a first portion of the transistor-level netlist of the chip is identical and / or similar to a second portion of the transistor-level netlist in the seventh preset library and / or the degree of similarity is greater than or equal to a ninth preset threshold, determining that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core; The seventh preset library does not include a transistor-level netlist designed by the design company of the target chip; comparing the transistor-level netlist of the chip with the transistor-level netlist in an eighth preset library; if a third portion of the transistor-level netlist of the chip is identical and / or similar to a fourth portion of the transistor-level netlist in the eighth preset library and / or the degree of similarity is greater than or equal to a tenth preset threshold, determining that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core; The eighth preset library includes a transistor-level netlist designed by the design company of the target chip, and / or a transistor-level netlist IP core library of the design company of the target chip, and / or an IP core library of the design company of the target chip; An LVS verification tool is used to perform LVS verification on the chip transistor-level netlist and the chip design layout. If the LVS verification fails, it is determined that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core.

9. The method according to claim 1, characterized in that The first information includes a gate-level netlist of the chip, and / or a chip design layout; the gate-level netlist of the chip includes but is not limited to one or more of the following: a gate-level netlist of a completed final design, a gate-level netlist corresponding to the chip design layout, a gate-level netlist synthesized from the chip register transfer level RTL code, a front-end gate-level netlist, a back-end gate-level netlist, and a gate-level netlist during the chip design process; the front-end gate-level netlist and / or the back-end gate-level netlist and / or the gate-level netlist during the chip design process include but are not limited to one or more gate-level netlists; The determining, based on the first information, whether an IP core is called and / or whether an IP core is suspected of being called in the target chip and / or the information of the target chip includes, but is not limited to, one or more of the following: If a seventh identifier exists in the gate-level netlist of the chip, it is determined that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core; the seventh identifier is an identifier of a company other than the design company of the target chip, and / or an identifier representing a company other than the design company of the target chip; If an eighth identifier exists in the gate-level netlist of the chip, it is determined that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core; the eighth identifier is an identifier of a design company of the target chip and / or an identifier representing a design company of the target chip; Comparing the gate-level netlist of the chip with the gate-level netlist in a ninth preset library, if a fifth portion of the gate-level netlist of the chip is identical and / or similar to a sixth portion of the gate-level netlist in the ninth preset library and / or the degree of similarity is greater than or equal to an eleventh preset threshold, determining that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core; and the ninth preset library does not contain a gate-level netlist designed by the design company of the target chip; Comparing the gate-level netlist of the chip with the gate-level netlist in a tenth preset library, if the seventh portion of the gate-level netlist of the chip is identical and / or similar to the eighth portion of the gate-level netlist in the tenth preset library and / or the degree of similarity is greater than or equal to a twelfth preset threshold, determining that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core; The tenth preset library contains a gate-level netlist designed by the design company of the target chip, and / or a gate-level netlist IP core library of the design company of the target chip, and / or an IP core library of the design company of the target chip; Performing LVS verification on the gate-level netlist of the chip and the chip design layout using an LVS verification tool; if the LVS verification fails, determining that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core; After converting the gate-level netlist of the chip into a chip transistor-level netlist, performing LVS verification on the converted chip transistor-level netlist and the chip design layout using an LVS verification tool; if the LVS verification fails, it is determined that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core; Performing formal verification on the two gate-level netlists of the chip using a formal verification tool; if the formal verification fails, determining that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core; Among them, when carrying out formal verification, if there are differences in the functions and / or logic of auxiliary design and / or auxiliary testing between two gate-level netlists, the functions and / or logic corresponding to the differences are not verified or verified; wherein, the method of not verifying the functions and / or logic corresponding to the differences includes but is not limited to: when setting constants, prohibiting the functions and / or logic and / or pins and / or pins of auxiliary design and / or auxiliary testing, and / or setting the functions and / or logic and / or pins and / or pins of auxiliary design and / or auxiliary testing to be invalid; the functions and / or logic and / or pins and / or pins of the auxiliary design and / or auxiliary testing include but are not limited to one or more of the following: scanning the SCAN chain and / or the enable pins and / or enable pins corresponding to the SCAN chain, the JTAG chain and / or the enable pins and / or enable pins corresponding to the JTAG chain, and the pins and / or pins corresponding to the chip testability design and / or the testability design.

10. The method according to claim 1, characterized in that The first information includes chip RTL code, and / or a gate-level netlist of the chip; the gate-level netlist of the chip includes but is not limited to one or more of the following: a gate-level netlist of a completed final design, a gate-level netlist corresponding to a chip design layout, a gate-level netlist synthesized from chip RTL code, a front-end gate-level netlist, a back-end gate-level netlist, and a gate-level netlist during the chip design process; the front-end gate-level netlist and / or the back-end gate-level netlist and / or the gate-level netlist during the chip design process include but are not limited to one or more gate-level netlists; The determining, based on the first information, whether an IP core is called and / or whether an IP core is suspected of being called in the target chip and / or the information of the target chip includes, but is not limited to, one or more of the following: If a ninth identifier exists in the chip RTL code, it is determined that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core; the ninth identifier is an identifier of a company other than the design company of the target chip, and / or an identifier representing a company other than the design company of the target chip; If a tenth identifier exists in the chip RTL code, it is determined that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core; the tenth identifier is an identifier of a design company of the target chip and / or an identifier representing a design company of the target chip; The other level descriptions except the register transfer level description include but are not limited to gate level descriptions; wherein, the method for checking whether there are other level descriptions except the register transfer level description in the chip RTL code includes but is not limited to one or more of the following: keyword retrieval of the chip RTL code; comparing the chip RTL code with the gate-level netlist of the chip, if the ninth part of the chip RTL code is the same and / or similar to the tenth part of the gate-level netlist of the chip and / or the similarity is greater than or equal to the thirteenth preset threshold, then it is determined that there are other level descriptions except the register transfer level description in the chip RTL code; wherein, the method for keyword retrieval of the chip RTL code includes but is not limited to one or more of the following: using one or more keywords representing other level descriptions except the register transfer level description to search the RTL code, if it is found that one or more of the keywords are present in the RTL code and / or one of the keywords are present in the RTL code. If the total number of one or more keywords is greater than or equal to a fourteenth preset threshold and / or the proportion of the total number of one or more keywords in the RTL code to the total number of RTL code words is greater than or equal to a fifteenth preset threshold, it is determined that other levels of description except the register transfer level description exist in the chip RTL code; one or more keywords representing the register transfer level description are used to search the RTL code, and if it is found that various keywords do not exist in the RTL code and / or one or more keywords do not exist in the RTL code, it is determined that other levels of description except the register transfer level description exist in the chip RTL code; the types of keywords include but are not limited to one or more of the following: code at the representation description level, vocabulary and / or phrases at the representation description level, script at the representation description level, program at the representation description level, RTL code at the representation description level, netlist at the representation description level, wherein the netlist includes but is not limited to a gate-level netlist; Comparing the chip RTL code with the RTL code in the eleventh preset library, if an eleventh portion of the chip RTL code is identical and / or similar to a twelfth portion of the RTL code in the eleventh preset library and / or the similarity is greater than or equal to a sixteenth preset threshold, determining that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core; the eleventh preset library does not contain the RTL code designed by the design company of the target chip; Comparing the chip RTL code with the RTL code in the twelfth preset library, if the thirteenth part of the chip RTL code is identical and / or similar to the fourteenth part of the RTL code in the twelfth preset library and / or the similarity is greater than or equal to the seventeenth preset threshold, then determining that the target chip and / or the information of the target chip has called the IP core and / or is suspected of calling the IP core; the RTL code designed by the design company of the target chip in the twelfth preset library, and / or the RTL code IP core library of the design company of the target chip, and / or the IP core library of the design company of the target chip; Performing formal verification on the chip RTL code and the gate-level netlist of the chip using a formal verification tool; if the formal verification fails, determining that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core; Among them, when carrying out formal verification, if there are differences between the RTL code and the gate-level netlist in the functions and / or logic of auxiliary design and / or auxiliary testing, the functions and / or logic corresponding to the differences are verified or not verified; wherein, the method of not verifying the functions and / or logic corresponding to the differences includes but is not limited to: when setting constants, prohibiting the functions and / or logic and / or pins and / or pins of auxiliary design and / or auxiliary testing, and / or setting the functions and / or logic and / or pins and / or pins of auxiliary design and / or auxiliary testing to be invalid; the functions and / or logic and / or pins and / or pins of the auxiliary design and / or auxiliary testing include but are not limited to one or more of the following: scanning the SCAN chain and / or the enable pin and / or enable pin corresponding to the SCAN chain, the JTAG chain and / or the enable pin and / or enable pin corresponding to the JTAG chain, the chip testability design and / or the pins and / or pins corresponding to the testability design.

11. The method according to claim 3, characterized in that The second information includes a chip design layout, and / or a physical chip and / or a physical layout and / or a physical layout and / or a physical layout and / or a physical layout and wiring and / or a physical layout and wiring diagram; The determining, based on the second information, of the target chip and / or the information of the target chip, and the calling and / or suspected calling of the IP core include, but are not limited to, one or more of the following: Determine a blank area in the chip design layout, and / or a blank area with an area greater than or equal to an eighteenth preset threshold, and / or a blank area with an occupancy ratio greater than or equal to a nineteenth preset threshold, and / or a blank area of ​​a regular geometric figure, and determine the blank area, and / or the design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram corresponding to the blank area, and / or the module and / or design information corresponding to the blank area as the target chip and / or the information call and / or suspected call of the IP core of the target chip; the occupancy ratio refers to the ratio of the blank area to the design layout and / or design layout and / or design layout wiring and / or design layout wiring diagram, the regular geometric figure includes but is not limited to one or more of the following: square, rectangle, rhombus, trapezoid, parallelogram, circle, ellipse, triangle, polygon, arc, and arc; the blank area includes but is not limited to one or more areas; Determine inconsistencies when comparing a chip design layout with a corresponding physical chip and / or physical layout and / or physical layout and / or physical layout and / or physical layout and / or physical layout and / or physical layout and / or physical layout and / or physical layout and / or physical layout and / or physical layout and / or physical layout and / or physical layout and / or physical layout and / or physical layout and / or physical layout and / or physical layout and / or physical layout and / or physical layout and / or physical layout and / or physical layout and / or physical layout and / or physical layout and / or physical layout and / or physical layout and / or physical layout and / or physical layout and / or the inconsistency, and / or determine the inconsistencies, and / or the design layout and / or the design layout and / or the design layout and / or the design layout and / or the design layout and / or the corresponding inconsistencies, and / or the module and / or design information corresponding to the inconsistencies as the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; wherein the inconsistencies include but are not limited to one or more of the following situations: inconsistencies in comparison of all layers and / or part of the layers and / or one layer; inconsistencies in comparison of the entire area and / or multiple local areas and / or one local area in all layers and / or part of the layers and / or one layer; wherein the inconsistencies include but are not limited to one or more layouts and / or ... Determining that the position of the eleventh identifier in the chip design layout, and / or the physical chip and / or the physical layout and / or the physical layout and / or the physical layout and / or the physical layout and wiring and / or the physical layout and wiring diagram and / or the area where the eleventh identifier is located and / or an area whose distance from the eleventh identifier is less than or equal to a twentieth preset threshold, and / or the module and / or design information corresponding to the position and / or the area and / or the eleventh identifier is the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; After determining the position of the eleventh identifier in the chip design layout, and / or the physical chip and / or the physical layout and / or the physical layout and / or the physical layout and / or the physical layout and / or the physical layout and wiring and / or the physical layout and wiring diagram, and / or the area where the eleventh identifier is located and / or the area whose distance from the eleventh identifier is less than or equal to a twenty-first preset threshold, and / or the module and / or design information corresponding to the position and / or area and / or the eleventh identifier, one or more layers of the position and / or area, and / or the module and / or design information corresponding to the one or more layers of the position and / or area are determined as the target chip and / or the information call and / or suspected call of the IP core of the target chip; wherein the twenty-first preset threshold is the same as or different from the twenty-first preset threshold; The eleventh identifier is an identifier of a company other than the design company of the target chip, and / or an identifier representing a company other than the design company of the target chip; Determine that the position of the twelfth identifier in the chip design layout, and / or the physical chip and / or the physical layout and / or the physical layout and / or the physical layout and / or the physical layout and wiring and / or the physical layout and wiring diagram is located, and / or the area where the twelfth identifier is located, and / or the area whose distance from the twelfth identifier is less than or equal to a twenty-second preset threshold, and / or the module and / or design information corresponding to the position and / or the area and / or the twelfth identifier is the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; After determining the position of the twelfth identifier in the chip design layout, and / or the physical chip and / or the physical layout and / or the physical layout and / or the physical layout and / or the physical layout and / or the physical layout and wiring and / or the physical layout and wiring diagram, and / or the area where the twelfth identifier is located and / or the area whose distance from the twelfth identifier is less than or equal to the twenty-third preset threshold, and / or the module and / or design information corresponding to the position and / or area and / or the twelfth identifier, one or more layers of the position and / or area, and / or the modules and / or design information corresponding to the one or more layers of the position and / or area are determined as the target chip and / or the information call and / or suspected call of the IP core of the target chip; wherein the twenty-third preset threshold is the same as or different from the twenty-second preset threshold; The twelfth identifier is an identifier of a design company of the target chip and / or an identifier representing a design company of the target chip; Determine the fourteenth region in the chip design layout, and / or the module and / or design information corresponding to the fourteenth region, which is identical and / or similar and / or has a similarity greater than or equal to a twenty-fourth preset threshold to the thirteenth region of the layout and / or layout and / or layout-wiring and / or layout-wiring diagram in the thirteenth preset library, as the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; the thirteenth preset library does not contain the layout and / or layout and / or layout and / or layout-wiring and / or layout-wiring diagram designed by the design company of the target chip; Determine the sixteenth area in the chip design layout, and / or the module and / or design information corresponding to the sixteenth area, which is identical and / or similar and / or has a similarity greater than or equal to the twenty-fifth preset threshold to the fifteenth area of ​​the layout and / or layout and / or layout and wiring and / or layout wiring diagram in the fourteenth preset library, as the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; the layout and / or layout and / or layout and wiring and / or layout wiring diagram designed by the design company of the target chip in the fourteenth preset library, and / or the layout and / or layout and / or layout and wiring and / or layout wiring diagram IP core library of the design company of the target chip, and / or the IP core library of the design company of the target chip; Determining the eighteenth region in the physical chip and / or the physical layout and / or the physical layout and / or the physical layout and / or the physical layout and / or the physical layout and / or the IP core called and / or suspected of being called by the information of the target chip, which is identical and / or similar and / or has a similarity greater than or equal to the seventeenth region of the layout and / or the layout and / or the layout and wiring and / or the layout and wiring diagram in the fifteenth preset library, and / or the module and / or design information corresponding to the eighteenth region as the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; the fifteenth preset library does not contain the layout and / or the layout and / or the layout and wiring and / or the layout and wiring diagram designed by the design company of the target chip; Determine the twentieth region in the physical chip and / or the physical layout and / or the physical layout and / or the physical layout and / or the physical layout and / or the physical layout and / or the module and / or the design information corresponding to the twentieth region, which is identical and / or similar and / or has a similarity greater than or equal to the twenty-seventh preset threshold to the nineteenth region of the layout and / or the layout and / or the layout and wiring and / or the layout and wiring diagram in the sixteenth preset library, as the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; the layout and / or the layout and / or the layout and wiring and / or the layout and wiring diagram designed by the design company of the target chip in the sixteenth preset library, and / or the IP core library of the layout and / or the layout and / or the layout and / or the layout and wiring and / or the layout and wiring diagram of the design company of the target chip, and / or the IP core library of the design company of the target chip; The physical chip and / or physical layout and / or physical layout and / or physical layout wiring and / or physical layout wiring diagram of the target chip and / or the IP core called and / or suspected by the information of the target chip, and / or the position and / or area, and / or the module and / or design information corresponding to the position and / or area, the corresponding chip design layout and / or the module and / or design information corresponding to the position and / or area are determined as the target chip and / or the IP core called and / or suspected by the information of the target chip.

12. The method according to claim 3, characterized in that The second information includes a schematic diagram of the chip and / or a chip design layout; The determining, based on the second information, of the target chip and / or the information of the target chip, and the calling and / or suspected calling of the IP core include, but are not limited to, one or more of the following: Determining that the position of the thirteenth identifier in the schematic diagram of the chip and / or the area where the thirteenth identifier is located and / or an area whose distance from the thirteenth identifier is less than or equal to the twenty-eighth preset threshold, and / or the module and / or design information corresponding to the position and / or area and / or the thirteenth identifier is the target chip and / or an IP core called and / or suspected of being called by the information of the target chip; The thirteenth logo is a logo of a company other than the design company of the target chip, and / or a logo representing a company other than the design company of the target chip; Determining that the position of the fourteenth marker in the schematic diagram of the chip and / or the area where the fourteenth marker is located and / or an area whose distance from the fourteenth marker is less than or equal to the twenty-ninth preset threshold, and / or the module and / or design information corresponding to the position and / or area and / or the fourteenth marker is the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; The fourteenth identifier is the identifier of the design company of the target chip and / or an identifier representing the design company of the target chip; Determining the 22nd region in the schematic diagram of the chip, and / or the module and / or design information corresponding to the 22nd region, which is identical and / or similar to the 21st region of the schematic diagram in the 17th preset library and / or whose similarity is greater than or equal to a 30th preset threshold, as the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; The seventeenth preset library does not include the schematic diagram designed by the design company of the target chip; Determine the 24th region in the schematic diagram of the chip, and / or the module and / or design information corresponding to the 24th region, which is identical and / or similar to the 23rd region of the schematic diagram in the 18th preset library and / or whose similarity is greater than or equal to the 31st preset threshold, as the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; The eighteenth preset library contains schematics designed by the design company of the target chip, and / or a schematic IP core library of the design company of the target chip, and / or an IP core library of the design company of the target chip; Determine the target chip and / or the IP core that is called by information and / or suspected of being called by the target chip based on the schematic diagram and chip design layout of the chip, the results and / or reports of the LVS verification performed using the LVS verification tool, and the results of the LVS verification that failed; the determination method includes but is not limited to one or more of the following: determine that the schematic diagram area that failed the verification, and / or the chip design layout area that failed, and / or the module and / or design information corresponding to the failed area are the target chip and / or the IP core that is called by information and / or suspected of being called by the target chip; determine that the devices and / or connection relationships in the schematic diagram found in the verification, the differences between the devices and / or connection relationships in the chip design layout, and / or the schematic diagram area, and / or the chip design layout area, and / or the module, and / or the unit, and / or the design information corresponding to the differences are the target chip and / or the IP core that is called by information and / or suspected of being called by the target chip; The determination method includes but is not limited to one or more of the following: determining that the schematic area that failed the verification, and / or the chip design layout area that failed, and / or the module and / or design information corresponding to the failed area are the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; determining that the devices and / or connection relationships in the schematic found in the verification, the differences between the devices and / or connection relationships in the chip design layout, and / or the schematic area, and / or chip design layout area, and / or module, and / or unit, and / or design information corresponding to the differences are the target chip and / or the IP core called and / or suspected of being called by the information of the target chip.

13. The method according to claim 3, characterized in that The second information includes a chip transistor-level netlist and / or a chip design layout; the transistor-level netlist includes but is not limited to one or more of the following: a netlist described as transistor-level, a transistor-level netlist corresponding to a chip schematic, a transistor-level netlist corresponding to a gate-level netlist of a final chip design, a transistor-level netlist corresponding to a chip design layout, and a transistor-level netlist in a mixed analog-digital chip composed of a transistor-level netlist corresponding to an analog module schematic and / or a transistor-level netlist corresponding to a gate-level netlist of a final digital module design; The determining, based on the second information, of the target chip and / or the information of the target chip, and the calling and / or suspected calling of the IP core include, but are not limited to, one or more of the following: Determine in a chip transistor-level netlist the position where the fifteenth identifier is located and / or the portion where the fifteenth identifier is located and / or the portion whose code length between the fifteenth identifier and the fifteenth identifier is less than or equal to a thirty-second preset threshold and / or the portion whose code length between the fifteenth identifier and the fifteenth identifier accounts for less than or equal to a first proportion threshold in the chip transistor-level netlist, and / or the module and / or design information corresponding to the position and / or portion and / or the fifteenth identifier is the target chip and / or an IP core called and / or suspected of being called by the information of the target chip; The fifteenth mark is a mark of a company other than the design company of the target chip, and / or a mark representing a company other than the design company of the target chip; Determine in a chip transistor-level netlist that the position at which the sixteenth identifier is located and / or the portion at which the sixteenth identifier is located and / or the portion between the sixteenth identifier and the portion whose code length is less than or equal to a thirty-third preset threshold and / or the portion whose code length between the sixteenth identifier and the portion in the chip transistor-level netlist is less than or equal to a second proportion threshold, and / or the module and / or design information corresponding to the position and / or portion and / or the sixteenth identifier is the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; the sixteenth identifier is the identifier of the design company of the target chip and / or the identifier representing the design company of the target chip; Determining the sixteenth part of the transistor-level netlist of the chip, which is identical and / or similar and / or has a similarity greater than or equal to a thirty-fourth preset threshold, and / or the module and / or design information corresponding to the sixteenth part, as the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; The nineteenth preset library does not include a transistor-level netlist designed by the design company of the target chip; Determining the eighteenth part of the transistor-level netlist of the chip, which is identical and / or similar and / or has a similarity greater than or equal to a thirty-fifth preset threshold, and / or the module and / or design information corresponding to the eighteenth part, as the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; The twentieth preset library includes a transistor-level netlist designed by the design company of the target chip, and / or a transistor-level netlist IP core library of the design company of the target chip, and / or an IP core library of the design company of the target chip; Determine the target chip and / or the IP core called by information and / or suspected of being called by information of the target chip based on the chip transistor-level netlist and chip design layout, and the results and / or reports of LVS verification performed using an LVS verification tool, or the results of LVS verification that failed; the determination method includes but is not limited to one or more of the following: determine that the module and / or design information corresponding to the transistor-level netlist portion that failed the verification, and / or the chip design layout area that failed, and / or the failed portion and / or the failed area is the target chip and / or the IP core called by information and / or suspected of being called by information of the target chip; Determining that the devices and / or connection relationships in the transistor-level netlist discovered during the verification, the differences between the devices and / or connection relationships in the chip design layout, and / or the transistor-level netlist portions, and / or chip design layout regions, and / or modules, and / or units, and / or design information corresponding to the differences are the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; The determination method includes but is not limited to one or more of the following: determining that the transistor-level netlist portion that failed the verification, and / or the chip design layout area that failed, and / or the module and / or design information corresponding to the failed portion and / or the failed area are the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; Determine that the devices and / or connection relationships in the transistor-level netlist discovered during the verification, the differences between the devices and / or connection relationships in the chip design layout, and / or the transistor-level netlist parts corresponding to the differences, and / or the chip design layout areas, and / or modules, and / or units, and / or design information are the target chip and / or the IP core called and / or suspected of being called by the information of the target chip.

14. The method according to claim 3, characterized in that The second information includes a gate-level netlist of the chip and / or a chip design layout; the gate-level netlist of the chip includes but is not limited to one or more of the following: a gate-level netlist of a completed final design, a gate-level netlist corresponding to the chip design layout, a gate-level netlist synthesized from the chip RTL code, a front-end gate-level netlist, a back-end gate-level netlist, and a gate-level netlist during the chip design process; the front-end gate-level netlist and / or the back-end gate-level netlist and / or the gate-level netlist during the chip design process include but are not limited to one or more gate-level netlists; The determining, based on the second information, of the target chip and / or the information of the target chip, and the calling and / or suspected calling of the IP core include, but are not limited to, one or more of the following: Determine in the gate-level netlist of the chip that the position at which the seventeenth identifier is located and / or the portion at which the seventeenth identifier is located and / or the portion whose code length between the seventeenth identifier and the seventeenth identifier is less than or equal to the thirty-sixth preset threshold and / or the portion whose code length between the seventeenth identifier and the seventeenth identifier accounts for less than or equal to the third proportion threshold in the gate-level netlist of the chip, and / or the module and / or design information corresponding to the position and / or portion and / or the seventeenth identifier is the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; The seventeenth logo is a logo of a company other than the design company of the target chip, and / or a logo representing a company other than the design company of the target chip; Determine in the gate-level netlist of the chip that the position at which the eighteenth identifier is located and / or the portion at which the eighteenth identifier is located and / or the portion whose code length between the eighteenth identifier and the eighteenth identifier is less than or equal to the thirty-seventh preset threshold and / or the portion whose code length between the eighteenth identifier and the eighteenth identifier accounts for less than or equal to the fourth proportion threshold in the gate-level netlist of the chip, and / or the module and / or design information corresponding to the position and / or portion and / or the eighteenth identifier is the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; The eighteenth identifier is the identifier of the design company of the target chip and / or an identifier representing the design company of the target chip; Determine the twentieth part in the gate-level netlist of the chip, and / or the module and / or design information corresponding to the twentieth part, which is identical and / or similar to the nineteenth part of the gate-level netlist in the twenty-first preset library and / or whose similarity is greater than or equal to a thirty-eighth preset threshold, as the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; The twenty-first preset library does not include a gate-level netlist designed by the design company of the target chip; Determine the 22nd part in the gate-level netlist of the chip, and / or the module and / or design information corresponding to the 22nd part, which is identical and / or similar to the 21st part of the gate-level netlist in the 22nd preset library and / or whose similarity is greater than or equal to a 39th preset threshold, as the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; The twenty-second preset library includes a gate-level netlist designed by the design company of the target chip, and / or a gate-level netlist IP core library of the design company of the target chip, and / or an IP core library of the design company of the target chip; Determine the target chip and / or the IP core that is called by information and / or suspected to be called by the target chip based on the gate-level netlist and chip design layout of the chip, the results and / or reports of the LVS verification performed using an LVS verification tool, and the results of the LVS verification that failed. The determination method includes but is not limited to one or more of the following: determine that the gate-level netlist portion that failed the verification, and / or the chip design layout area that failed, and / or the module and / or design information corresponding to the failed portion and / or the failed area are the target chip and / or the IP core that is called by information and / or suspected to be called by the target chip; determine that the devices and / or connection relationships in the gate-level netlist found in the verification, the differences between the devices and / or connection relationships in the chip design layout, and / or the gate-level netlist portion, and / or the chip design layout area, and / or the module, and / or the unit, and / or the design information corresponding to the differences are the target chip and / or the IP core that is called by information and / or suspected to be called by the target chip; The determination method includes but is not limited to one or more of the following: determining that the gate-level netlist portion that failed the verification, and / or the chip design layout area that failed, and / or the module and / or design information corresponding to the failed portion and / or the failed area are the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; determining that the devices and / or connection relationships in the gate-level netlist found in the verification, the differences between the devices and / or connection relationships in the chip design layout, and / or the gate-level netlist portion, and / or the chip design layout area, and / or the module, and / or the unit, and / or the design information corresponding to the differences are the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; After the gate-level netlist of the chip is converted into the chip transistor-level netlist, the converted chip transistor-level netlist and the chip design layout, the results and / or reports of the LVS verification performed using the LVS verification tool, and the LVS verification that failed, are used to determine the target chip and / or the IP core that is called by the information of the target chip and / or suspected of being called; the determination method includes but is not limited to one or more of the following: determining that the transistor-level netlist portion that failed the verification, and / or the gate-level netlist portion corresponding to the failed transistor-level netlist portion, and / or the failed chip design layout area, and / or the module and / or design information corresponding to the failed portion and / or failed area are the target chip and / or the IP core that is called by the information of the target chip and / or suspected of being called; Determining that the devices and / or connection relationships in the transistor-level netlist discovered during the verification, the differences between the devices and / or connection relationships in the chip design layout, and / or the transistor-level netlist portion corresponding to the difference, and / or the gate-level netlist portion corresponding to the corresponding transistor-level netlist portion, and / or the corresponding chip design layout area, and / or module, and / or unit, and / or design information are the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; The determination method includes but is not limited to one or more of the following: determining that the transistor-level netlist portion that failed the verification, and / or the gate-level netlist portion corresponding to the failed transistor-level netlist portion, and / or the failed chip design layout area, and / or the module and / or design information corresponding to the failed portion and / or failed area are the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; Determining that the devices and / or connection relationships in the transistor-level netlist discovered during the verification, the differences between the devices and / or connection relationships in the chip design layout, and / or the transistor-level netlist portion corresponding to the difference, and / or the gate-level netlist portion corresponding to the corresponding transistor-level netlist portion, and / or the corresponding chip design layout area, and / or module, and / or unit, and / or design information are the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; The determination method includes but is not limited to one or more of the following: determining that the transistor-level netlist portion that failed the verification, and / or the gate-level netlist portion corresponding to the failed transistor-level netlist portion, and / or the failed chip design layout area, and / or the module and / or design information corresponding to the failed portion and / or failed area are the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; Determining that the devices and / or connection relationships in the transistor-level netlist discovered during the verification, the differences between the devices and / or connection relationships in the chip design layout, and / or the transistor-level netlist portion corresponding to the difference, and / or the gate-level netlist portion corresponding to the corresponding transistor-level netlist portion, and / or the corresponding chip design layout area, and / or module, and / or unit, and / or design information are the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; Determine the target chip and / or the IP core that is called by information and / or suspected of being called by information of the target chip based on the two gate-level netlists of the chip and the results and / or reports of the formal verification performed using a formal verification tool; the determination method includes but is not limited to one or more of the following: determine the gate-level netlist portion that failed the verification, and / or the module and / or design information corresponding to the failed portion as the target chip and / or the IP core that is called by information and / or suspected of being called by information of the target chip; determine the gate-level netlist portion corresponding to the mismatch point found in the verification, and / or the module and / or design information corresponding to the portion and / or mismatch point; The design information is for the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; determining the inequivalent parts found in the verification, and / or the gate-level netlist parts corresponding to the inequivalent parts, and / or the modules corresponding to the inequivalent parts and / or the IP core called and / or suspected of being called by the information of the target chip; determining the differences in logic and / or function between two gate-level netlists found in the verification, and / or the gate-level netlist parts corresponding to the differences, and / or the modules and / or the IP core called and / or suspected of being called by the information of the target chip; The determination method includes but is not limited to one or more of the following: determining that the gate-level netlist portion that failed the verification, and / or the module and / or design information corresponding to the failed portion are the target chip and / or the IP core called by the information of the target chip and / or suspected of being called; determining that the gate-level netlist portion corresponding to the mismatch point found in the verification, and / or the module and / or design information corresponding to the portion and / or the mismatch point are the target chip and / or the IP core called by the information of the target chip and / or suspected of being called; determining that the inequivalent portion found in the verification, and / or the gate-level netlist portion corresponding to the inequivalent portion, and / or the module and / or design information corresponding to the inequivalent portion are the target chip and / or the IP core called by the information of the target chip and / or suspected of being called; determining the difference in logic and / or function between two gate-level netlists found in the verification, and / or the gate-level netlist portion corresponding to the difference, and / or the module and / or design information corresponding to the target chip and / or the IP core called by the information of the target chip and / or suspected of being called; Among them, when carrying out formal verification, if there are differences in the functions and / or logic of auxiliary design and / or auxiliary testing between two gate-level netlists, the functions and / or logic corresponding to the differences are not verified or verified; wherein, the method of not verifying the functions and / or logic corresponding to the differences includes but is not limited to: when setting constants, prohibiting the functions and / or logic and / or pins and / or pins of auxiliary design and / or auxiliary testing, and / or setting the functions and / or logic and / or pins and / or pins of auxiliary design and / or auxiliary testing to be invalid; the functions and / or logic and / or pins and / or pins of the auxiliary design and / or auxiliary testing include but are not limited to one or more of the following: scanning the SCAN chain and / or the enable pins and / or enable pins corresponding to the SCAN chain, the JTAG chain and / or the enable pins and / or enable pins corresponding to the JTAG chain, and the pins and / or pins corresponding to the chip testability design and / or the testability design.

15. The method according to claim 3, characterized in that The second information includes chip RTL code, and / or a gate-level netlist of the chip; the gate-level netlist of the chip includes but is not limited to one or more of the following: a gate-level netlist of a completed final design, a gate-level netlist corresponding to a chip design layout, a gate-level netlist synthesized from chip RTL code, a front-end gate-level netlist, a back-end gate-level netlist, and a gate-level netlist during the chip design process; the front-end gate-level netlist and / or the back-end gate-level netlist and / or the gate-level netlist during the chip design process include but are not limited to one or more gate-level netlists; The determining, based on the second information, of the target chip and / or the information of the target chip, and the calling and / or suspected calling of the IP core include, but are not limited to, one or more of the following: Determine in the chip RTL code the position where the nineteenth identifier is located and / or the portion where the nineteenth identifier is located and / or the portion where the code length between the nineteenth identifier and the nineteenth identifier is less than or equal to the fortieth preset threshold and / or the portion where the code length between the nineteenth identifier and the nineteenth identifier accounts for less than or equal to the fifth proportion threshold in the chip RTL code, and / or the module and / or design information corresponding to the position and / or portion and / or the nineteenth identifier is the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; the nineteenth identifier is an identifier of a company other than the design company of the target chip, and / or an identifier representing a company other than the design company of the target chip; Determine that the position of the 20th identifier in the chip RTL code and / or the portion where the 20th identifier is located and / or the portion between the 20th identifier and the portion whose code length is less than or equal to a 41st preset threshold and / or the portion whose code length between the 20th identifier and the portion in the chip RTL code is less than or equal to a 6th proportion threshold, and / or the module and / or design information corresponding to the position and / or portion and / or the 20th identifier is the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; The twentieth identifier is an identifier of a design company of the target chip and / or an identifier representing a design company of the target chip; The other level descriptions except the register transfer level description are not limited to gate level description; wherein, the determination method includes but is not limited to one or more of the following: determining that one or more keywords existing in the chip RTL code, and / or the total number of one or more keywords existing in the chip RTL code is greater than or equal to the keyword corresponding to the forty-second preset threshold, and / or the proportion of the total number of one or more keywords in the chip RTL code in the entire chip RTL code is greater than or equal to the keyword corresponding to the forty-third preset threshold, and the position and / or part of the keyword and / or the code length between the keyword is less than or equal to the forty-fourth preset threshold and / or the code length between the keyword and the part in the chip RTL code is less than or equal to the seventh proportion threshold, and / or the position and / or part and / or the keyword The module and / or design information corresponding to the keyword is determined as the target chip and / or the IP core called by information and / or suspected of being called by the target chip, wherein the keyword is a keyword representing descriptions at other levels except the register transfer level description, and the types of the keyword include but are not limited to one or more of the following: code at the representation description level, vocabulary and / or phrases at the representation description level, script at the representation description level, program at the representation description level, netlist at the representation description level, wherein the netlist includes but is not limited to a gate-level netlist; the twenty-fourth part in the RTL code of the chip, which is identical and / or similar to the twenty-third part of the gate-level netlist of the chip and / or the module and / or design information corresponding to the twenty-fourth part, is determined as the target chip and / or the IP core called by information and / or suspected of being called by the target chip; Determining the twenty-sixth portion of the chip RTL code, and / or the module and / or design information corresponding to the twenty-sixth portion, which is identical and / or similar to the twenty-fifth portion of the RTL code in the twenty-third preset library and / or has a similarity greater than or equal to a forty-sixth preset threshold, as the target chip and / or an IP core called and / or suspected of being called by the information of the target chip; the twenty-third preset library does not contain the RTL code designed by the design company of the target chip; Determine the twenty-eighth part of the chip RTL code, which is identical and / or similar and / or has a similarity greater than or equal to a forty-seventh preset threshold, and / or the module and / or design information corresponding to the twenty-eighth part as the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; the RTL code designed by the design company of the target chip in the twenty-fourth preset library, and / or the RTL code IP core library of the design company of the target chip, and / or the IP core library of the design company of the target chip; According to the chip RTL code and the chip gate-level netlist, the results and / or reports of the formal verification performed by the formal verification tool, the target chip and / or the information call and / or the suspected call IP core of the target chip are determined; the determination method includes but is not limited to one or more of the following: determining that the RTL code part and / or the gate-level netlist part that failed in the verification, and / or the module and / or design information corresponding to the failed part are the target chip and / or the information call and / or the suspected call IP core of the target chip; determining that the RTL code part and / or the gate-level netlist part corresponding to the mismatch point found in the verification, and / or the module and / or design information corresponding to the part and / or the mismatch point are the target The chip and / or the target chip's information call and / or suspected call of the IP core; determining that the inequivalent part found in the verification, and / or the RTL code part corresponding to the inequivalent part, and / or the gate-level netlist part corresponding to the inequivalent part, and / or the module and / or design information corresponding to the inequivalent part are the target chip and / or the IP core called by the information of the target chip and / or suspected call; determining that the logic and / or function in the RTL code found in the verification, and the difference between the logic and / or function in the gate-level netlist, and / or the RTL code part, and / or the gate-level netlist part, and / or the module and / or design information corresponding to the difference are the target chip and / or the IP core called by the information of the target chip and / or suspected call; The determination method includes but is not limited to one or more of the following: determining that the RTL code portion and / or the gate-level netlist portion that failed in the verification, and / or the module and / or design information corresponding to the failed portion are the target chip and / or the IP core called by the information of the target chip and / or suspected of being called; determining that the RTL code portion and / or the gate-level netlist portion corresponding to the mismatch point found in the verification, and / or the module and / or design information corresponding to the portion and / or the mismatch point are the target chip and / or the IP core called by the information of the target chip and / or suspected of being called; determining that the mismatch point found in the verification The equivalent part, and / or the RTL code part and / or the gate-level netlist part corresponding to the non-equivalent part, and / or the module and / or design information corresponding to the non-equivalent part are the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; determining the differences between the logic and / or function in the RTL code found in the verification and the logic and / or function in the gate-level netlist, and / or the RTL code part, and / or the gate-level netlist part, and / or the module and / or design information corresponding to the differences are the target chip and / or the IP core called and / or suspected of being called by the information of the target chip; Among them, when carrying out formal verification, if there are differences between the RTL code and the gate-level netlist in the functions and / or logic of auxiliary design and / or auxiliary testing, the functions and / or logic corresponding to the differences are verified or not verified; wherein, the method of not verifying the functions and / or logic corresponding to the differences includes but is not limited to: when setting constants, prohibiting the functions and / or logic and / or pins and / or pins of auxiliary design and / or auxiliary testing, and / or setting the functions and / or logic and / or pins and / or pins of auxiliary design and / or auxiliary testing to be invalid; the functions and / or logic and / or pins and / or pins of the auxiliary design and / or auxiliary testing include but are not limited to one or more of the following: scanning the SCAN chain and / or the enable pin and / or enable pin corresponding to the SCAN chain, the JTAG chain and / or the enable pin and / or enable pin corresponding to the JTAG chain, the chip testability design and / or the pins and / or pins corresponding to the testability design.

16. The method according to claim 3, characterized in that the preset threshold and / or identifier and / or preset library and / or the region and / or portion thereof used when determining, based on the first information, whether an IP core is called and / or whether an IP core is suspected of being called in a target chip and / or information of the target chip, and are the same as or different from the preset threshold and / or identifier and / or preset library and / or the region and / or portion thereof used when determining, based on the second information, the target chip and / or information of the target chip, the IP core to be called and / or suspected of being called; When determining, based on the first information, in the target chip and / or in the information of the target chip, whether the IP core is called and / or whether the IP core is suspected of being called, the preset thresholds and / or identifiers and / or preset libraries and / or the regions and / or parts thereof used, whether the preset thresholds and / or identifiers and / or preset libraries and / or the regions and / or parts thereof of the same type are the same or different; According to the second information, determine the target chip and / or the information of the target chip, the IP core called and / or suspected of being called, the preset thresholds and / or identifiers and / or preset libraries used and / or the areas and / or parts therein, and whether the preset thresholds and / or identifiers and / or preset libraries and / or the areas and / or parts therein of the same type are the same or different.

17. The method according to claim 1, wherein The IP cores include but are not limited to non-self-developed IP cores and / or self-developed IP cores; Among them, the non-self-developed IP core includes but is not limited to one or more of the following: an IP core that is not designed by the design company of the target chip, an IP core purchased by the design company of the target chip from other companies, an IP core called by the design company of the target chip from a non-self-developed IP core library, and an IP core whose intellectual property rights do not belong to the design company of the target chip; Among them, the self-developed IP core includes but is not limited to one or more of the following: the IP core designed by the design company of the target chip, the IP core independently developed by the design company of the target chip, the IP core owned by the design company of the target chip, the IP core accumulated by the design company of the target chip itself, and the IP core whose intellectual property rights belong to the design company of the target chip.

18. The method according to any one of claims 3 or 6-15, characterized in that: Also includes: Determining, based on the first information and / or the second information and / or the information of the target chip and / or the design documents of the target chip and / or the authorization information of the target chip, whether the target chip and / or the information of the target chip, the called and / or suspected called IP core is a non-self-developed IP core and / or whether it is a self-developed IP core; and / or While determining the target chip and / or information of the target chip based on the second information, and calling and / or suspected calling the IP core, determining whether the IP core is a non-self-developed IP core and / or whether it is a self-developed IP core; Among them, the method of determining that the target chip and / or the information of the target chip, the called and / or suspected called IP core is a non-self-developed IP core includes but is not limited to one or more of the following: The IP core determined by the blank area in the chip design layout and / or the content corresponding to the blank area is a non-self-developed IP core; The IP core is determined to be a non-self-developed IP core through the inconsistencies found when comparing the chip design layout with the corresponding physical chip and / or physical layout and / or physical layout and / or physical layout and wiring and / or physical layout and wiring diagram, and / or the content corresponding to the inconsistencies; The IP core determined by the twenty-first identifier in the third information of the target chip is a non-self-developed IP core; the twenty-first identifier is an identifier of a company other than the design company of the target chip, and / or an identifier representing a company other than the design company of the target chip; The IP core determined by the 26th region in the third information of the target chip, which is identical and / or similar to the 25th region of the information in the 25th preset library and / or whose similarity is greater than or equal to the 48th preset threshold, and / or the content corresponding to the 26th region, is a non-self-developed IP core; the 25th preset library does not contain information designed by the design company of the target chip; The IP core determined by the 30th part of the third information of the target chip, and / or the content corresponding to the 30th part, being identical and / or similar to the 29th part of the information in the 26th preset library and / or having a similarity greater than or equal to the 49th preset threshold, is a non-self-developed IP core; the 26th preset library does not contain information designed by the design company of the target chip; By determining the position and / or area of ​​the physical chip and / or physical layout and / or physical layout and / or physical layout wiring and / or physical layout wiring diagram, and / or the module and / or design information corresponding to the position and / or area of ​​the non-self-developed IP core, the position and / or area of ​​the corresponding chip design layout, and / or the module and / or design information corresponding to the position and / or area are determined as the IP core, which is a non-self-developed IP core; The IP core determined by the LVS verification tool to have failed the LVS verification results and / or reports is not a self-developed IP core; The IP core determined by the formal verification tool to have failed the formal verification results and / or reports is not a self-developed IP core; The IP cores identified by the descriptions of other levels except the register transfer level in the chip RTL code are non-self-developed IP cores; For the target chip and / or the IP core called and / or suspected of being called by the information of the target chip, if it is determined that the IP core is not the self-developed IP core called and / or suspected of being called by the information of the target chip and / or the target chip, then the IP core is a non-self-developed IP core called and / or suspected of being called by the information of the target chip and / or the target chip; The method for determining whether the target chip and / or the target chip information, the called and / or suspected called IP core is a self-developed IP core includes but is not limited to one or more of the following: The IP core determined by the twenty-second identifier in the third information of the target chip is a self-developed IP core; the twenty-second identifier is an identifier of a design company of the target chip and / or an identifier representing a design company of the target chip; The IP core determined to be a self-developed IP core is the 28th region in the third information of the target chip, and / or the content corresponding to the 28th region, which is identical and / or similar to the 27th region of the information in the 27th preset library and / or has a similarity greater than or equal to the 50th preset threshold; the information designed by the design company of the target chip in the 27th preset library, and / or the information IP core library of the design company of the target chip, and / or the IP core library of the design company of the target chip; The IP core determined to be a self-developed IP core is the thirty-second part of the third information of the target chip, and / or the content corresponding to the thirty-second part, which is identical and / or similar to the thirty-first part of the information in the twenty-eighth preset library and / or has a similarity greater than or equal to the fifty-first preset threshold; the information designed by the design company of the target chip in the twenty-eighth preset library, and / or the information IP core library of the design company of the target chip, and / or the IP core library of the design company of the target chip; By determining the position and / or area of ​​the physical chip and / or physical layout and / or physical layout and / or physical layout and / or physical layout wiring and / or physical layout wiring diagram of the self-developed IP core, and / or the module and / or design information corresponding to the position and / or area, the position and / or area of ​​the corresponding chip design layout, and / or the module and / or design information corresponding to the position and / or area are determined to be the IP core, which is the self-developed IP core; For the target chip and / or the IP core called and / or suspected of being called by the information of the target chip, if it is determined that the IP core is not a non-self-developed IP core called by the information, called and / or suspected of being called by the target chip and / or the target chip, then the IP core is the self-developed IP core called and / or suspected of being called by the information of the target chip and / or the target chip; The third information of the target chip includes but is not limited to one or more of the following: chip design layout, chip physical and / or physical layout and / or physical layout and / or physical layout and wiring and / or physical layout and wiring diagram, chip schematic, chip transistor-level netlist, chip gate-level netlist, chip RTL code, all or part of one or more of the first information, and all or part of one or more of the second information; Among them, the types of information in the 25th preset library and / or the 26th preset library and / or the 27th preset library and / or the 28th preset library and / or the information designed by the design company of the target chip, and / or the information in the IP core library of the design company of the target chip, include but are not limited to one or more of the following: layout and / or layout and / or layout and wiring and / or layout and wiring diagram, schematic diagram, transistor-level netlist, gate-level netlist, RTL code.

19. The method according to claim 3 or 17, characterized in that Also includes: Determine the degree of autonomy and / or controllability of the chip; the determination method includes but is not limited to one or more of the following: Determining one or more fourth information required to determine the autonomy and / or controllability of the chip, the fourth information including but not limited to one or more of the following: chip design layout, physical chip and / or physical layout and / or physical layout and / or physical layout and wiring and / or physical layout and wiring diagram, chip schematic, chip transistor-level netlist, chip gate-level netlist, chip RTL code, all or part of one or more of the first information, all or part of one or more of the second information, and other information of the chip other than the first information and the second information; For each of the one or more required fourth information, assign a score corresponding to the fourth information; wherein the method of assigning the score includes but is not limited to: assigning a score based on the difficulty and / or criticality of implementing and / or designing each type of fourth information; For each type of required fourth information, if the fourth information obtained does not contain all the information of the chip to be determined, and / or does not contain all functions and / or all logics and / or all modules and / or all units of the chip to be determined, and / or if the fourth information obtained calls a non-self-developed IP core and / or is suspected of calling a non-self-developed IP core, the score obtained by the chip is: the score corresponding to the fourth information, minus the part of the information of the chip to be determined that is missing in the fourth information and / or the missing functions. The score corresponding to the function and / or missing logic and / or missing module and / or missing unit is subtracted from the score corresponding to the non-self-developed IP core called and / or suspected to be called in the obtained fourth information, and / or the score obtained by the chip is: the score corresponding to the fourth information, minus the first proportion of the score corresponding to the part of the information to be determined and / or the missing function and / or missing logic and / or missing module and / or missing unit obtained in the fourth information. The score is the score remaining after subtracting the second proportion of the score corresponding to the non-self-developed IP core called and / or suspected to be called in the obtained fourth information; wherein, if the information part of the chip to be determined and / or the missing function and / or the missing logic and / or the missing module and / or the missing unit missing in the obtained fourth information have repeated and / or overlapping content with the non-self-developed IP core called and / or suspected to be called in the obtained fourth information, then only one is subtracted for the repeated and / or overlapping content. sub-points, and / or non-repeated deductions; wherein, the method for determining the first ratio and / or the second ratio includes but is not limited to one or more of the following: the ratio is less than or equal to 1, the ratio is greater than or equal to 0, the ratio of the missing information part of the chip to be determined and / or the missing function and / or the missing logic and / or the missing module and / or the missing unit when they are domestically produced is less than or equal to the ratio when they are non-domestic produced, and the ratio of the non-self-developed IP core called and / or suspected of being called when it is domestically produced is less than or equal to the ratio when the non-self-developed IP core is non-domestic produced; For each type of required fourth information, if the fourth information obtained contains all such information of the chip to be determined and / or contains all functions and / or all logic and / or all modules and / or all units of the chip to be determined, and the fourth information obtained does not call a non-self-developed IP core and is not suspected of calling a non-self-developed IP core, then the score obtained by the chip is: the score corresponding to the fourth information; For each type of required fourth information, if the fourth information is not obtained and / or it cannot be confirmed that the obtained fourth information is the fourth information of the chip, the chip will not receive any score for the fourth information. summing the actual scores obtained by the chip for each of the one or more required fourth information to obtain a total score for the chip, and determining the degree of autonomy and / or controllability of the chip based on the total score; Among them, one situation in which the fourth information obtained does not include all such information of the chip to be determined and / or does not include all functions and / or all logic and / or all modules and / or all units of the chip to be determined is that a non-self-developed IP core is called in other information after the design of the fourth information is completed, and the functions and / or logic and / or modules corresponding to the IP core have not yet been designed in the fourth information; In the case of assigning scores corresponding to the required one or more types of fourth information, it is necessary to ensure that the scores corresponding to the same degree of autonomy and / or controllability for a chip with a given function are the same under different solutions. Methods for ensuring the same scores corresponding to the same degree of autonomy and / or controllability include, but are not limited to, ensuring that the sum of the scores corresponding to the required types of fourth information for a chip with a given function is the same under different solutions. Determining various functions and / or logics and / or modules required to determine the degree of autonomy and / or controllability of the chip; For each of the various functions and / or logics and / or modules required, assign a score corresponding to the function and / or logic and / or module; wherein the method of assigning scores includes but is not limited to: assigning scores based on the difficulty and / or criticality of each function and / or logic and / or module, implementation and / or design; For each of the required functions and / or logic and / or modules, if the function and / or logic and / or module of the chip to be determined does not call a non-self-developed IP core and is not suspected of calling a non-self-developed IP core, the chip obtains a score corresponding to the function and / or logic and / or module; For each of the required functions and / or logic and / or modules, if the function and / or logic and / or module of the chip to be determined calls a non-self-developed IP core and / or is suspected of calling a non-self-developed IP core, the chip does not obtain the score corresponding to the function and / or logic and / or module, and / or the chip obtains a score of a third ratio of the score corresponding to the function and / or logic and / or module; wherein the method for determining the third ratio includes but is not limited to one or more of the following: the ratio is less than or equal to 1, the ratio is greater than or equal to 0, the ratio of the non-self-developed IP core called and / or suspected of being called is domestically produced is greater than or equal to the ratio of the non-self-developed IP core being non-domestic; For each required function and / or logic and / or module, if the chip to be determined lacks the function and / or logic and / or module, the chip will not receive a score for the function and / or logic and / or module. Summing up the actual scores obtained by the chip for each of the various required functions and / or logics and / or modules as the total score of the chip, and determining the degree of autonomy and / or controllability of the chip based on the total score; Among them, when allocating scores corresponding to the various functions and / or logic and / or modules required, it is necessary to ensure that the scores corresponding to the same degree of autonomy and / or controllability of a chip with a given function are the same under different schemes; the implementation method of ensuring that the scores corresponding to the same degree of autonomy and / or controllability are the same includes but is not limited to: the sum of the scores corresponding to the various functions and / or logic and / or modules required under different schemes of a chip with a given function is the same.

20. The method according to claim 19, characterized in that The scores corresponding to the information portion of the chip to be determined that is missing in the obtained fourth information and / or the missing functions and / or missing logic and / or missing modules and / or missing units, and / or the calculation method for the scores corresponding to the non-self-developed IP cores called and / or suspected of being called in the obtained fourth information, include but are not limited to one or more of the following: For the required fourth information, for each function and / or logic and / or module therein, a score corresponding to each function and / or logic and / or module is assigned, and the sum of the scores corresponding to each function and / or logic and / or module is the score corresponding to the fourth information; wherein the method of assigning scores includes but is not limited to: assigning scores based on the difficulty and / or criticality of each function and / or logic and / or module, implementation and / or design; Among the various functions and / or logics and / or modules in the required fourth information, find the information portion and / or functions and / or logics and / or modules of the chip to be determined that are missing from the obtained fourth information. The scores assigned to these functions and / or logics and / or modules, or the sum of the scores, are the scores corresponding to the information portion of the chip to be determined that is missing from the obtained fourth information and / or the missing functions and / or logics and / or modules. Among the various functions and / or logic and / or modules in the required fourth information, find the functions and / or logic and / or modules corresponding to the non-self-developed IP core called and / or suspected to be called in the obtained fourth information. The score or the sum of the scores assigned to this part of the functions and / or logic and / or modules is the score corresponding to the non-self-developed IP core called and / or suspected to be called in the obtained fourth information.

21. The method according to claim 1, wherein The method further includes confirming that the acquired information is information of the target chip; the information includes but is not limited to one or more of the following: chip design layout, physical chip and / or physical layout and / or physical layout and / or physical layout and wiring and / or physical layout and wiring diagram, chip schematic, chip transistor-level netlist, chip gate-level netlist, chip RTL code, all or part of one or more of the first information, all or part of one or more of the second information; other information of the chip other than the first information and the second information; the method of confirming includes but is not limited to one or more of the following: The acquired information has been declared or identified as information of the target chip; Determining the acquired physical chip and / or physical layout and / or physical layout and / or physical layout and wiring and / or physical layout and wiring diagram as information of the target chip; Comparing and / or verifying the acquired information to confirm whether it is the information of the target chip, including but not limited to one or more of the following: comparing and / or verifying the acquired information with information that has been declared or identified as the target chip one or more times, and if the comparison and / or verification passes, the acquired information is the information of the target chip; comparing and / or verifying the acquired information with a physical chip and / or a physical layout and / or a physical layout and / or a physical layout and wiring and / or a physical layout and wiring diagram one or more times, and if the comparison and / or verification passes, the acquired information is the information of the target chip; The acquired information is compared and / or verified with the information of the target chip through comparison and / or verification, and is compared and / or verified once or multiple times. If the comparison and / or verification pass, the acquired information is the information of the target chip.

22. The method according to claim 21, characterized in that The comparison and / or verification includes, but is not limited to, one or more of the following: Comparing the chip design layout with the physical chip and / or the physical layout and / or the physical layout and / or the physical layout and / or the physical layout and / or the physical layout and / or the physical layout; Comparing the chip design layout with the physical chip and / or the physical layout ... Perform LVS verification on the chip schematic and chip design layout; Perform LVS verification on the chip schematics and chip design layout after removing the parts and / or regions and / or modules and / or design information of the non-self-developed IP cores that have been confirmed or suspected to be called by the target chip; Perform LVS verification on the chip transistor-level netlist and chip design layout; After removing the parts and / or regions and / or modules and / or design information of the non-self-developed IP cores that have been confirmed or suspected to be called by the target chip, the remaining chip transistor-level netlist and chip design layout are subjected to LVS verification; Perform LVS verification on the chip's gate-level netlist and chip design layout; After removing the parts and / or regions and / or modules and / or design information of the non-self-developed IP cores that have been confirmed or suspected to be called by the target chip from the chip gate-level netlist and chip design layout, LVS verification is performed on the remaining chip gate-level netlist and chip design layout; After converting the chip's gate-level netlist into a chip transistor-level netlist, LVS verification is performed on the converted chip transistor-level netlist and the chip design layout; After converting the chip's gate-level netlist to a chip transistor-level netlist, perform LVS verification on the converted chip transistor-level netlist and the chip design layout, removing the portion and / or region and / or module and / or design information of the non-self-developed IP core that has been confirmed to be called or suspected to be called by the target chip. After removing the parts and / or regions and / or modules and / or design information of the non-self-developed IP cores that have been confirmed or suspected to be called by the target chip from the chip gate-level netlist and chip design layout, the remaining gate-level netlist is converted into a transistor-level netlist. LVS verification is then performed on the converted transistor-level netlist and the remaining chip design layout. Perform formal verification on one gate-level netlist of the chip and another gate-level netlist of the chip; After removing the portion and / or region and / or module and / or design information of the non-self-developed IP core that has been confirmed to be called or suspected to be called by the target chip, formal verification is performed on the gate-level netlist of the chip and the gate-level netlist of the chip; Perform formal verification on the chip RTL code and the chip's gate-level netlist; After removing the parts and / or regions and / or modules and / or design information of the non-self-developed IP cores that have been confirmed to be called or suspected to be called by the target chip, the chip RTL code and the chip gate-level netlist are formally verified. Among them, when carrying out formal verification, if there are differences in the functions and / or logic of auxiliary design and / or auxiliary test between the two gate-level netlists being verified, and / or between the verified RTL code and the gate-level netlist, the functions and / or logic corresponding to the differences are not verified or verified; wherein, the method of not verifying the functions and / or logic corresponding to the differences includes but is not limited to: when setting constants, prohibiting the functions and / or logic and / or pins and / or pins of auxiliary design and / or auxiliary test, and / or setting the functions and / or logic and / or pins and / or pins of auxiliary design and / or auxiliary test to be invalid; the functions and / or logic and / or pins and / or pins of the auxiliary design and / or auxiliary test include but are not limited to one or more of the following: scanning the SCAN chain and / or the enable pin and / or enable pin corresponding to the SCAN chain, the JTAG chain and / or the enable pin and / or enable pin corresponding to the JTAG chain, and the chip testability design and / or the pins and / or pins corresponding to the testability design.

23. The method according to claim 6 or 11, characterized in that Including but not limited to one or more of the following: The chip design layout, and / or the regions within the chip design layout, include but are not limited to the chip design layout of all layers and / or partial layers and / or one layer. For one layer, the chip design layout includes but is not limited to the chip design layout of the entire region and / or multiple local regions and / or one local region; wherein the positions and / or ranges of the entire region and / or multiple local regions and / or one local region of different layers are the same or different; The physical chip and / or physical layout and / or physical layout and / or physical layout and / or physical layout wiring and / or physical layout wiring diagram, and / or the physical chip and / or physical layout and / or physical layout and / or physical layout wiring and / or the area in the physical layout wiring diagram, include but are not limited to the physical chip and / or physical layout and / or physical layout and / or physical layout wiring and / or physical layout wiring diagram of all layers and / or part of the layers and / or one layer. For one layer, the physical chip and / or physical layout and / or physical layout and / or physical layout wiring and / or physical layout wiring diagram include but are not limited to the physical chip and / or physical layout and / or physical layout and / or physical layout wiring and / or physical layout wiring diagram of the entire area and / or multiple local areas and / or one local area; wherein the positions and / or ranges of the entire area and / or multiple local areas and / or one local area of ​​different layers are the same or different; The layout and / or layout and / or layout wiring and / or layout wiring diagram, and / or the regions in the layout and / or layout and / or layout and / or layout wiring and / or layout wiring diagram in the preset library include but are not limited to the layout and / or layout and / or layout wiring and / or layout wiring and / or layout wiring diagram of all layers and / or part of the layers and / or one layer, and for one layer, the layout and / or layout and / or layout and / or layout wiring and / or layout wiring diagram include but are not limited to the layout and / or layout and / or layout and / or layout wiring and / or layout wiring diagram of the entire region and / or multiple local regions and / or one local region; wherein the positions and / or ranges of the entire region and / or multiple local regions and / or one local region of different layers are the same or different; The schematic diagram of the chip, and / or a region in the schematic diagram of the chip, including but not limited to a schematic diagram of the chip for the entire region and / or multiple local regions and / or a local region; The schematic diagrams in the preset library, and / or regions in the schematic diagrams, include but are not limited to the schematic diagrams of the entire region and / or multiple local regions and / or one local region; The chip transistor-level netlist, and / or part of the transistor-level netlist, including but not limited to: the entire transistor-level netlist, and part of the transistor-level netlist; The transistor-level netlist in the preset library, and / or a portion of the transistor-level netlist, including but not limited to: an entire transistor-level netlist, a partial transistor-level netlist; The gate-level netlist of the chip, and / or part of the gate-level netlist, including but not limited to: the entire gate-level netlist, a part of the gate-level netlist; The gate-level netlist in the preset library, and / or part of the gate-level netlist, including but not limited to: the entire gate-level netlist, part of the gate-level netlist; The chip RTL code, and / or part of the RTL code, includes but is not limited to one or more of the following: the entire RTL code, part of the RTL code, the RTL code claimed by the design company of the target chip, and the code designed by the design company of the target chip during the RTL design stage; The RTL code in the preset library, and / or part of the RTL code, including but not limited to: the entire RTL code, part of the RTL code; The chip design layout includes but is not limited to one or more of the following: chip design layout, annotations and / or descriptions in the chip design layout; The physical chip and / or physical layout ... The schematic diagram of the chip includes, but is not limited to, one or more of the following: a schematic diagram of the chip, annotations and / or descriptions in the schematic diagram of the chip; The chip transistor-level netlist includes, but is not limited to, one or more of the following: a chip transistor-level netlist, and comments and / or descriptions in the chip transistor-level netlist; The gate-level netlist of the chip includes, but is not limited to, one or more of the following: the gate-level netlist of the chip, and comments and / or descriptions in the gate-level netlist of the chip; The chip RTL code includes but is not limited to one or more of the following: chip RTL code, comments and / or instructions in the chip RTL code; The identification includes one or more of the following: text, graphics, trademarks, names, logos, marks, and watermarks.

24. A detection device for IP core call, characterized in that: include: An IP core calling judgment module is configured to determine, based on the first information, whether an IP core is called in a target chip and / or in the information of the target chip and / or whether an IP core is suspected of being called; in: The first information includes a chip schematic and a chip design layout; The IP core call judgment module includes: A fourteenth judgment submodule is configured to modify the names of modules in the schematic diagram and the chip design layout of the chip, and perform LVS verification using an LVS verification tool after the modification; if the LVS verification fails, it is determined that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core; and / or The first information includes a chip transistor-level netlist and a chip design layout; The IP core call judgment module includes: a twentieth judgment submodule, configured to modify the module names in the chip transistor-level netlist and the chip design layout, and perform LVS verification using an LVS verification tool after the modification; if the LVS verification fails, determining that the target chip and / or the target chip information has called an IP core and / or is suspected of calling an IP core; and / or The first information includes a gate-level netlist of the chip and / or a chip design layout; The IP core call judgment module includes one or more of the following: a twenty-sixth judgment submodule, configured to modify the names of modules in the gate-level netlist and the chip design layout of the chip, and perform LVS verification using an LVS verification tool after the modification; if the LVS verification fails, determining that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core; a twenty-eighth judgment submodule, configured to convert the gate-level netlist of the chip into a chip transistor-level netlist, modify the module names in the converted chip transistor-level netlist and the chip design layout, and perform LVS verification using an LVS verification tool after the modification; if the LVS verification fails, determining that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core; a twenty-ninth judgment submodule, configured to modify the names of modules in a gate-level netlist of a chip and the chip design layout, convert the modified gate-level netlist into a chip transistor-level netlist, and perform LVS verification on the converted chip transistor-level netlist and the modified chip design layout using an LVS verification tool; if the LVS verification fails, it is determined that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core; a thirty-first judgment submodule, configured to modify the names of modules in two gate-level netlists of the chip, and perform formal verification using a formal verification tool after the modification; if the formal verification fails, determining that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core; and / or The first information includes chip RTL code and / or chip gate-level netlist; The IP core call judgment module includes one or more of the following: a thirty-fourth judgment submodule, configured to determine that the target chip and / or the information of the target chip has called an IP core and / or is suspected of calling an IP core if other level descriptions except the register transfer level description exist in the chip RTL code; The thirty-eighth judgment submodule is used to modify the name of the module in the chip RTL code and the gate-level netlist of the chip, and perform formal verification using a formal verification tool after the modification. If the formal verification fails, it is determined that the target chip and / or the information of the target chip has called the IP core and / or is suspected of calling the IP core.

25. The device according to claim 24, characterized in that Also includes: An IP core calling determination module is configured to determine the target chip and / or the information of the target chip according to the second information, and to call and / or suspect to call the IP core; in: The second information includes a schematic diagram of the chip and a chip design layout; The IP core call determination module includes: An eighteenth determination submodule is configured to determine the target chip and / or the information call and / or suspected call IP core of the target chip based on the chip schematic and chip design layout, after modifying the module name, and using an LVS verification tool to perform LVS verification, and the result and / or report of the failed LVS verification; and / or The second information includes a chip transistor-level netlist and a chip design layout; The IP core call determination module includes: A twenty-fourth determination submodule is configured to determine the target chip and / or the IP core called and / or suspected of being called by the target chip based on the chip transistor-level netlist and chip design layout, after modifying the module names therein, and the results and / or report of LVS verification performed by an LVS verification tool, including the results of failed LVS verification; and / or The second information includes a gate-level netlist of the chip and / or a chip design layout; The IP core call determination module includes one or more of the following: A 30th determination submodule, configured to determine the target chip and / or the IP core called and / or suspected of being called by the target chip based on the gate-level netlist and chip design layout of the chip, after modifying the names of the modules therein, and the results and / or reports of LVS verification performed by an LVS verification tool, including the results of LVS verification that failed; A thirty-second determination submodule is configured to determine the target chip and / or the information call and / or suspected call of the target chip IP core based on the converted chip transistor-level netlist and the chip design layout after the chip gate-level netlist is converted into the chip transistor-level netlist, the LVS verification tool used to perform LVS verification after the module names are modified, and the results and / or reports of the failed LVS verification; A thirty-third determination submodule is configured to determine the target chip and / or the information call and / or suspected call IP core of the target chip based on the gate-level netlist of the chip and the chip design layout, after modifying the module names therein, converting the modified gate-level netlist into a chip transistor-level netlist, and performing LVS verification on the converted chip transistor-level netlist and the modified chip design layout using an LVS verification tool, and the results and / or reports of failed LVS verification; A thirty-fifth determination submodule is configured to determine the target chip and / or the IP core called and / or suspected of being called by the target chip based on two gate-level netlists of the chip, after modifying the names of the modules therein, and the results and / or reports of the formal verification performed using a formal verification tool, or the results of the formal verification that failed; and / or The second information includes chip RTL code and / or a gate-level netlist of the chip; The IP core call determination module includes one or more of the following: A thirty-eighth determination submodule is configured to determine the target chip and / or the IP core called and / or suspected of being called by the information of the target chip based on the portion of the chip RTL code where descriptions at other levels other than the register transfer level description are located; The forty-second determination submodule is used to determine the target chip and / or the information call and / or suspected call IP core of the target chip based on the chip RTL code and the chip's gate-level netlist, after modifying the module name therein, using a formal verification tool for formal verification, and the results and / or report of the failed formal verification.

26. An electronic device comprising a memory, a processor, and a program stored in the memory and executable on the processor; characterized in that: When the processor executes the program, the steps in the method for detecting IP core calls according to any one of claims 1 to 23 are implemented.

27. A readable storage medium having a program stored thereon, characterized in that: When the program is executed by a processor, the steps of the method for detecting an IP core call according to any one of claims 1 to 23 are implemented.

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