Display substrate and driving method thereof, and display device

Abstract

The present application provides a display substrate and a driving method thereof, and a display device, which belong to the field of display technology. Since in the display substrate, among the multiple pixels connected to each shift circuit, the colors of the pixels sharing the same data line are the same, and each shift circuit is connected to an enable signal terminal, it is possible to flexibly control the enable signal provided by the enable signal terminal, so that each data line can continuously provide data signals to pixels of the same color. In this way, when displaying a pure color picture, the number of potential flips on each data line is small, which effectively reduces the power consumption of the display device.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a driving method thereof, and a display device. Background Art

[0002] Liquid crystal display (LCD) devices are widely used in the display field due to their advantages such as high resolution, light weight and low energy consumption.

[0003] Related art proposes a dual gate LCD device, which includes: multiple gate lines, multiple data lines and multiple pixels arranged in an array. Among them, multiple pixels located in the same row can be divided into multiple groups, each group can include two adjacent pixels with different colors, and the two pixels can be connected to different gate lines respectively, and can be connected to the same data line. That is, each row of pixels can be connected to two gate lines respectively. Moreover, the scanning drive mode of the dual gate LCD device is currently row-by-row scanning, that is, multiple gate lines are turned on in sequence according to the arrangement order, so as to drive each row of pixels to emit light in sequence.

[0004] However, if a pure color image is to be displayed, in the related art, the potential on each data line needs to be constantly changed (also called flipping), which results in high power consumption. Summary of the invention

[0005] The present disclosure provides a display substrate and a driving method thereof, and a display device, which can solve the problem of high power consumption in the related art. The technical solution is as follows:

[0006] In one aspect, a display substrate is provided, the display substrate comprising: a base substrate;

[0007] A plurality of gate lines, a plurality of data lines and a plurality of rows of pixels arranged in an array are located on the substrate, each row of the pixels includes a plurality of pixel groups, each of the pixel groups includes two adjacent pixels of different colors, and the two pixels are connected to different gate lines and the same data line;

[0008] A plurality of shift circuits located on the substrate, each of the shift circuits being connected to an enable signal terminal and at least two gate lines of the plurality of gate lines, and each of the shift circuits being used to provide a gate drive signal to each of the connected gate lines in response to an enable signal provided by the enable signal terminal;

[0009] Among the multiple pixels connected to each of the shift circuits, the colors of the pixels connected to the same data line are the same.

[0010] Optionally, each of the shift circuits comprises: at least four shift register units, each of the shift register units is connected to a gate line, and the at least four shift register units in each of the shift circuits can be divided into two shift register groups;

[0011] Each of the shift register groups includes a plurality of cascaded shift register units, and one of the shift register units in each of the shift register groups is connected to the start signal terminal.

[0012] Optionally, each of the shift register groups includes multiple shift register sub-groups, each of the shift register sub-groups includes two adjacent and cascaded shift register units, and the two shift register units in each of the shift register sub-groups are respectively connected to the adjacent i-th gate line and i+s-th gate line, where i is a positive integer and s is 1 or 2.

[0013] Optionally, the number d of clock signal terminals connected to the multiple shift circuits in the display substrate is an integer multiple of 4.

[0014] Optionally, the number d of clock signal terminals connected to the multiple shift circuits in the display substrate is 16.

[0015] Optionally, the plurality of shift circuits include: a first shift circuit, a second shift circuit, a third shift circuit and a fourth shift circuit, a total of four shift circuits;

[0016] The first shift circuit and the second shift circuit are located on one side of the multiple rows of pixels, and the third shift circuit and the fourth shift circuit are located on the other side of the multiple rows of pixels.

[0017] Optionally, the 2n-1th shift register subgroup located on one side of the multiple rows of pixels belongs to the first shift circuit, and the 2nth shift register subgroup located on one side of the multiple rows of pixels belongs to the second shift circuit, where n is a positive integer;

[0018] The 2n-1th shift register subgroup located on the other side of the multiple rows of pixels belongs to the third shift circuit, and the 2nth shift register subgroup located on the other side of the multiple rows of pixels belongs to the fourth shift circuit.

[0019] Optionally, the 4n-3rd shift register subgroup located on one side of the multiple rows of pixels belongs to one shift register group in the first shift circuit, and the 4n-1th shift register subgroup located on one side of the multiple rows of pixels belongs to another shift register group in the first shift circuit;

[0020] The 4n-2 th shift register subgroup located on one side of the plurality of rows of pixels belongs to one shift register group in the second shift circuit; the 4n th shift register subgroup located on one side of the plurality of rows of pixels belongs to another shift register group in the second shift circuit;

[0021] The 4n-3rd shift register subgroup located on the other side of the plurality of rows of pixels belongs to one shift register group in the third shift circuit, and the 4n-1st shift register subgroup located on the other side of the plurality of rows of pixels belongs to another shift register group in the third shift circuit;

[0022] The 4n-2 th shift register subgroup located on the zero side of the multiple rows of pixels belongs to one shift register group in the fourth shift circuit; the 4n th shift register subgroup located on the other side of the multiple rows of pixels belongs to another shift register group in the fourth shift circuit.

[0023] Optionally, s is 2, and the shift register unit connected to the i-th gate line is the i-th shift register unit;

[0024] The first shift register unit and the third shift register unit are cascaded with each other, the first shift register unit is used to provide a carry signal to the third shift register unit; the third shift register unit is used to provide a reset signal to the first shift register unit;

[0025] The third shift register unit is also cascaded with the 1+dth shift register unit, and the third shift register unit is used to provide a carry signal to the 1+dth shift register unit; the 1+dth shift register unit is used to provide a reset signal to the third shift register unit;

[0026] The fifth shift register unit and the seventh shift register unit are cascaded with each other, the fifth shift register unit is used to provide a carry signal to the seventh shift register unit; the seventh shift register unit is used to provide a reset signal to the fifth shift register unit;

[0027] The 7th shift register unit is also cascaded with the 5+dth shift register unit, the 7th shift register unit is used to provide a carry signal to the 5+dth shift register unit; the 5+dth shift register unit is used to provide a reset signal to the 7th shift register unit;

[0028] The 9th shift register unit and the 11th shift register unit are cascaded with each other, the 9th shift register unit is used to provide a carry signal to the 11th shift register unit; the 11th shift register unit is used to provide a reset signal to the 9th shift register unit;

[0029] The 11th shift register unit is also cascaded with the 9+dth shift register unit, the 11th shift register unit is used to provide a carry signal to the 9+dth shift register unit; the 9+dth shift register unit is used to provide a reset signal to the 11th shift register unit;

[0030] The 13th shift register unit and the 15th shift register unit are cascaded with each other, the 13th shift register unit is used to provide a carry signal to the 15th shift register unit; the 15th shift register unit is used to provide a reset signal to the 13th shift register unit;

[0031] The 15th shift register unit is also cascaded with the 13+dth shift register unit, the 15th shift register unit is used to provide a carry signal to the 13+dth shift register unit; the 13+dth shift register unit is used to provide a reset signal to the 15th shift register unit;

[0032] The second shift register unit and the fourth shift register unit are cascaded with each other, the second shift register unit is used to provide a carry signal to the fourth shift register unit; the fourth shift register unit is used to provide a reset signal to the second shift register unit;

[0033] The fourth shift register unit is also cascaded with the 2+dth shift register unit, the fourth shift register unit is used to provide a carry signal to the 2+dth shift register unit; the 2+dth shift register unit is used to provide a reset signal to the fourth shift register unit;

[0034] The sixth shift register unit and the eighth shift register unit are cascaded with each other, the sixth shift register unit is used to provide a carry signal to the eighth shift register unit; the eighth shift register unit is used to provide a reset signal to the sixth shift register unit;

[0035] The 8th shift register unit is also cascaded with the 6+dth shift register unit, the 8th shift register unit is used to provide a carry signal to the 6+dth shift register unit; the 6+dth shift register unit is used to provide a reset signal to the 8th shift register unit;

[0036] The tenth shift register unit and the twelfth shift register unit are cascaded with each other, the tenth shift register unit is used to provide a carry signal to the twelfth shift register unit; the twelfth shift register unit is used to provide a reset signal to the tenth shift register unit;

[0037] The 12th shift register unit is also cascaded with the 10+dth shift register unit, the 12th shift register unit is used to provide a carry signal to the 10+dth shift register unit; the 10+dth shift register unit is used to provide a reset signal to the 12th shift register unit;

[0038] The 14th shift register unit and the 16th shift register unit are cascaded with each other, the 14th shift register unit is used to provide a carry signal to the 16th shift register unit; the 16th shift register unit is used to provide a reset signal to the 14th shift register unit;

[0039] The 16th shift register unit is also cascaded with the 14+dth shift register unit, and the 16th shift register unit is used to provide a carry signal to the 14+dth shift register unit; the 14+dth shift register unit is used to provide a reset signal to the 16th shift register unit.

[0040] Optionally, s is 1, and the shift register unit connected to the i-th gate line is the i-th shift register unit;

[0041] The first shift register unit and the second shift register unit are cascaded with each other, the first shift register unit is used to provide a carry signal to the second shift register unit; the second shift register unit is used to provide a reset signal to the first shift register unit;

[0042] The second shift register unit is also cascaded with the 1+dth shift register unit, the second shift register unit is used to provide a carry signal to the 1+dth shift register unit; the 1+dth shift register unit is used to provide a reset signal to the second shift register unit;

[0043] The third shift register unit and the fourth shift register unit are cascaded with each other, the third shift register unit is used to provide a carry signal to the fourth shift register unit; the fourth shift register unit is used to provide a reset signal to the third shift register unit;

[0044] The fourth shift register unit is also cascaded with the 3+dth shift register unit, the fourth shift register unit is used to provide a carry signal to the 3+dth shift register unit; the 3+dth shift register unit is used to provide a reset signal to the fourth shift register unit;

[0045] The fifth shift register unit and the sixth shift register unit are cascaded with each other, the fifth shift register unit is used to provide a carry signal to the sixth shift register unit; the sixth shift register unit is used to provide a reset signal to the fifth shift register unit;

[0046] The sixth shift register unit is also cascaded with the fifth + dth shift register unit, the sixth shift register unit is used to provide a carry signal to the fifth + dth shift register unit; the fifth + dth shift register unit is used to provide a reset signal to the sixth shift register unit;

[0047] The seventh shift register unit and the eighth shift register unit are cascaded with each other, the seventh shift register unit is used to provide a carry signal to the eighth shift register unit; the eighth shift register unit is used to provide a reset signal to the seventh shift register unit;

[0048] The 8th shift register unit is also cascaded with the 7+dth shift register unit, the 8th shift register unit is used to provide a carry signal to the 7+dth shift register unit; the 7+dth shift register unit is used to provide a reset signal to the 8th shift register unit;

[0049] The 9th shift register unit and the 10th shift register unit are cascaded with each other, the 9th shift register unit is used to provide a carry signal to the 10th shift register unit; the 10th shift register unit is used to provide a reset signal to the 9th shift register unit;

[0050] The 10th shift register unit is also cascaded with the 9+dth shift register unit, the 10th shift register unit is used to provide a carry signal to the 9+dth shift register unit; the 9+dth shift register unit is used to provide a reset signal to the 10th shift register unit;

[0051] The 11th shift register unit and the 12th shift register unit are cascaded with each other, the 11th shift register unit is used to provide a carry signal to the 12th shift register unit; the 12th shift register unit is used to provide a reset signal to the 11th shift register unit;

[0052] The 12th shift register unit is also cascaded with the 11+dth shift register unit, the 12th shift register unit is used to provide a carry signal to the 11+dth shift register unit; the 11+dth shift register unit is used to provide a reset signal to the 12th shift register unit;

[0053] The 13th shift register unit and the 14th shift register unit are cascaded with each other, the 13th shift register unit is used to provide a carry signal to the 14th shift register unit; the 14th shift register unit is used to provide a reset signal to the 13th shift register unit;

[0054] The 14th shift register unit is also cascaded with the 13+dth shift register unit, the 14th shift register unit is used to provide a carry signal to the 13+dth shift register unit; the 13+dth shift register unit is used to provide a reset signal to the 14th shift register unit;

[0055] The 15th shift register unit and the 16th shift register unit are cascaded with each other, the 15th shift register unit is used to provide a carry signal to the 16th shift register unit; the 16th shift register unit is used to provide a reset signal to the 15th shift register unit;

[0056] The 16th shift register unit is also cascaded with the 15+dth shift register unit, and the 16th shift register unit is used to provide a carry signal to the 15+dth shift register unit; the 15+dth shift register unit is used to provide a reset signal to the 16th shift register unit.

[0057] Optionally, the display substrate comprises: a first start-up signal terminal, a second start-up signal terminal, a third start-up signal terminal and a fourth start-up signal terminal, a total of four start-up signal terminals;

[0058] In the first shift circuit, the first shift register unit in the first shift register subgroup and the first shift register unit in the second shift register subgroup are connected to the first start signal terminal;

[0059] In the second shift circuit, the first shift register unit in the first shift register subgroup and the first shift register unit in the second shift register subgroup are connected to the third start signal terminal;

[0060] In the third shift circuit, the first shift register unit in the first shift register subgroup and the first shift register unit in the second shift register subgroup are connected to the second start signal terminal;

[0061] In the fourth shift circuit, the first shift register unit in the first shift register subgroup and the first shift register unit in the second shift register subgroup are connected to the fourth start signal terminal.

[0062] Optionally, each pixel in the same row is arranged in sequence according to the first color, the second color and the third color, and each pixel in the same column has the same color.

[0063] Optionally, in two adjacent pixel groups connected to the same data line, pixels are located in different columns.

[0064] Optionally, each of the data lines includes: a plurality of data line segments and a plurality of connection line segments;

[0065] Wherein, both ends of each connecting line segment are respectively connected to two adjacent data line segments; each pixel group corresponds to one data line segment, and any two adjacent data line segments are respectively located between two pixels included in pixel groups in adjacent rows but different columns.

[0066] Optionally, in two adjacent pixel groups connected to the same data line, at least two pixels are located in the same column.

[0067] On the other hand, a method for driving a display substrate is provided, for driving the display substrate as described in the above aspect, the method comprising:

[0068] sequentially providing a start signal to each start signal terminal in the display substrate, and each shift circuit provides a gate drive signal to each gate line connected thereto in response to the start signal;

[0069] A data signal is provided to each data line in the display substrate, and each pixel in the display substrate emits light in response to a gate driving signal provided by the connected gate line and a data signal provided by the connected data line.

[0070] Optionally, the display substrate includes: four shift circuits, namely, a first shift circuit, a second shift circuit, a third shift circuit and a fourth shift circuit, and four start-up signal terminals, namely, a first start-up signal terminal, a second start-up signal terminal, a third start-up signal terminal and a fourth start-up signal terminal; wherein the first start-up signal terminal is connected to the first shift circuit, the third start-up signal terminal is connected to the second shift circuit, the second start-up signal terminal is connected to the third shift circuit, and the fourth start-up signal terminal is connected to the fourth shift circuit;

[0071] The step of sequentially providing a start signal to each start signal terminal in the display substrate comprises:

[0072] An on signal is sequentially provided to the first on signal terminal, the third on signal terminal, the second on signal terminal and the fourth on signal terminal.

[0073] Optionally, each of the shift circuits comprises at least four shift register units, each of the shift register units is connected to a gate line, and the at least four shift register units in each of the shift circuits can be divided into two shift register groups; each of the shift register groups comprises a plurality of cascaded shift register units, and one of the shift register units in each of the shift register groups is connected to the start signal terminal; each of the shift register groups comprises a plurality of shift register subgroups, each of the shift register subgroups comprises two adjacent and cascaded shift register units, and the two shift register units in each of the shift register subgroups are respectively connected to the adjacent i-th gate line and i+2-th gate line, where i is a positive integer;

[0074] Each of the shift circuits provides a gate drive signal to each of the gate lines connected thereto in response to the start signal, including the following steps performed in sequence:

[0075] In the first shift circuit, the shift register unit connected to the first gate line provides a gate drive signal to the first gate line in response to the start signal provided by the first start signal terminal, and provides a carry signal to the shift register unit connected to the third gate line;

[0076] In the second shift circuit, the shift register unit connected to the fifth gate line provides a gate drive signal to the fifth gate line in response to the start signal provided by the third start signal terminal, and provides a carry signal to the shift register unit connected to the seventh gate line;

[0077] In the first shift circuit, the shift register unit connected to the ninth gate line provides a gate drive signal to the ninth gate line in response to the start signal provided by the first start signal terminal, and provides a carry signal to the shift register unit connected to the eleventh gate line;

[0078] In the second shift circuit, the shift register unit connected to the thirteenth gate line provides a gate drive signal to the thirteenth gate line in response to the start signal provided by the third start signal terminal, and provides a carry signal to the shift register unit connected to the fifteenth gate line;

[0079] In the first shift circuit, the shift register unit connected to the third gate line provides a gate drive signal to the third gate line in response to a received carry signal;

[0080] In the second shift circuit, the shift register unit connected to the seventh gate line provides a gate drive signal to the seventh gate line in response to a received carry signal;

[0081] In the first shift circuit, the shift register unit connected to the eleventh gate line provides a gate drive signal to the eleventh gate line in response to a received carry signal;

[0082] In the second shift circuit, the shift register unit connected to the fifteenth gate line provides a gate drive signal to the fifteenth gate line in response to a received carry signal;

[0083] In the third shift circuit, the shift register unit connected to the second gate line provides a gate drive signal to the second gate line in response to the start signal provided by the second start signal terminal, and provides a carry signal to the shift register unit connected to the fourth gate line;

[0084] In the fourth shift circuit, the shift register unit connected to the sixth gate line provides a gate drive signal to the sixth gate line in response to the start signal provided by the fourth start signal terminal, and provides a carry signal to the shift register unit connected to the eighth gate line;

[0085] In the third shift circuit, the shift register unit connected to the tenth gate line provides a gate drive signal to the tenth gate line in response to the start signal provided by the second start signal terminal, and provides a carry signal to the shift register unit connected to the twelfth gate line;

[0086] In the fourth shift circuit, the shift register unit connected to the fourteenth gate line provides a gate drive signal to the fourteenth gate line in response to the start signal provided by the fourth start signal terminal, and provides a carry signal to the shift register unit connected to the sixteenth gate line;

[0087] In the third shift circuit, the shift register unit connected to the fourth gate line provides a gate drive signal to the fourth gate line in response to a received carry signal;

[0088] In the fourth shift circuit, the shift register unit connected to the eighth gate line provides a gate drive signal to the eighth gate line in response to a received carry signal;

[0089] In the third shift circuit, the shift register unit connected to the twelfth gate line provides a gate drive signal to the twelfth gate line in response to a received carry signal;

[0090] In the fourth shift circuit, the shift register unit connected to the sixteenth gate line provides a gate driving signal to the sixteenth gate line in response to a received carry signal.

[0091] Optionally, each of the shift circuits comprises at least four shift register units, each of the shift register units is connected to a gate line, and at least four shift register units in each of the shift circuits can be divided into two shift register groups; each of the shift register groups comprises a plurality of cascaded shift register units, and one of the shift register units in each of the shift register groups is connected to the start signal terminal; each of the shift register groups comprises a plurality of shift register subgroups, each of the shift register subgroups comprises two adjacent and cascaded shift register units, and the two shift register units in each of the shift register subgroups are respectively connected to the adjacent i-th gate line and i+1-th gate line, where i is a positive integer;

[0092] Each of the shift circuits provides a gate drive signal to each of the gate lines connected thereto in response to the start signal, including the following steps performed in sequence:

[0093] In the first shift circuit, the shift register unit connected to the first gate line provides a gate drive signal to the first gate line in response to the start signal provided by the first start signal terminal, and provides a carry signal to the shift register unit connected to the second gate line;

[0094] In the second shift circuit, the shift register unit connected to the fifth gate line provides a gate drive signal to the fifth gate line in response to the start signal provided by the third start signal terminal, and provides a carry signal to the shift register unit connected to the sixth gate line;

[0095] In the first shift circuit, the shift register unit connected to the ninth gate line provides a gate drive signal to the ninth gate line in response to the start signal provided by the first start signal terminal, and provides a carry signal to the shift register unit connected to the tenth gate line;

[0096] In the second shift circuit, the shift register unit connected to the thirteenth gate line provides a gate drive signal to the thirteenth gate line in response to the start signal provided by the third start signal terminal, and provides a carry signal to the shift register unit connected to the fourteenth gate line;

[0097] In the third shift circuit, the shift register unit connected to the third gate line provides a gate drive signal to the third gate line in response to the start signal provided by the second start signal terminal, and provides a carry signal to the shift register unit connected to the fourth gate line;

[0098] In the fourth shift circuit, the shift register unit connected to the seventh gate line provides a gate drive signal to the seventh gate line in response to the start signal provided by the fourth start signal terminal, and provides a carry signal to the shift register unit connected to the eighth gate line;

[0099] In the third shift circuit, the shift register unit connected to the eleventh gate line provides a gate drive signal to the eleventh gate line in response to the start signal provided by the second start signal terminal, and provides a carry signal to the shift register unit connected to the twelfth gate line;

[0100] In the fourth shift circuit, the shift register unit connected to the fifteenth gate line provides a gate drive signal to the fifteenth gate line in response to the start signal provided by the fourth start signal terminal, and provides a carry signal to the shift register unit connected to the sixteenth gate line;

[0101] In the first shift circuit, the shift register unit connected to the second gate line provides a gate drive signal to the second gate line in response to a received carry signal;

[0102] In the second shift circuit, the shift register unit connected to the sixth gate line provides a gate drive signal to the sixth gate line in response to a received carry signal;

[0103] In the first shift circuit, the shift register unit connected to the tenth gate line provides a gate drive signal to the tenth gate line in response to a received carry signal;

[0104] In the second shift circuit, the shift register unit connected to the fourteenth gate line provides a gate drive signal to the fourteenth gate line in response to a received carry signal;

[0105] In the third shift circuit, the shift register unit connected to the fourth gate line provides a gate drive signal to the fourth gate line in response to a received carry signal;

[0106] In the fourth shift circuit, the shift register unit connected to the eighth gate line provides a gate drive signal to the eighth gate line in response to a received carry signal;

[0107] In the third shift circuit, the shift register unit connected to the twelfth gate line provides a gate drive signal to the twelfth gate line in response to a received carry signal;

[0108] In the fourth shift circuit, the shift register unit connected to the sixteenth gate line provides a gate driving signal to the sixteenth gate line in response to a received carry signal.

[0109] In yet another aspect, a display device is provided, the display device comprising: a signal providing circuit, and the display substrate as described in the above aspect;

[0110] The signal providing circuit is connected to the start-up signal terminal in the display substrate, and is used for providing a start-up signal to the start-up signal terminal.

[0111] The beneficial effects of the technical solution provided by this application may at least include:

[0112] In summary, the embodiments of the present disclosure provide a display substrate and a driving method thereof, and a display device. Since in the display substrate, among the multiple pixels connected to each shift circuit, the colors of the pixels sharing the same data line are the same, and each shift circuit is connected to an enable signal terminal, the enable signal provided by the enable signal terminal can be flexibly controlled so that each data line can continuously provide data signals to pixels of the same color. In this way, when displaying a pure color picture, the number of potential flips on each data line is small, which effectively reduces the power consumption of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0113] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0114] Figure 1 is a structural schematic diagram of a display substrate provided by an embodiment of the present disclosure;

[0115] Figure 2 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure;

[0116] Figure 3 is a structural schematic diagram of another display substrate provided by an embodiment of the present disclosure;

[0117] Figure 4 is a structural schematic diagram of another display substrate provided by an embodiment of the present disclosure;

[0118] Figure 5 is a structural schematic diagram of another display substrate provided by an embodiment of the present disclosure;

[0119] Figure 6 is a structural schematic diagram of another display substrate provided by an embodiment of the present disclosure;

[0120] Figure 7 is a structural schematic diagram of another display substrate provided by an embodiment of the present disclosure;

[0121] Figure 8 is a structural schematic diagram of another display substrate provided by an embodiment of the present disclosure;

[0122] Fig. 9 is a signal timing diagram of a display substrate provided by an embodiment of the present disclosure;

[0123] Fig.10 is a signal timing diagram of another display substrate provided by an embodiment of the present disclosure;

[0124] Fig.11 is a waveform diagram of a data signal provided by a data line provided by an embodiment of the present disclosure;

[0125] Fig.12 It is a data signal waveform diagram provided by a data line in the related art;

[0126] Fig.13 is a flow chart of a method for driving a display substrate provided by an embodiment of the present disclosure;

[0127] Fig.14 It is a structural schematic diagram of a display device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0128] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0129] Figure 1 Schematic diagram of a display substrate provided by an embodiment of the present disclosure. Figure 1 As shown, the display substrate may include: a base substrate 01, a plurality of gate lines G1 to Gm, a plurality of data lines D1 to Dk, and a plurality of rows of pixels arranged in an array (not shown in the figure), where m and k are both integers greater than 0. Each row of pixels may include a plurality of pixel groups 02, each pixel group 02 may include two adjacent pixels 021 of different colors, and the two pixels 021 may be connected to different gate lines and the same data line, respectively. That is, referring to Figure 1 , a plurality of pixels 021 located in the same row may be connected to two gate lines, and two pixels 021 connected to the same data line may be connected to different gate lines, respectively.

[0130] For example, for the first pixel 021 and the second pixel 021 located in the first row and adjacent to each other, the first pixel 021 is connected to the first gate line G1, the second pixel 021 is connected to the second gate line G2, and the first pixel 021 and the second pixel 021 are both connected to the first data line D1. It can be seen that the number of data lines k required to be set in the display substrate is only 1 / 2 of the number of pixel columns, and accordingly, the number of leads in the binding area is relatively reduced, which is conducive to the realization of a narrow frame. Based on Figure 1 It can be seen from the connection method shown that the display substrate recorded in the embodiment of the present disclosure is a display substrate with a zigzag structure.

[0131] Optionally, the display substrate provided by the disclosed embodiment may also include: a plurality of shift circuits on the substrate substrate 01, each shift circuit may be connected to at least two gate lines in a plurality of gate lines with a start-up signal terminal respectively. Each shift circuit may be used to provide a gate drive signal to each connected gate line in response to the start-up signal provided by the start-up signal terminal. That is, each shift circuit may provide a gate drive signal to each connected gate line when the connected start-up signal terminal provides a start-up signal. In addition, in the disclosed embodiment, among the plurality of pixels 021 to which each shift circuit is connected, the colors of the respective pixels 021 connected to the same data line are the same.

[0132] For example, Figure 1The display substrate shown includes 4 shift circuits 03a, 03b, 03c and 03d, wherein two shift circuits 03a and 03c are located on one side of the gate line extension direction, and two shift circuits 03b and 03d are located on the other side of the gate line extension direction. The shift circuit 03a is connected to the start signal terminal STV1, the first gate line G1, the third gate line G3 and the m-1th gate line Gm-1 respectively, and the first gate line G1, the third gate line G3 and the m-1th gate line Gm-1 are connected to each pixel 021, that is, among the pixels 021 connected to the shift circuit 03a, the pixels 021 connected to the first data line D1 (that is, the pixel 021 located in the first row and the first column, the pixel 021 in the second row and the pixel 021 in the first column of the mth row) can all be red (red, R).

[0133] The shift circuit 03b is connected to the start signal terminal STV2, the second gate line G2, the fourth gate line G4 and the m-th gate line Gm, respectively, and the colors of the pixels 021 connected to the second gate line G2, the fourth gate line G4 and the m-th gate line Gm, that is, the pixels 021 connected to the shift circuit 03b, and the pixels 021 connected to the first data line D1 (that is, the pixel 021 located in the first row and second column, the pixel 021 in the second row and second column, and the pixel 021 in the m-th row and second column) can all be green (green, G).

[0134] The shift circuit 03c is connected to the start signal terminal STV3, the fifth gate line G5 and the seventh gate line G7 respectively, and the colors of the pixels 021 connected to the fifth gate line G5 and the seventh gate line G7, that is, the pixels 021 connected to the shift circuit 03c, and the pixels 021 connected to the second data line D2 (that is, the pixel 021 located in the third row and third column and the pixel 021 in the fourth row and third column) can all be blue (blue, B).

[0135] The shift circuit 03d is connected to the start signal terminal STV4, the sixth gate line G6 and the eighth gate line G8 respectively, and the colors of the pixels 021 connected to the sixth gate line G6 and the eighth gate line G8, that is, the pixels 021 connected to the shift circuit 03d, and the pixels 021 connected to the second data line D2 (that is, the pixel 021 located in the third row and fourth column and the pixel 021 in the fourth row and fourth column) can all be red R.

[0136] Of course, each of the four shift circuits 03a to 03d described above is not only related to Figure 1 Several grid lines are shown, and also connected to other Figure 1 The gate line connections not shown are not described here in detail.

[0137] Taking the shift circuit 03a connected to the start signal terminal STV1 as an example, when the start signal terminal STV1 provides a start signal, the shift circuit 03a can sequentially provide gate drive signals to the gate line G1, the gate line G3 and the gate line Gm-1, and then the first data line D1 can sequentially provide data signals to the pixel 021 in the first row and the first column, the pixel 021 in the second row and the pixel 021 in the first column of the mth row. Based on the above records, since the pixel 021 in the first row and the first column, the pixel 021 in the second row and the pixel 021 in the first column of the mth row have the same color, the first data line D1 can continuously provide data signals to the same color pixels. In this way, when displaying a pure color picture, the potential of the data signal provided by the first data line D1 does not need to be constantly flipped, which effectively reduces power consumption. The same is true for other data lines, which will not be repeated here.

[0138] In summary, the embodiment of the present disclosure adopts a display substrate. Since in the display substrate, among the multiple pixels connected to each shift circuit, the colors of the pixels sharing the same data line are the same, and each shift circuit is connected to an enable signal terminal, it is possible to flexibly control the enable signal provided by the enable signal terminal so that each data line can continuously provide data signals to pixels of the same color. In this way, when displaying a pure color picture, the number of potential flips on each data line is small, which effectively reduces the power consumption of the display device.

[0139] Figure 2 is a schematic diagram of the structure of another display substrate provided by an embodiment of the present disclosure. Figure 1 and Figure 2 It can be seen that the pixels 021 in the same row can be arranged in the first color, the second color and the third color in sequence. Optionally, the first color can be red R, the second color can be green G, and the third color can be blue B. That is, Figure 2 As shown, each row of pixels 021 in the display substrate may be arranged in sequence according to the colors of RG and B. Of course, the pixels in the display substrate are not limited to the three colors of RGB, and may also include other colors such as yellow (yello, Y) and white (white, W).

[0140] In addition, in two adjacent pixel groups 02 connected to the same data line, each pixel 021 may be located in different columns. Alternatively, in two adjacent pixel groups 02 connected to the same data line, at least two pixels 021 may be located in the same column.

[0141] For example, refer to Figure 2, taking the second data line D2 as an example, in the pixel groups 02 connected to the data line D2 and located in the first row and the second row, one pixel B in the pixel group 02 located in the first row is located in the third column, and another pixel R is located in the fourth column; one pixel R in the pixel group 02 located in the second row is located in the first column, and another pixel G is located in the second column. That is, they are located in different columns.

[0142] For the arrangement described above, each data line can be arranged in an arc shape on the base substrate 01. That is, each data line can include: multiple data line segments and multiple connecting line segments, wherein the two ends of each connecting line segment are respectively connected to two adjacent data line segments; each pixel group corresponds to a data line segment, and any two adjacent data line segments are respectively located between two pixels included in pixel groups of adjacent rows but different columns. In addition, the embodiments of the present disclosure do not limit the directions of the two adjacent openings of each data line arranged in an arc shape. The following embodiments are all based on Figure 2 The display substrate shown is taken as an example for description.

[0143] Combination Figure 1 , taking shift circuits 03a and 03b as an example, Figure 3 FIG. 2 shows a schematic diagram of another structure of a display substrate. Figure 3 It can be seen that each shift circuit may include: at least four shift register units, each of which may be connected to a gate line. Further, it can be seen that since the display substrate includes a total of m gate lines G1 to Gm, Figure 1 and Figure 3 , the display substrate may include a total of m shift register units GOA1 to GOAm, wherein the first shift register unit GOA1 may be connected to the first gate line G1, and so on.

[0144] Optionally, the number d of clock signal terminals connected to the multiple shift circuits in the display substrate may be an integer multiple of 4. That is, multiple rows of pixels in the display substrate may be driven by a phase clock that is an integer multiple of 4. Alternatively, the number of clock signal terminals connected to the multiple shift circuits may also be an integer multiple of 2.

[0145] For example, assuming that the number of clock signal terminals d connected to the multiple shift circuits is 16, then the multiple rows of pixels in the display substrate are driven by a 16-phase clock. Figure 4 and Figure 5 The display substrate shown is driven by a 16-phase clock, that is, starting from the first shift register unit GOA1, each adjacent 16 shift register units are sequentially connected to 16 clock signal terminals CLK1 to CLK16. The following embodiments of the present disclosure all take the 16-phase clock as an example to illustrate the display substrate.

[0146] Optional, combined Figure 1And the following Figures 6 to 8 It can be seen that the display substrate can include a total of four shift circuits: a first shift circuit 03a, a second shift circuit 03b, a third shift circuit 03c and a fourth shift circuit 03d. Moreover, the first shift circuit 03a and the second shift circuit 03b can be located on one side of the multiple rows of pixels 0, and the third shift circuit 03c and the fourth shift circuit 03d can be located on the other side of the multiple rows of pixels. Furthermore, a total of four start signal terminals STV1 to STV4 are included, the first shift circuit 03a is connected to the start signal terminal STV1, the second shift circuit 03b is connected to the start signal terminal STV3, the third shift circuit 03c is connected to the start signal terminal STV2, and the dead low shift circuit 03d is connected to the start signal terminal STV4.

[0147] Furthermore, reference Figure 6 and Figure 8 It can also be seen that at least four shift register units in each shift circuit can be divided into two shift register groups 031, and each shift register group 031 can include multiple shift register subgroups 0311. Each shift register group 031 can include multiple shift register units cascaded with each other, and each shift register subgroup 0311 can include two adjacent and cascaded shift register units. And the start signal terminal is only connected to one shift register unit in one shift register group 031. For example, Figure 7 and Figure 8 In the display substrate shown, in each shift register group 031, the first shift register unit (eg, GOA1, GOA9, GOA5 and GOA13) in the first shift register subgroup 0311 is connected to the start signal terminal.

[0148] It should be noted that, combined with Figure 6 and Figure 7 It can be seen that along the target direction from the first row to the last row, the multiple shift register subgroups 0311 in each shift register group 031 are arranged in sequence, and the two shift register units in each shift register subgroup 0311 are arranged in sequence. Accordingly, the first shift register subgroup 0311 in each shift register group 031 can refer to a shift register subgroup at the starting position of the target direction. For example, for the first shift register group 031 included in the shift circuit 03a, the first shift register subgroup 0311 included therein refers to the shift register subgroup including GOA1 and GOA3. The first shift register unit included in each shift register subgroup 0311 can refer to the shift register unit located at the starting position of the target direction. For example, for the shift register subgroup 0311 including GOA1 and GOA3, the first shift register unit included therein refers to GOA1.

[0149] Recombination Figures 6 to 8 , the 2n-1th shift register subgroup 0311 located on one side of the multiple rows of pixels may belong to the first shift circuit 03a, and the 2nth shift register subgroup 0311 located on one side of the multiple rows of pixels may belong to the second shift circuit 03b. The 2n-1th shift register subgroup 0311 located on the other side of the multiple rows of pixels may belong to the third shift circuit 03c, and the 2nth shift register subgroup 0311 located on the other side of the multiple rows of pixels may belong to the fourth shift circuit 03d, and n may be a positive integer. That is, the shift register subgroups 0311 located on the same side and with odd serial numbers may belong to the same shift circuit, and the shift register subgroups 0311 located on the same side and with even serial numbers may belong to the same shift circuit.

[0150] In this implementation, for the first shift circuit 03a and the second shift circuit 03b, the 4n-3rd shift register subgroup 0311 located on the side thereof may belong to one shift register group 031 in the first shift circuit 03a, and the 4n-1th shift register subgroup 0311 may belong to another shift register group 031 in the first shift circuit 03a. The 4n-2th shift register subgroup 0311 may belong to one shift register group 031 in the second shift circuit 03b, and the 4nth shift register subgroup 0311 may belong to another shift register group 031 in the second shift circuit 03b. For the third shift circuit 03c and the fourth shift circuit 03d, the 4n-3rd shift register subgroup 0311 located on the side thereof may belong to one shift register group 031 in the third shift circuit 03c, and the 4n-1th shift register subgroup 0311 may belong to another shift register group 031 in the third shift circuit 03c. The 4n-2th shift register subgroup 0311 may belong to one shift register group 031 in the fourth shift circuit 03d. The 4nth shift register subgroup 0311 may belong to another shift register group 031 in the fourth shift circuit 03d.

[0151] For example, refer to Figures 6 to 8, on the side where the first shift circuit 03a and the second shift circuit 03b are located, along the direction from the first row of pixels to the last row of pixels, the first shift register subgroup 0311 and the fifth shift register subgroup 0311 belong to a shift register group 031 in the first shift circuit 03a. The second shift register subgroup 0311 and the sixth shift register subgroup 0311 belong to a shift register group 031 in the second shift circuit 03b. The third shift register subgroup 0311 and the seventh shift register subgroup 0311 belong to another shift register group 031 in the first shift circuit 03a. The fourth shift register subgroup 0311 and the eighth shift register subgroup 0311 belong to another shift register group 031 in the second shift circuit 03b. Similarly, on the side where the third shift circuit 03c and the fourth shift circuit 03d are located, the first shift register subgroup 0311 and the fifth shift register subgroup 0311 belong to a shift register group 031 in the third shift circuit 03c. The second shift register subgroup 0311 and the sixth shift register subgroup 0311 belong to a shift register group 031 in the fourth shift circuit 03d. The third shift register subgroup 0311 and the seventh shift register subgroup 0311 belong to another shift register group 031 in the third shift circuit 03c. The fourth shift register subgroup 0311 and the eighth shift register subgroup 0311 belong to another shift register group 031 in the fourth shift circuit 03d.

[0152] For example, combining Figure 6 and Figure 7 In the display substrate shown, along the direction from the first row of pixels to the last row of pixels, taking the first shift register group 031 in the first shift circuit 03a as an example, the shift register units GOA1 and GOA3 included in the first shift register subgroup 0311 in the shift register group 031 are cascaded with each other, and the shift register unit GOA3 is cascaded with the shift register unit GOA17 in the second shift register subgroup 0311, and the shift register unit GOA17 is also cascaded with the shift register unit GOA19 in the second shift register subgroup 0311. In the shift register group 031, the first shift register unit GOA1 of the first shift register subgroup 0311 is connected to the start signal terminal STV1. And so on.

[0153] Optionally, in the embodiment of the present disclosure, the two shift register units in each shift register subgroup 0311 may be connected to the i-th gate line and the i+s-th gate line respectively, where i is a positive integer and s may be 1 or 2.

[0154] For example, Figure 4 , Figure 6 and Figure 7In the display substrate shown, s is 2. That is, the shift register units with odd numbers are located on the same side, and the shift register units with even numbers are located on the same side. In this way, the pixels in the same row can be driven simultaneously by the shift register units located on both sides. That is, the pixels in the same row are driven on both sides.

[0155] Assume that the shift register unit connected to the i-th gate line is the i-th shift register unit, and the number of clock signals d is 16. Then Figure 4 , Figure 6 and Figure 7 , the cascade relationship of the display substrate is described as follows:

[0156] The first shift register unit GOA1 and the third shift register unit GOA3 are cascaded to each other, and the first shift register unit GOA1 can be used to provide a carry signal to the third shift register unit GOA3. The third shift register unit can be used to provide a reset signal to the first shift register unit GOA1.

[0157] The third shift register unit GOA3 is also cascaded with the 1+16th, i.e., 17th, shift register unit (not shown in the figure), and the third shift register unit GOA3 can be used to provide a carry signal to the 17th shift register unit. The 17th shift register unit is used to provide a reset signal to the third shift register unit GOA3.

[0158] The fifth shift register unit GOA5 and the seventh shift register unit GOA7 are cascaded to each other, and the fifth shift register unit GOA5 can be used to provide a carry signal to the seventh shift register unit GOA7. The seventh shift register unit GOA7 can be used to provide a reset signal to the fifth shift register unit GOA5.

[0159] The 7th shift register unit GOA7 is also cascaded with the 5th+16th, i.e., 21st, shift register unit (not shown in the figure). The 7th shift register unit GOA7 can be used to provide a carry signal to the 21st shift register unit. The 21st shift register unit can be used to provide a reset signal to the 7th shift register unit GOA7.

[0160] The ninth shift register unit GOA9 and the eleventh shift register unit GOA11 are cascaded to each other, and the ninth shift register unit GOA9 is used to provide a carry signal to the eleventh shift register unit GOA11. The eleventh shift register unit GOA11 is used to provide a reset signal to the ninth shift register unit GOA9.

[0161] The 11th shift register unit GOA11 is also cascaded with the 9th+16th, i.e., the 25th shift register unit (not shown in the figure), and the 11th shift register unit GOA11 is used to provide a carry signal to the 25th shift register unit. The 25th shift register unit is used to provide a reset signal to the 11th shift register unit GOA11.

[0162] The 13th shift register unit GOA13 and the 15th shift register unit GOA15 are cascaded to each other, and the 13th shift register unit GOA13 is used to provide a carry signal to the 15th shift register unit GOA15. The 15th shift register unit GOA15 is used to provide a reset signal to the 13th shift register unit GOA13.

[0163] The 15th shift register unit GOA15 is also cascaded with the 13th+16th, i.e., the 29th shift register unit (not shown in the figure), and the 15th shift register unit GOA15 is used to provide a carry signal to the 29th shift register unit. The 29th shift register unit is used to provide a reset signal to the 15th shift register unit GOA15.

[0164] The second shift register unit GOA2 can be cascaded with the fourth shift register unit GOA4, and the second shift register unit GOA2 is used to provide a carry signal to the fourth shift register unit GOA4. The fourth shift register unit GOA4 is used to provide a reset signal to the second shift register unit GOA2.

[0165] The fourth shift register unit GOA4 is also cascaded with the 2nd+16th, i.e., the 18th shift register unit (not shown in the figure), and the fourth shift register unit GOA4 is used to provide a carry signal to the 18th shift register unit. The 18th shift register unit is used to provide a reset signal to the fourth shift register unit GOA4.

[0166] The sixth shift register unit GOA6 and the eighth shift register unit GOA8 are cascaded to each other, and the sixth shift register unit GOA6 is used to provide a carry signal to the eighth shift register unit GOA8. The eighth shift register unit GOA8 is used to provide a reset signal to the sixth shift register unit GOA6.

[0167] The 8th shift register unit GOA8 is also cascaded with the 6th+16th, i.e., the 22nd, shift register unit (not shown in the figure). The 8th shift register unit GOA8 can be used to provide a carry signal to the 22nd shift register unit. The 22nd shift register unit is used to provide a reset signal to the 8th shift register unit GOA8.

[0168] The tenth shift register unit GOA10 and the twelfth shift register unit GOA12 are cascaded to each other, and the tenth shift register unit GOA10 is used to provide a carry signal to the twelfth shift register unit GOA12. The twelfth shift register unit GOA12 is used to provide a reset signal to the tenth shift register unit GOA10.

[0169] The 12th shift register unit GOA12 is also cascaded with the 10+16th, i.e., 26th, shift register unit (not shown in the figure). The 12th shift register unit GOA12 is used to provide a carry signal to the 26th shift register unit. The 26th shift register unit is used to provide a reset signal to the 12th shift register unit GOA12.

[0170] The 14th shift register unit GOA14 and the 16th shift register unit GOA16 are cascaded to each other, and the 14th shift register unit GOA14 is used to provide a carry signal to the 16th shift register unit GOA16. The 16th shift register unit GOA16 is used to provide a reset signal to the 14th shift register unit GOA14.

[0171] The 16th shift register unit GOA16 is also cascaded with the 14th+16th, i.e., the 30th shift register unit (not shown in the figure), and the 16th shift register unit GOA16 is used to provide a carry signal to the 30th shift register unit. The 30th shift register unit is used to provide a reset signal to the 16th shift register unit GOA16.

[0172] For example, Figure 5 and Figure 8 In the display substrate shown, s is 1. In this way, pixels in the same row can be driven simultaneously by the shift register units located on the same side, that is, pixels in the same row are driven on the same side.

[0173] Assume that the shift register unit connected to the i-th gate line is the i-th shift register unit, and the number of clock signals d is 16. Then Figure 5 and Figure 8 , the cascade relationship of the display substrate is described as follows:

[0174] The first shift register unit GOA1 and the second shift register unit GOA2 are cascaded to each other, and the first shift register unit GOA1 can be used to provide a carry signal to the second shift register unit GOA2. The second shift register unit GOA2 can be used to provide a reset signal to the first shift register unit GOA1.

[0175] The second shift register unit GOA2 is also cascaded with the 1+16th, i.e., 17th, shift register unit (not shown in the figure), and the second shift register unit GOA2 can be used to provide a carry signal to the 17th shift register unit. The 17th shift register unit can be used to provide a reset signal to the second shift register unit GOA2.

[0176] The third shift register unit GOA3 and the fourth shift register unit GOA4 are cascaded to each other, and the third shift register unit GOA3 can be used to provide a carry signal to the fourth shift register unit GOA4. The fourth shift register unit GOA4 can be used to provide a reset signal to the third shift register unit GOA3.

[0177] The fourth shift register unit GOA4 is also cascaded with the 3+16th, i.e., the 19th shift register unit (not shown in the figure), and the fourth shift register unit GOA4 can be used to provide a carry signal to the 19th shift register unit. The 19th shift register unit can be used to provide a reset signal to the fourth shift register unit GOA4.

[0178] The fifth shift register unit GOA5 and the sixth shift register unit GOA6 are cascaded to each other, and the fifth shift register unit GOA5 can be used to provide a carry signal to the sixth shift register unit GOA6. The sixth shift register unit GOA6 can be used to provide a reset signal to the fifth shift register unit GOA5.

[0179] The sixth shift register unit GOA6 is also cascaded with the fifth + 16th, i.e., the 21st, shift register unit (not shown in the figure). The sixth shift register unit GOA6 can be used to provide a carry signal to the 21st shift register unit. The 21st shift register unit can be used to provide a reset signal to the sixth shift register unit GOA6.

[0180] The seventh shift register unit GOA7 and the eighth shift register unit GOA8 are cascaded to each other, and the seventh shift register unit GOA7 can be used to provide a carry signal to the eighth shift register unit GOA8. The eighth shift register unit GOA8 can be used to provide a reset signal to the seventh shift register unit GOA7.

[0181] The 8th shift register unit GOA8 is also cascaded with the 7th+16th, i.e., 23rd, shift register unit (not shown in the figure). The 8th shift register unit GOA8 can be used to provide a carry signal to the 23rd shift register unit. The 23rd shift register unit can be used to provide a reset signal to the 8th shift register unit GOA8.

[0182] The ninth shift register unit GOA9 and the tenth shift register unit GOA10 are cascaded to each other, and the ninth shift register unit GOA9 can be used to provide a carry signal to the tenth shift register unit GOA10. The tenth shift register unit GOA10 can be used to provide a reset signal to the ninth shift register unit GOA9.

[0183] The 10th shift register unit GOA10 is also cascaded with the 9th+16th, i.e., the 25th shift register unit (not shown in the figure), and the 10th shift register unit GOA10 can be used to provide a carry signal to the 25th shift register unit. The 25th shift register unit can be used to provide a reset signal to the 10th shift register unit GOA10.

[0184] The 11th shift register unit GOA11 and the 12th shift register unit GOA12 are cascaded with each other, and the 11th shift register unit GOA11 can be used to provide a carry signal to the 12th shift register unit GOA12. The 12th shift register unit GOA12 can be used to provide a reset signal to the 11th shift register unit GOA11.

[0185] The 12th shift register unit GOA12 is also cascaded with the 11th+16th, i.e., the 28th shift register unit (not shown in the figure), and the 12th shift register unit GOA12 can be used to provide a carry signal to the 28th shift register unit. The 28th shift register unit can be used to provide a reset signal to the 12th shift register unit GOA12.

[0186] The 13th shift register unit GOA13 and the 14th shift register unit GOA14 are cascaded with each other, and the 13th shift register unit GOA13 can be used to provide a carry signal to the 14th shift register unit GOA14. The 14th shift register unit GOA14 can be used to provide a reset signal to the 13th shift register unit GOA13.

[0187] The 14th shift register unit GOA14 is also cascaded with the 13th+16th, i.e., the 29th shift register unit (not shown in the figure), and the 14th shift register unit GOA14 can be used to provide a carry signal to the 29th shift register unit. The 29th shift register unit can be used to provide a reset signal to the 14th shift register unit GOA14.

[0188] The 15th shift register unit GOA15 and the 16th shift register unit GOA16 are cascaded to each other, and the 15th shift register unit GOA15 can be used to provide a carry signal to the 16th shift register unit GOA16. The 16th shift register unit GOA16 can be used to provide a reset signal to the 15th shift register unit GOA15.

[0189] The 16th shift register unit GOA16 is also cascaded with the 15+16th, i.e., the 31st, shift register unit (not shown in the figure). The 16th shift register unit GOA16 can be used to provide a carry signal to the 31st shift register unit. The 31st shift register unit can be used to provide a reset signal to the 16th shift register unit GOA16.

[0190] Combined with the above-mentioned embodiment, it can be known that cascading means that during scanning, the previous bit register unit provides a carry signal to the next bit register unit, and the next bit register unit provides a reset signal to the previous bit register unit. That is, the output end of the previous shift register unit is connected to the input end of the next shift register unit, and the output end of the next shift register unit is connected to the reset end of the previous shift register unit. In this way, when the potential of the output end of the previous shift register unit is an effective potential, the next shift register unit can be turned on, so the signal provided by the previous bit register unit to the next bit register unit is called a carry signal. When the potential of the output end of the next shift register unit is an effective potential, the reset end of the previous shift register unit begins to reduce the noise of the previous shift register unit, so the signal provided by the next bit register unit to the previous bit register unit is called a carry signal and a reset signal.

[0191] So, for Figure 7 For the display substrate shown, when the first shift register unit GOA1 provides a carry signal to the third shift register unit GOA3, the third shift register unit GOA3 provides a reset signal to the first shift register unit GOA1 and simultaneously provides a carry signal to the seventeenth shift register unit GOA17, and so on.

[0192] for Figure 8 Similarly for the display substrate shown, when the first shift register unit GOA1 provides a carry signal to the second shift register unit GOA2, the second shift register unit GOA2 provides a reset signal to the first shift register unit GOA1 and simultaneously provides a carry signal to the seventeenth shift register unit GOA17, and so on.

[0193] also, Figure 8 The display substrate is shown relative to Figure 7In the display substrate shown, since GOA1 and GOA2 are cascaded with each other, it can be determined that the clock signal potentials provided by every two adjacent clock signal terminals are complementary, thereby further determining that the adjustable range of the pixel charging time is large.

[0194] based on Figure 7 The display substrate shown, Fig. 9 A timing diagram is shown. Figure 8 The display substrate shown, Fig.10 shows another timing diagram. Fig. 9 and Fig.10 It can be seen from the timing diagrams shown that the start signal terminals STV1, STV3, STV2 and STV4 provide start signals in sequence, and CLK1, CLK5, CLK9, CLK13, CLK3, CLK7, CLK11, CLK15, CLK2, CLK6, CLK10, CL K14, CLK4, CLK8, CLK12 and CLK16 start to provide clock signals of effective potential in sequence.

[0195] So, for Figure 7 The display substrate shown, combined with Fig. 9 As can be seen from the timing diagram shown, when the start signal terminal STV1 provides a start signal of effective potential, GOA1 can be turned on first, until the clock signal provided by the clock signal terminal CLK1 connected to GOA1 becomes an effective potential, and GOA1 outputs a gate drive signal of effective potential to the first gate line G1. At the same time, GOA1 also provides a carry signal to GOA3, and GOA3 is turned on. In order to avoid GOA3 first providing a gate drive signal of effective potential to the third connected gate line G3, the clock signal provided by the clock signal terminal CLK3 connected to GOA3 remains at an invalid potential. And so on. Optionally, the effective potential can be a high potential relative to the invalid potential.

[0196] for Figure 8 The display substrate shown, combined with Fig.10 It can be seen from the timing diagram that when the start signal terminal S TV1 provides a start signal with an effective potential, GOA1 can be turned on first, until the clock signal provided by the clock signal terminal CLK1 connected to GOA1 becomes an effective potential, and GOA1 outputs a gate drive signal with an effective potential to the first gate line G1. At the same time, GOA1 also provides a carry signal to GOA2, GOA2 is turned on, and in order to prevent GOA2 from first providing a gate drive signal with an effective potential to the second gate line G2 connected to it, the clock signal provided by the clock signal terminal CLK2 remains at an invalid potential. And so on.

[0197] Combining the order of CLK1 to CLK16 providing valid points, it can be seen that no matter Fig. 9 still Fig.10The timing drive corresponds to the display substrate, and when scanning, the gate line scanning sequence can be realized in one cycle: G1—>G5—>G9—>G13—>G3—>G7—>G11—>G15—>G2—>G6—>G10—>G14—>G4—>G8—>G12—>G16. That is, every four shift register units in one cycle, the gate line starts scanning in a jump manner, rather than sequentially. Based on this gate line scanning sequence, it can be made Figure 3 The second data line D2, the third data line D3 and the fourth data line D4 in the display substrate shown provide data signals to the pixels of the following colors in sequence within one cycle:

[0198] D2: R->R->R->R->R->R->R->R->B->B->B->B->G->G->G->G;

[0199] D3: R->R->R->R->B->B->B->B->G->G->G->G->G->G->G->G;

[0200] D4: B->B->B->B->R->R->R->R->G->G->G->G->B->B->B->B.

[0201] Take the red screen as an example. Fig.11 FIG. 2 shows a timing diagram of the data line D2 in one cycle. Fig.11 It can be determined that when displaying a pure color image, the potential of the data signal provided by the data line D2 is reversed only twice. The same is true for other data lines.

[0202] However, if the scanning method of the related technology is adopted, that is, each gate line is controlled to be turned on in sequence, when the display substrate displays a pure color picture, Figure 3 The second data line D2, the third data line D3 and the fourth data line D4 in the display substrate shown provide data signals to the pixels of the following colors in sequence within one cycle:

[0203] D2: R->B->R->G->R->B->R->G->R->B->R->G->R->B->R->G;

[0204] D3: B->G->R->B->B->G->R->B->B->G->R->B->B->G->R->B;

[0205] D4: R->G->B->G->R->G->B->G->R->G->B->G->R->G->B->G.

[0206] Still taking the red screen as an example, Fig.12FIG. 2 shows a timing diagram of the data line D2 in a cycle in the related art. Fig.12 It can be determined that the potential of the data signal provided by the data line D2 flips 16 times in one cycle. In addition, combined with the above sequence of providing data signals, it can be determined that the potential of the data signal provided by the data line D3 flips 8 times in one cycle, and the potential of the data signal provided by the data line D4 flips 8 times in one cycle. The three data lines flip 32 times in total.

[0207] A flip can refer to: flipping from an effective potential to an invalid potential, or flipping from an invalid potential to an effective potential. Assuming the invalid potential is 0 volts (V) and the effective potential is 5V, then Fig.11 and Fig.12 It can be seen that the potential on each data line in the related art needs to be switched between 0V and 5V for many times. However, since the number of potential flips of the data signal provided by the data line provided by the embodiment of the present disclosure is reduced, the switching frequency of the potential between 0V and 5V is relatively low, and the power consumption is reduced.

[0208] Furthermore, if the conventional cascade method is used to implement the scanning sequence recorded in the embodiment of the present disclosure, it is necessary to set GOA1 to connect the first gate line G1, GOA2 to connect the fifth gate line G5, GOA3 to connect the ninth gate line G9, and so on. This connection method is relatively complex and difficult to implement. Therefore, the embodiment of the present disclosure sets Figure 7 or Figure 8 The shift register unit arrangement shown in the figure not only reduces the difficulty of wiring and the difficulty of implementation, but also reliably realizes the above Fig.11 The scanning method shown reduces power consumption.

[0209] Furthermore, combined with the final scan sequence “G1—>G5—>G9—>G13—>G3—>G7—>G11—>G15—>G2—>G6—>G10—>G14—>G4—>G8—>G12—>G16”, it can be seen that Figure 7 In the display substrate shown, it takes only 4 cycles from the start of G1 to the start of the cascaded G3; Figure 8 The display substrate shown in the figure requires 8 cycles from the start of G1 to the start of the cascaded G2. Therefore, Figure 7 Relative to Figure 8 In terms of arrangement, G1 has a shorter on-time and correspondingly lower power consumption.

[0210] In summary, the embodiment of the present disclosure adopts a display substrate. Since in the display substrate, among the multiple pixels connected to each shift circuit, the colors of the pixels sharing the same data line are the same, and each shift circuit is connected to an enable signal terminal, it is possible to flexibly control the enable signal provided by the enable signal terminal so that each data line can continuously provide data signals to pixels of the same color. In this way, when displaying a pure color picture, the number of potential flips on each data line is small, which effectively reduces the power consumption of the display device.

[0211] Fig.13 is a flow chart of a method for driving a display substrate provided by an embodiment of the present disclosure. The method can be used to drive Figures 1 to 8 Any of the display substrates shown. Fig.13 As shown, the method may include:

[0212] Step 1301: providing a start signal to each start signal terminal in the display substrate in sequence, and each shift circuit provides a gate driving signal to each gate line connected thereto in response to the start signal.

[0213] Step 1302: Provide a data signal to each data line, and each pixel emits light in response to a gate driving signal provided by the connected gate line and a data signal provided by the connected data line.

[0214] Optional, assuming that Figure 7 and Figure 8 As shown, the display substrate includes: a first shift circuit, a second shift circuit, a third shift circuit and a fourth shift circuit, a total of four shift circuits, wherein the first shift circuit and the second shift circuit are located on one side of the multiple rows of pixels, and the third shift circuit and the fourth shift circuit are located on the other side of the multiple rows of pixels. Fig. 9 and Fig.10 As can be seen from the timing diagram shown, providing the start signal to each start signal terminal in the display substrate in sequence may include: first providing the start signal to the two start signal terminals connected to the first shift circuit and the second shift circuit in sequence; and then providing the start signal to the two start signal terminals connected to the third shift circuit and the fourth shift circuit in sequence.

[0215] As an optional implementation, combining Figure 7 The display substrate shown, and Fig. 9 Corresponding to the timing diagram, step 1301 is described as follows. Step 1301 may include the following methods executed in sequence:

[0216] In the first shift circuit, the shift register unit GOA1 connected to the first gate line G1 provides a gate drive signal to the first gate line G1 in response to the start signal provided by the first start signal terminal STV1, and provides a carry signal to the shift register unit GOA3 connected to the third gate line G3.

[0217] In the second shift circuit, the shift register unit GOA5 connected to the fifth gate line G5 provides a gate drive signal to the fifth gate line G5 in response to the start signal provided by the third start signal terminal STV3, and provides a carry signal to the shift register unit GOA7 connected to the seventh gate line G7.

[0218] In the first shift circuit, the shift register unit GOA9 connected to the ninth gate line G9 provides a gate drive signal to the ninth gate line G9 in response to the start signal provided by the first start signal terminal STV1, and provides a carry signal to the shift register unit GOA11 connected to the eleventh gate line G11.

[0219] In the second shift circuit, the shift register unit GOA13 connected to the thirteenth gate line G13 provides a gate drive signal to the thirteenth gate line G13 in response to the start signal provided by the third start signal terminal STV3, and provides a carry signal to the shift register unit GOA15 connected to the fifteenth gate line G15.

[0220] In the first shift circuit, the shift register unit GOA3 connected to the third gate line G3 provides a gate driving signal to the third gate line G3 in response to the received carry signal.

[0221] In the second shift circuit, the shift register unit GOA7 connected to the seventh gate line G7 provides a gate driving signal to the seventh gate line G7 in response to the received carry signal.

[0222] In the first shift circuit, the shift register unit GOA11 connected to the eleventh gate line G11 provides a gate driving signal to the eleventh gate line G11 in response to the received carry signal.

[0223] In the second shift circuit, the shift register unit GOA15 connected to the fifteenth gate line G15 provides a gate driving signal to the fifteenth gate line G15 in response to the received carry signal.

[0224] In the third shift circuit, the shift register unit GOA2 connected to the second gate line G2 provides a gate drive signal to the second gate line G2 in response to the start signal provided by the second start signal terminal STV2, and provides a carry signal to the shift register unit GOA4 connected to the fourth gate line G4.

[0225] In the fourth shift circuit, the shift register unit GOA6 connected to the sixth gate line G6 provides a gate drive signal to the sixth gate line G6 in response to the start signal provided by the fourth start signal terminal STV4, and provides a carry signal to the shift register unit GOA8 connected to the eighth gate line G8.

[0226] In the third shift circuit, the shift register unit GOA10 connected to the tenth gate line G10 provides a gate drive signal to the tenth gate line G10 in response to the start signal provided by the second start signal terminal STV2, and provides a carry signal to the shift register unit GOA12 connected to the twelfth gate line G12.

[0227] In the fourth shift circuit, the shift register unit GOA14 connected to the fourteenth gate line G14 provides a gate drive signal to the fourteenth gate line G14 in response to the start signal provided by the fourth start signal terminal STV4, and provides a carry signal to the shift register unit GOA16 connected to the sixteenth gate line G16.

[0228] In the third shift circuit, the shift register unit GOA4 connected to the fourth gate line G4 provides a gate driving signal to the fourth gate line G4 in response to the received carry signal.

[0229] In the fourth shift circuit, the shift register unit GOA8 connected to the eighth gate line G8 provides a gate driving signal to the eighth gate line G8 in response to the received carry signal.

[0230] In the third shift circuit, the shift register unit GOA12 connected to the twelfth gate line G12 provides a gate driving signal to the twelfth gate line G12 in response to the received carry signal.

[0231] In the fourth shift circuit, the shift register unit GOA16 connected to the sixteenth gate line G16 provides a gate driving signal to the sixteenth gate line G16 in response to the received carry signal.

[0232] As another optional implementation, combining Fig. 9 The display substrate shown, and Fig.10 Corresponding to the timing diagram, step 1301 is described as follows. Step 1301 may include the following methods executed in sequence:

[0233] In the first shift circuit, the shift register unit GOA1 connected to the first gate line G1 provides a gate drive signal to the first gate line G1 in response to the start signal provided by the first start signal terminal STV1, and provides a carry signal to the shift register unit GOA2 connected to the second gate line G2.

[0234] In the second shift circuit, the shift register unit GOA5 connected to the fifth gate line G5 provides a gate drive signal to the fifth gate line G5 in response to the start signal provided by the third start signal terminal STV3, and provides a carry signal to the shift register unit GOA6 connected to the sixth gate line G6.

[0235] In the first shift circuit, the shift register unit GOA9 connected to the ninth gate line G9 provides a gate drive signal to the ninth gate line G9 in response to the start signal provided by the first start signal terminal STV1, and provides a carry signal to the shift register unit GOA10 connected to the tenth gate line G10.

[0236] In the second shift circuit, the shift register unit GOA13 connected to the thirteenth gate line G13 provides a gate drive signal to the thirteenth gate line G13 in response to the start signal provided by the third start signal terminal STV3, and provides a carry signal to the shift register unit GOA14 connected to the fourteenth gate line G14.

[0237] In the third shift circuit, the shift register unit GOA3 connected to the third gate line G3 provides a gate drive signal to the third gate line G3 in response to the start signal provided by the second start signal terminal STV2, and provides a carry signal to the shift register unit GOA4 connected to the fourth gate line G4.

[0238] In the fourth shift circuit, the shift register unit GOA7 connected to the seventh gate line G7 provides a gate drive signal to the seventh gate line G7 in response to the start signal provided by the fourth start signal terminal STV4, and provides a carry signal to the shift register unit GOA8 connected to the eighth gate line G8.

[0239] In the third shift circuit, the shift register unit GOA11 connected to the eleventh gate line G11 provides a gate drive signal to the eleventh gate line G11 in response to the start signal provided by the second start signal terminal STV2, and provides a carry signal to the shift register unit GOA12 connected to the twelfth gate line G12.

[0240] In the fourth shift circuit, the shift register unit GOA15 connected to the fifteenth gate line G15 provides a gate drive signal to the fifteenth gate line G15 in response to the start signal provided by the fourth start signal terminal STV4, and provides a carry signal to the shift register unit GOA16 connected to the sixteenth gate line G16.

[0241] In the first shift circuit, the shift register unit GOA2 connected to the second gate line G2 provides a gate driving signal to the second gate line G2 in response to the received carry signal.

[0242] In the second shift circuit, the shift register unit GOA6 connected to the sixth gate line G6 provides a gate driving signal to the sixth gate line G6 in response to the received carry signal.

[0243] In the first shift circuit, the shift register unit GOA10 connected to the tenth gate line G10 provides a gate driving signal to the tenth gate line G10 in response to the received carry signal.

[0244] In the second shift circuit, the shift register unit GOA14 connected to the fourteenth gate line G14 provides a gate driving signal to the fourteenth gate line G14 in response to the received carry signal.

[0245] In the third shift circuit, the shift register unit GOA4 connected to the fourth gate line G4 provides a gate driving signal to the fourth gate line G4 in response to the received carry signal.

[0246] In the fourth shift circuit, the shift register unit GOA8 connected to the eighth gate line G8 provides a gate driving signal to the eighth gate line G8 in response to the received carry signal.

[0247] In the third shift circuit, the shift register unit GOA12 connected to the twelfth gate line G12 provides a gate driving signal to the twelfth gate line G12 in response to the received carry signal.

[0248] In the fourth shift circuit, the shift register unit GOA16 connected to the sixteenth gate line G16 provides a gate driving signal to the sixteenth gate line G16 in response to the received carry signal.

[0249] Combined with the above description of step 1301, it can be seen that whether Figure 7 The display substrate (ie, Fig. 9 timing shown), or Figure 8 The display substrate (ie, Fig.10 The timing shown in the figure can realize that the gate line scanning sequence in one cycle is:

[0250] G1—>G5—>G9—>G13—>G3—>G7—>G11—>G15—>G2—>G6—>G10—>G14—>G4—>G8—>G12—>G16.

[0251] In summary, the embodiment of the present disclosure adopts a driving method of a display substrate, because each shift circuit can respond to a start signal to provide a gate drive signal to each gate line connected thereto, and in the display substrate, among the multiple pixels connected to each shift circuit, the colors of the pixels sharing the same data line are the same, and each shift circuit is connected to an start signal terminal, so that each data line can continuously provide a data signal to pixels of the same color by flexibly controlling the start signal provided by the start signal terminal. In this way, when displaying a pure color picture, the number of potential flips on each data line is small, which effectively reduces the power consumption of the display device.

[0252] Fig.14 Schematic diagram of a display device provided by an embodiment of the present disclosure. Fig.14 As shown, the display device may include: a signal providing circuit 100, and Figures 1 to 8 Any of the display substrates 200 shown. The signal providing circuit 100 may be connected to the start signal terminal in the display substrate 200, and may be used to provide a start signal to the start signal terminal.

[0253] Optionally, the display device may be an organic light-emitting diode (OLED) display device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a navigator, or any other product or component with a display function.

[0254] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A display substrate, characterized in that: The display substrate comprises: substrate substrate; A plurality of gate lines, a plurality of data lines and a plurality of rows of pixels arranged in an array are located on the substrate, each row of the pixels includes a plurality of pixel groups, each of the pixel groups includes two adjacent pixels of different colors, and the two pixels are connected to different gate lines and the same data line; A plurality of shift circuits located on the substrate, each of the shift circuits being connected to an enable signal terminal and at least two gate lines of the plurality of gate lines, and each of the shift circuits being used to provide a gate drive signal to each of the connected gate lines in response to an enable signal provided by the enable signal terminal; Among the plurality of pixels connected to each of the shift circuits, the colors of the pixels connected to the same data line are the same; And, each of the shift circuits comprises: at least four shift register units, each of the shift register units is connected to a gate line, and the at least four shift register units in each of the shift circuits can be divided into two shift register groups; wherein each of the shift register groups comprises a plurality of the shift register units connected in cascade, and one of the shift register units in each of the shift register groups is connected to the start signal terminal; Furthermore, each of the shift register groups includes a plurality of shift register subgroups, each of the shift register subgroups includes two adjacent and cascaded shift register units, and the two shift register units in each of the shift register subgroups are respectively connected to the adjacent i-th gate line and i+s-th gate line, where i is a positive integer and s is 1 or 2; The number d of clock signal terminals connected to the plurality of shift circuits in the display substrate is an integer multiple of 4.

2. The display substrate according to claim 1, characterized in that: The number d of clock signal terminals connected to the plurality of shift circuits in the display substrate is 16.

3. The display substrate according to claim 2, characterized in that: The plurality of shift circuits include: a first shift circuit, a second shift circuit, a third shift circuit and a fourth shift circuit, a total of four shift circuits; The first shift circuit and the second shift circuit are located on one side of the multiple rows of pixels, and the third shift circuit and the fourth shift circuit are located on the other side of the multiple rows of pixels.

4. The display substrate according to claim 3, characterized in that: The 2n-1th shift register subgroup located on one side of the plurality of rows of pixels belongs to the first shift circuit, and the 2nth shift register subgroup located on one side of the plurality of rows of pixels belongs to the second shift circuit, where n is a positive integer; The 2n-1th shift register subgroup located on the other side of the multiple rows of pixels belongs to the third shift circuit, and the 2nth shift register subgroup located on the other side of the multiple rows of pixels belongs to the fourth shift circuit.

5. The display substrate according to claim 4, characterized in that: The 4n-3rd shift register subgroup located on one side of the plurality of rows of pixels belongs to one shift register group in the first shift circuit, and the 4n-1th shift register subgroup located on one side of the plurality of rows of pixels belongs to another shift register group in the first shift circuit; The 4n-2 th shift register subgroup located on one side of the plurality of rows of pixels belongs to one shift register group in the second shift circuit; the 4n th shift register subgroup located on one side of the plurality of rows of pixels belongs to another shift register group in the second shift circuit; The 4n-3rd shift register subgroup located on the other side of the plurality of rows of pixels belongs to one shift register group in the third shift circuit, and the 4n-1st shift register subgroup located on the other side of the plurality of rows of pixels belongs to another shift register group in the third shift circuit; The 4n-2 th shift register subgroup located on the other side of the multiple rows of pixels belongs to one shift register group in the fourth shift circuit; the 4n th shift register subgroup located on the other side of the multiple rows of pixels belongs to another shift register group in the fourth shift circuit.

6. The display substrate according to any one of claims 2 to 5, characterized in that: s is 2, and the shift register unit connected to the i-th gate line is the i-th shift register unit; The first shift register unit and the third shift register unit are cascaded with each other, the first shift register unit is used to provide a carry signal to the third shift register unit; the third shift register unit is used to provide a reset signal to the first shift register unit; The third shift register unit is also cascaded with the 1+dth shift register unit, and the third shift register unit is used to provide a carry signal to the 1+dth shift register unit; the 1+dth shift register unit is used to provide a reset signal to the third shift register unit; The fifth shift register unit and the seventh shift register unit are cascaded with each other, the fifth shift register unit is used to provide a carry signal to the seventh shift register unit; the seventh shift register unit is used to provide a reset signal to the fifth shift register unit; The 7th shift register unit is also cascaded with the 5+dth shift register unit, the 7th shift register unit is used to provide a carry signal to the 5+dth shift register unit; the 5+dth shift register unit is used to provide a reset signal to the 7th shift register unit; The 9th shift register unit and the 11th shift register unit are cascaded with each other, the 9th shift register unit is used to provide a carry signal to the 11th shift register unit; the 11th shift register unit is used to provide a reset signal to the 9th shift register unit; The 11th shift register unit is also cascaded with the 9+dth shift register unit, the 11th shift register unit is used to provide a carry signal to the 9+dth shift register unit; the 9+dth shift register unit is used to provide a reset signal to the 11th shift register unit; The 13th shift register unit and the 15th shift register unit are cascaded with each other, the 13th shift register unit is used to provide a carry signal to the 15th shift register unit; the 15th shift register unit is used to provide a reset signal to the 13th shift register unit; The 15th shift register unit is also cascaded with the 13+dth shift register unit, the 15th shift register unit is used to provide a carry signal to the 13+dth shift register unit; the 13+dth shift register unit is used to provide a reset signal to the 15th shift register unit; The second shift register unit and the fourth shift register unit are cascaded with each other, the second shift register unit is used to provide a carry signal to the fourth shift register unit; the fourth shift register unit is used to provide a reset signal to the second shift register unit; The fourth shift register unit is also cascaded with the 2+dth shift register unit, the fourth shift register unit is used to provide a carry signal to the 2+dth shift register unit; the 2+dth shift register unit is used to provide a reset signal to the fourth shift register unit; The sixth shift register unit and the eighth shift register unit are cascaded with each other, the sixth shift register unit is used to provide a carry signal to the eighth shift register unit; the eighth shift register unit is used to provide a reset signal to the sixth shift register unit; The 8th shift register unit is also cascaded with the 6+dth shift register unit, the 8th shift register unit is used to provide a carry signal to the 6+dth shift register unit; the 6+dth shift register unit is used to provide a reset signal to the 8th shift register unit; The tenth shift register unit and the twelfth shift register unit are cascaded with each other, the tenth shift register unit is used to provide a carry signal to the twelfth shift register unit; the twelfth shift register unit is used to provide a reset signal to the tenth shift register unit; The 12th shift register unit is also cascaded with the 10+dth shift register unit, the 12th shift register unit is used to provide a carry signal to the 10+dth shift register unit; the 10+dth shift register unit is used to provide a reset signal to the 12th shift register unit; The 14th shift register unit and the 16th shift register unit are cascaded with each other, the 14th shift register unit is used to provide a carry signal to the 16th shift register unit; the 16th shift register unit is used to provide a reset signal to the 14th shift register unit; The 16th shift register unit is also cascaded with the 14+dth shift register unit, and the 16th shift register unit is used to provide a carry signal to the 14+dth shift register unit; the 14+dth shift register unit is used to provide a reset signal to the 16th shift register unit.

7. The display substrate according to any one of claims 2 to 5, characterized in that: s is 1, the shift register unit connected to the i-th gate line is the i-th shift register unit; The first shift register unit and the second shift register unit are cascaded with each other, the first shift register unit is used to provide a carry signal to the second shift register unit; the second shift register unit is used to provide a reset signal to the first shift register unit; The second shift register unit is also cascaded with the 1+dth shift register unit, the second shift register unit is used to provide a carry signal to the 1+dth shift register unit; the 1+dth shift register unit is used to provide a reset signal to the second shift register unit; The third shift register unit and the fourth shift register unit are cascaded with each other, the third shift register unit is used to provide a carry signal to the fourth shift register unit; the fourth shift register unit is used to provide a reset signal to the third shift register unit; The fourth shift register unit is also cascaded with the 3+dth shift register unit, the fourth shift register unit is used to provide a carry signal to the 3+dth shift register unit; the 3+dth shift register unit is used to provide a reset signal to the fourth shift register unit; The fifth shift register unit and the sixth shift register unit are cascaded with each other, the fifth shift register unit is used to provide a carry signal to the sixth shift register unit; the sixth shift register unit is used to provide a reset signal to the fifth shift register unit; The sixth shift register unit is also cascaded with the fifth + dth shift register unit, the sixth shift register unit is used to provide a carry signal to the fifth + dth shift register unit; the fifth + dth shift register unit is used to provide a reset signal to the sixth shift register unit; The seventh shift register unit and the eighth shift register unit are cascaded with each other, the seventh shift register unit is used to provide a carry signal to the eighth shift register unit; the eighth shift register unit is used to provide a reset signal to the seventh shift register unit; The 8th shift register unit is also cascaded with the 7+dth shift register unit, the 8th shift register unit is used to provide a carry signal to the 7+dth shift register unit; the 7+dth shift register unit is used to provide a reset signal to the 8th shift register unit; The 9th shift register unit and the 10th shift register unit are cascaded with each other, the 9th shift register unit is used to provide a carry signal to the 10th shift register unit; the 10th shift register unit is used to provide a reset signal to the 9th shift register unit; The 10th shift register unit is also cascaded with the 9+dth shift register unit, the 10th shift register unit is used to provide a carry signal to the 9+dth shift register unit; the 9+dth shift register unit is used to provide a reset signal to the 10th shift register unit; The 11th shift register unit and the 12th shift register unit are cascaded with each other, the 11th shift register unit is used to provide a carry signal to the 12th shift register unit; the 12th shift register unit is used to provide a reset signal to the 11th shift register unit; The 12th shift register unit is also cascaded with the 11+dth shift register unit, the 12th shift register unit is used to provide a carry signal to the 11+dth shift register unit; the 11+dth shift register unit is used to provide a reset signal to the 12th shift register unit; The 13th shift register unit and the 14th shift register unit are cascaded with each other, the 13th shift register unit is used to provide a carry signal to the 14th shift register unit; the 14th shift register unit is used to provide a reset signal to the 13th shift register unit; The 14th shift register unit is also cascaded with the 13+dth shift register unit, the 14th shift register unit is used to provide a carry signal to the 13+dth shift register unit; the 13+dth shift register unit is used to provide a reset signal to the 14th shift register unit; The 15th shift register unit and the 16th shift register unit are cascaded with each other, the 15th shift register unit is used to provide a carry signal to the 16th shift register unit; the 16th shift register unit is used to provide a reset signal to the 15th shift register unit; The 16th shift register unit is also cascaded with the 15+dth shift register unit, and the 16th shift register unit is used to provide a carry signal to the 15+dth shift register unit; the 15+dth shift register unit is used to provide a reset signal to the 16th shift register unit.

8. The display substrate according to any one of claims 3 to 5, characterized in that: The display substrate comprises: a first start-up signal terminal, a second start-up signal terminal, a third start-up signal terminal and a fourth start-up signal terminal, a total of four start-up signal terminals; In the first shift circuit, the first shift register unit in the first shift register subgroup and the first shift register unit in the second shift register subgroup are connected to the first start signal terminal; In the second shift circuit, the first shift register unit in the first shift register subgroup and the first shift register unit in the second shift register subgroup are connected to the third start signal terminal; In the third shift circuit, the first shift register unit in the first shift register subgroup and the first shift register unit in the second shift register subgroup are connected to the second start signal terminal; In the fourth shift circuit, the first shift register unit in the first shift register subgroup and the first shift register unit in the second shift register subgroup are connected to the fourth start signal terminal.

9. The display substrate according to any one of claims 1 to 5, characterized in that: The pixels in the same row are arranged in sequence according to the first color, the second color and the third color, and the pixels in the same column have the same color.

10. The display substrate according to claim 9, characterized in that: In two adjacent pixel groups connected to the same data line, each pixel is located in a different column.

11. The display substrate according to claim 10, characterized in that: Each of the data lines comprises: a plurality of data line segments and a plurality of connection line segments; Wherein, both ends of each connecting line segment are respectively connected to two adjacent data line segments; each pixel group corresponds to one data line segment, and any two adjacent data line segments are respectively located between two pixels included in pixel groups in adjacent rows but different columns.

12. The display substrate according to claim 9, characterized in that: In two adjacent pixel groups connected to the same data line, at least two pixels are located in the same column.

13. A method for driving a display substrate, characterized in that: For driving the display substrate according to any one of claims 1 to 12, the method comprising: sequentially providing a start signal to each start signal terminal in the display substrate, and each of the shift circuits provides a gate drive signal to each of the gate lines connected thereto in response to the start signal; A data signal is provided to each data line in the display substrate, and each pixel in the display substrate emits light in response to a gate driving signal provided by the connected gate line and a data signal provided by the connected data line.

14. The method according to claim 13, characterized in that The display substrate comprises: four shift circuits, namely, a first shift circuit, a second shift circuit, a third shift circuit and a fourth shift circuit, and four start signal terminals, namely, a first start signal terminal, a second start signal terminal, a third start signal terminal and a fourth start signal terminal; wherein, the first start signal terminal is connected to the first shift circuit, the third start signal terminal is connected to the second shift circuit, the second start signal terminal is connected to the third shift circuit, and the fourth start signal terminal is connected to the fourth shift circuit; The step of sequentially providing a start signal to each start signal terminal in the display substrate comprises: An on signal is provided to the first on signal terminal, the third on signal terminal, the second on signal terminal and the fourth on signal terminal in sequence.

15. The method according to claim 14, characterized in that Each of the shift circuits comprises at least four shift register units, each of the shift register units is connected to a gate line, and the at least four shift register units in each of the shift circuits can be divided into two shift register groups; each of the shift register groups comprises a plurality of cascaded shift register units, and one of the shift register units in each of the shift register groups is connected to the start signal terminal; each of the shift register groups comprises a plurality of shift register subgroups, each of the shift register subgroups comprises two adjacent and cascaded shift register units, and the two shift register units in each of the shift register subgroups are respectively connected to the adjacent i-th gate line and i+2-th gate line, where i is a positive integer; Each of the shift circuits provides a gate drive signal to each of the gate lines connected thereto in response to the start signal, including the following steps performed in sequence: In the first shift circuit, the shift register unit connected to the first gate line provides a gate drive signal to the first gate line in response to the start signal provided by the first start signal terminal, and provides a carry signal to the shift register unit connected to the third gate line; In the second shift circuit, the shift register unit connected to the fifth gate line provides a gate drive signal to the fifth gate line in response to the start signal provided by the third start signal terminal, and provides a carry signal to the shift register unit connected to the seventh gate line; In the first shift circuit, the shift register unit connected to the ninth gate line provides a gate drive signal to the ninth gate line in response to the start signal provided by the first start signal terminal, and provides a carry signal to the shift register unit connected to the eleventh gate line; In the second shift circuit, the shift register unit connected to the thirteenth gate line provides a gate drive signal to the thirteenth gate line in response to the start signal provided by the third start signal terminal, and provides a carry signal to the shift register unit connected to the fifteenth gate line; In the first shift circuit, the shift register unit connected to the third gate line provides a gate drive signal to the third gate line in response to a received carry signal; In the second shift circuit, the shift register unit connected to the seventh gate line provides a gate drive signal to the seventh gate line in response to a received carry signal; In the first shift circuit, the shift register unit connected to the eleventh gate line provides a gate drive signal to the eleventh gate line in response to a received carry signal; In the second shift circuit, the shift register unit connected to the fifteenth gate line provides a gate drive signal to the fifteenth gate line in response to a received carry signal; In the third shift circuit, the shift register unit connected to the second gate line provides a gate drive signal to the second gate line in response to the start signal provided by the second start signal terminal, and provides a carry signal to the shift register unit connected to the fourth gate line; In the fourth shift circuit, the shift register unit connected to the sixth gate line provides a gate drive signal to the sixth gate line in response to the start signal provided by the fourth start signal terminal, and provides a carry signal to the shift register unit connected to the eighth gate line; In the third shift circuit, the shift register unit connected to the tenth gate line provides a gate drive signal to the tenth gate line in response to the start signal provided by the second start signal terminal, and provides a carry signal to the shift register unit connected to the twelfth gate line; In the fourth shift circuit, the shift register unit connected to the fourteenth gate line provides a gate drive signal to the fourteenth gate line in response to the start signal provided by the fourth start signal terminal, and provides a carry signal to the shift register unit connected to the sixteenth gate line; In the third shift circuit, the shift register unit connected to the fourth gate line provides a gate drive signal to the fourth gate line in response to a received carry signal; In the fourth shift circuit, the shift register unit connected to the eighth gate line provides a gate drive signal to the eighth gate line in response to a received carry signal; In the third shift circuit, the shift register unit connected to the twelfth gate line provides a gate drive signal to the twelfth gate line in response to a received carry signal; In the fourth shift circuit, the shift register unit connected to the sixteenth gate line provides a gate driving signal to the sixteenth gate line in response to a received carry signal.

16. The method according to claim 14, characterized in that Each of the shift circuits comprises at least four shift register units, each of the shift register units is connected to a gate line, and the at least four shift register units in each of the shift circuits can be divided into two shift register groups; each of the shift register groups comprises a plurality of the shift register units in cascade connection, and one of the shift register units in each of the shift register groups is connected to the start signal terminal; each of the shift register groups comprises a plurality of shift register subgroups, each of the shift register subgroups comprises two adjacent and cascaded shift register units, and the two shift register units in each of the shift register subgroups are respectively connected to the adjacent i-th gate line and i+1-th gate line, where i is a positive integer; Each of the shift circuits provides a gate drive signal to each of the gate lines connected thereto in response to the start signal, including the following steps performed in sequence: In the first shift circuit, the shift register unit connected to the first gate line provides a gate drive signal to the first gate line in response to the start signal provided by the first start signal terminal, and provides a carry signal to the shift register unit connected to the second gate line; In the second shift circuit, the shift register unit connected to the fifth gate line provides a gate drive signal to the fifth gate line in response to the start signal provided by the third start signal terminal, and provides a carry signal to the shift register unit connected to the sixth gate line; In the first shift circuit, the shift register unit connected to the ninth gate line provides a gate drive signal to the ninth gate line in response to the start signal provided by the first start signal terminal, and provides a carry signal to the shift register unit connected to the tenth gate line; In the second shift circuit, the shift register unit connected to the thirteenth gate line provides a gate drive signal to the thirteenth gate line in response to the start signal provided by the third start signal terminal, and provides a carry signal to the shift register unit connected to the fourteenth gate line; In the third shift circuit, the shift register unit connected to the third gate line provides a gate drive signal to the third gate line in response to the start signal provided by the second start signal terminal, and provides a carry signal to the shift register unit connected to the fourth gate line; In the fourth shift circuit, the shift register unit connected to the seventh gate line provides a gate drive signal to the seventh gate line in response to the start signal provided by the fourth start signal terminal, and provides a carry signal to the shift register unit connected to the eighth gate line; In the third shift circuit, the shift register unit connected to the eleventh gate line provides a gate drive signal to the eleventh gate line in response to the start signal provided by the second start signal terminal, and provides a carry signal to the shift register unit connected to the twelfth gate line; In the fourth shift circuit, the shift register unit connected to the fifteenth gate line provides a gate drive signal to the fifteenth gate line in response to the start signal provided by the fourth start signal terminal, and provides a carry signal to the shift register unit connected to the sixteenth gate line; In the first shift circuit, the shift register unit connected to the second gate line provides a gate drive signal to the second gate line in response to a received carry signal; In the second shift circuit, the shift register unit connected to the sixth gate line provides a gate drive signal to the sixth gate line in response to a received carry signal; In the first shift circuit, the shift register unit connected to the tenth gate line provides a gate drive signal to the tenth gate line in response to a received carry signal; In the second shift circuit, the shift register unit connected to the fourteenth gate line provides a gate drive signal to the fourteenth gate line in response to a received carry signal; In the third shift circuit, the shift register unit connected to the fourth gate line provides a gate drive signal to the fourth gate line in response to a received carry signal; In the fourth shift circuit, the shift register unit connected to the eighth gate line provides a gate drive signal to the eighth gate line in response to a received carry signal; In the third shift circuit, the shift register unit connected to the twelfth gate line provides a gate drive signal to the twelfth gate line in response to a received carry signal; In the fourth shift circuit, the shift register unit connected to the sixteenth gate line provides a gate driving signal to the sixteenth gate line in response to a received carry signal.

17. A display device, characterized in that: The display device comprises: a signal providing circuit, and a display substrate as claimed in any one of claims 1 to 12; The signal providing circuit is connected to the start-up signal terminal in the display substrate, and is used for providing a start-up signal to the start-up signal terminal.

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