Gate driving circuit and display device

Abstract

The present disclosure relates to a gate drive circuit and a display device including the gate drive circuit. The gate drive circuit includes: a first gate drive circuit and a second gate drive circuit, wherein the m first clock signals input to the first gate drive circuit include the (n+1)th clock signal and the (n+k)th clock signal, and the m second clock signals input to the second gate drive circuit include the (n+2)th clock signal and the (n+k+1)th clock signal, wherein n is an arbitrary integer, k is a natural number of 3 or greater, the high level voltage duration of the (n+1)th clock signal does not overlap with the high level voltage duration of the (n+k)th clock signal, and the high level voltage duration of the (n+2)th clock signal does not overlap with the high level voltage duration of the (n+k+1)th clock signal. Since the gate drive circuit has a clock input structure capable of reducing the output characteristic difference between the gate signals, the image quality can be improved.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority benefit of Korean Patent Application No. 10-2020-0183696 filed in the Korean Intellectual Property Office on December 24, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a gate driving circuit and a display device including the gate driving circuit. Background Art

[0004] With the development of information society, the demand for display devices for displaying images has increased. In order to meet this demand, various display devices such as liquid crystal display (LCD) devices, electroluminescent display (ELD) devices including quantum dot light-emitting display devices and organic light-emitting display (e.g., OLED) devices, etc. have been developed and widely used recently.

[0005] Typically, a display device charges a capacitor disposed in each of a plurality of sub-pixels arranged on a display panel and uses the charged capacitor for display driving. However, in such a conventional display device, such a capacitor in each sub-pixel may be insufficiently charged, thereby deteriorating image quality.

[0006] In a conventional display device, if the size of the non-display area of ​​the display panel can be reduced, the design freedom of the display device can be increased and the design quality can be improved. However, since various lines and circuit elements are arranged in the non-display area of ​​the display panel, it is not easy to actually reduce the size of the non-display area of ​​the display panel.

[0007] Furthermore, in the case of such a conventional display device, insufficient charging time may cause image quality to deteriorate, and in addition, gate driving may malfunction due to a difference in output characteristics between gate signals, which causes image quality to deteriorate. Summary of the invention

[0008] Embodiments of the present disclosure provide a gate driving circuit having a clock input structure capable of reducing output characteristic differences between gate signals, thereby improving image quality, and a display device including the same.

[0009] Embodiments of the present disclosure provide a gate driving circuit having a clock input structure capable of realizing overlapping gate driving and a Q-node sharing structure while reducing output characteristic differences between gate signals, and a display device including the same.

[0010] According to various aspects of the present disclosure, a display device is provided, comprising: a display panel including a plurality of gate lines; and a gate driving circuit, the gate driving circuit comprising: a first gate driving circuit, the first gate driving circuit being capable of outputting m first gate signals using a first clock signal group; and a second gate driving circuit, the second gate driving circuit being capable of outputting m second gate signals using a second clock signal group different from the first clock signal group, wherein m is a natural number of 2 or greater.

[0011] The first clock signal group and the second clock signal group may respectively include m first clock signals and m second clock signals, and the 2m clock signals including the m first clock signals included in the first clock signal group and the m second clock signals included in the second clock signal group may have respective high-level voltage durations at different timings.

[0012] The first gate driving circuit may include: m first output buffer circuits receiving the m first clock signals and outputting the m first gate signals; and a first control circuit capable of controlling the m first output buffer circuits.

[0013] The second gate driving circuit may include: m second output buffer circuits receiving the m second clock signals and outputting the m second gate signals; and a second control circuit capable of controlling the m second output buffer circuits.

[0014] Each of the m first output buffer circuits may include a pull-up transistor and a pull-down transistor, and all corresponding gate nodes of the respective pull-up transistors included in the m first output buffer circuits may be electrically connected to one first Q node.

[0015] Each of the m second output buffer circuits may include a pull-up transistor and a pull-down transistor, and all corresponding gate nodes of the respective pull-up transistors included in the m second output buffer circuits may be electrically connected to one second Q node.

[0016] The m first clock signals input to the first gate driving circuit may include an (n+1)th clock signal and an (n+k)th clock signal, and the m second clock signals input to the second gate driving circuit may include an (n+2)th clock signal and an (n+k+1)th clock signal, where n is an arbitrary integer and k is a natural number of 3 or greater.

[0017] The high level voltage duration of the (n+1)th clock signal may partially overlap with the high level voltage duration of the (n+2)th clock signal. The high level voltage duration of the (n+k)th clock signal may partially overlap with the high level voltage duration of the (n+k+1)th clock signal.

[0018] The high level voltage duration of the (n+1)th clock signal may not overlap with the high level voltage duration of the (n+k)th clock signal. The high level voltage duration of the (n+2)th clock signal may not overlap with the high level voltage duration of the (n+k+1)th clock signal.

[0019] In the case where k=3, the m first output buffer circuits included in the first gate driving circuit may include: a first output buffer circuit that receives the (n+1)th clock signal and outputs the (n+1)th gate signal, and another first output buffer circuit that receives the (n+3)th clock signal and outputs the (n+3)th gate signal. The m second output buffer circuits included in the second gate driving circuit may include: a second output buffer circuit that receives the (n+2)th clock signal and outputs the (n+2)th gate signal, and another second output buffer circuit that receives the (n+4)th clock signal and outputs the (n+4)th gate signal.

[0020] When k=3, the (n+1)th gate signal may be applied to the (n+1)th gate line, the (n+3)th gate signal may be applied to the (n+3)th gate line, the (n+2)th gate signal may be applied to the (n+2)th gate line, and the (n+4)th gate signal may be applied to the (n+4)th gate line.

[0021] In this case, the display panel may include at least one of the following connecting lines: a connecting line connected between the one first output buffer outputting the (n+1)th gate signal and the (n+1)th gate line set in the display panel, a connecting line connected between the other first output buffer outputting the (n+3)th gate signal and the (n+3)th gate line set in the display panel, a connecting line connected between the one second output buffer outputting the (n+2)th gate signal and the (n+2)th gate line set in the display panel, and a connecting line connected between the other second output buffer outputting the (n+4)th gate signal and the (n+4)th gate line set in the display panel.

[0022] When k=3, the (n+1)th gate signal may be applied to the (n+1)th gate line, the (n+3)th gate signal may be applied to the (n+2)th gate line, the (n+2)th gate signal may be applied to the (n+1+m)th gate line, and the (n+4)th gate signal may be applied to the (n+2+m)th gate line.

[0023] In the case where k=3 and m=4, the m first output buffer circuits included in the first gate driving circuit may include: another first output buffer circuit that receives the (n+5)th clock signal and outputs the (n+5)th gate signal, and another first output buffer circuit that receives the (n+7)th clock signal and outputs the (n+7)th gate signal. The m second output buffer circuits included in the second gate driving circuit may include: another second output buffer circuit that receives the (n+6)th clock signal and outputs the (n+6)th gate signal, and another second output buffer circuit that receives the (n+8)th clock signal and outputs the (n+8)th gate signal.

[0024] When k=3 and m=4, the (n+1)th gate signal may be applied to the (n+1)th gate line, the (n+3)th gate signal may be applied to the (n+3)th gate line, the (n+5)th gate signal may be applied to the (n+5)th gate line, the (n+7)th gate signal may be applied to the (n+7)th gate line, the (n+2)th gate signal may be applied to the (n+2)th gate line, the (n+4)th gate signal may be applied to the (n+4)th gate line, the (n+6)th gate signal may be applied to the (n+6)th gate line, and the (n+8)th gate signal may be applied to the (n+8)th gate line.

[0025] In this case, the display panel may include at least one of the following connection lines: a connection line connected between the one first output buffer outputting the (n+1)th gate signal and the (n+1)th gate line provided in the display panel, a connection line connected between the another first output buffer outputting the (n+3)th gate signal and the (n+3)th gate line provided in the display panel, a connection line connected between the further one first output buffer outputting the (n+5)th gate signal and the (n+5)th gate line provided in the display panel, a connection line connected between the further one first output buffer outputting the (n+7)th gate signal and the (n+8)th gate line provided in the display panel, +7) gate lines, a connecting line connected between the one second output buffer outputting the (n+2)th gate signal and the (n+2)th gate line arranged in the display panel, a connecting line connected between the other second output buffer outputting the (n+4)th gate signal and the (n+4)th gate line arranged in the display panel, a connecting line connected between the still another second output buffer outputting the (n+6)th gate signal and the (n+6)th gate line arranged in the display panel, and a connecting line connected between the still another second output buffer outputting the (n+8)th gate signal and the (n+8)th gate line arranged in the display panel.

[0026] When k=3 and m=4, the (n+1)th gate signal may be applied to the (n+1)th gate line, the (n+3)th gate signal may be applied to the (n+2)th gate line, the (n+5)th gate signal may be applied to the (n+3)th gate line, the (n+7)th gate signal may be applied to the (n+4)th gate line, the (n+2)th gate signal may be applied to the (n+1+m)th gate line, the (n+4)th gate signal may be applied to the (n+2+m)th gate line, the (n+6)th gate signal may be applied to the (n+3+m)th gate line, and the (n+8)th gate signal may be applied to the (n+4+m)th gate line.

[0027] The first gate driving circuit may output the (n+1)th gate signal based on the (n+1)th clock signal and output the (n+k)th gate signal based on the (n+k)th clock signal. The second gate driving circuit may output the (n+2)th gate signal based on the (n+2)th clock signal and output the (n+k+1)th gate signal based on the (n+k+1)th clock signal.

[0028] The on-level voltage duration of the (n+1)th gate signal may partially overlap with the on-level voltage duration of the (n+2)th gate signal, and the on-level voltage duration of the (n+1)th gate signal may not overlap with the on-level voltage duration of the (n+k)th gate signal.

[0029] According to various aspects of the present disclosure, a gate driving circuit capable of driving a plurality of gate lines disposed in a display panel is provided, wherein the gate driving circuit has the same structure as the gate driving circuit included in the above-mentioned display device.

[0030] According to an embodiment of the present disclosure, a gate driving circuit having a clock input structure capable of reducing output characteristic differences between gate signals, thereby improving image quality, and a display device including the same may be provided.

[0031] According to an embodiment of the present disclosure, a gate driving circuit having a clock input structure capable of realizing overlapping gate driving and Q-node sharing structure while reducing output characteristic differences between gate signals and a display device including the same may be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of the present disclosure, illustrate various aspects of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0033] Figure 1 illustrates a system configuration of a display device according to various aspects of the present disclosure;

[0034] Figure 2A and Figure 2B An equivalent circuit of a sub-pixel of a display device according to various aspects of the present disclosure is illustrated;

[0035] Figure 3 An exemplary system implementation of a display device according to various aspects of the present disclosure is illustrated;

[0036] Figure 4 is a block diagram of a gate driving circuit of a display device according to various aspects of the present disclosure;

[0037] Figure 5 A gate driving circuit having a first clock input structure included in a display device according to various aspects of the present disclosure is illustrated;

[0038] Fig. 6A Illustrated when using Figure 5The gate driving circuit shown in is 4 clock signals input to the first gate driving circuit, and the voltage fluctuation at the Q node of the first gate driving circuit;

[0039] Figure 6B Illustrated when using Figure 5 The gate driving circuit shown in is 4 gate signals output from the first gate driving circuit;

[0040] Fig. 7A A gate driving circuit having a second clock input structure included in a display device according to various aspects of the present disclosure is illustrated;

[0041] Figure 7B Illustrated input to Fig. 7A A clock signal of the gate drive circuit shown in ;

[0042] Figure 8 More detailed map Fig. 7A The gate drive circuit shown in;

[0043] Fig. 9 Illustrated Fig. 7A An example of a gate drive circuit is shown in;

[0044] Fig.10 More detailed map Fig. 9 The gate drive circuit shown in;

[0045] Fig.11A Illustrated when using Fig. 9 The gate driving circuit shown in FIG. 1 is four clock signals input to the first gate driving circuit, and the voltage fluctuation at the Q1 node of the first gate driving circuit;

[0046] Fig. 11B Illustrated when using Fig. 9 The gate driving circuit shown in is 4 gate signals output from the first gate driving circuit;

[0047] Fig. 11C Illustrated when using Fig. 9 The gate driving circuit shown in is 4 clock signals input to the second gate driving circuit, and the voltage fluctuation at the Q2 node of the second gate driving circuit;

[0048] Fig.11D Illustrated when using Fig. 9 The gate driving circuit shown in is 4 gate signals output from the second gate driving circuit;

[0049] Fig.12illustrates simulation results for detecting output characteristics of each of a first clock input structure and a second clock input structure used in a gate driving circuit of a display device according to various aspects of the present disclosure;

[0050] Fig.13 Illustrated Fig.10 An exemplary implementation of the gate drive circuit shown in ;

[0051] Fig.14 Schematic diagram Fig.10 The gate drive circuit shown in;

[0052] Fig.15 and Fig.16 Illustrated Fig.14 A connection structure between a gate driving circuit and a gate line arranged in a display area;

[0053] Fig.17 Illustrated Fig. 7A An example of a gate drive circuit is shown in . DETAILED DESCRIPTION

[0054] In the following description of the embodiments or implementations of the present disclosure, reference will be made to the accompanying drawings, in which specific embodiments or implementations that can be implemented are shown by way of example, and the same reference numerals and symbols may be used in the accompanying drawings to refer to the same or similar parts, even if they are shown in different drawings from each other. In addition, in the following description of the embodiments or implementations of the present disclosure, when it is determined that the detailed description of the known functions and components combined herewith will make the subject matter in some embodiments of the present disclosure unclear, its detailed description will be omitted. Terms such as "including", "having", "comprising", "consisting of", "consisting of", and "formed of" used herein are generally intended to allow the addition of other components, unless the terms use the term "only". As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0055] Terms such as "first", "second", "A", "B", "(A)", and "(B)" may be used herein to describe elements of the present disclosure. Each of these terms is not used to limit the nature, order, sequence, or quantity of the elements, etc., but is only used to distinguish the corresponding element from other elements.

[0056] When it is mentioned that a first element is “connected or combined”, “contacted or overlapped”, etc. with a second element, it should be interpreted that the first element may not only be “directly connected or combined” or “directly contacted or overlapped” with the second element, but also a third element may be “interposed” between the first element and the second element, or the first element and the second element may be “connected or combined”, “contacted or overlapped”, etc. with each other via a fourth element. Here, the second element may be included in at least one of the two or more elements that are “connected or combined”, “contacted or overlapped”, etc. with each other.

[0057] When time relative terms such as "after", "subsequently", "next", "before", etc. are used to describe a process or operation of an element or construction, or a flow and step in an operating method, a processing method, or a manufacturing method, these terms can be used to describe non-continuous or non-sequential processes or operations unless the terms "directly" or "immediately" are used together.

[0058] In addition, when any scale, relative size, etc. is mentioned, even if no relevant description is specified, it should be considered that the numerical value (e.g., level, range, etc.) of the element or feature or corresponding information includes tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external impacts, noise, etc.). In addition, the term "may" fully encompasses all meanings of the term "can".

[0059] Figure 1 A system configuration of a display device 100 according to various aspects of the present disclosure is illustrated.

[0060] Reference Figure 1 , a display device 100 according to various aspects of the present disclosure includes a display panel 110 and a driving circuit driving the display panel 110 .

[0061] The driving circuit may include a data driving circuit 120 and a gate driving circuit 130 , etc., and may further include a controller 140 that controls the data driving circuit 120 and the gate driving circuit 130 .

[0062] The display panel 110 may include a substrate SUB and signal lines such as a plurality of data lines DL, a plurality of gate lines GL, etc. disposed on the substrate SUB. The display panel 110 may include a plurality of sub-pixels SP connected to the plurality of gate lines GL and the plurality of data lines DL.

[0063] The display panel 110 may include a display area DA that displays an image and a non-display area NDA that does not display an image, which is different from the display area DA. In the display panel 110, a plurality of sub-pixels SP for displaying an image may be disposed in the display area DA, and the driving circuits 120, 130, and 140 may be electrically connected to the non-display area NDA or may be installed in the non-display area NDA. A pad portion connected to an integrated circuit or a printed circuit may be disposed in the non-display area NDA of the display panel 110.

[0064] The data driving circuit 120 is a circuit for driving a plurality of data lines DL, and may provide data signals to the plurality of data lines DL. The gate driving circuit 130 is a circuit for driving a plurality of gate lines GL, and may provide gate signals to the plurality of gate lines GL. The controller 140 may provide a data control signal DCS to the data driving circuit 120 so as to control the operation timing of the data driving circuit 120. The controller 140 may provide a gate control signal GCS to the gate driving circuit 130 so as to control the operation timing of the gate driving circuit 130.

[0065] The controller 140 can start a scanning operation according to the timing implemented in each frame, convert the image data input from other devices or other image supply sources (for example, a host system) into a data signal form used in the data driving circuit 120, and then provide the converted image data Data to the data driving circuit 120, and control the loading of data to at least one pixel at a predetermined time according to the scanning timing.

[0066] In addition to input image data, the controller 140 may also receive various timing signals including a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, an input data enable signal DE, a clock signal CLK, etc. from other devices, networks, or systems (eg, the host system 150 ).

[0067] In order to control the data driving circuit 120 and the gate driving circuit 130, the controller 140 can receive one or more timing signals such as a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, an input data enable signal DE, a clock signal CLK, etc., generate various control signals (DCS, GCS), and provide the generated signals to the data driving circuit 120 and the gate driving circuit 130.

[0068] The controller 140 may be implemented as a separate component from the data driving circuit 120 , or may be integrated with the data driving circuit 120 to be implemented as an integrated circuit.

[0069] The data driving circuit 120 may drive the plurality of data lines DL by receiving the image data Data from the controller 140 and providing the plurality of data lines DL with data voltages. Here, the data driving circuit 120 may also be referred to as a source driving circuit.

[0070] The data driving circuit 120 may include one or more source driver integrated circuits SDIC. Each source driver integrated circuit SDIC may include a shift register, a latch circuit, a digital-to-analog converter DAC, an output buffer, etc. In some cases, each source driver integrated circuit SDIC may further include an analog-to-digital converter ADC.

[0071] In some embodiments, each source driver integrated circuit SDIC can be connected to the display panel 110 in a tape automated bonding (TAB) manner, or can be connected to a conductive pad such as a bonding pad of the display panel 110 in a chip on glass (COG) manner or a chip on panel (COP) manner, or can be connected to the display panel 110 in a chip on film (COF) manner.

[0072] The gate driving circuit 130 may output a gate signal of an on-level voltage or a gate signal of an off-level voltage according to the control of the controller 140. The gate driving circuit 130 may sequentially drive the plurality of gate lines GL by sequentially providing the gate signal of an on-level voltage to the plurality of gate lines GL.

[0073] In some embodiments, the gate driving circuit 130 may be connected to the display panel 110 in a tape automated bonding (TAB) manner, or may be connected to a conductive pad such as a bonding pad of the display panel 110 in a chip on glass (COG) manner or a chip on panel (COP) manner, or may be connected to the display panel 110 in a chip on film (COF) manner. In another embodiment, the gate driving circuit 130 may be located in a non-display area NDA of the display panel 110 in a gate in panel (GIP) manner. The gate driving circuit 130 may be disposed on or above the substrate SUB, or connected to the substrate SUB. That is, in the case of the GIP manner, the gate driving circuit 130 may be disposed in the non-display area NDA of the substrate SUB. In the case of a chip on glass (COG) manner, a chip on film (COF) manner, etc., the gate driving circuit 130 may be connected to the substrate SUB.

[0074] At least one of the data driving circuit 120 and the gate driving circuit 130 may be disposed in the display area DA. For example, at least one of the data driving circuit 120 and the gate driving circuit 130 may be disposed not to overlap with the subpixels SP, or to overlap with one or more or all of the subpixels SP.

[0075] When a specific gate line is selected by the gate driving circuit 130 , the data driving circuit 120 may convert the image data Data received from the controller 140 into a data voltage in an analog form and provide the converted data voltage to the plurality of data lines DL.

[0076] The data driving circuit 120 may be located on only one portion (e.g., the upper portion or the lower portion) of the display panel 110, but is not limited thereto. In some embodiments, the data driving circuit 120 may be located on two portions (e.g., the upper portion and the lower portion) of the display panel 110 or at least two of the four portions (e.g., the upper portion, the lower portion, the left side, and the right side) of the display panel 110, but is not limited thereto, depending on a driving method, a panel design method, etc.

[0077] The gate driving circuit 130 may be located on only one portion (e.g., the left side or the right side) of the display panel 110, but is not limited thereto. In some embodiments, the gate driving circuit 130 may be located on two portions (e.g., the left side and the right side) of the display panel 110 or at least two of the four portions (e.g., the upper portion, the lower portion, the left side, and the right side) of the display panel 110, but is not limited thereto, depending on a driving method, a panel design method, etc.

[0078] The controller 140 may be a timing controller used in general display technology, or a control device / apparatus capable of additionally performing other control functions in addition to the general functions of the timing controller. In some embodiments, the controller 140 may be one or more other control circuits different from the circuits or components in the timing controller or the control device / apparatus. The controller 140 may be implemented using, for example, an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a processor, or the like.

[0079] The controller 140 may be mounted on a printed circuit board, a flexible printed circuit, or the like, and may be electrically connected to the data driving circuit 120 and the gate driving circuit 130 through the printed circuit board, the flexible printed circuit, or the like.

[0080] The controller 140 may send signals to and receive signals from the data driving circuit 120 via one or more predetermined interfaces. In some embodiments, such interfaces may include a low voltage differential signaling (LVDS) interface, an EPI interface, a serial peripheral interface (SPI), etc. The controller 140 may include a storage medium such as one or more registers.

[0081] The display device 100 according to various aspects of the present disclosure may be a display including a backlight unit such as a liquid crystal display device, or may be a self-luminous display such as an organic light emitting diode (OLED) display, a quantum dot (QD) display, a micro light emitting diode (M-LED) display, etc.

[0082] In the case where the display device 100 according to various aspects of the present disclosure is an OLED display, each sub-pixel SP may include a self-luminous OLED as a light-emitting element. In the case where the display device 100 according to various aspects of the present disclosure is a QD display, each sub-pixel may include a light-emitting element including quantum dots, which are self-luminous semiconductor crystals. In the case where the display device 100 according to various aspects of the present disclosure is a micro-LED display, each sub-pixel SP may include a self-luminous and inorganic material-based micro-LED as a light-emitting element.

[0083] Figure 2A and Figure 2B An exemplary equivalent circuit of a sub-pixel SP of the display device 100 according to various aspects of the present disclosure is illustrated.

[0084] Reference Figure 2A Each of a plurality of sub-pixels SP provided in the display panel 110 of the display device 100 according to various aspects of the present disclosure may include a light emitting element ED, a driving transistor DRT, a scanning transistor SCT, and a storage capacitor Cst.

[0085] Reference Figure 2A The light emitting element ED may include a pixel electrode PE and a common electrode CE, and include a light emitting layer EL located between the pixel electrode PE and the common electrode CE.

[0086] The pixel electrode PE of the light emitting element ED may be an electrode provided in each sub-pixel SP, and the common electrode CE may be an electrode provided in common in all sub-pixels SP or some sub-pixels SP. Here, the pixel electrode PE may be an anode electrode, and the common electrode CE may be a cathode electrode. In another embodiment, the pixel electrode PE may be a cathode electrode, and the common electrode CE may be an anode electrode.

[0087] In one embodiment, the light emitting element ED may be an organic light emitting diode (OLED), a light emitting diode (LED), a quantum dot light emitting element, or the like.

[0088] The driving transistor DRT is a transistor that drives the light emitting element ED, and may include a first node N1, a second node N2, a third node N3, and the like.

[0089] The first node N1 of the driving transistor DRT may be a gate node of the driving transistor DRT and may be electrically connected to a source node or a drain node of the scanning transistor SCT. The second node N2 of the driving transistor DRT may be a source node or a drain node of the driving transistor DRT. The second node N2 may also be electrically connected to a source node or a drain node of the sensing transistor SENT and may be connected to a pixel electrode PE of the light emitting element ED. The third node N3 of the driving transistor DRT may be electrically connected to a driving voltage line DVL that provides a driving voltage EVDD.

[0090] The scanning transistor SCT may be controlled by a scanning signal SCAN (a gate signal) and may be connected between the first node N1 of the driving transistor DRT and the data line DL. In other words, the scanning transistor SCT may be turned on or off according to the scanning signal SCAN provided through the scanning signal line SCL (a gate line GL), and may control the electrical connection between the data line DL and the first node N1 of the driving transistor DRT.

[0091] The scan transistor SCT is turned on by the scan signal SCAN having an on-level voltage, and transmits the data voltage Vdata provided through the data line DL to the first node N1 of the driving transistor DRT.

[0092] In one embodiment, when the scan transistor SCT is an n-type transistor, the on-level voltage of the scan signal SCAN may be a high level voltage. In another embodiment, when the scan transistor SCT is a p-type transistor, the on-level voltage of the scan signal SCAN may be a low level voltage.

[0093] The storage capacitor Cst may be connected between the first node N1 and the second node N2 of the driving transistor DRT. The storage capacitor Cst may store a charge amount corresponding to the voltage difference between the two ends and maintain the voltage difference between the two ends for a predetermined frame time. Therefore, the corresponding subpixel SP may emit light within a predetermined frame time.

[0094] Each of the plurality of sub-pixels SP provided in the display panel 110 of the display device 100 according to various aspects of the present disclosure may further include a sensing transistor SENT.

[0095] The sensing transistor SENT may be controlled by a sensing signal SENSE (another gate signal) and may be connected between the second node N2 of the driving transistor DRT and the reference voltage line RVL. In other words, the sensing transistor SENT may be turned on or off according to the sensing signal SENSE provided through the sensing signal line SENL (another gate line GL) and control the electrical connection between the reference voltage line RVL and the second node N2 of the driving transistor DRT.

[0096] The sensing transistor SENT may be turned on by the sensing signal SENSE having an on-level voltage and transfer the reference voltage Vref transmitted through the reference voltage line RVL to the second node N2 of the driving transistor DRT.

[0097] In addition, the sensing transistor SENT may be turned on by the sensing signal SENSE having the on-level voltage and transmit the voltage at the second node N2 of the driving transistor DRT to the reference voltage line RVL.

[0098] In one embodiment, when the sensing transistor SENT is an n-type transistor, the on-level voltage of the sensing signal SENSE may be a high level voltage. In another embodiment, when the sensing transistor SENT is a p-type transistor, the on-level voltage of the sensing signal SENSE may be a low level voltage.

[0099] When driving to sense at least one characteristic value of the sub-pixel SP, the function of transmitting the voltage at the second node N2 of the driving transistor DRT to the reference voltage line RVL can be used by the sensing transistor SENT. In this case, the voltage transmitted to the reference voltage line RVL can be a voltage for calculating at least one characteristic value of the sub-pixel SP or a voltage reflected by at least one characteristic value of the sub-pixel SP.

[0100] Herein, the characteristic value of the subpixel SP may be a characteristic value of the driving transistor DRT or the light emitting element ED. At least one characteristic value of the driving transistor DRT may include a threshold voltage and / or mobility of the driving transistor DRT. The characteristic value of the light emitting element ED may include a threshold voltage of the light emitting element ED.

[0101] The driving transistor DRT, the scanning transistor SCT and the sensing transistor SENT may be n-type transistors, p-type transistors or a combination thereof. Herein, for ease of description, it is assumed that the driving transistor DRT, the scanning transistor SCT and the sensing transistor SENT are n-type transistors.

[0102] The storage capacitor Cst may be an external capacitor intentionally designed to be located outside the driving transistor DRT, rather than an internal capacitor formed between the gate node and the source node (or drain node) of the driving transistor DRT, such as a parasitic capacitor (eg, Cgs, Cgd).

[0103] The scanning signal line SCL and the sensing signal line SENL may be different gate lines GL. In some embodiments, the scanning signal SCAN and the sensing signal SENSE may be separate gate signals, and the on-off timing of the scanning transistor SCT and the on-off timing of the sensing transistor SENT in one sub-pixel SP may be independent. That is, the on-off timing of the scanning transistor SCT and the on-off timing of the sensing transistor SENT in one sub-pixel SP may be the same as or different from each other.

[0104] In another embodiment, the scanning signal line SCL and the sensing signal line SENL may be the same gate line GL. That is, the gate node of the scanning transistor SCT and the gate node of the sensing transistor SENT in one sub-pixel SP may be connected to one gate line GL. In this embodiment, the scanning signal SCAN and the sensing signal SENSE may be the same gate signal, and the on-off timing of the scanning transistor SCT and the on-off timing of the sensing transistor SENT in one sub-pixel SP may be the same.

[0105] It should be understood that Figure 2A and Figure 2B The sub-pixel structure shown in is only an example of a possible sub-pixel structure for ease of description, and the embodiments of the present disclosure may be implemented in any various structures as required. For example, the sub-pixel SP may further include at least one transistor and / or at least one capacitor.

[0106] In addition, although it is assumed that the display device 100 is a self-luminous display device Figure 2A and Figure 2B However, when the display device 100 is a liquid crystal display, each sub-pixel SP may include a transistor, a pixel electrode, etc.

[0107] Figure 3 An exemplary system implementation of the display device 100 according to various aspects of the present disclosure is illustrated.

[0108] Reference Figure 3 , the display device 100 may include a display area DA where an image is displayed and a non-display area NDA where no image is displayed.

[0109] Reference Figure 3 When the data driving circuit 120 includes one or more source driver integrated circuits SDIC and is implemented in a chip on film (COF) manner, each source driver integrated circuit SDIC may be mounted on a circuit film SF connected to the non-display area NDA of the display panel 110 .

[0110] Reference Figure 3, the gate driving circuit 130 may be implemented in a gate-in-panel (GIP) manner. In this embodiment, the gate driving circuit 130 may be located in the non-display area NDA of the display panel 110. In another embodiment, Figure 3 Unlike shown in , the gate driving circuit 130 can be implemented in a chip on film (COF) manner.

[0111] The display device 100 may include: at least one source printed circuit board SPCB for circuit connection between one or more source driver integrated circuits SDIC and other devices, components, etc.; and a control printed circuit board CPCB on which a control component and various electronic devices or components are mounted.

[0112] The circuit film SF on which the source driver integrated circuit SDIC is mounted may be connected to at least one source printed circuit board SPCB. That is, one side of the circuit film SF on which the source driver integrated circuit SDIC is mounted may be electrically connected to the display panel 110 and the other side thereof may be electrically connected to the source printed circuit board SPCB.

[0113] The controller 140 and the power management integrated circuit PMIC 310 may be mounted on the control printed circuit board CPCB. The controller 140 may perform an overall control function related to the driving of the display panel 110 and control the operations of the data driving circuit 120 and the gate driving circuit 130. The power management integrated circuit 310 may provide various voltages or currents to the data driving circuit 120 and the gate driving circuit 130 or control various voltages or currents to be provided.

[0114] The circuit connection between the at least one source printed circuit board SPCB and the control printed circuit board CPCB may be performed through at least one connection cable CBL. The connection cable CBL may be, for example, a flexible printed circuit FPC, a flexible flat cable FFC, or the like.

[0115] At least one source printed circuit board SPCB and the control printed circuit board CPCB may be integrated to be implemented as one printed circuit board.

[0116] The display device 100 according to various aspects of the present disclosure may further include a level converter 300 for adjusting a voltage level. In one embodiment, the level converter 300 may be disposed on the control printed circuit board CPCB or the source printed circuit board SPCB.

[0117] In the display device 100 according to various aspects of the present disclosure, the level converter 300 may provide a signal required for gate driving to the gate driving circuit 130. In one embodiment, the level converter 300 may provide a plurality of clock signals to the gate driving circuit 130. Therefore, the gate driving circuit 130 may provide a plurality of gate signals to the plurality of gate lines GL based on the plurality of clock signals input from the level converter 300. The plurality of gate lines GL may transmit the gate signals to the sub-pixels SP disposed in the display area DA of the substrate SUB.

[0118] Figure 4 is a block diagram of a gate driving circuit 130 of a display device 100 according to various aspects of the present disclosure.

[0119] Reference Figure 4 The gate driving circuit 130 included in the display device 100 according to various aspects of the present disclosure may be a circuit capable of driving a plurality of gate lines GL disposed on the display panel 110, generating a plurality of gate signals using a plurality of clock signals, and providing the generated gate signals to the plurality of gate lines GL.

[0120] The gate driving circuit 130 may include: a first gate driving circuit GDC1, the first gate driving circuit GDC1 uses a first clock signal group CSG1 to output m gate signals; and a second gate driving circuit GDC2, the second gate driving circuit GDC2 uses a second clock signal group CSG2 different from the first clock signal group CSG1 to output m gate signals, where m is a natural number of 2 or greater.

[0121] Each of the first clock signal group CSG1 and the second clock signal group CSG2 may include m clock signals, where m is a natural number of 2 or more.

[0122] The first gate driving circuit GDC1 and the second gate driving circuit GDC2 may generate and output Figure 2A and Figure 2B Therefore, the m gate signals output from each of the first gate driving circuit GDC1 and the second gate driving circuit GDC2 may be the scanning signal SCAN.

[0123] In another embodiment, the first gate driving circuit GDC1 and the second gate driving circuit GDC2 may generate and output Figure 2B Therefore, the m gate signals output from each of the first gate driving circuit GDC1 and the second gate driving circuit GDC2 may be the sensing signal SENSE.

[0124] The first gate driving circuit GDC1 may include m first output buffer circuits. The m first output buffer circuits may be electrically connected to the m gate lines GL. The m first output buffer circuits may output m gate signals to the m gate lines GL. Each of the m first output buffer circuits may include a pull-up transistor and a pull-down transistor.

[0125] The second gate driving circuit GDC2 may include m second output buffer circuits. The m second output buffer circuits may be electrically connected to the m gate lines GL. The m second output buffer circuits may output m gate signals to the m gate lines GL. Each of the m second output buffer circuits may include a pull-up transistor and a pull-down transistor.

[0126] In some embodiments, the gate driving circuit 130 may have a Q node sharing structure in which m output buffer circuits share one Q node as a reference, and a QB node sharing structure in which m output buffer circuits share one QB node as a reference. The size of the frame area (non-display area NDA) of the display panel 110 can be reduced by the Q node sharing structure and / or the QB node sharing structure. Here, m represents the number of output buffer circuits sharing one Q node, and may represent the reference of the output buffer circuits sharing one Q node or the size of the output buffer circuits sharing one Q node.

[0127] The first gate driving circuit GDC1 may have a first Q node and a first QB node. The gate nodes of the respective pull-up transistors included in the m first output buffer circuits included in the first gate driving circuit GDC1 may share a first Q node. The gate nodes of the respective pull-down transistors included in the m first output buffer circuits included in the first gate driving circuit GDC1 may share a first QB node.

[0128] The second gate driving circuit GDC2 may include m second output buffer circuits. The m second output buffer circuits may be electrically connected to the m gate lines GL. The m second output buffer circuits may output m gate signals to the m gate lines GL. Each of the m second output buffer circuits may include a pull-up transistor and a pull-down transistor.

[0129] The second gate driving circuit GDC2 may have a second Q node and a second QB node. The gate nodes of the respective pull-up transistors included in the m second output buffer circuits included in the second gate driving circuit GDC2 may share a second Q node. The gate nodes of the respective pull-down transistors included in the m second output buffer circuits included in the second gate driving circuit GDC2 may share a second QB node.

[0130] Furthermore, in some embodiments, the gate driving circuit 130 can perform overlap gate driving to improve image quality by increasing insufficient charging time in each sub-pixel.

[0131] When the gate driving circuit 130 performs overlapping gate driving, the gate driving circuit 130 may output a gate signal having an on-level voltage duration longer than one horizontal period (1H). In addition, the on-level voltage duration of one gate signal among the gate signals output from the gate driving circuit 130 may partially overlap with the on-level voltage duration of another gate signal.

[0132] For example, in some embodiments, when the gate driving circuit 130 performs 2H overlapping gate driving, the on-level voltage duration of each gate signal may have a period of 2H. In addition, a 1H period corresponding to the second half of the on-level voltage duration of one gate signal may overlap with a 1H period corresponding to the first half of the on-level voltage duration of another gate signal.

[0133] In some embodiments, when the gate driving circuit 130 performs 3H overlapping gate driving, the on-level voltage duration of each gate signal may have a 3H period. In addition, a 2H period corresponding to the second half of the on-level voltage duration of one gate signal may overlap with a 2H period corresponding to the first half of the on-level voltage duration of another gate signal. Figure 5 , Fig. 6A and Figure 6B Describe the Q-node sharing structure and overlapping gate drive briefly described above.

[0134] Figure 5 The gate driving circuit 130 having a first clock input structure included in the display device 100 according to various aspects of the present disclosure is illustrated. Figure 5 An example in the case of m=4 is illustrated. Fig. 6A Illustrated when using Figure 5 The gate driving circuit 130 is input to the four clock signals (CLK(n+1), CLK(n+2), CLK(n+3) and CLK(n+4)) of the first gate driving circuit GDC1, and the voltage fluctuation at the Q node of the first gate driving circuit GDC1. Figure 6B Illustrated when using Figure 5 The gate driving circuit 130 is four gate signals (G(n+1), G(n+2), G(n+3) and G(n+4)) output from the first gate driving circuit GDC1.

[0135] Reference Figure 5The first gate driving circuit GDC1 can use the four (m=4) clock signals (CLK(n+1), CLK(n+2), CLK(n+3) and CLK(n+4)) included in the first clock signal group CSG1 to output four (m=4) gate signals (G(n+1), G(n+2), G(n+3) and G(n+4)). The second gate driving circuit GDC2 can use the four (m=4) clock signals (CLK(n+5), CLK(n+6), CLK(n+7) and CLK(n+8)) included in the second clock signal group CSG2 to output four (m=4) gate signals (G(n+5), G(n+6), G(n+7) and G(n+8)).

[0136] The first gate driving circuit GDC1 may include four (m=4) first output buffer circuits. The four first output buffer circuits may be electrically connected to four (m=4) gate lines. The four first output buffer circuits may output four (m=4) gate signals (G(n+1), G(n+2), G(n+3), and G(n+4)) to four gate lines GL. Each of the four first output buffer circuits may include a pull-up transistor and a pull-down transistor.

[0137] The second gate driving circuit GDC2 may include four second output buffer circuits. The four second output buffer circuits may be electrically connected to the four gate lines. The four second output buffer circuits may output four gate signals (G(n+5), G(n+6), G(n+7), and G(n+8)) to the four gate lines GL. Each of the four second output buffer circuits may include a pull-up transistor and a pull-down transistor.

[0138] Reference Figure 5 and Fig. 6A , the four first output buffer circuits in the first gate driving circuit GDC1 can share one Q node and one QB node.

[0139] Gate nodes of each pull-up transistor included in four first output buffer circuits included in the first gate driving circuit GDC1 may share one Q node. Gate nodes of each pull-down transistor included in four first output buffer circuits included in the first gate driving circuit GDC1 may share one QB node.

[0140] Reference Figure 5 , Fig. 6A and Figure 6BFor example, when the first gate drive circuit GDC1 performs 2H overlapping gate drive, the first gate drive circuit GDC1 may receive four clock signals CLK(n+1), CLK(n+2), CLK(n+3) and CLK(n+4) having a high-level voltage duration corresponding to a 2H period, and output four gate signals (G(n+1), G(n+2), G(n+3) and G(n+4)) having a turn-on level voltage duration corresponding to a 2H period.

[0141] The high-level voltage durations of the four clock signals CLK(n+1), CLK(n+2), CLK(n+3), and CLK(n+4) may overlap for a predetermined period (e.g., 1H). Furthermore, the on-level voltage durations of the four gate signals (G(n+1), G(n+2), G(n+3), and G(n+4)) may overlap for a predetermined period (e.g., 1H).

[0142] Reference Figure 5 and Fig. 6A , the first gate drive circuit GDC1 can sequentially receive four (m=4) clock signals (CLK(n+1), CLK(n+2), CLK(n+3) and CLK(n+4)) whose high-level voltage durations partially overlap. Similarly, the second gate drive circuit GDC2 can sequentially receive four (m=4) clock signals (CLK(n+5), CLK(n+6), CLK(n+7) and CLK(n+8)) whose high-level voltage durations partially overlap. This sequential clock input structure is called a first clock input structure.

[0143] Reference Fig. 6A Since the first gate drive circuit GDC1 has a Q-node sharing structure and performs overlapping gate drive, a Q-node shared by four output buffer circuits will greatly experience voltage fluctuations (rise and fall) of four clock signals (CLK(n+1), CLK(n+2), CLK(n+3) and CLK(n+4)), so a step-like voltage fluctuation will be generated at a Q-node during a period after the first clock signal (CLK(n+1)) of the four clock signals (CLK(n+1), CLK(n+2), CLK(n+3) and CLK(n+4)) rises and before the last clock signal (CLK(n+4)) falls.

[0144] Reference Figure 6B , the voltage fluctuation characteristics at the Q node caused by the Q node sharing structure and overlapping gate drive will cause differences between the individual output characteristics of the four gate signals (G(n+1), G(n+2), G(n+3) and G(n+4)).

[0145] Reference Figure 6B , among the four gate signals (G(n+1), G(n+2), G(n+3) and G(n+4)), the (n+1)th gate signal G(n+1) output based on the (n+1)th clock signal CLK(n+1) that first rises to a high level voltage has the longest rising time (rising period). That is, among the four gate signals (G(n+1), G(n+2), G(n+3) and G(n+4)), the (n+1)th gate signal G(n+1) output based on the (n+1)th clock signal CLK(n+1) that first rises to a high level voltage has the worst rising characteristic.

[0146] Reference Figure 6B , among the four gate signals (G(n+1), G(n+2), G(n+3) and G(n+4)), the (n+4)th gate signal G(n+4) output based on the (n+4)th clock signal CLK(n+4) that finally drops to the low level voltage has the longest falling time (falling period). That is, among the four gate signals (G(n+1), G(n+2), G(n+3) and G(n+4)), the (n+4)th gate signal G(n+4) output based on the (n+4)th clock signal CLK(n+4) that finally drops to the low level voltage has the worst falling characteristic.

[0147] Such a gate signal output characteristic difference (rising characteristic difference and falling characteristic difference) may cause an image abnormality in which an abnormal horizontal line is seen on the screen of the display device 100 at a point where the difference occurs.

[0148] The second gate drive circuit GDC2 is similar to the above, and the above reference is repeated for the convenience of description. Fig. 6A and Figure 6B The operation and image abnormality of the first gate driving circuit GDC1 are described.

[0149] The Q-node voltage fluctuation characteristics and the resulting gate signal output characteristic differences (rising characteristic differences and falling characteristic differences) due to the Q-node sharing structure and overlapping gate driving are attributed to the first clock input structure (ie, sequential clock input structure).

[0150] Hereinafter, in order to solve this problem, a second clock input structure, a gate driving circuit 130 using the second clock input structure, and a display device 100 including the gate driving circuit 130 will be described. Even when a Q-node sharing structure and overlapping gate driving are performed, the second clock input structure can reduce such gate signal output characteristic differences (rising characteristic differences and falling characteristic differences).

[0151] Fig. 7AThe gate driving circuit 130 having the second clock input structure included in the display device 100 according to various aspects of the present disclosure is illustrated. Figure 7B Illustrated input to Fig. 7A The clock signal of the gate driving circuit 130 shown in FIG. Figure 8 More detailed map Fig. 7A The gate driving circuit 130 shown in FIG.

[0152] Reference Fig. 7A According to various aspects of the present disclosure, the gate driving circuit 130 with a second clock input structure included in the display device 100 may include: a first gate driving circuit GDC1, the first gate driving circuit GDC1 is capable of outputting m gate signals (G(n+1), G(n+k), ..., G(n+A)) using a first clock signal group CSG1; and a second gate driving circuit GDC2, the second gate driving circuit GDC2 is capable of outputting m gate signals (G(n+2), G(n+k+1), ..., G(n+A+1)) using a second clock signal group CSG2 different from the first clock signal group CSG1, where n is an arbitrary integer and m is a natural number of 2 or greater. Here, A represents the value of the mth term of an arithmetic sequence with an initial term of 1 and a common difference of (k-1) (i.e., increasing (k-1)), which is given by 1+(m-1)(k-1). (k-1) is not 1 and is a natural number greater than or equal to 2. The second clock input structure is also referred to as a non-sequential clock input structure.

[0153] Reference Fig. 7A In the second clock input structure, the first clock signal group CSG1 input to the first gate drive circuit GDC1 may include m clock signals (CLK(n+1), CLK(n+k), ..., CLK(n+A)), and the second clock signal group CSG2 input to the second gate drive circuit GDC2 may include m clock signals (CLK(n+2), CLK(n+k+1), ..., CLK(n+A+1)). In addition, Figure 5 In the first clock input structure, the first clock signal group CSG1 input to the first gate drive circuit GDC1 may include four (m=4) sequential clock signals (CLK(n+1), CLK(n+2), CLK(n+3) and CLK(n+4)), and the second clock signal group CSG2 input to the second gate drive circuit GDC2 may include four (m=4) sequential clock signals (CLK(n+5), CLK(n+6), CLK(n+7) and CLK(n+8)).

[0154] As described above, the clock signal included in the first clock signal group CSG1 input to the first gate drive circuit GDC1 in the second clock input structure may be different from the clock signal included in the first clock signal group CSG1 input to the first gate drive circuit GDC1 in the first clock input structure. Similarly, the clock signal included in the second clock signal group CSG2 input to the second gate drive circuit GDC2 in the second clock input structure may be different from the clock signal included in the second clock signal group CSG2 input to the second gate drive circuit GDC2 in the first clock input structure. Here, the "first" in the first clock signal group CSG1 and the "second" in the second clock signal group CSG2 may correspond to the "first" in the first gate drive circuit GDC1 and the "second" in the second gate drive circuit GDC2, respectively.

[0155] 2m clock signals including m clock signals (CLK(n+1), CLK(n+k), ..., CLK(n+A)) included in the first clock signal group CSG1 and m clock signals (CLK(n+2), CLK(n+k+1), ..., CLK(n+A+1)) included in the second clock signal group CSG2 may have high-level voltage durations at different timings from each other. That is, all 2m clock signals may be different clock signals.

[0156] Reference Figure 8 The first gate drive circuit GDC1 may include: m first output buffer circuits (GBUF11, GBUF12, ..., GBUF1m) capable of receiving m clock signals (CLK(n+1), CLK(n+k), ..., CLK(n+A)) and outputting m gate signals (G(n+1), G(n+k), ..., G(n+A)); and a first control circuit 510 capable of controlling the m first output buffer circuits (GBUF11, GBUF12, ..., GBUF1m).

[0157] The first control circuit 510 may receive a start signal VST, a reset signal RST, etc., and control operations of the m first output buffer circuits (GBUF11, GBUF12, . . . , GBUF1m).

[0158] Reference Figure 8The second gate drive circuit GDC2 may include: m second output buffer circuits (GBUF21, GBUF22, ..., GBUF2m) capable of receiving m clock signals (CLK(n+2), CLK(n+k+1), ..., CLK(n+A+1)) and outputting m gate signals (G(n+2), G(n+k+1), ..., G(n+A+1)); and a second control circuit 520 capable of controlling the m second output buffer circuits (GBUF21, GBUF22, ..., GBUF2m).

[0159] The second control circuit 520 may receive a start signal VST, a reset signal RST, etc., and control operations of the m second output buffer circuits (GBUF21, GBUF22, . . . , GBUF2m).

[0160] Reference Figure 8 , each of the m first output buffer circuits (GBUF11, GBUF12, ..., GBUF1m) may include a pull-up transistor Tu1 and a pull-down transistor Td1. The pull-up transistor Tu1 and the pull-down transistor Td1 may be connected in series between a node to which a corresponding clock signal is applied and a node to which a base voltage GVSS0 is applied. The point at which the pull-up transistor Tu1 and the pull-down transistor Td1 are connected is a point that is connected to a corresponding gate line and outputs a corresponding gate signal. All gate nodes of each pull-up transistor Tu1 included in the m first output buffer circuits (GBUF11, GBUF12, ..., GBUF1m) may be electrically connected to a first Q node Q1, and all gate nodes of each pull-down transistor Td1 included in the m first output buffer circuits (GBUF11, GBUF12, ..., GBUF1m) may be electrically connected to a first QB node QB1.

[0161] Reference Figure 8 , each of the m second output buffer circuits (GBUF21, GBUF22, ..., GBUF2m) may include a pull-up transistor Tu2 and a pull-down transistor Td2. The pull-up transistor Tu2 and the pull-down transistor Td2 may be connected in series between a node to which a corresponding clock signal is applied and a node to which a base voltage GVSS0 is applied. The point at which the pull-up transistor Tu2 and the pull-down transistor Td2 are connected is a point connected to a corresponding gate line and outputs a corresponding gate signal. All gate nodes of each pull-up transistor Tu2 included in the m second output buffer circuits (GBUF21, GBUF22, ..., GBUF2m) may be electrically connected to a second Q node Q2, and all gate nodes of each pull-down transistor Td2 included in the m second output buffer circuits (GBUF21, GBUF22, ..., GBUF2m) may be electrically connected to a second QB node QB2.

[0162] Reference Figure 8 The m clock signals (CLK(n+1), CLK(n+k), ..., CLK(n+A)) input to the m first output buffer circuits (GBUF11, GBUF12, ..., GBUF1m) of the first gate drive circuit GDC1 may include the (n+1)th clock signal CLK(n+1) and the (n+k)th clock signal CLK(n+k).

[0163] Reference Figure 8 , the m clock signals (CLK(n+2), CLK(n+k+1), ..., CLK(n+A+1)) input to the m second output buffer circuits (GBUF21, GBUF22, ..., GBUF2m) of the second gate driving circuit GDC2 may include the (n+2)th clock signal CLK(n+2) and the (n+k+1)th clock signal CLK(n+k+1). Here, n is an arbitrary integer, and k is a natural number of 3 or more.

[0164] Reference Figure 7B , the gate driving circuit 130 may perform (k-1)H overlapping gate driving. As a result, the high level voltage duration of the (n+1)th clock signal CLK(n+1) input to the first gate driving circuit GDC1 and the high level voltage duration of the (n+2)th clock signal CLK(n+2) input to the second gate driving circuit GDC2 may partially overlap with each other. The high level voltage duration of the (n+k)th clock signal CLK(n+k) input to the first gate driving circuit GDC1 and the high level voltage duration of the (n+k+1)th clock signal CLK(n+k+1) input to the second gate driving circuit GDC2 may partially overlap with each other.

[0165] Reference Figure 7B , the high level voltage durations of the m clock signals (CLK(n+1), CLK(n+k), ..., CLK(n+A)) input to the m first output buffer circuits (GBUF11, GBUF12, ..., GBUF1m) of the first gate drive circuit GDC1 may not overlap with each other. Similarly, the high level voltage durations of the m clock signals (CLK(n+2), CLK(n+k+1), ..., CLK(n+A+1)) input to the m second output buffer circuits (GBUF21, GBUF22, ..., GBUF2m) of the second gate drive circuit GDC2 may not overlap with each other.

[0166] For example, the high level voltage duration of the (n+1)th clock signal CLK(n+1) and the high level voltage duration of the (n+k)th clock signal CLK(n+k) may not overlap with each other. In addition, the high level voltage duration of the (n+2)th clock signal CLK(n+2) and the high level voltage duration of the (n+k+1)th clock signal CLK(n+k+1) may not overlap with each other.

[0167] Reference Fig. 7A , Figure 7B and Figure 8 , the first gate driving circuit may output the (n+1)th gate signal G(n+1) based on the (n+1)th clock signal CLK(n+1), and output the (n+k)th gate signal G(n+k) based on the (n+k)th clock signal CLK(n+k). The second gate driving circuit may output the (n+2)th gate signal G(n+2) based on the (n+2)th clock signal CLK(n+2), and output the (n+k+1)th gate signal G(n+k+1) based on the (n+k+1)th clock signal CLK(n+k+1).

[0168] Reference Figure 7B , the on-level voltage duration of the (n+1)th gate signal G(n+1) may partially overlap with the on-level voltage duration of the (n+2)th gate signal G(n+2). In contrast, the on-level voltage duration of the (n+1)th gate signal G(n+1) may not overlap with the on-level voltage duration of the (n+k)th gate signal G(n+k).

[0169] Reference Figure 7B , the on-level voltage duration of the (n+2)th gate signal G(n+2) may partially overlap with the on-level voltage duration of the (n+1)th gate signal G(n+1). In contrast, the on-level voltage duration of the (n+2)th gate signal G(n+2) may not overlap with the on-level voltage duration of the (n+k+1)th gate signal G(n+k+1).

[0170] In the above description, m may be the number of first output buffer circuits sharing one first Q node, or the number of pull-up transistors whose gate nodes are commonly connected to one first Q node. In addition, m may be the number of second output buffer circuits sharing one second Q node, or the number of pull-up transistors whose gate nodes are commonly connected to one second Q node.

[0171] In the above description, k is proportional to the length of the high-level voltage duration of each clock signal, and the value obtained by multiplying one horizontal period H by (k-1) is equal to the length of the high-level voltage duration of each clock signal ((k-1)*H). For example, k may be 3, 4, 5, etc., and the high-level voltage duration of each clock signal may have a length of 2H, 3H, 4H, etc. Hereinafter, the gate driving circuit 130 having the second clock input structure will be described in the case where m=4 and k=3.

[0172] Fig. 9 Illustrated Fig. 7A An example of the gate driving circuit 130 is shown in FIG. Fig.10 More detailed map Fig. 9 The gate driving circuit 130 shown in FIG. Fig.11A Illustrated when using Fig. 9 The gate driving circuit 130 shown in FIG. 1 is four clock signals input to the first gate driving circuit GDC1 , and the voltage fluctuation at the Q1 node of the first gate driving circuit GDC1 . Fig. 11B Illustrated when using Fig. 9 The gate driving circuit 130 shown in FIG. 1 is four gate signals output from the first gate driving circuit GDC1. Fig. 11C Illustrated when using Fig. 9 The gate driving circuit 130 shown in FIG. 1 is four clock signals input to the second gate driving circuit GDC2, and the voltage fluctuation at the Q2 node of the second gate driving circuit GDC2. Fig.11D Illustrated when using Fig. 9 The gate driving circuit 130 shown in FIG. 1 is four gate signals output from the second gate driving circuit GDC2. Figures 9 to 11D 1 is an example of the gate driving circuit 130 in the case where k = 3 and m = 4. Here, k = 3 means that 2H overlapping gate driving is performed, and m = 4 means that the number of output buffer circuits sharing the Q node is 4.

[0173] Reference Fig. 9 and Fig.10, when m=4 and k=3, the four first output buffer circuits (GBUF11, GBUF12, GBUF13 and GBUF14) included in the first gate drive circuit GDC1 may include: a first output buffer circuit GBUF11 capable of receiving the (n+1)th clock signal CLK(n+1) and outputting the (n+1)th gate signal G(n+1) based on the (n+1)th clock signal CLK(n+1); a first output buffer circuit GBUF12 capable of receiving the (n+3)th clock signal CLK(n+3) and outputting the (n+3)th gate signal G(n+1) based on the (n+3)th clock signal CLK(n+ 3) a first output buffer circuit GBUF12 that outputs the (n+3)th gate signal G(n+3); a first output buffer circuit GBUF13 that can receive the (n+5)th clock signal CLK(n+5) and output the (n+5)th gate signal G(n+5) based on the (n+5)th clock signal CLK(n+5); and a first output buffer circuit GBUF14 that can receive the (n+7)th clock signal CLK(n+7) and output the (n+7)th gate signal G(n+7) based on the (n+7)th clock signal CLK(n+7).

[0174] Reference Fig.10 , each of the four first output buffer circuits (GBUF11, GBUF12, GBUF13, and GBUF14) may include a pull-up transistor Tu1 and a pull-down transistor Td1. The pull-up transistor Tu1 and the pull-down transistor Td1 may be connected in series between a node to which a corresponding clock signal is applied and a node to which a base voltage GVSS0 is applied. The point at which the pull-up transistor Tu1 and the pull-down transistor Td1 are connected is a point that is connected to a corresponding gate line and outputs a corresponding gate signal. All gate nodes of each pull-up transistor Tu1 included in the four first output buffer circuits (GBUF11, GBUF12, GBUF13, and GBUF14) may be electrically connected to a first Q node Q1, and all gate nodes of each pull-down transistor Td1 included in the four first output buffer circuits (GBUF11, GBUF12, GBUF13, and GBUF14) may be electrically connected to a first QB node QB1.

[0175] Reference Fig.10 , the first control circuit 510 may receive a start signal VST, a reset signal RST, etc., and control operations of four first output buffer circuits (GBUF11, GBUF12, GBUF13, and GBUF14).

[0176] Reference Fig. 9 and Fig.10, when m=4 and k=3, the four second output buffer circuits (GBUF21, GBUF22, GBUF23 and GBUF24) included in the second gate drive circuit GDC2 may include: a second output buffer circuit GBUF21 capable of receiving the (n+2)th clock signal CLK(n+2) and outputting the (n+2)th gate signal G(n+2) based on the (n+2)th clock signal CLK(n+2); a second output buffer circuit GBUF21 capable of receiving the (n+4)th clock signal CLK(n+4) and outputting the (n+4)th gate signal G(n+ 4) a second output buffer circuit GBUF22 that outputs the (n+4)th gate signal G(n+4); a second output buffer circuit GBUF23 that can receive the (n+6)th clock signal CLK(n+6) and output the (n+6)th gate signal G(n+6) based on the (n+6)th clock signal CLK(n+6); and a second output buffer circuit GBUF24 that can receive the (n+8)th clock signal CLK(n+8) and output the (n+8)th gate signal G(n+8) based on the (n+8)th clock signal CLK(n+8).

[0177] Reference Fig.10 , each of the four second output buffer circuits (GBUF21, GBUF22, GBUF23, and GBUF24) may include a pull-up transistor Tu2 and a pull-down transistor Td2. The pull-up transistor Tu2 and the pull-down transistor Td2 may be connected in series between a node to which a corresponding clock signal is applied and a node to which a base voltage GVSS0 is applied. The point at which the pull-up transistor Tu2 and the pull-down transistor Td2 are connected is a point connected to a corresponding gate line and outputs a corresponding gate signal. All gate nodes of each pull-up transistor Tu2 included in the four second output buffer circuits (GBUF21, GBUF22, GBUF23, and GBUF24) may be electrically connected to a second Q node Q2, and all gate nodes of each pull-down transistor Td2 included in the four second output buffer circuits (GBUF21, GBUF22, GBUF23, and GBUF24) may be electrically connected to a second QB node QB2.

[0178] Reference Fig.10 , the second control circuit 520 may receive a start signal VST, a reset signal RST, etc., and control operations of the four second output buffer circuits (GBUF21, GBUF22, GBUF23, and GBUF24).

[0179] Reference Fig.11A, the first gate driving circuit GDC1 has a second clock input structure. Therefore, even when the high-level voltage durations of the (n+1)th clock signal CLK(n+1), the (n+3)th clock signal CLK(n+3), the (n+5)th clock signal CLK(n+5), and the (n+7)th clock signal CLK(n+7) input to the four first output buffer circuits (GBUF11, GBUF12, GBUF13, and GBUF14) included in the first gate driving circuit GDC1 have a 2H period, the respective high-level voltage durations may not overlap with each other.

[0180] Therefore, the first Q node Q1 shared by the four first output buffer circuits (GBUF11, GBUF12, GBUF13, and GBUF14) does not significantly experience the respective voltage fluctuations (increases and decreases) of the four clock signals (CLK(n+1), CLK(n+3), CLK(n+5), and CLK(n+7)). That is, the voltage of the first Q node Q1 may increase as the first clock signal CLK(n+1) among the four clock signals (CLK(n+1), CLK(n+3), CLK(n+5), and CLK(n+7)) increases, and the voltage of the first Q node Q1 may decrease as the last clock signal CLK(n+7) among the four clock signals (CLK(n+1), CLK(n+3), CLK(n+5), and CLK(n+7)) decreases. During a period between the rising time of the first clock signal CLK(n+1) and the falling time of the last clock signal CLK(n+7), the first Q node Q1 maintains a constant voltage, and thus large voltage fluctuations such as step-like voltage fluctuations are not differentially generated.

[0181] Therefore, refer to Fig. 11B , the respective rising characteristics (rising period) and falling characteristics (falling period) of the four gate signals (G(n+1), G(n+3), G(n+5) and G(n+7)) output from the four first output buffer circuits (GBUF11, GBUF12, GBUF13 and GBUF14) included in the first gate drive circuit GDC1 may be substantially or almost the same or similar to each other. That is, although the first gate drive circuit GDC1 performs overlapping gate drive and has a Q-node sharing structure, the second clock input structure applied to the first gate drive circuit GDC1 can reduce the output characteristic difference (rising characteristic difference and falling characteristic difference) of the gate signal.

[0182] Reference Fig. 11C, the second gate driving circuit GDC2 has a second clock input structure. Therefore, even when the high-level voltage durations of the (n+2)th clock signal CLK(n+2), the (n+4)th clock signal CLK(n+4), the (n+6)th clock signal CLK(n+6), and the (n+8)th clock signal CLK(n+8) input to the four second output buffer circuits (GBUF21, GBUF22, GBUF23, and GBUF24) included in the second gate driving circuit GDC2 have a 2H period, the respective high-level voltage durations may not overlap with each other.

[0183] Therefore, the second Q node Q2 shared by the four second output buffer circuits (GBUF21, GBUF22, GBUF23, and GBUF24) does not significantly experience the respective voltage fluctuations of the four clock signals (CLK(n+2), CLK(n+4), CLK(n+6), and CLK(n+8)). That is, during the period after the first clock signal CLK(n+2) of the four clock signals (CLK(n+2), CLK(n+4), CLK(n+6), and CLK(n+8)) rises and before the last clock signal CLK(n+8) falls, the second Q node Q2 shared by the four second output buffer circuits (GBUF21, GBUF22, GBUF23, and GBUF24) hardly generates a step-shaped voltage fluctuation.

[0184] Therefore, refer to Fig.11D , the respective rising characteristics (rising period) and falling characteristics (falling period) of the four gate signals (G(n+2), G(n+4), G(n+6) and G(n+8)) output from the four second output buffer circuits (GBUF21, GBUF22, GBUF23 and GBUF24) included in the second gate drive circuit GDC2 may be substantially or almost the same or similar to each other. That is, although the second gate drive circuit GDC2 performs overlapping gate drive and has a Q-node sharing structure, the second clock input structure applied to the second gate drive circuit GDC2 can reduce the output characteristic difference (rising characteristic difference and falling characteristic difference) of the gate signal.

[0185] Fig.12 Various cases (Case 1 and Case 2) in which the gate driving circuit 130 of the display device 100 according to various aspects of the present disclosure has a first clock input structure and a second clock input structure are illustrated.

[0186] Reference Fig.12When the first gate driving circuit GDC1 has a first clock input structure (Case 1), the first gate driving circuit GDC1 can receive four sequential clock signals (CLK(n+1), CLK(n+2), CLK(n+3) and CLK(n+4)).

[0187] When k defining the characteristics of overlapping gate driving is 3, each high level voltage duration of the four clock signals (CLK(n+1), CLK(n+2), CLK(n+3) and CLK(n+4)) input to the first gate driving circuit GDC1 has a period of 2H. The high level voltage duration of the (n+1)th clock signal CLK(n+1) may partially overlap with the high level voltage duration of the (n+2)th clock signal CLK(n+2), the high level voltage duration of the (n+2)th clock signal CLK(n+2) may partially overlap with the high level voltage duration of the (n+3)th clock signal CLK(n+3), and the high level voltage duration of the (n+3)th clock signal CLK(n+3) may partially overlap with the high level voltage duration of the (n+4)th clock signal CLK(n+4).

[0188] When the gate driving circuit 130 has the first clock input structure (case 1), the first Q node Q1 in the first gate driving circuit GDC1 may significantly experience four clock signals (CLK(n+1), CLK(n+2), CLK(n+3), and CLK(n+4)) whose respective high-level voltage durations partially overlap with each other. Therefore, this may cause serious voltage fluctuations, thereby causing an increase in the difference in the output characteristics of the corresponding gate signals (G(n+1), G(n+2), G(n+3), and G(n+4)).

[0189] Reference Fig.12 , when the first gate driving circuit GDC1 has the second clock input structure (Case 2), the first gate driving circuit GDC1 can receive four non-sequential clock signals (CLK(n+1), CLK(n+3), CLK(n+5) and CLK(n+7)). Here, the non-sequential clock signals (e.g., CLK(n+1), CLK(n+3), CLK(n+5) and CLK(n+7)) refer to that the time period between the start time (rise time) of each high-level voltage duration of the clock signals (e.g., CLK(n+1), CLK(n+3), CLK(n+5) and CLK(n+7)) does not have a 1H period. In contrast, Fig. 6AThe clock signals (e.g., CLK(n+1), CLK(n+2), CLK(n+3), and CLK(n+4)) in are defined as being sequential, which may mean that the time period between the start times (rise times) of the clock signals (e.g., CLK(n+1), CLK(n+2), CLK(n+3), and CLK(n+4)) has a period of 1H.

[0190] When k, which defines the characteristic of overlapping gate drive, is 3, the respective high-level voltage durations of the four clock signals (CLK(n+1), CLK(n+3), CLK(n+5) and CLK(n+7)) input to the first gate drive circuit GDC1 have a period of 2H and do not overlap with each other.

[0191] When the gate driving circuit 130 has the second clock input structure (Case 2), the first Q node Q1 in the first gate driving circuit GDC1 does not significantly experience four clock signals (CLK(n+1), CLK(n+3), CLK(n+5), and CLK(n+7)) whose respective high-level voltage durations do not overlap with each other. Therefore, the difference in the output characteristics of the corresponding gate signals (G(n+1), G(n+2), G(n+3), and G(n+4)) can be reduced.

[0192] Fig.13 Illustrated Fig.10 An exemplary implementation of the gate drive circuit 130 is shown in FIG.

[0193] Fig.13 Illustrated Fig.10 The gate driving circuit 130 is partially modified, and thus descriptions of the same elements and operations will be omitted for ease of description.

[0194] Reference Fig.13 The first gate driving circuit GDC1 may further include a first carry output buffer circuit CBUF1 capable of receiving the (n+1)th carry clock signal CRCLK(n+1) and outputting a carry signal C(n+1), and the second gate driving circuit GDC2 may further include a second carry output buffer circuit CBUF2 capable of receiving the (n+2)th carry clock signal CRCLK(n+2) and outputting a carry signal C(n+2).

[0195] The first carry output buffer circuit CBUF1 may include a pull-up transistor Tuc1 and a pull-down transistor Tdc1 connected in series between a node to which the (n+1)th carry clock signal CRCLK(n+1) is input and a node to which the base voltage GVSS2 is applied. The second carry output buffer circuit CBUF2 may include a pull-up transistor Tuc2 and a pull-down transistor Tdc2 connected in series between a node to which the (n+2)th carry clock signal CRCLK(n+2) is input and a node to which the base voltage GVSS2 is applied.

[0196] Reference Fig.13 , capacitors CAP_GS and CAP_CR may be connected between gate nodes and source nodes (nodes outputting gate signals or carry signals) of the pull-up transistors (Tu1, Tuc1, Tu2, and Tuc2).

[0197] Hereinafter, the Fig. 9 and Fig.10 How the gate signals (G(n+1) to G(n+8)) output by the gate driving circuit 130 are provided to the gate lines (GL(n+1) to GL(n+8)). That is, the following will be described. Fig.10 A structure in which eight output buffer circuits (GBUF11, GBUF12, GBUF13, GBUF14, GBUF21, GBUF22, GBUF23 and GBUF24) are connected to eight gate lines (GL(n+1) to GL(n+8)).

[0198] Fig.14 Schematic diagram Fig.10 The gate driving circuit 130 shown in FIG. Fig.15 and Fig.16 Illustrated Fig.14 A connection structure between a gate driving circuit and gate lines (GL(n+1) to GL(n+8)) arranged in a display area.

[0199] Reference Fig.15 , the (n+1)th gate signal G(n+1), the (n+3)th gate signal G(n+3), the (n+5)th gate signal G(n+5) and the (n+7)th gate signal G(n+7) may be applied to the (n+1)th gate line GL(n+1), the (n+3)th gate line GL(n+3), the (n+5)th gate line GL(n+5) and the (n+7)th gate line GL(n+7), respectively.

[0200] Reference Fig.15, the (n+2)th gate signal G(n+2), the (n+4)th gate signal G(n+4), the (n+6)th gate signal G(n+6) and the (n+8)th gate signal G(n+8) may be applied to the (n+2)th gate line GL(n+2), the (n+4)th gate line GL(n+4), the (n+6)th gate line GL(n+6) and the (n+8)th gate line GL(n+8), respectively.

[0201] Reference Fig.15 Since the order in which the gate signals (G(n+1) to G(n+8)) are output from the gate driving circuit 130 is not consistent with the order in which the gate lines (GL(n+1) to GL(n+8)) are arranged, it is necessary to set one or more separate connecting lines CL between the first gate driving circuit GDC1 and the second gate driving circuit GDC2 included in the gate driving circuit 130 and the display area DA of the display panel 110.

[0202] To this end, the display panel 110 may include at least one of the following connection lines: a connection line CL connected between the first output buffer GBUF11 outputting the (n+1)th gate signal G(n+1) and the (n+1)th gate line GL(n+1) provided in the display panel 110, a connection line CL connected between the first output buffer GBUF12 outputting the (n+3)th gate signal G(n+3) and the (n+3)th gate line GL(n+3) provided in the display panel 110, a connection line CL connected between the first output buffer GBUF13 outputting the (n+5)th gate signal G(n+5) and the (n+5)th gate line GL(n+5) provided in the display panel 110, a connection line CL connected between the first output buffer GBUF14 outputting the (n+7)th gate signal G(n+7) and the (n+7)th gate line GL(n+7) provided in the display panel 110, +7), a connecting line CL connected between the second output buffer GBUF21 outputting the (n+2)th gate signal G(n+2) and the (n+2)th gate line GL(n+2) arranged in the display panel 110, a connecting line CL connected between the second output buffer GBUF22 outputting the (n+4)th gate signal G(n+4) and the (n+4)th gate line GL(n+4) arranged in the display panel 110, a connecting line CL connected between the second output buffer GBUF23 outputting the (n+6)th gate signal G(n+6) and the (n+6)th gate line GL(n+6) arranged in the display panel 110, and a connecting line CL connected between the second output buffer GBUF24 outputting the (n+8)th gate signal G(n+8) and the (n+8)th gate line GL(n+8) arranged in the display panel 110.

[0203] according to Fig.15 The connection structure of FIG. 1 has a disadvantage of requiring a separate connection line CL, but provides an advantage that data driving can be sequentially performed according to the gate lines (GL(n+1) to GL(n+8)).

[0204] Reference Fig.16 , when k=3, the (n+1)th gate signal G(n+1), the (n+3)th gate signal G(n+3), the (n+2)th gate signal G(n+2) and the (n+4)th gate signal G(n+4) can be applied to the (n+1)th gate line GL(n+1), the (n+2)th gate line GL(n+2), the (n+1+m)th gate line and the (n+2+m)th gate line, respectively.

[0205] like Fig.16 As shown in, when k=3 and m=4, the (n+1)th gate signal G(n+1), the (n+3)th gate signal G(n+3), the (n+5)th gate signal G(n+5), the (n+7)th gate signal G(n+7), the (n+2)th gate signal G(n+2), the (n+4)th gate signal G(n+4), the (n+6)th gate signal G(n+6) and the (n+8)th gate signal G(n+8) can be applied to the (n+1)th gate line GL(n+1), the (n+2)th gate line GL(n+2), the (n+3)th gate line GL(n+3), the (n+4)th gate line GL(n+4), the (n+5)th gate line GL(n+5), the (n+6)th gate line GL(n+6), the (n+7)th gate line GL(n+7) and the (n+8)th gate line GL(n+8), respectively.

[0206] As described above, the order in which the gate signals (G(n+1) to G(n+8)) are output from the gate driving circuit 130 is consistent with the order in which the gate lines (GL(n+1) to GL(n+8)) are arranged. Therefore, the output portion of the gate driving circuit 130 can be directly connected to the gate lines (GL(n+1) to GL(n+8)) disposed in the display area DA of the display panel 110 without a separate connection line. Thus, the layout of the display panel 110 can be simplified.

[0207] Fig.17 Illustrated Fig. 7A An example of a gate drive circuit 130 is shown in FIG. Fig.17 In the example, Fig. 9 The construction in is different, k=4 is used. However, as described below, it should be understood that various k can be applied in addition to k=4. Similarly, various m can be used.

[0208] Reference Fig.17, in the case where k=4 and m=4, the first gate driving circuit GDC1 may include four first output buffer circuits capable of receiving four clock signals (CLK(n+1), CLK(n+4), CLK(n+7) and CLK(n+10)) included in the first clock signal group CSG1 and outputting four gate signals (G(n+1), G(n+4), G(n+7) and G(n+10)). The second gate driving circuit GDC2 may include four second output buffer circuits capable of receiving four clock signals (CLK(n+2), CLK(n+5), CLK(n+8) and CLK(n+11)) included in the second clock signal group CSG2 and outputting four gate signals (G(n+2), G(n+5), G(n+8) and G(n+11)).

[0209] Reference Fig.17 , the first gate driving circuit GDC1 has a second clock input structure. Therefore, although the high-level voltage durations of the four clock signals (CLK(n+1), CLK(n+4), CLK(n+7), and CLK(n+10)) input to the first gate driving circuit GDC1 have a period of 2H, the high-level voltage durations do not overlap with each other.

[0210] Thus, the respective rising characteristics (rising period) and falling characteristics (falling period) of the four gate signals (G(n+1), G(n+4), G(n+7) and G(n+10)) output from the first gate drive circuit GDC1 may be substantially or almost identical or similar to each other. That is, although the first gate drive circuit GDC1 performs overlapping gate drive and has a Q-node sharing structure, the second clock input structure applied to the first gate drive circuit GDC1 can reduce the output characteristic difference (rising characteristic difference and falling characteristic difference) of the gate signal.

[0211] Reference Fig.17 , the second gate driving circuit GDC2 has a second clock input structure. Therefore, although the high-level voltage durations of the four clock signals (CLK(n+2), CLK(n+5), CLK(n+8), and CLK(n+11)) input to the second gate driving circuit GDC2 have a period of 2H, the high-level voltage durations do not overlap with each other.

[0212] Thus, the respective rising characteristics (rising period) and falling characteristics (falling period) of the four gate signals (G(n+2), G(n+5), G(n+8) and G(n+11)) output from the second gate drive circuit GDC2 may be substantially or almost identical or similar to each other. That is, although the second gate drive circuit GDC2 performs overlapping gate drive and has a Q-node sharing structure, the second clock input structure applied to the second gate drive circuit GDC2 can reduce the output characteristic differences (rising characteristic differences and falling characteristic differences) of the gate signals.

[0213] According to the embodiments described herein, a gate driving circuit having a clock input structure capable of reducing output characteristic differences between gate signals, thereby improving image quality, and a display device including the same may be provided.

[0214] According to the embodiments described herein, a gate driving circuit having a clock input structure capable of realizing overlapping gate driving and Q-node sharing structures while reducing output characteristic differences between gate signals and a display device including the same may be provided.

[0215] The above description has been provided to enable any person skilled in the art to obtain and use the technical concept of the present invention, and the above description is provided in the context of a specific application and its requirements. Various modifications, additions and substitutions to the above-described embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention. The above description and accompanying drawings provide examples of the technical concept of the present invention for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical concept of the present invention. Therefore, the scope of the present invention is not limited to the embodiments shown, but is consistent with the widest scope consistent with the claims. The scope of protection of the present invention should be interpreted based on the subsequent claims, and all technical concepts within their equivalent ranges should be interpreted as included within the scope of the present invention.

Claims

1. A display device, comprising: A display panel including a plurality of gate lines; and A gate driving circuit, the gate driving circuit comprising: a first gate driving circuit, the first gate driving circuit being capable of outputting m first gate signals using a first clock signal group; and a second gate driving circuit, the second gate driving circuit being capable of outputting m second gate signals using a second clock signal group different from the first clock signal group, wherein m is a natural number of 2 or greater, The first clock signal group and the second clock signal group include m first clock signals and m second clock signals respectively, and 2m clock signals including the m first clock signals included in the first clock signal group and the m second clock signals included in the second clock signal group have respective high level voltage durations at different timings, The first gate driving circuit includes: m first output buffer circuits configured to receive the m first clock signals and output the m first gate signals; and a first control circuit capable of controlling the m first output buffer circuits, and each of the m first output buffer circuits includes a pull-up transistor and a pull-down transistor. wherein all gate nodes of the respective pull-up transistors included in the m first output buffer circuits are electrically connected to a first Q node, The second gate driving circuit includes: m second output buffer circuits configured to receive the m second clock signals and output the m second gate signals; and a second control circuit capable of controlling the m second output buffer circuits, and each of the m second output buffer circuits includes a pull-up transistor and a pull-down transistor. wherein all gate nodes of the respective pull-up transistors included in the m second output buffer circuits are electrically connected to a second Q node, wherein the m first clock signals input to the first gate driving circuit include an (n+1)th clock signal and an (n+k)th clock signal, and the m second clock signals input to the second gate driving circuit include an (n+2)th clock signal and an (n+k+1)th clock signal, wherein n is an arbitrary integer and k is a natural number of 3 or greater, wherein the high level voltage duration of the (n+1)th clock signal does not overlap with the high level voltage duration of the (n+k)th clock signal, wherein the high level voltage duration of the (n+2)th clock signal does not overlap with the high level voltage duration of the (n+k+1)th clock signal, and wherein a high-level voltage duration of the (n+1)th clock signal input to the first gate drive circuit partially overlaps with a high-level voltage duration of the (n+2)th clock signal input to the second gate drive circuit, but does not overlap with a high-level voltage duration of the (n+k+1)th clock signal input to the second gate drive circuit, and a high-level voltage duration of the (n+2)th clock signal input to the second gate drive circuit partially overlaps with a high-level voltage duration of the (n+k)th clock signal input to the first gate drive circuit, but does not overlap with a high-level voltage duration of the (n+k+1)th clock signal input to the first gate drive circuit.

2. The display device according to claim 1, wherein a high-level voltage duration of the (n+k)th clock signal input to the first gate driving circuit partially overlaps with a high-level voltage duration of the (n+k+1)th clock signal input to the second gate driving circuit. 3 . The display device according to claim 1 , wherein m is equal to the number of pull-up transistors whose gate nodes are commonly connected to the one first Q node, and is equal to the number of pull-up transistors whose gate nodes are commonly connected to the one second Q node.

4. The display device according to claim 1, wherein k is proportional to the length of the high-level voltage duration of each of the 2m clock signals, and a value obtained by multiplying one horizontal period by (k-1) is equal to the length of the high-level voltage duration of each of the 2m clock signals. The display device according to claim 1 , wherein k is 3 or 4.

6. The display device according to claim 5, wherein when k is 3, the m first output buffer circuits included in the first gate driving circuit include: a first output buffer circuit receiving the (n+1)th clock signal and outputting the (n+1)th gate signal; as well as another first output buffer circuit receiving the (n+3)th clock signal and outputting the (n+3)th gate signal, and The m second output buffer circuits included in the second gate driving circuit include: a second output buffer circuit receiving the (n+2)th clock signal and outputting the (n+2)th gate signal; as well as Another second output buffer circuit receives the (n+4)th clock signal and outputs the (n+4)th gate signal.

7. The display device according to claim 6, wherein the (n+1)th gate signal is applied to the (n+1)th gate line, the (n+3)th gate signal is applied to the (n+3)th gate line, the (n+2)th gate signal is applied to the (n+2)th gate line, and the (n+4)th gate signal is applied to the (n+4)th gate line.

8. The display device according to claim 7, further comprising at least one of the following connecting lines: a connection line connected between the one first output buffer outputting the (n+1)th gate signal and the (n+1)th gate line provided in the display panel; a connection line connected between the another first output buffer outputting the (n+3)th gate signal and the (n+3)th gate line provided in the display panel; a connection line connected between the one second output buffer outputting the (n+2)th gate signal and the (n+2)th gate line provided in the display panel; as well as A connection line connected between the other second output buffer outputting the (n+4)th gate signal and the (n+4)th gate line provided in the display panel.

9. The display device according to claim 6, wherein the (n+1)th gate signal is applied to the (n+1)th gate line, the (n+3)th gate signal is applied to the (n+2)th gate line, the (n+2)th gate signal is applied to the (n+1+m)th gate line, and the (n+4)th gate signal is applied to the (n+2+m)th gate line.

10. The display device according to claim 6, wherein when m is 4, the m first output buffer circuits included in the first gate driving circuit include: yet another first output buffer circuit receiving the (n+5)th clock signal and outputting the (n+5)th gate signal; as well as another first output buffer circuit that receives the (n+7)th clock signal and outputs the (n+7)th gate signal, and The m second output buffer circuits included in the second gate driving circuit include: yet another second output buffer circuit receiving the (n+6)th clock signal and outputting the (n+6)th gate signal; as well as Still another second output buffer circuit receives the (n+8)th clock signal and outputs the (n+8)th gate signal.

11. The display device according to claim 10, wherein the (n+1)th gate signal is applied to the (n+1)th gate line, the (n+3)th gate signal is applied to the (n+3)th gate line, the (n+5)th gate signal is applied to the (n+5)th gate line, the (n+7)th gate signal is applied to the (n+7)th gate line, the (n+2)th gate signal is applied to the (n+2)th gate line, the (n+4)th gate signal is applied to the (n+4)th gate line, the (n+6)th gate signal is applied to the (n+6)th gate line, and the (n+8)th gate signal is applied to the (n+8)th gate line.

12. The display device according to claim 11 further comprises at least one of the following connecting lines: a connecting line connected between the one first output buffer outputting the (n+1)th gate signal and the (n+1)th gate line arranged in the display panel, a connecting line connected between the another first output buffer outputting the (n+3)th gate signal and the (n+3)th gate line arranged in the display panel, a connecting line connected between the further first output buffer outputting the (n+5)th gate signal and the (n+5)th gate line arranged in the display panel, a connecting line connected between the further first output buffer outputting the (n+7)th gate signal and the further first output buffer arranged in the display panel a connecting line connected between the (n+7)th gate line, a connecting line connected between the one second output buffer outputting the (n+2)th gate signal and the (n+2)th gate line arranged in the display panel, a connecting line connected between the other second output buffer outputting the (n+4)th gate signal and the (n+4)th gate line arranged in the display panel, a connecting line connected between the still another second output buffer outputting the (n+6)th gate signal and the (n+6)th gate line arranged in the display panel, and a connecting line connected between the still another second output buffer outputting the (n+8)th gate signal and the (n+8)th gate line arranged in the display panel.

13. The display device according to claim 9, wherein the (n+1)th gate signal is applied to the (n+1)th gate line, the (n+3)th gate signal is applied to the (n+2)th gate line, the (n+5)th gate signal is applied to the (n+3)th gate line, the (n+7)th gate signal is applied to the (n+4)th gate line, the (n+2)th gate signal is applied to the (n+1+m)th gate line, the (n+4)th gate signal is applied to the (n+2+m)th gate line, the (n+6)th gate signal is applied to the (n+3+m)th gate line, and the (n+8)th gate signal is applied to the (n+4+m)th gate line.

14. The display device according to claim 1, wherein the first gate driving circuit is configured to output an (n+1)th gate signal based on the (n+1)th clock signal and to output an (n+k)th gate signal based on the (n+k)th clock signal, the second gate driving circuit is configured to output an (n+2)th gate signal based on the (n+2)th clock signal and to output an (n+k+1)th gate signal based on the (n+k+1)th clock signal, and The on-level voltage duration of the (n+1)th gate signal partially overlaps with the on-level voltage duration of the (n+2)th gate signal, and the on-level voltage duration of the (n+1)th gate signal does not overlap with the on-level voltage duration of the (n+k)th gate signal. 15 . The display device according to claim 1 , wherein the display panel includes a display area and a non-display area different from the display area, and the gate driving circuit is provided in the non-display area.

16. A gate driving circuit capable of driving a plurality of gate lines arranged in a display panel, the gate driving circuit comprising: a first gate driving circuit, the first gate driving circuit being configured to output m first gate signals using a first clock signal group; and a second gate driving circuit configured to output m second gate signals using a second clock signal group, wherein m is a natural number of 2 or greater, The first clock signal group and the second clock signal group include m first clock signals and m second clock signals respectively, and 2m clock signals including the m first clock signals included in the first clock signal group and the m second clock signals included in the second clock signal group have respective high level voltage durations at different timings, The first gate driving circuit includes: m first output buffer circuits configured to receive the m first clock signals and output the m first gate signals; and a first control circuit capable of controlling the m first output buffer circuits, and each of the m first output buffer circuits includes a pull-up transistor and a pull-down transistor. wherein all gate nodes of the respective pull-up transistors included in the m first output buffer circuits are electrically connected to a first Q node, The second gate driving circuit includes: m second output buffer circuits receiving the m second clock signals and outputting the m second gate signals; and a second control circuit capable of controlling the m second output buffer circuits, and each of the m second output buffer circuits includes a pull-up transistor and a pull-down transistor. wherein all gate nodes of the respective pull-up transistors included in the m second output buffer circuits are electrically connected to a second Q node, wherein the m first clock signals input to the first gate driving circuit include an (n+1)th clock signal and an (n+k)th clock signal, and the m second clock signals input to the second gate driving circuit include an (n+2)th clock signal and an (n+k+1)th clock signal, wherein n is an arbitrary integer and k is a natural number of 3 or greater, wherein the high level voltage duration of the (n+1)th clock signal does not overlap with the high level voltage duration of the (n+k)th clock signal, wherein the high level voltage duration of the (n+2)th clock signal does not overlap with the high level voltage duration of the (n+k+1)th clock signal, and wherein a high-level voltage duration of the (n+1)th clock signal input to the first gate drive circuit partially overlaps with a high-level voltage duration of the (n+2)th clock signal input to the second gate drive circuit, but does not overlap with a high-level voltage duration of the (n+k+1)th clock signal input to the second gate drive circuit, and a high-level voltage duration of the (n+2)th clock signal input to the second gate drive circuit partially overlaps with a high-level voltage duration of the (n+k)th clock signal input to the first gate drive circuit, but does not overlap with a high-level voltage duration of the (n+k+1)th clock signal input to the first gate drive circuit.

17. The gate driving circuit according to claim 16, wherein a high-level voltage duration of the (n+k)th clock signal input to the first gate driving circuit partially overlaps with a high-level voltage duration of the (n+k+1)th clock signal input to the second gate driving circuit.

18. The gate driving circuit according to claim 16, wherein the first gate driving circuit is configured to output an (n+1)th gate signal based on the (n+1)th clock signal and to output an (n+k)th gate signal based on the (n+k)th clock signal, the second gate driving circuit is configured to output an (n+2)th gate signal based on the (n+2)th clock signal and to output an (n+k+1)th gate signal based on the (n+k+1)th clock signal, a turn-on level voltage duration of the (n+1)th gate signal partially overlaps with a turn-on level voltage duration of the (n+2)th gate signal, and a turn-on level voltage duration of the (n+1)th gate signal does not overlap with a turn-on level voltage duration of the (n+k)th gate signal.

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