Input buffer circuit

Abstract

An input buffer circuit includes an input differential amplifier unit, a differential amplifier stage, and a buffer. The input differential amplifier unit has input terminals and at least one output terminal, wherein at least two input terminals of the input differential amplifier unit are configured to be capacitively coupled, respectively, to provide at least one pair of signal paths for a first input signal and a second input signal of a differential input signal. The differential amplifier stage coupled to the input differential amplifier unit has first and second differential input terminals, and a corresponding output terminal, wherein the first and second differential input terminals are capable of being coupled to the first input signal and the second input signal, respectively. The buffer is coupled to the output terminal of the differential amplifier stage for outputting an output single-ended signal.

Description

Technical Field

[0001] This invention relates to an input buffer circuit, and more particularly to an input buffer circuit capable of improving reliability by providing protection against accidental short circuits or connections between a first or second frequency signal of a differential frequency input signal and power supply or ground. Background Technology

[0002] To receive one or more input signals from the first circuit, an input buffer is applied in the second circuit to prevent the second circuit from exerting unacceptable loads on the first circuit and interfering with the desired operation of the first circuit. Among the multiple input signals, frequency signals are typically transmitted between the two different circuits for signal synchronization. In high data rate applications, such as memory devices like double-data-rate (DDR) memory devices, differential frequency signals of a pair of first and second frequency signals are typically transmitted instead of single-ended frequency signals due to the many benefits of using differential signal transmission, such as common-mode noise suppression.

[0003] Accordingly, the input buffer for receiving the differential frequency signal typically utilizes a subtractor, for example, implemented using a differential amplifier, to receive the differential frequency signal so as to obtain a single frequency signal for use in the second circuit by conceptually subtracting the first and second frequency signals of the differential frequency signal, thereby reducing electronic crosstalk and electromagnetic interference imposed on the plurality of differential frequency signals during transmission.

[0004] Based on this approach, a frequency receiver can be implemented including a capacitively coupled circuit for filtering out DC voltage from a differential frequency signal, such as the "AC-coupled frequency receiver with common-mode noise suppression" in U.S. Patent No. 8,693,557. Thus, the capacitively coupled circuit can also suppress common-mode noise in the differential frequency signal.

[0005] However, if the power supply or ground is accidentally connected or short-circuited to one of the first or second frequency signals received by the differential amplifier in the above example, or to one of the inputs of the differential amplifier, the differential amplifier may output a distorted waveform that is inconsistent with the differential frequency signal, resulting in data errors in subsequent processing by the second circuit. Summary of the Invention

[0006] The object of the present invention is to provide an input buffer circuit that has additional signal paths for the first and second input signals of a differential input signal, so as to provide protection against accidental short circuits to voltage or ground at the input of the input buffer circuit.

[0007] To achieve the above objectives, the present invention provides an embodiment of an input buffer circuit. The input buffer circuit includes an input differential amplifier unit, a differential amplifier stage, and a buffer. The input differential amplifier unit has multiple input terminals and at least one output terminal, wherein at least two input terminals of the input differential amplifier unit are configured to be capacitively coupled to provide at least one pair of signal paths for a first input signal and a second input signal of a differential input signal. The differential amplifier stage coupled to the input differential amplifier unit has a first differential input terminal, a second differential input terminal, and a corresponding output terminal, wherein the first differential input terminal and the second differential input terminal can be coupled to the first input signal and the second input signal, respectively. The buffer is coupled to the output terminal of the differential amplifier stage for outputting a single-ended output signal.

[0008] Optionally, the input differential amplifier unit includes a first amplifier stage. The first amplifier stage includes a first differential amplifier having a first input terminal, a second input terminal, and a first output terminal. The first output terminal serves as the output terminal of the input differential amplifier unit. The first and second input terminals are configured to be capacitively coupled to the first input signal and the second input signal, respectively, to provide a pair of signal paths for the first and second input signals. The first output terminal is coupled to a corresponding output terminal of the differential amplifier stage. The first and second input terminals are the two input terminals of the input differential amplifier unit, and the first output terminal is the output terminal of the input differential amplifier unit.

[0009] Optionally, the first amplifier stage further includes a capacitive coupling circuit, wherein the first input terminal and the second input terminal are respectively able to receive the first input signal and the second input signal through the capacitive coupling circuit.

[0010] Optionally, the capacitive coupling circuit includes a first capacitor coupled to the first input terminal and a second capacitor coupled to the second input terminal.

[0011] Optionally, the input differential amplifier unit includes a first amplifier stage, a second amplifier stage, a third amplifier stage, and a fourth amplifier stage. The first amplifier stage includes a first differential amplifier having a first input terminal, a second input terminal, and a first output terminal, wherein the first input terminal and the second input terminal are respectively capable of receiving the first input signal and the second input signal. The second amplifier stage includes a second differential amplifier having a third input terminal, a fourth input terminal, and a second output terminal, wherein the third input terminal and the fourth input terminal are configured to be capacitively coupled to the first input signal and the second input signal, respectively, to provide a first pair of signal paths for the first input signal and the second input signal. The third amplifier stage includes a third differential amplifier having a fifth input terminal, a sixth input terminal, and a third output terminal, wherein the fifth input terminal and the sixth input terminal are respectively capable of receiving the second input signal and the first input signal. The fourth amplifier stage includes a fourth differential amplifier having a seventh input, an eighth input, and a fourth output. The seventh and eighth inputs are configured to be capacitively coupled to the second input signal and the first input signal, respectively, to provide a second pair of signal paths for the first and second input signals. The first and second outputs are coupled to the first differential input, and the third and fourth outputs are coupled to the second differential input. The input differential amplifier unit has a plurality of inputs including the first to eighth inputs, and a plurality of outputs including the first to fourth outputs.

[0012] Optionally, the input differential amplifier unit further includes a first capacitive coupling circuit and a second capacitive coupling circuit. The third input terminal and the fourth input terminal can receive the first input signal and the second input signal respectively through the first capacitive coupling circuit. The seventh input terminal and the eighth input terminal can receive the second input signal and the first input signal respectively through the second capacitive coupling circuit.

[0013] Optionally, the first capacitive coupling circuit includes a first capacitor coupled to the third input terminal and a second capacitor coupled to the fourth input terminal.

[0014] Optionally, the second capacitive coupling circuit includes a third capacitor coupled to the seventh input terminal and a fourth capacitor coupled to the eighth input terminal.

[0015] Optionally, the input differential amplifier unit includes a first amplifier stage and a second amplifier stage. The first amplifier stage includes a first differential amplifier having a first input terminal, a second input terminal, and a first output terminal, wherein the first input terminal and the second input terminal are respectively capable of receiving the first input signal and the second input signal; the first input terminal is configured to be capacitively coupled to the first output terminal, and the first output terminal is coupled to the first differential input terminal to provide a first signal path for the first input signal. The second amplifier stage includes a second differential amplifier having a third input terminal, a fourth input terminal, and a second output terminal, wherein the third input terminal and the fourth input terminal are respectively capable of receiving the first input signal and the second input signal; the fourth input terminal is configured to be capacitively coupled to the second output terminal, and the second output terminal is coupled to the second differential input terminal to provide a second signal path for the second input signal. The plurality of input terminals of the input differential amplifier unit include the first to fourth input terminals, and the input differential amplifier unit has a plurality of output terminals including the first and second output terminals.

[0016] Optionally, the input differential amplifier unit includes a first capacitive coupling circuit coupled between the first input terminal and the first output terminal; and a second capacitive coupling circuit coupled between the fourth input terminal and the second output terminal.

[0017] Optionally, the first capacitive coupling circuit includes a first capacitor coupled between the first input terminal and the first output terminal.

[0018] Optionally, the second capacitive coupling circuit includes a second capacitor coupled between the fourth input terminal and the second output terminal.

[0019] Optionally, the buffer includes at least one inverter.

[0020] Optionally, the differential input signal is a differential frequency signal.

[0021] To further understand the features and technical content of this invention, please refer to the following detailed description and accompanying drawings. However, this description and accompanying drawings are only for illustrating the invention and are not intended to limit the scope of the invention in any way. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a block diagram illustrating an input buffer circuit according to an embodiment of the present invention;

[0024] Figure 2 This is a block diagram illustrating an input buffer circuit according to another embodiment of the present invention;

[0025] Figure 3 It shows based on Figure 1 A block diagram of one embodiment of the input buffer circuit;

[0026] Figure 4 It shows based on Figure 2 A block diagram of one embodiment of the input buffer circuit;

[0027] Figure 5 It shows based on Figure 2 A block diagram of another embodiment of the input buffer circuit;

[0028] Figure 6 This is a schematic diagram illustrating one embodiment of a differential amplifier that can be used in the implementation of an input buffer circuit;

[0029] Figure 7 This is a schematic diagram illustrating another embodiment of a differential amplifier that can be utilized in the implementation of an input buffer circuit.

[0030] Explanation of reference numerals in the attached figures:

[0031] 1. Input buffer circuit

[0032] 2. Input buffer circuit

[0033] 3. Input buffer circuit

[0034] 4. Input buffer circuit

[0035] 5. Input buffer circuit

[0036] 11 Input Differential Amplifier Unit

[0037] 12-Input Differential Amplifier Unit

[0038] 13 Input Differential Amplifier Unit

[0039] 20 Differential Amplifier Stages

[0040] 30 Buffer

[0041] 110 First Amplifier Stage

[0042] 115 Capacitive Coupling Circuit

[0043] 121 First Amplifier Stage

[0044] 122 Second Amplifier Stage

[0045] 123 Third Amplifier Stage

[0046] 124 Fourth Amplifier Stage

[0047] 125 First capacitor coupling circuit

[0048] 126 Second Capacitor Coupling Circuit

[0049] 131 First Amplifier Stage

[0050] 132 Second Amplifier Stage

[0051] 135 First Capacitor Coupling Circuit

[0052] 136 Second Capacitor Coupling Circuit

[0053] 10A Input Differential Amplifier Unit

[0054] 10B Input Differential Amplifier Unit

[0055] AMP First Differential Amplifier

[0056] AMP1 First Differential Amplifier

[0057] AMP2 Second Differential Amplifier

[0058] AMP3 Third Differential Amplifier

[0059] AMP4 Fourth Differential Amplifier

[0060] AMP5 First Differential Amplifier

[0061] AMP6 Second Differential Amplifier

[0062] C1 First capacitor

[0063] C11 First capacitor

[0064] C12 Second capacitor

[0065] C2 Second capacitor

[0066] C21 Third Capacitor

[0067] C22 Fourth capacitor

[0068] C3 First Capacitor

[0069] C4 Second capacitor

[0070] IN1 First Input Signal

[0071] IN2 Second Input Signal

[0072] N1 input terminal

[0073] N2 input terminal

[0074] Nout output terminal

[0075] SN1 signal path

[0076] SN2 signal path

[0077] SPN signal path

[0078] SPN1 signal path

[0079] SPN2 signal path

[0080] SPX signal path

[0081] SPX1 First pair of signal paths

[0082] SPX2 Second Pair of Signal Paths

[0083] SX1 First Signal Path

[0084] SX2 Second Signal Path Detailed Implementation

[0085] To facilitate understanding of the objectives, features, and effects of the present invention, embodiments and accompanying drawings are provided for a detailed description of the invention.

[0086] Several embodiments of input buffer circuits will be provided, which are capable of having additional signal paths for first and second input signals for differential input signals. As described below, the input buffer circuit with additional signal paths can help protect against accidental short circuits to voltage or ground at the input of the input buffer circuit, thereby improving the reliability of devices utilizing the input buffer circuit (e.g., data receivers, network devices, computer devices, memory devices, etc.).

[0087] Please refer to Figure 1 Or 2, a block diagram illustrating input buffer circuits according to various embodiments of the present invention. For example... Figure 1As shown in Figure 2, the input buffer circuit 1 (or 2) includes an input differential amplifier unit 10A (or 10B), a differential amplifier stage 20, and a buffer 30.

[0088] The input differential amplifier unit (e.g., 10A or 10B) has multiple input terminals and at least one output terminal, wherein at least two input terminals of the input differential amplifier unit (e.g., 10A or 10B) are configured to be capacitively coupled respectively to provide at least one pair of signal paths, such as represented by SPX, for the first input signal IN1 and the second input signal IN2 of the differential input signal.

[0089] The differential amplifier stage 20 is coupled to the input differential amplifier unit (e.g., 10A or 10B). The differential amplifier stage 20 has a first differential input terminal, a second differential input terminal, and a corresponding output terminal. The first differential input terminal and the second differential input terminal can be coupled to the first input signal IN1 and the second input signal IN2, respectively, as shown below. Figure 1 As shown, this is to provide another pair of signal paths represented by SPN for the first input signal IN1 and the second input signal IN2.

[0090] The buffer 30 is coupled to the output terminal of the differential amplifier stage 20, and the buffer 30 is used to output a single-ended signal.

[0091] like Figure 1 and 2 As shown, the differential amplifier stage 20 can be coupled to the input differential amplifier unit (e.g., 10A or 10B) in different ways.

[0092] exist Figure 1 In the embodiment shown, the output of the differential amplifier stage 20 can be coupled (e.g., electrically connected) in parallel to the output of the input differential amplifier unit 10A.

[0093] exist Figure 2 In the illustrated embodiment, the differential amplifier stage 20 can be coupled (e.g., electrically connected) in series to the input differential amplifier unit 10B. For example, with Figure 1Compared to the input differential amplifier unit 10A, the input differential amplifier unit 10B further has two input terminals that can be coupled to the first input signal IN1 and the second input signal IN2, respectively, to provide another pair of signal paths represented by SPN for the first input signal IN1 and the second input signal IN2. In this way, the input differential amplifier unit 10B has two output terminals that can be coupled (e.g., electrically connected) to the first and second differential input terminals of the differential amplifier stage 20, respectively.

[0094] As shown in the embodiments, the input buffer circuit (e.g., 1 or 2) includes the input differential amplifier unit (e.g., 10A or 10B) and differential amplifier stage 20, so as to include at least two amplifier stages capable of providing at least one pair of signal paths (e.g., SPN) and at least one pair of capacitively coupled signal paths (e.g., SPX) for the differential input signal. This circuit configuration of the input buffer circuit can help protect against the possibility of the input of the input buffer circuit being accidentally shorted to voltage or ground, as will be illustrated below.

[0095] Figure 3 The diagram is shown in the form of a block diagram. Figure 1 An embodiment of the input buffer circuit. For example... Figure 3 As shown, the input buffer circuit 3 includes an input differential amplifier unit 11, a differential amplifier stage 20, and a buffer 30. Figure 3 In this configuration, the differential amplifier stage 20 is coupled (e.g., electrically connected) in parallel to the input differential amplifier unit 11.

[0096] The input differential amplifier unit 11 has two input terminals and an output terminal. The two input terminals of the input differential amplifier unit 11 are capacitively coupled to provide at least one pair of signal paths for the first input signal IN1 and the second input signal IN2 of the differential input signal. The differential amplifier stage 20 is coupled to the input differential amplifier unit 11. The differential amplifier stage 20 has a first differential input terminal, a second differential input terminal, and a corresponding output terminal. The first differential input terminal and the second differential input terminal can be coupled to the first input signal IN1 and the second input signal IN2, respectively. The buffer 30 is coupled to the output terminal of the differential amplifier stage 20 and is used to output a single-ended signal.

[0097] like Figure 3As shown, the input differential amplifier unit 11 includes a first amplifier stage 110. The first amplifier stage 110 includes a first differential amplifier AMP, which has a first input terminal, a second input terminal, and a first output terminal as the output terminal of the input differential amplifier unit 11. The first input terminal and the second input terminal are configured to be capacitively coupled to the first input signal IN1 and the second input signal IN2, respectively, to provide a pair of signal paths for the first input signal IN1 and the second input signal IN2. The first output terminal is coupled to the corresponding output terminal of the differential amplifier stage 20. The first and second input terminals are the input terminals of the input differential amplifier unit 11, and the first output terminal is the output terminal of the input differential amplifier unit 11.

[0098] In one embodiment, the first amplifier stage 110 further includes a capacitive coupling circuit 115, wherein the first input terminal and the second input terminal are respectively able to receive the first input signal IN1 and the second input signal IN2 through the capacitive coupling circuit 115.

[0099] In one embodiment, the capacitive coupling circuit 115 includes a first capacitor C1 coupled to the first input terminal and a second capacitor C2 coupled to the second input terminal.

[0100] In one embodiment, the buffer 30 may include at least one inverter as an inverting buffer. In another embodiment, such as Figure 3 As shown, the buffer may include multiple inverters (e.g., two inverters) connected as a buffer gate.

[0101] like Figure 3 As shown, the input buffer circuit 3 includes the input differential amplifier unit 11 and the differential amplifier stage 20, so as to include at least two amplifier stages, which are capable of providing at least one pair of signal paths (e.g., SPN) for the differential input signal and at least one pair of capacitively coupled signal paths (e.g., SPX) for the differential input signal.

[0102] In the practical application of the input buffer circuit 3, the two input terminals of the input differential amplifier unit 11 provide a pair of capacitively coupled signal paths SPX for receiving the differential input signals (e.g., IN1 and IN2), and the first and second differential input terminals of the differential amplifier stage 20 provide a pair of signal paths SPN for receiving the differential input signals (e.g., IN1 and IN2). Under normal circumstances, there are no undesirable connections between the four input terminals and a voltage (e.g., a voltage source) or ground. In this case, the differential amplifier stage 20 provides the pair of signal paths SPN, which governs the operation of the input buffer circuit 3, allowing the buffer 30 to output the single-ended output signal based on the differential input signals.

[0103] In an unexpected situation, when one of the two input terminals of the input differential amplifier unit 11 is accidentally connected to a voltage (e.g., a voltage source) or ground, the input buffer circuit 3 can still output the output single-ended signal as if it were operating normally, because the differential amplifier stage 20 provides the signal path SPN.

[0104] In another unforeseen event, when one of the first and second differential inputs of the differential amplifier stage 20 is accidentally connected to a voltage (e.g., a voltage source) or ground, the input differential amplifier unit 11 provides the signal path SPX, which governs the operation of the input buffer circuit 3, allowing the buffer 30 to still output the output single-ended signal normally. For example, when the differential input signal is a differential frequency signal, the input buffer circuit 3 can output the output single-ended signal, the duty cycle of which corresponds to the duty cycle of the differential frequency signal.

[0105] Compared to existing input buffer circuits that only have an amplifier stage (or only one pair of signal paths) for the differential input signal, the input buffer circuit 3 is more reliable because it has two pairs of signal paths for the differential input signal, thereby further reducing the risk of the input being accidentally connected to voltage or ground.

[0106] Therefore, the circuit configuration of the input buffer circuit 3 can help protect against accidental short circuits to voltage or ground at the input of the input buffer circuit, thereby improving the reliability of the device using the input buffer circuit 3.

[0107] Figure 4 It shows based on Figure 2 A block diagram of an embodiment of the input buffer circuit. (See diagram below.) Figure 4As shown, the input buffer circuit 4 includes an input differential amplifier unit 12, a differential amplifier stage 20, and a buffer 30. Figure 4 In this configuration, the differential amplifier stage 20 is coupled (e.g., electrically connected) in series to the input differential amplifier unit 12.

[0108] In one embodiment, the input differential amplifier unit 12 includes a first amplifier stage 121, a second amplifier stage 122, a third amplifier stage 123, and a fourth amplifier stage 124. The first amplifier stage 121 includes a first differential amplifier AMP1, which has a first input terminal (e.g., a non-inverting input), a second input terminal (e.g., an inverting input), and a first output terminal, wherein the first input terminal and the second input terminal are respectively capable of receiving the first input signal IN1 and the second input signal IN2. The second amplifier stage 122 includes a second differential amplifier AMP2, which has a third input terminal (e.g., a non-inverting input), a fourth input terminal (e.g., an inverting input), and a second output terminal, wherein the third input terminal and the fourth input terminal are configured to capacitively couple to the first input signal IN1 and the second input signal IN2, respectively, to provide a first pair of signal paths (e.g., represented by SPX1) for the first input signal IN1 and the second input signal IN2. The third amplifier stage 123 includes a third differential amplifier AMP3 having a fifth input (e.g., a non-inverting input), a sixth input (e.g., an inverting input), and a third output, wherein the fifth and sixth inputs are capable of receiving the second input signal IN2 and the first input signal IN1, respectively. The fourth amplifier stage 124 includes a fourth differential amplifier AMP4 having a seventh input (e.g., a non-inverting input), an eighth input (e.g., an inverting input), and a fourth output, wherein the seventh and eighth inputs are configured to capacitively couple to the second input signal IN2 and the first input signal IN1, respectively, to provide a second pair of signal paths (e.g., represented by SPX2) for the first input signal IN1 and the second input signal IN2. The first and second outputs are coupled to the first differential input, and the third and fourth outputs are coupled to the second differential input. The plurality of input terminals of the input differential amplifier unit 12 include the first to eighth input terminals, and the input differential amplifier unit 12 has a plurality of output terminals including the first to fourth output terminals.

[0109] In one embodiment, the input differential amplifier unit 12 further includes a first capacitive coupling circuit 125 and a second capacitive coupling circuit 126. The third input terminal and the fourth input terminal can receive the first input signal IN1 and the second input signal IN2 respectively through the first capacitive coupling circuit 125. The seventh input terminal and the eighth input terminal can receive the second input signal IN2 and the first input signal IN1 respectively through the second capacitive coupling circuit 126.

[0110] In one embodiment, the first capacitive coupling circuit 125 includes a first capacitor C11 coupled to the third input terminal and a second capacitor C12 coupled to the fourth input terminal.

[0111] In one embodiment, the second capacitive coupling circuit 126 includes a third capacitor C21 coupled to the seventh input terminal and a fourth capacitor C22 coupled to the eighth input terminal.

[0112] like Figure 4 As shown, the input buffer circuit 4 includes the input differential amplifier unit 12 and the differential amplifier stage 20 to provide four different signal paths (e.g., SPN1, SPN2, SPX1, SPX2) for the differential input signal.

[0113] In the practical application of the input buffer circuit 4, the first and second input terminals, and the fifth and sixth input terminals of the input differential amplifier unit 12 provide two pairs of signal paths (e.g., SPN1, SPN2) for receiving the differential input signal, while the third and fourth input terminals, and the seventh and eighth input terminals of the input differential amplifier unit 12 provide two pairs of capacitively coupled signal paths (e.g., SPX1, SPX2). These input terminals are not undesirably connected to a voltage (e.g., a voltage source) or ground. Under normal conditions, the first and third differential amplifiers AMP1 and AMP3, providing the two pairs of signal paths SPN1 and SPN2, can control the operation of the input buffer circuit 4, allowing the buffer 30 to output the single-ended output signal based on the differential input signal.

[0114] In an unexpected situation, when one end of one of the two pairs of input terminals of the input differential amplifier unit 12, which provides two pairs of capacitively coupled signal paths SPX1 and SPX2, is accidentally connected to voltage (e.g., voltage source) or ground, the first and third differential amplifiers AMP1 and AMP3, which provide the two pairs of signal paths SPN1 and SPN2, can control the operation of the input buffer circuit 4, so that the buffer 30 can still output the output single-ended signal under normal operation.

[0115] In another unexpected scenario, when one end of one of the two pairs of input terminals of the input differential amplifier unit 12, which provides the two pairs of signal paths SPN1 and SPN2, is accidentally connected to voltage (e.g., a voltage source) or ground, the second and fourth differential amplifiers AMP2 and AMP4, which provide the two pairs of capacitively coupled signal paths SPX1 and SPX2, can dominate the input buffer circuit 4, allowing the buffer 30 to still output the single-ended output signal normally. For example, when the differential input signal is a differential frequency signal, the input buffer circuit 4 can output the single-ended output signal, the duty cycle of which corresponds to the duty cycle of the differential frequency signal.

[0116] Compared to the output buffer circuit 3, the input buffer circuit 4 is more reliable because it has four pairs of signal paths for the differential input signal, thereby further reducing the risk of the input terminal being accidentally connected to voltage or ground.

[0117] Therefore, the circuit configuration of the input buffer circuit 4 can help protect against accidental short circuits to voltage or ground at the input of the input buffer circuit, thereby improving the reliability of the device using the input buffer circuit 4.

[0118] Figure 5 It shows based on Figure 2 A block diagram of another embodiment of the input buffer circuit. (See also...) Figure 5 As shown, the input buffer circuit 5 includes an input differential amplifier unit 13, a differential amplifier stage 20, and a buffer 30. Figure 5 In this configuration, the differential amplifier stage 20 is coupled (e.g., electrically connected) in series to the input differential amplifier unit 13.

[0119] In one embodiment, the input differential amplifier unit 13 includes a first amplifier stage 131 and a second amplifier stage 132. The first amplifier stage 131 includes a first differential amplifier AMP5, which has a first input terminal (e.g., a non-inverting input), a second input terminal (e.g., an inverting input), and a first output terminal, wherein the first input terminal and the second input terminal are respectively capable of receiving the first input signal IN1 and the second input signal IN2. The first input terminal is configured to be capacitively coupled to the first output terminal, and the first output terminal is coupled to the first differential input terminal (e.g., a non-inverting input) to provide a first signal path SX1 for the first input signal IN1. The second amplifier stage 132 includes a second differential amplifier AMP6, which has a third input terminal (e.g., an inverting input), a fourth input terminal (e.g., a non-inverting input), and a second output terminal, wherein the third input terminal and the fourth input terminal are respectively capable of receiving the first input signal IN1 and the second input signal IN2. The fourth input terminal is configured to be capacitively coupled to the second output terminal, and the second output terminal is coupled to the second differential input terminal (e.g., the inverting input) to provide a second signal path SX2 for the second input signal IN2. The plurality of input terminals of the input differential amplifier unit 13 include the first to fourth input terminals, and the input differential amplifier unit 13 has a plurality of output terminals including the first and second output terminals. In this way, the input differential amplifier unit 13 provides a pair of capacitively coupled signal paths via the first and second signal paths SX1 and SX2.

[0120] In one embodiment, the input differential amplifier unit 13 includes a first capacitive coupling circuit 135 coupled between the first input terminal and the first output terminal; and a second capacitive coupling circuit 136 coupled between the fourth input terminal and the second output terminal.

[0121] In one embodiment, the first capacitive coupling circuit 135 includes a first capacitor (e.g., C3) coupled between the first input terminal and the first output terminal.

[0122] In one embodiment, the second capacitive coupling circuit 136 includes a second capacitor (e.g., C4) coupled between the fourth input terminal and the second output terminal.

[0123] In the practical application of the input buffer circuit 5, the first and fourth input terminals of the input differential amplifier unit 13 provide a pair of capacitively coupled signal paths (e.g., SX1, SX2) for receiving the differential input signal (e.g., IN1 and IN2), while the second and third input terminals of the input differential amplifier unit 13 provide a pair of signal paths (e.g., SN1, SN2) for the differential input signal. Under normal circumstances, there is no undesirable connection between the above-mentioned input terminals and voltage (e.g., voltage source) or ground. In this case, the capacitively coupled signal paths (e.g., SX1, SX2) can couple the differential input signal to the differential amplifier stage 20, so that the buffer 30 can output the output single-ended signal based on the differential input signal. In this case, the first and fourth input terminals providing the capacitively coupled signal paths can be considered as the inputs that dominate the differential input signal.

[0124] In an unexpected situation, when one end of the second and third terminals of the input differential amplifier unit 13, which provides a pair of signal paths (e.g., SN1 and SN2), is accidentally connected to a voltage (e.g., a voltage source) or ground, the input of the differential input signal to the input buffer circuit 5 can be dominated by the first and fourth input terminals, which provide a pair of capacitively coupled signal paths (e.g., SX1 and SX2), so that the buffer 30 can still output the output single-ended signal as in normal operation.

[0125] In another unexpected scenario, when one end of the first and fourth input terminals of the input differential amplifier unit 13, which provides the signal paths (e.g., SX1 and SX2) for capacitive coupling, is accidentally connected to a voltage (e.g., a voltage source) or ground, the second and third input terminals providing the signal paths (e.g., SN1 and SN2) can dominate the input of the differential input signal to the input buffer circuit 5, and the differential input signal can be coupled to the differential amplifier stage 20 through the first and second amplifier stages 131 and 132, so that the buffer 30 can still output the output single-ended signal normally. For example, when the differential input signal is a differential frequency signal, the input buffer circuit 5 can output the output single-ended signal, the duty cycle of which corresponds to the duty cycle of the differential frequency signal.

[0126] Compared to existing input buffer circuits that only have an amplifier stage (or only for the signal path) for the differential input signal, the input buffer circuit 5 is more reliable due to having two pairs of signal paths for the differential input signal, thereby further reducing the risk of accidental connection of the input to voltage or ground.

[0127] Therefore, the circuit configuration of the input buffer circuit 5 can help protect against accidental short circuits to voltage or ground at the input of the input buffer circuit, thereby improving the reliability of the device using the input buffer circuit 5.

[0128] In the above embodiments, the buffer 30 may include one or more inverters as a buffer. Of course, the embodiments of the present invention are not limited to these examples.

[0129] exist Figure 1-5 In any embodiment, the input differential amplifier unit (e.g., 10A, 10B, 11-13) can be implemented using a differential amplifier, wherever appropriate. For example, Figure 6 An embodiment of a differential amplifier that can be utilized in the implementation of the input buffer circuit is shown. Figure 7 Another embodiment of a differential amplifier that can be utilized in the implementation of the input buffer circuit is shown. As in Figure 6 As shown in Figure 7, the differential amplifier has two input terminals N1 and N2 and an output terminal Nout.

[0130] In some embodiments, it can be configured based on Figure 1-5 The input buffer circuit in any of the embodiments is such that the capacitively coupled circuit can be implemented or regarded as an environmental component. For example, the input of the input buffer circuit is configured to be capacitively coupled, such that the input can be coupled to a capacitively coupled circuit (e.g., a capacitor) regarded as an environmental component. For example, the input buffer circuit can be implemented as a chip with some specific pins for designers or technicians to arbitrarily connect to one or more capacitively coupled circuits.

[0131] In other embodiments, based on reasons of use or product manufacturing, Figure 1-5 Any one of the input buffer circuits in one of the plurality of embodiments may be configured to include the capacitive coupling circuit.

[0132] Furthermore, as in the above embodiments, the input buffer circuit (e.g., Figure 1-5The input buffer circuit can be exemplified by receiving a differential input signal, such as a differential frequency input signal. However, the implementation of the invention is not limited to the type of input signal received by the input buffer circuit. In some examples of practical applications, a single-ended input signal (such as a frequency signal) can be applied to the input buffer circuit, enabling the device employing the input buffer circuit to receive either a differential input signal or a single-ended input signal. For example, the single-ended input signal can be considered as one of a first and a second input signal (e.g., IN1 or IN2) of the differential input signal and applied to multiple input terminals for the first input signal IN1 or the second input signal IN2, wherein other input terminals that do not receive the single-ended input signal can be configured to be connected to a direct current (DC) voltage. Thus, the input buffer circuit can also help enable the device employing the input buffer circuit to use different types of input signals, where appropriate.

[0133] Although the invention has been described by way of specific embodiments, those skilled in the art can make various modifications, combinations and variations thereto without departing from the scope and spirit of the invention as set forth in the claims.

Claims

1. An input buffer circuit, characterized in that, The input buffer circuit includes: An input differential amplifier unit has a plurality of input terminals and at least one output terminal, wherein at least two of the plurality of input terminals of the input differential amplifier unit are configured to be capacitively coupled respectively to provide at least one pair of signal paths for a first input signal and a second input signal of a differential input signal; A differential amplifier stage, coupled to the input differential amplifier unit, the differential amplifier stage having a first differential input terminal, a second differential input terminal, and a corresponding output terminal, wherein the first differential input terminal and the second differential input terminal can be coupled to the first input signal and the second input signal, respectively; and A buffer, coupled to the output terminal of the differential amplifier stage, is used to output a single-ended signal. The input differential amplifier unit includes: A first amplifier stage includes a first differential amplifier having a first input terminal, a second input terminal, and a first output terminal, wherein the first input terminal and the second input terminal are respectively capable of receiving a first input signal and a second input signal; the first input terminal is configured to be capacitively coupled to the first output terminal, and the first output terminal is coupled to the first differential input terminal to provide a first signal path for the first input signal; and The second amplifier stage includes a second differential amplifier having a third input terminal, a fourth input terminal, and a second output terminal, wherein the third input terminal and the fourth input terminal are respectively capable of receiving the first input signal and the second input signal; the fourth input terminal is configured to be capacitively coupled to the second output terminal, and the second output terminal is coupled to the second differential input terminal to provide a second signal path for the second input signal; The input differential amplifier unit has a plurality of input terminals including the first to fourth input terminals, and the input differential amplifier unit has a plurality of output terminals including the first and second output terminals.

2. The input buffer circuit according to claim 1, characterized in that, The input differential amplifier unit includes: A first capacitive coupling circuit is coupled between the first input terminal and the first output terminal; and The second capacitor coupling circuit is coupled between the fourth input terminal and the second output terminal.

3. The input buffer circuit according to claim 2, characterized in that, The first capacitive coupling circuit includes a first capacitor coupled between the first input terminal and the first output terminal.

4. The input buffer circuit according to claim 2, characterized in that, The second capacitive coupling circuit includes a second capacitor coupled between the fourth input terminal and the second output terminal.

5. The input buffer circuit according to claim 1, characterized in that, The buffer mentioned therein contains at least one inverter.

6. The input buffer circuit according to claim 1, characterized in that, The differential input signal is a differential frequency signal.

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