Display device including overlapping pixel drive circuits

Abstract

A display device including overlapping pixel drive circuits is provided, including: a first pixel drive circuit; an electric field blocking layer on the first pixel drive circuit; a second pixel drive circuit on the electric field blocking layer; and a first display element and a second display element on the second pixel drive circuit, wherein each of the first pixel drive circuit and the second pixel drive circuit includes at least one thin film transistor, the first pixel drive circuit overlaps the second pixel drive circuit, the first display element is connected to the first pixel drive circuit, and the second display element is connected to the second pixel drive circuit.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0188938, filed on December 31, 2020, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0003] This invention relates to a display device including overlapping pixel driving circuits. Background Technology

[0004] Display devices, used to display various information on a screen, are devices that integrate core technologies of the information and communication era. Recently, display devices have been manufactured to be thinner and lighter, and have been developed to achieve high performance.

[0005] Thin-film transistors (TFTs) are used as switching or driving elements to drive the pixels that make up a display device. As display devices achieve higher quality and resolution, TFTs are highly integrated into them. Consequently, a large number of TFTs are placed in a limited area, leading to TFT crowding and insufficient capacitor area.

[0006] Therefore, it is necessary to study methods to solve the problem of thin-film transistor congestion in display devices and to place a large number of thin-film transistors in a limited area. Summary of the Invention

[0007] The present invention was developed in view of the above-mentioned problems. One object of the present invention is to provide a display device with high-density integration of thin-film transistors. Another object of the present invention is to provide a high-resolution display device.

[0008] Another object of the present invention is to provide a display device in which a plurality of pixel driving circuits are arranged overlapping each other to provide a large number of thin-film transistors in a limited area.

[0009] Another object of the present invention is to provide a display device that can have excellent display performance even when thin-film transistors are arranged overlapping each other, due to the absence of electrical interference between the thin-film transistors.

[0010] Another object of the present invention is to provide a display device comprising pixels that, despite their small size, can be stably driven.

[0011] In addition to the objectives of the present invention described above, other objectives and features of the present invention will become clear to those skilled in the art from the following description.

[0012] According to one aspect of the present invention, the above and other objectives can be achieved by providing a display device comprising: a first pixel driving circuit; an electric field blocking layer on the first pixel driving circuit; a second pixel driving circuit on the electric field blocking layer; and a first display element and a second display element on the second pixel driving circuit, wherein each of the first pixel driving circuit and the second pixel driving circuit includes at least one thin-film transistor, the first pixel driving circuit and the second pixel driving circuit overlap, the first display element is connected to the first pixel driving circuit, and the second display element is connected to the second pixel driving circuit.

[0013] The first display element may overlap with the first pixel driving circuit and the second pixel driving circuit, and the second display element may overlap with the first pixel driving circuit and the second pixel driving circuit.

[0014] The electric field blocking layer may have a thickness of 1 μm or greater between the first pixel driving circuit and the second pixel driving circuit, and the thickness of the electric field blocking layer may be limited to the distance between the upper surface of the first pixel driving circuit and the lower surface of the second pixel driving circuit.

[0015] The electric field blocking layer may have a dielectric constant of 3.9 or less.

[0016] The electric field blocking layer may include siloxane compounds.

[0017] Each of the first pixel driving circuit and the second pixel driving circuit may include two or more thin-film transistors.

[0018] Each of the first pixel driving circuit and the second pixel driving circuit may include four or more thin-film transistors.

[0019] Any thin-film transistor of the first pixel driving circuit and any thin-film transistor of the second pixel driving circuit may overlap each other, and each of the overlapping thin-film transistors of the first pixel driving circuit and the second pixel driving circuit may include: an active layer; and a gate electrode separated from and at least partially overlapping the active layer, and the separation distance between the gate electrode of the thin-film transistor of the first pixel driving circuit and the active layer of the thin-film transistor of the second pixel driving circuit may be 1 μm or greater.

[0020] The first display element may include a first electrode, a first organic light-emitting layer, and a second electrode, and the second display element may include a first electrode, a second organic light-emitting layer, and a second electrode.

[0021] Each of the first electrode of the first display element and the first electrode of the second display element may have a reflective layer.

[0022] The display device may be a top-emitting type in which each of the first display element and the second display element emits light through the second electrode.

[0023] The display device may further include: a dam layer defining a light-emitting area of ​​the first display element and a light-emitting area of ​​the second display element; a first connecting portion connecting the first display element to the first pixel driving circuit; and a second connecting portion connecting the second display element to the second pixel driving circuit, wherein at least one of the first connecting portion and the second connecting portion may overlap with the dam layer.

[0024] At least a portion of the first connecting portion may overlap with the embankment layer.

[0025] The first connection may include a first portion passing through the electric field blocking layer, the first portion overlapping the dam layer.

[0026] Each of the thin-film transistors in the first pixel driving circuit and the second pixel driving circuit may include an active layer and a gate electrode separated from the active layer, and the thickness t of the electric field blocking layer may satisfy the following equation 1:

[0027] [Equation 1]

[0028] t≥(V GH / V TH )×(κ / 3.9)×(t GI ),

[0029] In Equation 1, t is the thickness of the electric field blocking layer, κ is the dielectric constant of the electric field blocking layer, and V... GH It is the on-state voltage of the thin-film transistor applied to the first pixel driving circuit, V TH It is the threshold voltage of the thin-film transistor in the second pixel driving circuit, t GI It is the distance between the gate electrode of the thin-film transistor in the second pixel driving circuit and the active layer.

[0030] According to another aspect of the present invention, the above and other objectives can be achieved by providing a display device comprising: a first pixel, the first pixel including a first pixel driving circuit and a first display element connected to the first pixel driving circuit; a second pixel, the second pixel including a second pixel driving circuit and a second display element connected to the second pixel driving circuit; a third pixel, the third pixel including a third pixel driving circuit and a third display element connected to the third pixel driving circuit; a fourth pixel, the fourth pixel including a fourth pixel driving circuit and a fourth display element connected to the fourth pixel driving circuit; and an electric field blocking layer disposed between the first pixel driving circuit and the second pixel driving circuit and between the third pixel driving circuit and the fourth pixel driving circuit, wherein the first pixel driving circuit and the second pixel driving circuit overlap each other, the third pixel driving circuit and the fourth pixel driving circuit overlap each other, the first pixel and the second pixel constitute a first display unit, the third pixel and the fourth pixel constitute a second display unit, and the first display unit and the second display unit are adjacent to each other.

[0031] The electric field blocking layer may have a thickness of 1 μm or greater. In this case, the thickness of the electric field blocking layer may be limited to the distance between the upper surface of the first pixel driving circuit and the lower surface of the second pixel driving circuit.

[0032] The electric field blocking layer may have a dielectric constant of 3.9 or less.

[0033] The electric field blocking layer may include siloxane compounds.

[0034] Each of the first pixel driving circuit and the second pixel driving circuit may include at least one thin-film transistor. Each of the thin-film transistors in the first pixel driving circuit and the second pixel driving circuit may include an active layer and a gate electrode separated from the active layer. The thickness t of the electric field blocking layer may satisfy the following equation 1:

[0035] [Equation 1]

[0036] t≥(V GH / V TH )x(κ / 3.9)x(t GI ),

[0037] In Equation 1, t is the thickness of the electric field blocking layer, κ is the dielectric constant of the electric field blocking layer, and V... GH It is the on-state voltage of the thin-film transistor applied to the first pixel driving circuit, V TH It is the threshold voltage of the thin-film transistor in the second pixel driving circuit, tGI It is the distance between the gate electrode of the thin-film transistor in the second pixel driving circuit and the active layer.

[0038] Each of the first pixel driving circuit, the second pixel driving circuit, the third pixel driving circuit, and the fourth pixel driving circuit may include two or more thin-film transistors.

[0039] The display device is a top-emitting display device.

[0040] Each of the first pixel driving circuit, the second pixel driving circuit, the third pixel driving circuit, and the fourth pixel driving circuit may include four or more thin-film transistors.

[0041] The first pixel may display a first color, the second pixel may display a second color, the third pixel may display a third color, and the fourth pixel may display a fourth color. The first color, the second color, the third color, and the fourth color may be different from each other, and any one of the first color, the second color, the third color, and the fourth color may be white.

[0042] One of the first color, the second color, the third color, and the fourth color can be red, another can be green, and the last one can be blue.

[0043] The first pixel can display a first color, the second pixel can display a second color, the third pixel can display the first color, and the fourth pixel can display a third color. The first color, the second color, and the third color can be different from each other.

[0044] The first color can be green, and either the second color or the third color can be red, while the other can be blue.

[0045] The display device may further include a light-transmitting portion adjacent to the first display unit and the second display unit, wherein the light-transmitting portion can transmit light.

[0046] The display device may further include: a fifth pixel, the fifth pixel including a fifth pixel driving circuit and a fifth display element connected to the fifth pixel driving circuit; and a sixth pixel, the sixth pixel including a sixth pixel driving circuit and a sixth display element connected to the sixth pixel driving circuit, wherein the fifth pixel driving circuit and the sixth pixel driving circuit may overlap each other, the electric field blocking layer may be disposed between the fifth pixel driving circuit and the sixth pixel driving circuit, the fifth pixel and the sixth pixel may constitute a third display unit, and the third display unit may be adjacent to at least one of the first display unit and the second display unit.

[0047] The first pixel can display a first color, the second pixel can display a second color, the third pixel can display a third color, the fourth pixel can display the first color, the fifth pixel can display the second color, and the sixth pixel can display the third color, and the first color, the second color, and the third color can be different colors from each other.

[0048] The first color can be red, the second color can be green, and the third color can be blue. Attached Figure Description

[0049] The above and other objects, features and advantages of the invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0050] Figure 1 This is a schematic diagram illustrating a display device according to an embodiment of the present invention;

[0051] Figure 2 It is a diagram Figure 1 The circuit diagram of any pixel;

[0052] Figure 3 This is a schematic diagram illustrating the pixel array of a display device according to an embodiment of the present invention;

[0053] Figure 4 This is a schematic plan view illustrating the first pixel and the second pixel according to an embodiment of the present invention;

[0054] Figure 5 This is a plan view illustrating the first pixel driving circuit;

[0055] Figure 6 It is a plan view illustrating the second pixel driving circuit and display element;

[0056] Figure 7 It is along Figure 4 , Figure 5 and Figure 6 A cross-sectional view taken from line I-I';

[0057] Figure 8 It is a diagram Figure 7 A magnified view of a portion;

[0058] Figure 9 This is a circuit diagram illustrating the pixels of a display device according to another embodiment of the present invention;

[0059] Figure 10 This is a circuit diagram illustrating the pixels of a display device according to another embodiment of the present invention;

[0060] Figure 11 It is a diagram. Figure 10 A schematic cross-sectional view of one embodiment of a display device with pixels;

[0061] Figure 12 It is a diagram illustrating the voltage-current curves of a thin-film transistor according to the embodiments and comparative examples;

[0062] Figure 13A This is a plan view illustrating the pixel array of a display device according to another embodiment of the present invention;

[0063] Figure 13B yes Figure 13A A schematic perspective view;

[0064] Figure 14 This is a plan view illustrating the pixel array of a display device according to another embodiment of the present invention;

[0065] Figure 15 This is a plan view illustrating the pixel array of a display device according to yet another embodiment of the present invention;

[0066] Figure 16 This is a plan view illustrating the pixel array of a display device according to yet another embodiment of the present invention. Detailed Implementation

[0067] The advantages and features of the invention, and its implementation methods, will be illustrated by the following embodiments described with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments listed herein. Rather, these embodiments are provided to make the disclosure of the invention comprehensive and complete, and to fully convey the scope of the invention to those skilled in the art. Furthermore, the invention is defined only by the scope of the claims.

[0068] The shapes, dimensions, proportions, angles, and quantities disclosed in the accompanying drawings for the purpose of describing embodiments of the invention are merely examples, and therefore the invention is not limited to the details illustrated. Similar reference numerals denote similar elements throughout. In the following description, detailed descriptions of related known functions or constructions will be omitted where it is determined that such detailed descriptions would unnecessarily obscure the focus of the invention.

[0069] Where the terms “including,” “having,” and “contains” are used in this application, additional parts may be added unless “only” is used.

[0070] When interpreting a factor, even if not explicitly stated, the factor should be interpreted as including a range of error.

[0071] When describing positional relationships, such as when the positional relationship is described as "on," "above," "below," and "after," one or more other parts may be arranged between the two parts, unless "exactly" or "directly" is used.

[0072] Spatially relative terms such as “below,” “under,” “below,” “above,” and “above” may be used throughout this document to readily describe the relationship of one or more elements shown in the figures to other elements. It will be understood that these terms are intended to cover different device locations other than those depicted in the figures. For example, if the device shown in the figures is inverted, a device described as being arranged “below” or “below” another device may be arranged “above” another device. Thus, the exemplary term “below or below” can include both “below or below” and “above” locations. Similarly, the exemplary terms “above” or “on” can include both “above” and “below or below” locations.

[0073] When describing temporal relationships, such as when time sequence is described as “after,” “following,” “next,” and “before,” discontinuous cases may be included unless “exactly” or “directly” is used.

[0074] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, without departing from the scope of the invention, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0075] The term "at least one" should be understood to include all combinations of any one or more of the relevant listed items. For example, "at least one of the first, second, and third items" could mean a combination of all items selected from the first, second, and third items, as well as the first, second, or third item.

[0076] As will be fully understood by those skilled in the art, the features of the various embodiments of the present invention can be combined or integrated with each other, either partially or entirely, and can be technically interoperable and driven in various ways. The embodiments of the present invention can be implemented independently of each other or together in an interdependent relationship.

[0077] In the accompanying drawings, identical or similar elements are indicated by the same reference numerals, even though they are depicted in different drawings. Use the same reference numerals throughout the drawings whenever possible to denote identical or similar parts.

[0078] In embodiments of the present invention, for ease of description, the source electrode and the drain electrode are distinguished from each other. However, the source electrode and the drain electrode can be used interchangeably. The source electrode can be the drain electrode, and the drain electrode can be the source electrode. Furthermore, the source electrode in any embodiment of the present invention can be the drain electrode in other embodiments of the present invention, and the drain electrode in any embodiment of the present invention can be the source electrode in other embodiments of the present invention.

[0079] In some embodiments of the present invention, for ease of description, the source region is distinguished from the source electrode, and the drain region is distinguished from the drain electrode. However, the embodiments of the present invention are not limited to this structure. For example, the source region may be the source electrode, and the drain region may be the drain electrode. Furthermore, the source region may be the drain electrode, and the drain region may be the source electrode.

[0080] Figure 1 This is a schematic diagram illustrating a display device 100 according to an embodiment of the present invention.

[0081] like Figure 1 As shown, the display device 100 includes a display panel 310, a gate driver 320, a data driver 330, and a controller 340.

[0082] A gate line GL and a data line DL are provided in the display panel 310, and a pixel P is provided in the intersection area of ​​the gate line GL and the data line DL. An image is displayed by driving the pixel P.

[0083] The controller 340 controls the gate driver 320 and the data driver 330.

[0084] The controller 340 outputs a gate control signal GCS for controlling the gate driver 320 and a data control signal DCS for controlling the data driver 330 using signals provided from an external system (not shown). Furthermore, the controller 340 samples input image data from the external system, rearranges the sampled data, and provides the rearranged digital image data (RGB) to the data driver 330.

[0085] The gate control signal GCS includes the gate start pulse GSP, the gate shift clock GSC, the gate output enable signal GOE, the start signal Vst, and the gate clock GCLK. Furthermore, the gate control signal GCS may include control signals for controlling the shift register.

[0086] The data control signal DCS includes the source start pulse SSP, the source shift clock signal SSC, the source output enable signal SOE, and the polarity control signal POL.

[0087] The data driver 330 provides data voltage to the data line DL of the display panel 310. Specifically, the data driver 330 converts the image data RGB input from the controller 340 into analog data voltage and provides the data voltage to the data line DL.

[0088] The gate driver 320 includes a shift register 350.

[0089] The shift register 350 sequentially provides gate pulses to the gate line GL within a frame using a start signal and a gate clock transmitted from the controller 340. In this case, a frame refers to a time period during which an image is output through the display panel 310. The gate pulses have an on-state voltage for turning on the switching elements (thin-film transistors) disposed in the pixel P.

[0090] In addition, shift register 350 provides a gate cut-off signal to gate line GL during other periods in a frame when no gate pulse is provided, which turns off the switching element. Hereinafter, the gate pulse and gate cut-off signal are collectively referred to as the scan signal SS or Scan.

[0091] According to one embodiment of the present invention, the gate driver 320 may be packaged on the display panel 310. In this way, the structure in which the gate driver 320 is directly packaged on the display panel 310 is referred to as a gate-in-panel (GIP) structure.

[0092] Figure 2 yes Figure 1 The circuit diagram for any one pixel.

[0093] Figure 2The circuit diagram is an equivalent circuit diagram of pixel P of the display device, which includes an organic light-emitting diode (OLED) as a display element DU. According to one embodiment of the present invention, the display device 100 is an organic light-emitting display device including an organic light-emitting diode (OLED).

[0094] Pixel P includes display element DU and pixel driving circuit PDC for driving display element DU.

[0095] Figure 2 The pixel driving circuit PDC includes a first thin-film transistor TR1 as a switching transistor and a second thin-film transistor TR2 as a driving transistor.

[0096] The first thin-film transistor TR1 is connected to the gate line GL and the data line DL, and the first thin-film transistor TR1 is turned on or off by the scan signal SS provided through the gate line GL.

[0097] The data line DL provides the data voltage Vdata to the pixel driving circuit PDC, and the first thin-film transistor TR1 controls the application of the data voltage Vdata.

[0098] The driving power line PL provides a driving voltage Vdd to the display element DU, and the second thin-film transistor TR2 controls the driving voltage Vdd. The driving voltage Vdd is the pixel driving voltage used to drive the organic light-emitting diode (OLED) that serves as the display element DU.

[0099] When the first thin-film transistor TR1 is turned on by the scan signal SS applied from the gate driver 320 via the gate line GL, the data voltage Vdata supplied via the data line DL is provided to the gate electrode of the second thin-film transistor TR2, which is connected to the display element DU. The data voltage Vdata is charged into the first capacitor C1 formed between the gate electrode and the source electrode of the second thin-film transistor TR2. The first capacitor C1 is a storage capacitor Cst.

[0100] The amount of current supplied to the organic light-emitting diode (OLED) that serves as the display element DU is controlled by the data voltage Vdata, thereby controlling the gray level of the light emitted from the display element DU.

[0101] Figure 3 This is a schematic diagram illustrating an array of pixels P1 and P2 in a display device according to an embodiment of the present invention.

[0102] Reference Figure 3According to one embodiment of the present invention, a display device 100 includes a first pixel driving circuit PDC1, an electric field blocking layer 210 on the first pixel driving circuit PDC1, a second pixel driving circuit PDC2 on the electric field blocking layer 210, and a first display element DU1 and a second display element DU2 on the second pixel driving circuit PDC2.

[0103] Each of the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2 may include at least one thin-film transistor.

[0104] According to one embodiment of the present invention, the first display element DU1 is connected to the first pixel driving circuit PDC1. (Refer to...) Figure 3 The first display element DU1 and the first pixel driving circuit PDC1 can be connected to each other through the connecting part CT1.

[0105] A first pixel P1 can be formed by a first display element DU1 and a first pixel driving circuit PDC1. The first pixel P1 may further include a color filter. The first pixel P1 may have... Figure 2 The pixel P shown has the same structure. The first pixel P1 can be derived from... Figure 2 The circuit diagram is shown.

[0106] The first pixel driving circuit PDC1 can have the same... Figure 2 The pixel driving circuit PDC shown has the same structure. The first pixel driving circuit PDC1 can be composed of the same... Figure 2 The pixel driving circuit PDC shown is represented by the same circuit diagram. The first display element DU1 may be, for example, an organic light-emitting diode (OLED). The first display element DU1 may include an organic light-emitting layer.

[0107] According to one embodiment of the present invention, the second display element DU2 is connected to the second pixel driving circuit PDC2. (Refer to...) Figure 3 The second display element DU2 and the second pixel driving circuit PDC2 can be connected to each other through the connecting part CT2.

[0108] The second pixel P2 can be formed by the second display element DU2 and the second pixel driving circuit PDC2. The second pixel P2 may further include a color filter. The second pixel P2 may have... Figure 2 The second pixel P2 has the same structure as the pixel P shown. Figure 2 The circuit diagram is shown.

[0109] The second pixel driving circuit PDC2 can have the same... Figure 2 The pixel driving circuit PDC shown has the same structure. The second pixel driving circuit PDC2 can be composed of the same... Figure 2The pixel driving circuit PDC shown is represented by the same circuit diagram. The second display element DU2 may be, for example, an organic light-emitting diode (OLED). The second display element DU2 may include an organic light-emitting layer.

[0110] According to one embodiment of the present invention, the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2 overlap. (Refer to...) Figure 3 The first pixel driving circuit PDC1 and the second pixel driving circuit PDC2 are disposed in different layers and overlap each other along the thickness direction. Because the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2 are overlapped, they can be disposed respectively within the area occupied by the two pixels P1 and P2, with a planar reference. As a result, the area occupied by each of the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2 can be increased.

[0111] Typically, the area of ​​pixel P is considered to be the area of ​​display element DU. Therefore, according to one embodiment of the present invention, the area of ​​the first display element DU1 can be referred to as the area of ​​the first pixel P1, and the area of ​​the second display element DU2 can be referred to as the area of ​​the second pixel P2. According to one embodiment of the present invention, since the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2 can be disposed in the area combined with the area of ​​the first pixel P1 and the area of ​​the second pixel P2, the area of ​​each of the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2 can be increased.

[0112] According to one embodiment of the present invention, when the area of ​​each of the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2 is increased, the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2 can be easily designed, and the space for arranging the electrodes, lines, contact holes, capacitors, etc. included in the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2 can be increased. In particular, the area of ​​the first capacitor C1 of the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2 can be increased.

[0113] Furthermore, even if each of the first pixel P1 and the second pixel P2 has a small area in a high-resolution display device, the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2 can still have an area that can be designed.

[0114] Unlike the construction according to one embodiment of the invention, when simply depositing multiple thin-film transistors one on top of the other, additional contact holes are required to connect the deposited thin-film transistors to other components. As the number of contact holes in the pixel driving circuit increases, the area occupied by the contact holes increases, resulting in area loss due to the contact holes. Consequently, the area occupied by other components (e.g., capacitors or channel portions of the active layer) becomes smaller.

[0115] On the other hand, according to one embodiment of the invention, in a pixel driving circuit, the thin-film transistors do not overlap each other; instead, multiple pixel driving circuits PDC1 and PDC2 overlap each other. As a result, no additional contact holes are needed to connect the deposited thin-film transistors to other components, thus avoiding area loss due to contact holes. Therefore, according to one embodiment of the invention, since the pixel driving circuits PDC1 and PDC2 are arranged in a relatively wide area, the area of ​​the capacitor or channel portion can be easily ensured.

[0116] Reference Figure 3 The first display element DU1 overlaps with the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2, and the second display element DU2 also overlaps with the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2. The first pixel P1 and the second pixel P2 can form a pixel unit (display unit).

[0117] like Figure 3 As shown, when the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2 overlap, the thin-film transistors included in the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2 may overlap. When the thin-film transistors overlap, they will affect each other, and their driving will become unstable. According to one embodiment of the present invention, an electric field blocking layer 210 is disposed between the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2 to prevent the thin-film transistors included in the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2 from affecting each other.

[0118] The electric field barrier layer 210 prevents the electric field generated by the thin-film transistor included in the first pixel driving circuit PDC1 from affecting the thin-film transistor included in the second pixel driving circuit PDC2. Furthermore, the electric field barrier layer 210 prevents the electric field generated by the thin-film transistor included in the second pixel driving circuit PDC2 from affecting the thin-film transistor included in the first pixel driving circuit PDC1.

[0119] To prevent the thin-film transistors included in the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2 from interfering with each other, the electric field blocking layer 210 has a low dielectric constant and a large thickness.

[0120] According to one embodiment of the present invention, the electric field blocking layer 210 has a thickness of 1 μm or greater between the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2. In this case, the thickness of the electric field blocking layer 210 is defined as the distance from the upper surface of the first pixel driving circuit PDC1 to the lower surface of the second pixel driving circuit PDC2.

[0121] According to one embodiment of the present invention, the electric field blocking layer 210 has a thickness of 1 μm or greater in the entire region between the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2. More specifically, in the entire region between the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2, the electric field blocking layer 210 may have a thickness of 1.5 μm or greater, or may have a thickness of 2.0 μm or greater.

[0122] Because the electric field blocking layer 210 has a low dielectric constant, the mutual electrical interference between the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2 can be reduced. The thickness of the electric field blocking layer 210 can vary depending on its dielectric constant. According to one embodiment of the invention, the electric field blocking layer 210 may have a dielectric constant of 3.9 or less. More specifically, the electric field blocking layer 210 may have a dielectric constant of 3.5 or less, 3.0 or less, or 2.5 or less.

[0123] According to one embodiment of the present invention, the electric field blocking layer 210 may include a siloxane compound. More specifically, the electric field blocking layer 210 may be made of a siloxane compound. A siloxane compound with a low dielectric constant may be used as the siloxane compound.

[0124] According to one embodiment of the present invention, the smaller the dielectric constant of the electric field blocking layer 210, the smaller the thickness of the electric field blocking layer 210. The larger the dielectric constant of the electric field blocking layer 210, the larger the thickness of the electric field blocking layer 210. The thickness of the electric field blocking layer 210 can be proportional to the dielectric constant of the electric field blocking layer 210. When the dielectric constant of the electric field blocking layer 210 is κ, the thickness "t" of the electric field blocking layer 210 can satisfy the following relationship 1.

[0125] [Relation 1]

[0126] t∝κ

[0127] According to one embodiment of the present invention, each of the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2 may include two or more thin-film transistors. Furthermore, according to one embodiment of the present invention, each of the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2 may include four or more thin-film transistors.

[0128] In the following text, reference will be made to Figures 4 to 7 A display device 100 according to an embodiment of the present invention will be described in more detail.

[0129] Figure 4 This is a schematic plan view illustrating the first pixel P1 and the second pixel P2 according to an embodiment of the present invention. Figure 4 The sedimentary structure can be compared with Figure 3 Similar to. Figure 5 This is a plan view illustrating the first pixel driving circuit PDC1. Figure 6 This is a plan view illustrating the second pixel driving circuit PDC2 and display elements DU1 and DU2.

[0130] In a display device 100 according to an embodiment of the present invention, the first pixel P1 and the second pixel P2 may have the following characteristics: Figure 4 The planar layer shown. Figure 5 and Figure 6 The cutting line I-I' reflects Figure 4 The cutting line I-I'. In Figure 4 , Figure 5 and Figure 6 In the diagram, the cutting line I-I' is a cutting line for the same part.

[0131] Figure 5 This is a plan view of the first pixel driving circuit, PDC1. In detail... Figure 5 It can be Figure 3 and Figure 4 Plan view of the lower part of the electric field blocking layer 210.

[0132] Figure 6 This is a plan view of the second pixel driving circuit PDC2 and display elements DU1 and DU2. In detail, Figure 6 It can be Figure 3 and Figure 4 Plan view of the upper part of the electric field blocking layer 210.

[0133] Figure 7 It is along Figure 4 , Figure 5 and Figure 6 A cross-sectional view taken from line I-I'. Figure 8 yes Figure 7 A magnified view of a portion of it.

[0134] Reference Figure 7 The first thin-film transistor TR1 and the second thin-film transistor TR2 are disposed on the substrate 110.

[0135] The first pixel driving circuit PDC1 includes a first thin-film transistor TR1_1 and a second thin-film transistor TR2_1. The first thin-film transistor TR1_1 of the first pixel driving circuit PDC1 includes an active layer A1_1, a gate electrode G1_1, a source electrode S1_1, and a drain electrode D1_1. The second thin-film transistor TR2_1 of the first pixel driving circuit PDC1 includes an active layer A2_1, a gate electrode G2_1, a source electrode S2_1, and a drain electrode D2_1.

[0136] The first pixel driving circuit PDC1 can be composed of and Figure 2 The pixel driving circuit PDC shown is represented by the same circuit diagram. Furthermore, the second pixel driving circuit PDC2 can also be represented by the same circuit diagram. Figure 2 The pixel driving circuit PDC shown in the figure has the same circuit diagram representation.

[0137] The substrate 110 may be made of glass or plastic. Flexible plastics, such as polyimide (PI), may be used as the substrate 110.

[0138] A light-shielding layer 120 is disposed on the substrate 110. The light-shielding layer 120 can block light incident from the outside to protect the active layers A1_1 and A2_1. The light-shielding layer 120 can be omitted.

[0139] A buffer layer 125 is disposed on the light-shielding layer 120 and the substrate 110. The buffer layer 125 is made of insulating material and protects the active layers A1_1 and A2_1 from external moisture or oxygen.

[0140] The active layer A1_1 of the first thin-film transistor TR1_1 and the active layer A2_1 of the second thin-film transistor TR2_1 are disposed on the buffer layer 125.

[0141] Each of the active layers A1_1 and A2_1 may comprise an oxide semiconductor material. According to one embodiment of the invention, the active layers A1_1 and A2_1 may be oxide semiconductor layers made of an oxide semiconductor material.

[0142] According to one embodiment of the present invention, active layers A1_1 and A2_1 are disposed on substrate 110. Active layers A1_1 and A2_1 may include at least one of the following: ZO (ZnO) based oxide semiconductor material, IZO (InZnO) based oxide semiconductor material, IGZO (InGaZnO) based oxide semiconductor material, TO (SnO) based oxide semiconductor material, IGO (InGaO) based oxide semiconductor material, ITO (InSnO) based oxide semiconductor material, IGZTO (InGaZnSnO) based oxide semiconductor material, GZTO (GaZnSnO) based oxide semiconductor material, GZO (GaZnO) based oxide semiconductor material, GO (GaO) based oxide semiconductor material, IO (InO) based oxide semiconductor material, FIZO (FeInZnO) based oxide semiconductor material, or ITZO (InSnZnO) based oxide semiconductor material. The active layers A1_1 and A2_1 may have a single-layer structure or a multilayer structure including two or more oxide semiconductor layers.

[0143] According to one embodiment of the present invention, active layers A1_1 and A2_1 may include channel portions and conductive portions disposed on both sides of the channel portions. According to one embodiment of the present invention, active layers A1_1 and A2_1 can be selectively conductive by using gate electrodes G1_1 and G2_1 as masks. Regions of active layers A1_1 and A2_1 that overlap with gate electrodes G1_1 and G2_1 are not conductive and thus can form channel portions. Regions of active layers A1_1 and A2_1 that do not overlap with gate electrodes G1_1 and G2_1 are conductive and thus can form conductive portions.

[0144] According to one embodiment of the present invention, one of the conductive portions may be a source region and the other may be a drain region. The source region serves as a source connection portion connected to source electrodes S1_1 and S2_1. The drain region serves as a drain connection portion connected to drain electrodes D1_1 and D2_1.

[0145] A gate insulating layer 145 is disposed on the active layers A1_1 and A2_1. The gate insulating layer 145 has insulating properties and separates the active layers A1_1 and A2_1 from the gate electrodes G1_1 and G2_1. Figure 7 The diagram shows a patterned gate insulating layer 145, but one embodiment of the invention is not limited thereto. The gate insulating layer 145 may not be patterned.

[0146] The gate electrode G1_1 of the first thin-film transistor TR1_1 and the gate electrode G2_1 of the second thin-film transistor TR2_1 are disposed on the gate insulating layer 145.

[0147] The gate electrode G1_1 of the first thin-film transistor TR1_1 is separated from the active layer A1_1 of the first thin-film transistor TR1_1 and overlaps with at least a portion of the active layer A1_1 of the first thin-film transistor TR1_1. The gate electrode G2_1 of the second thin-film transistor TR2_1 is separated from the active layer A2_1 of the second thin-film transistor TR2_1 and overlaps with at least a portion of the active layer A2_1 of the second thin-film transistor TR2_1.

[0148] Reference Figure 7 The first capacitor electrode CE11 of the first capacitor C1_1 is disposed in the same layer as the gate electrodes G1_1 and G2_1. The gate electrodes G1_1 and G2_1 and the first capacitor electrode CE11 can be fabricated together using the same materials and the same process.

[0149] An interlayer dielectric layer 170 is disposed on the gate electrodes G1_1 and G2_1 and the first capacitor electrode CE11.

[0150] Source electrodes S1_1 and S2_1 and drain electrodes D1_1 and D2_1 are disposed on the interlayer dielectric layer 170. According to one embodiment of the present invention, for ease of description, source electrodes S1_1 and S2_1 and drain electrodes D1_1 and D2_1 are distinguished, but they are interchangeable. Therefore, source electrodes S1_1 and S2_1 can be drain electrodes D1_1 and D2_1, and drain electrodes D1_1 and D2_1 can be source electrodes S1_1 and S2_1.

[0151] Data line DL_1 and drive power line PL_1 are disposed on the interlayer dielectric layer 170. The source electrode S1_1 of the first thin-film transistor TR1_1 can be integrally formed with the data line DL1_1. The drain electrode D2_1 of the second thin-film transistor TR2_1 can be integrally formed with the drive power line PL_1.

[0152] According to one embodiment of the present invention, the source electrode S1_1 and drain electrode D1_1 of the first thin-film transistor TR1_1 are separated from each other and connected to the active layer A1_1 of the first thin-film transistor TR1_1. The source electrode S2_1 and drain electrode D2_1 of the second thin-film transistor TR2_1 are separated from each other and connected to the active layer A2_1 of the second thin-film transistor TR2_1.

[0153] In detail, the source electrode S1_1 of the first thin-film transistor TR1_1 is in contact with the source region of the active layer A1_1 through the first contact hole H1_1.

[0154] The drain electrode D1_1 of the first thin-film transistor TR1_1 is in contact with the drain region of the active layer A1_1 through the second contact hole H2_1, and is connected to the first capacitor electrode CE11 of the first capacitor C1_1 through the third contact hole H3_1.

[0155] The source electrode S2_1 of the second thin-film transistor TR2_1 is in contact with the source region of the active layer A2_1 through the fourth contact hole H4_1.

[0156] The source electrode S2_1 of the second thin-film transistor TR2_1 extends onto the interlayer dielectric layer 170, and a portion thereof serves as the second capacitor electrode CE21 of the first capacitor C1_1. The first capacitor electrode CE11 and the second capacitor electrode CE21 overlap each other to form the first capacitor C1_1.

[0157] Reference Figure 5 and Figure 7 The second capacitor electrode CE21 of the first capacitor C1_1 extends outside the region of the first capacitor C1_1, thereby forming the first bridging portion BR1.

[0158] The drain electrode D2_1 of the second thin-film transistor TR2_1 is in contact with the drain region of the active layer A2_1 through the fifth contact hole H5_1.

[0159] The first thin-film transistor TR1_1 includes an active layer A1_1, a gate electrode G1_1, a source electrode S1_1, and a drain electrode D1_1, and is used as a switching transistor for controlling the data voltage Vdata applied to the first pixel driving circuit PDC1.

[0160] The second thin-film transistor TR2_1 includes an active layer A2_1, a gate electrode G2_1, a source electrode S2_1, and a drain electrode D2_1, and serves as a drive transistor for controlling the drive voltage Vdd applied to the first display element DU1. (Refer to...) Figure 5 The second thin-film transistor TR2_1 is connected to the first display element DU1 through the first bridging part BR1.

[0161] An electric field blocking layer 210 is disposed on the source electrodes S1_1 and S2_1, the drain electrodes D1_1 and 2_1, the data line DL_1, the drive power line PL_1, and the first bridge portion BR1.

[0162] The electric field blocking layer 210 is used to prevent the thin-film transistors TR1_1 and TR2_1 included in the first pixel driving circuit PDC1 from electrically interfering with each other and the thin-film transistors TR1_2 and TR2_2 included in the pixel driving circuit PDC2. To prevent the thin-film transistors TR1_1 and TR2_1 included in the first pixel driving circuit PDC1 from electrically interfering with each other and the thin-film transistors TR1_2 and TR2_2 included in the pixel driving circuit PDC2, the electric field blocking layer 210 has a low dielectric constant and a large thickness.

[0163] According to one embodiment of the present invention, the electric field blocking layer 210 may have a dielectric constant of 3.9 or less. More specifically, the electric field blocking layer 210 may have a dielectric constant of 3.5 or less, or a dielectric constant of 3.0 or less, or a dielectric constant of 2.5 or less.

[0164] According to one embodiment of the present invention, the electric field blocking layer 210 may include a siloxane compound. More specifically, the electric field blocking layer 210 may be made of a siloxane compound. A siloxane compound with a low dielectric constant may be used as the aforementioned siloxane compound.

[0165] According to one embodiment of the present invention, the thickness "t" of the electric field blocking layer 210 is defined as the distance from the upper surface of the first pixel driving circuit PDC1 to the lower surface of the second pixel driving circuit PDC2. (Refer to...) Figure 8 The distance t1 from the upper surface of the first thin-film transistor TR1_1 of the first pixel driving circuit PDC1 to the lower surface of the first thin-film transistor TR1_2 of the second pixel driving circuit PDC2 can be defined as the thickness "t" of the electric field blocking layer 210.

[0166] As described above, the thickness “t” of the electric field blocking layer 210 can be proportional to the dielectric constant κ of the electric field blocking layer 210. Considering that the dielectric constant of silicon oxide (SiO2), which is widely used as an insulating layer, is about 3.9, the thickness “t” of the electric field blocking layer 210 can be expressed as the ratio of the dielectric constant κ of the electric field blocking layer 210 to 3.9 [κ / 3.9].

[0167] Reference Figure 8 The first thin-film transistor TR1_2 of the second pixel driving circuit PDC2 is subjected to a voltage V applied to the gate electrode G1_1 to turn on the first thin-film transistor TR1_1 of the first pixel driving circuit PDC1. GH Impact. In this case, the voltage applied to the gate electrode G1_1 to turn on the first thin-film transistor TR1_1 of the first pixel driving circuit PDC1 is called the turn-on voltage V of the first thin-film transistor TR1_1 applied to the first pixel driving circuit PDC1. GHThe on-state voltage V applied to the first thin-film transistor TR1_1 of the first pixel driving circuit PDC1. GH The larger the voltage V, the higher the voltage V. GH The greater the impact on the first thin-film transistor TR1_2 of the second pixel driving circuit PDC2, the greater the influence. Furthermore, the threshold voltage V of the first thin-film transistor TR1_2 of the second pixel driving circuit PDC2... TH The larger the value, the less the first thin-film transistor TR1_2 of the second pixel driving circuit PDC2 is affected by the external electric field.

[0168] Furthermore, the active layer A1_2 of the channel of the first thin-film transistor TR1_2, which serves as the second pixel driving circuit PDC2, is directly affected by the gate electrode G1_2, and the distance between the gate electrode G1_2 and the active layer A1_2 is equal to the thickness t of the gate insulating layer 245. GI Therefore, the thickness "t" of the electric field blocking layer 210 can be determined by the thickness "t" of the gate insulating layer included in the first thin-film transistor TR1_2 of the second pixel driving circuit PDC2. GI express.

[0169] Considering these characteristics, the distance t1 between the upper surface of the first thin-film transistor TR1_1 of the first pixel driving circuit PDC1 and the lower surface of the first thin-film transistor TR1_2 of the second pixel driving circuit PDC2 can satisfy the following equation 1.

[0170] [Equation 1]

[0171] t1=t≥(V GH / V TH )×(κ / 3.9)×(t GI )

[0172] In Equation 1, κ represents the dielectric constant of the electric field blocking layer 210, and V GH It is the turn-on voltage (V) applied to the first thin-film transistor TR1_1 of the first pixel driving circuit PDC1. TH It is the threshold voltage of the first thin-film transistor TR1_2 in the second pixel driving circuit PDC2, t GI It is the distance between the gate electrode G1_2 of the first thin-film transistor TR1_2 of the second pixel driving circuit PDC2 and the active layer A1_2.

[0173] According to one embodiment of the present invention, the thickness t1 of the electric field blocking layer 210 can be 1 μm or greater.

[0174] The electric field barrier layer 210 planarizes the upper part of the first thin film transistor TR1_1 and the second thin film transistor TR2_1 and protects the first thin film transistor TR1_1 and the second thin film transistor TR2_1.

[0175] The buffer layer 225 of the second pixel driving circuit PDC2 is disposed on the electric field blocking layer 210. The buffer layer 225 is made of insulating material and protects the active layers A1_2 and A2_2 from external moisture or oxygen. The buffer layer 225 can be omitted.

[0176] The first thin-film transistor TR1_2 and the second thin-film transistor TR2_2 of the second pixel driving circuit PDC2 are disposed on the buffer layer 225. Specifically, the active layer A1_2 of the first thin-film transistor TR1_2 and the active layer A2_2 of the second thin-film transistor TR2_2 are disposed on the buffer layer 225.

[0177] Active layers A1_2 and A2_2 may comprise oxide semiconductor materials. According to one embodiment of the present invention, active layers A1_2 and A2_2 may be oxide semiconductor layers made of oxide semiconductor materials.

[0178] A gate insulating layer 245 is disposed on the active layers A1_2 and A2_2. The gate insulating layer 245 has insulating properties and separates the active layers A1_2 and A2_2 from the gate electrodes G1_2 and G2_2. Figure 7 The diagram shows a patterned gate insulating layer 245, but one embodiment of the invention is not limited thereto. The gate insulating layer 245 may not be patterned.

[0179] The gate electrode G1_2 of the first thin-film transistor TR1_2 and the gate electrode G2_2 of the second thin-film transistor TR2_2 are disposed on the gate insulating layer 245.

[0180] The gate electrode G1_2 of the first thin-film transistor TR1_2 is separated from the active layer A1_2 of the first thin-film transistor TR1_2 and overlaps with at least a portion of the active layer A1_2 of the first thin-film transistor TR1_2. The gate electrode G2_2 of the second thin-film transistor TR2_2 is separated from the active layer A2_2 of the second thin-film transistor TR2_2 and overlaps with at least a portion of the active layer A2_2 of the second thin-film transistor TR2_2.

[0181] Reference Figure 7 The first capacitor electrode CE12 of the first capacitor C1_2 is disposed in the same layer as the gate electrodes G1_2 and G2_2. The gate electrodes G1_2 and G2_2 and the first capacitor electrode CE12 can be fabricated together using the same materials and the same process.

[0182] An interlayer dielectric layer 270 is disposed on the gate electrodes G1_2 and G2_2 and the first capacitor electrode CE12.

[0183] Source electrodes S1_2 and S2_2 and drain electrodes D1_2 and D2_2 are disposed on the interlayer dielectric layer 270. According to one embodiment of the present invention, for ease of description, source electrodes S1_2 and S2_2 and drain electrodes D1_2 and D2_2 are distinguished, but they are interchangeable. Therefore, source electrodes S1_2 and S2_2 can be drain electrodes D1_2 and D2_2, and drain electrodes D1_2 and D2_2 can be source electrodes S1_2 and S2_2.

[0184] Data line DL_2 and drive power line PL_2 are disposed on the interlayer dielectric layer 270. The source electrode S1_2 of the first thin-film transistor TR1_2 can be integrally formed with the data line DL_2. The drain electrode D2_2 of the second thin-film transistor TR2_2 can be integrally formed with the drive power line PL_2.

[0185] According to one embodiment of the present invention, the source electrode S1_2 and drain electrode D1_2 of the first thin-film transistor TR1_2 are separated from each other and connected to the active layer A1_2 of the first thin-film transistor TR1_2. The source electrode S2_2 and drain electrode D2_2 of the second thin-film transistor TR2_2 are separated from each other and connected to the active layer A2_2 of the second thin-film transistor TR2_2.

[0186] In detail, the source electrode S1_2 of the first thin-film transistor TR1_2 is in contact with the source region of the active layer A1_2 through the first contact hole H1_2.

[0187] The drain electrode D1_2 of the first thin-film transistor TR1_2 is in contact with the drain region of the active layer A1_2 through the second contact hole H2_2, and is connected to the first capacitor electrode CE12 of the first capacitor C1_2 through the third contact hole H3_2.

[0188] The source electrode S2_2 of the second thin-film transistor TR2_2 is in contact with the source region of the active layer A2_2 through the fourth contact hole H4_2.

[0189] The source electrode S2_2 of the second thin-film transistor TR2_2 extends onto the interlayer dielectric layer 270, and a portion of the source electrode S2_2 of the second thin-film transistor TR2_2 serves as the second capacitor electrode CE22 of the first capacitor C1_2. The first capacitor electrode CE12 and the second capacitor electrode CE22 overlap each other to form the first capacitor C1_2.

[0190] The drain electrode D2_2 of the second thin-film transistor TR2_2 is in contact with the drain region of the active layer A2_2 through the fifth contact hole H5_2.

[0191] The first thin-film transistor TR1_2 includes an active layer A1_2, a gate electrode G1_2, a source electrode S1_2, and a drain electrode D1_2, and is used as a switching transistor for controlling the data voltage Vdata applied to the second pixel driving circuit PDC2.

[0192] The second thin-film transistor TR2_2 includes an active layer A2_2, a gate electrode G2_2, a source electrode S2_2, and a drain electrode D2_2, and is used as a driving transistor for controlling the driving voltage Vdd applied to the second display element DU2.

[0193] Reference Figure 5 and Figure 7 The second bridging portion BR2 is formed on the interlayer dielectric layer 270. (Refer to...) Figure 7 The second bridging part BR2 is connected to the first bridging part BR1 through the first part CT11 of the first connecting part CT1.

[0194] A passivation layer 275 is disposed on the source electrodes S1_2 and S2_2, drain electrodes D1_2 and 2_2, data line DL_2, drive power line PL_2, and second bridge portion BR2 of the second pixel driving circuit PDC2. The passivation layer 275 planarizes the upper parts of the first thin-film transistor TR1_2 and the second thin-film transistor TR2_2, and protects the first thin-film transistor TR1_2 and the second thin-film transistor TR2_2.

[0195] According to one embodiment of the present invention, a thin-film transistor TR1_1 or TR2_1 of the first pixel driving circuit PDC1 and a thin-film transistor TR1_2 or TR2_2 of the second pixel driving circuit PDC2 may overlap each other. (Refer to...) Figure 7 The first thin-film transistor TR1_1 of the first pixel driving circuit PDC1 overlaps with the first thin-film transistor TR1_2 of the second pixel driving circuit PDC2. Furthermore, the second thin-film transistor TR2_1 of the first pixel driving circuit PDC1 overlaps with the second thin-film transistor TR2_2 of the second pixel driving circuit PDC2.

[0196] To prevent overlapping thin-film transistors from electrically interfering with each other, according to one embodiment of the invention, these thin-film transistors are separated from each other by a predetermined interval or a greater interval. In particular, the gate electrode of any one of the overlapping thin-film transistors is separated from the active layer of the other thin-film transistor by a predetermined interval or a greater interval.

[0197] According to one embodiment of the present invention, the separation distance between the gate electrodes G1_1 and G2_1 of the thin-film transistors TR1_1 and TR2_1 of the first pixel driving circuit PDC1 and the active layers A1_2 and A2_2 of the thin-film transistors TR1_2 and TR2_2 of the second pixel driving circuit PDC2 can be 1 μm or greater.

[0198] More specifically, refer to Figure 7 and Figure 8 The separation distance t2 between the gate electrode G1_1 of the first thin-film transistor TR1_1 of the first pixel driving circuit PDC1 and the active layer A1_2 of the first thin-film transistor TR1_2 of the second pixel driving circuit PDC2 can be 1 μm or greater. Furthermore, the separation distance between the gate electrode G2_1 of the second thin-film transistor TR2_1 of the first pixel driving circuit PDC1 and the active layer A2_2 of the second thin-film transistor TR2_2 of the second pixel driving circuit PDC2 is 1 μm or greater.

[0199] When an electric field blocking layer 210 according to an embodiment of the present invention is applied, and the separation distance between the gate electrodes G1_1 and G1_2 of one of the thin-film transistors TR1_1 and TR1_2 and the active layers A1_2 and A1_1 of the other thin-film transistor is 1 μm or greater, the gate electrodes G1_1 and G1_2 of one thin-film transistor can be prevented from affecting the active layers A1_2 and A1_1 of the other thin-film transistor. As a result, each thin-film transistor can be driven stably.

[0200] The first electrode 711 of the first display element DU1 and the first electrode 712 of the second display element DU2 are disposed on the passivation layer 275.

[0201] The first electrode 711 of the first display element DU1 is connected to the second bridging portion BR2 via the second portion CT12 of the first connecting portion CT1. As a result, the first display element DU1 can be connected to the second thin-film transistor TR2_1 of the first pixel driving circuit PDC1 via the second bridging portion BR2 and the first bridging portion BR1.

[0202] The second portion CT12 of the first connection portion CT1 may be formed in a contact hole formed in the passivation layer 275. The first portion CT11 of the first connection portion CT1 may be disposed in a contact hole passing through the interlayer dielectric layer 270, the buffer layer 225, and the electric field blocking layer 210. The first portion CT11 of the first connection portion CT1 may be disposed in a contact hole formed in the second pixel driving circuit PDC2.

[0203] According to one embodiment of the present invention, the first connecting portion CT1 includes a first portion CT11 and a second portion CT12. Therefore, according to one embodiment of the present invention, the first display element DU1 is connected to the first pixel driving circuit PDC1 through the first connecting portion CT1.

[0204] The first electrode 712 of the second display element DU2 is connected to the source electrode S2_2 of the second thin-film transistor TR2_2 of the second pixel driving circuit PDC2 via the second connection portion CT2. Therefore, according to one embodiment of the present invention, the second display element DU2 can be connected to the second pixel driving circuit PDC2 via the second connection portion CT2. The second connection portion CT2 may be disposed in a contact hole formed in the passivation layer 275.

[0205] A dam layer 750 is disposed around the first electrode 711 of the first display element DU1 and the first electrode 712 of the second display element DU2. The dam layer 750 defines the light-emitting areas of the display elements DU1 and DU2. According to one embodiment of the invention, the area exposed from the dam layer 750 may be referred to as the light-emitting area. According to one embodiment of the invention, the areas of the first electrode 711 of the first display element DU1 and the first electrode 712 of the second display element DU2 that are exposed from the dam layer 750 but not covered by the dam layer 750 emit light. Therefore, according to one embodiment of the invention, the area of ​​the first electrode 711 of the first display element DU1 exposed from the dam layer 750 may be referred to as the light-emitting area of ​​the first display element DU1, and the area of ​​the first electrode 712 of the second display element DU2 exposed from the dam layer 750 may be referred to as the light-emitting area of ​​the second display element DU2.

[0206] although Figure 7 The example shows a levee layer 750, but the location of the levee layer 750 is not limited to this. Figure 7 According to one embodiment of the present invention, the embankment 750 may be configured to overlap with at least one of the first connecting portion CT1 and the second connecting portion CT2.

[0207] According to one embodiment of the present invention, the first connecting portion CT1 and the second connecting portion CT2 are formed in the contact hole, and the portion forming the contact hole may not be planar. Therefore, the first connecting portion CT1 and the second connecting portion CT2 may be disposed in the region overlapping with the embankment layer 750, rather than in the light-emitting region. Consequently, the first electrode 711 of the first display element DU1 and the first electrode 712 of the second display element DU2 may be planarized in the light-emitting region, and ultimately the first organic light-emitting layer 721 and the second organic light-emitting layer 722 may be planarized.

[0208] For example, such as Figure 3As shown, at least one of the first connecting portion CT1 and the second connecting portion CT2 may be disposed below the embankment layer 750. More specifically, at least a portion of the first connecting portion CT1 may overlap with the embankment layer 750. In particular, a first portion CT11 of the first connecting portion CT1 may overlap with the embankment layer 750. According to one embodiment of the invention, the first connecting portion CT1 may completely overlap with the embankment layer 750, and both the first connecting portion CT1 and the second connecting portion CT2 may overlap with the embankment layer 750.

[0209] According to one embodiment of the present invention, the first connecting portion CT1 connects the first display element DU1 to the first pixel driving circuit PDC1. Since the first pixel driving circuit PDC1 is positioned closer to the substrate 110 than the second pixel driving circuit PDC2, the first pixel driving circuit PDC1 can be disposed below the second pixel driving circuit PDC2. Therefore, the contact hole where the first connecting portion CT1 is located is relatively deep. If the contact hole is deep, an uneven surface is likely to be generated around the contact hole. Therefore, according to one embodiment of the present invention, the first connecting portion CT1 is disposed below the embankment layer 750, such that the uneven surface caused by the first connecting portion CT1 is covered by the embankment layer 750.

[0210] According to one embodiment of the present invention, the first connecting portion CT1 includes a first portion CT11 and a second portion CT12. In this case, the first portion CT11, which is formed to penetrate the electric field blocking layer 210, may be deeper than the second portion CT12. Therefore, according to one embodiment of the present invention, the first portion CT11 of the first connecting portion CT1, which penetrates the electric field blocking layer 210, may overlap with the embankment layer 750.

[0211] A first organic light-emitting layer 721 is disposed on the first electrode 711 of the first display element DU1. A second organic light-emitting layer 722 is disposed on the first electrode 712 of the second display element DU2. The first display element DU1 includes the first organic light-emitting layer 721, and the second display element DU2 includes the second organic light-emitting layer 722.

[0212] Second electrodes 731 and 732 are disposed on the first organic light-emitting layer 721 and the second organic light-emitting layer 722. Specifically, the second electrode 731 is disposed on the first organic light-emitting layer 721 of the first display element DU1, and the second electrode 732 is disposed on the second organic light-emitting layer 722 of the second display element DU2. The second electrode 731 of the first display element DU1 and the second electrode 732 of the second display element DU2 can be integrally formed. The second electrodes 731 and 732 can be integrally formed on the entire display device 100.

[0213] Figure 7The display elements DU1 and DU2 shown are organic light-emitting diodes (OLEDs). Therefore, the display device 100 according to one embodiment of the present invention is an organic light-emitting display device.

[0214] Although not shown, color filters may be placed along the path of the light emitted from display elements DU1 and DU2. The color filters may, for example, be one of red, green, and blue.

[0215] According to one embodiment of the present invention, each of the first electrode 711 of the first display element DU1 and the first electrode 712 of the second display element DU2 may have a reflective layer (not shown). For example, the first electrode 711 of the first display element DU1 and the first electrode 712 of the second display element DU2 may have a structure in which layers of transparent conductive oxide (TCO) and reflective metal are deposited alternately. More specifically, the first electrode 711 of the first display element DU1 and the first electrode 712 of the second display element DU2 may have a structure in which layers of ITO (InSnO), reflective metal, and ITO (InSnO) are deposited alternately.

[0216] Furthermore, each of the second electrode 731 of the first display element DU1 and the second electrode 732 of the second display element DU2 can be formed of a semi-transparent, semi-reflective conductive layer. As a result, light generated from the first organic light-emitting layer 721 and the second organic light-emitting layer 722 can be emitted to the outside through the second electrodes 731 and 732, respectively.

[0217] As described above, a display device 100 having a structure that emits light generated from display elements DU1 and DU1 through second electrodes 731 and 732 to the outside is called a top-emitting display device. According to one embodiment of the present invention, the display device 100 is a top-emitting display device in which light generated from display elements DU1 and DU1 is emitted in a direction opposite to the direction toward the substrate 110. Alternatively, according to one embodiment of the present invention, the display device 100 may be a top-emitting display device in which light generated from display elements DU1 and DU1 may be emitted in a direction opposite to the direction toward the pixel driving circuits PDC1 and PDC2.

[0218] Figure 9 This is a circuit diagram of a pixel P of a display device 200 according to another embodiment of the present invention. In the following text, descriptions of the previously described components will be omitted to avoid repetition.

[0219] Figure 9 This is an equivalent circuit diagram illustrating the pixel P of an organic light-emitting display device.

[0220] Figure 9The pixel P of the display device 200 shown includes an organic light-emitting diode (OLED) as a display element DU, and a pixel driving circuit PDC for driving the display element DU. The display element DU is connected to the pixel driving circuit PDC. Figure 9 The pixel P shown can be Figure 3 The first pixel P1 or the second pixel P2 shown.

[0221] Reference Figure 9 In pixel P, signal lines DL, GL, PL, RL and SCL are provided for providing signals to the pixel driving circuit PDC.

[0222] The data voltage Vdata is provided to the data line DL, the scan signal SS is provided to the gate line GL, the driving voltage Vdd for driving the pixel is provided to the driving power line PL, the reference voltage Vref is provided to the reference line RL, and the sensing control signal SCS is provided to the sensing control line SCL.

[0223] Reference Figure 9 Assume that the gate line of the nth pixel P is "GLn", and the gate line of the (n-1)th pixel P adjacent to the nth pixel P is "GLn-1". The gate line "GLn-1" of the (n-1)th pixel P is used as the sensing control line SCL of the nth pixel P.

[0224] For example, the pixel driving circuit PDC includes: a first thin-film transistor TR1 (switching transistor), which is connected to the gate line GL and the data line DL; a second thin-film transistor TR2 (driving transistor), which controls the amplitude of the current output to the display element DU according to the data voltage Vdata transmitted through the first thin-film transistor TR1; and a third thin-film transistor TR3 (reference transistor), which senses the characteristics of the second thin-film transistor TR2.

[0225] The first capacitor C1 is disposed between the gate electrode of the second thin-film transistor TR2 and the display element DU. The first capacitor C1 is referred to as the storage capacitor Cst.

[0226] The first thin-film transistor TR1 is turned on by the scan signal SS provided to the gate line GL, thereby transmitting the data voltage Vdata provided to the data line DL to the gate electrode of the second thin-film transistor TR2.

[0227] The third thin-film transistor TR3 is connected to the first node n1 between the second thin-film transistor TR2 and the display element DU, as well as the reference line RL. Therefore, the third thin-film transistor TR3 is turned on or off by the sensing control signal SCS, and senses the characteristics of the second thin-film transistor TR2 as a driving transistor during the sensing period.

[0228] A second node n2, connected to the gate electrode of the second thin-film transistor TR2, is connected to the first thin-film transistor TR1. A first capacitor C1 is formed between the second node n2 and the first node n1.

[0229] When the first thin-film transistor TR1 is turned on, the data voltage Vdata supplied through the data line DL is provided to the gate electrode of the second thin-film transistor TR2. The first capacitor C1 formed between the gate electrode and the source electrode of the second thin-film transistor TR2 is charged with the data voltage Vdata.

[0230] When the second thin-film transistor TR2 is turned on, current is supplied to the display element DU through the second thin-film transistor TR2 according to the driving voltage Vdd used to drive the pixel, thereby outputting light from the display element DU.

[0231] Figure 10 This is a circuit diagram of a pixel of a display device 300 according to another embodiment of the present invention.

[0232] Figure 10 The pixel P of the display device 300 shown includes an organic light-emitting diode (OLED) as a display element DU, and a pixel driving circuit PDC for driving the display element DU. The display element DU is connected to the pixel driving circuit PDC. Figure 10 The pixel P shown can be Figure 3 The first pixel P1 or the second pixel P2 shown.

[0233] The pixel drive circuit PDC includes thin-film transistors TR1, TR2, TR3, and TR4.

[0234] exist Figure 10 The pixel P shown has signal lines DL, EL, GL, PL, SCL and RL for providing drive signals to the pixel drive circuit PDC.

[0235] and Figure 9 Compared to the pixel P, Figure 10 The pixel P further includes an emission control line EL. An emission control signal EM is provided to the emission control line EL.

[0236] In addition, with Figure 9 Compared to the pixel drive circuit PDC, Figure 10 The pixel driving circuit PDC further includes a fourth thin-film transistor TR4 as a light-emitting control transistor, which is used to control the light-emitting timing of the second thin-film transistor TR2.

[0237] Reference Figure 10If the gate line of the nth pixel P is "GLn", the gate line of the (n-1)th pixel P adjacent to the nth pixel P is "GLn-1", and the gate line "GLn-1" of the (n-1)th pixel P is used as the sensing control line SCL of the nth pixel P.

[0238] The first capacitor C1 is disposed between the gate electrode of the second thin-film transistor TR2 and the display element DU. The second capacitor C2 is disposed between the terminal of the fourth thin-film transistor TR4 that is supplied with the driving voltage Vdd and one electrode of the display element DU.

[0239] The first thin-film transistor TR1 is turned on by the scan signal SS provided to the gate line GL, thereby transmitting the data voltage Vdata provided to the data line DL to the gate electrode of the second thin-film transistor TR2.

[0240] The third thin-film transistor TR3 is connected to the reference line RL and is thus turned on or off by the sensing control signal SCS. The third thin-film transistor TR3 senses the characteristics of the second thin-film transistor TR2, which is the driving transistor, during the sensing period.

[0241] The fourth thin-film transistor TR4 transmits the driving voltage Vdd to the second thin-film transistor TR2 according to the light emission control signal EM, or shields the driving voltage Vdd. When the fourth thin-film transistor TR4 is turned on, current is supplied to the second thin-film transistor TR2, thereby outputting light from the display element DU.

[0242] Figure 11 It is a diagram. Figure 10 A schematic cross-sectional view of one embodiment of a pixel-based display device 400.

[0243] Reference Figure 11 According to another embodiment of the present invention, a display device 400 includes a first pixel driving circuit PDC1, an electric field blocking layer 210 on the first pixel driving circuit PDC1, a second pixel driving circuit PDC2 on the electric field blocking layer 210, and a first display element DU1 and a second display element DU2 on the second pixel driving circuit PDC2. The first display element DU1 and the first pixel driving circuit PDC1 are connected to each other through a first connecting portion CT1, and the second display element DU2 and the second pixel driving circuit PDC2 are connected to each other through a second connecting portion CT2.

[0244] The first pixel driving circuit PDC1 includes a first thin-film transistor TR1_1, a second thin-film transistor TR2_1, a third thin-film transistor TR3_1, and a fourth thin-film transistor TR4_1. The first pixel driving circuit PDC1 may have the following characteristics: Figure 10The pixel driving circuit DC shown has the same construction. Specifically, the first thin-film transistor TR1_1 of the first pixel driving circuit PDC1 can be used to perform the same... Figure 10 The first thin-film transistor TR1 has the same function as the second thin-film transistor TR2_1 of the first pixel driving circuit PDC1, which can be used to perform the same function. Figure 10 The second thin-film transistor TR2 has the same function, and the third thin-film transistor TR3_1 of the first pixel driving circuit PDC1 can be used to perform the same function. Figure 10 The third thin-film transistor TR3 has the same function, and the fourth thin-film transistor TR4_1 of the first pixel driving circuit PDC1 can be used to perform the same function. Figure 10 It has the same function as the fourth thin-film transistor TR4.

[0245] Reference Figure 11 The first pixel driving circuit PDC1 is disposed on the substrate 110. Specifically, a buffer layer 125 is disposed on the substrate 110, and a first thin-film transistor TR1_1, a second thin-film transistor TR2_1, a third thin-film transistor TR3_1, and a fourth thin-film transistor TR4_1 are disposed on the buffer layer 125. More specifically, an active layer is disposed on the buffer layer 125, a gate insulating layer 145 is disposed on the active layer, a gate electrode is disposed on the gate insulating layer 145, an interlayer dielectric layer 170 is disposed on the gate electrode, and source and drain electrodes are disposed on the interlayer dielectric layer 170.

[0246] An electric field blocking layer 210 is disposed on the first thin-film transistor TR1_1, the second thin-film transistor TR2_1, the third thin-film transistor TR3_1, and the fourth thin-film transistor TR4_1 constituting the first pixel driving circuit PDC1.

[0247] A buffer layer 225 is disposed on the electric field blocking layer 210, and the first thin-film transistor TR1_2, the second thin-film transistor TR2_2, the third thin-film transistor TR3_2, and the fourth thin-film transistor TR4_2 are disposed on the buffer layer 225. More specifically, an active layer is disposed on the buffer layer 225, a gate insulating layer 245 is disposed on the active layer, a gate electrode is disposed on the gate insulating layer 245, an interlayer dielectric layer 270 is disposed on the gate electrode, a source electrode and a drain electrode are disposed on the interlayer dielectric layer 270, and a passivation layer 275 is disposed on the source electrode and the drain electrode.

[0248] A first display element DU1 and a second display element DU2 are disposed on a passivation layer 275. The first display element DU1 includes a first electrode 711, a first organic light-emitting layer 721, and a second electrode 731. The second display element DU2 includes a first electrode 712, a second organic light-emitting layer 722, and a second electrode 732.

[0249] The first display element DU1 is connected to the first pixel driving circuit PDC1 via the first connecting part CT1, and the second display element DU2 is connected to the second pixel driving circuit PDC2 via the second connecting part CT2. (Refer to...) Figure 11 At least one of the first connecting portion CT1 and the second connecting portion CT2 may be disposed below the embankment layer 750. More specifically, at least a portion of the first connecting portion CT1 may overlap with the embankment layer 750. In particular, the first connecting portion CT1 may include a first portion CT11 and a second portion CT12, and the first portion CT11 of the first connecting portion CT1 may overlap with the embankment layer 750. Figure 11 In the display device 400 shown according to another embodiment of the present invention, the first connecting portion CT1 and the second connecting portion CT2 may overlap with the embankment 750.

[0250] According to another embodiment of the present invention, each of the first electrode 711 of the first display element DU1 and the first electrode 712 of the second display element DU2 may have a reflective layer (not shown). For example, the first electrode 711 of the first display element DU1 and the first electrode 712 of the second display element DU2 may have a structure in which an ITO (InSnO) layer, a reflective metal layer and an ITO (InSnO) layer are deposited alternately.

[0251] Furthermore, each of the second electrode 731 of the first display element DU1 and the second electrode 732 of the second display element DU2 can be formed of a semi-transparent, semi-reflective conductive layer. As a result, light generated from the first organic light-emitting layer 721 and the second organic light-emitting layer 722 can be emitted to the outside through the second electrodes 731 and 732, respectively.

[0252] As described above, a display device 400 having a structure that emits light generated from display elements DU1 and DU1 to the outside through second electrodes 731 and 732 is referred to as a top-emitting display device. According to another embodiment of the present invention, the display device 400 is a top-emitting display device in which light generated from display elements DU1 and DU1 is emitted in a direction opposite to the direction toward the substrate 110. Alternatively, according to another embodiment of the present invention, the display device 400 may be a top-emitting display device in which light generated from display elements DU1 and DU1 may be emitted in a direction opposite to the direction toward the pixel driving circuits PDC1 and PDC2.

[0253] According to another embodiment of the present invention, the pixel driving circuit PDC, the first pixel driving circuit PDC1, and the second pixel driving circuit PDC2 can be formed in various structures other than those described above. For example, the pixel driving circuit PDC, the first pixel driving circuit PDC1, and the second pixel driving circuit PDC2 may include five or more thin-film transistors.

[0254] Figure 12 It is a diagram illustrating the voltage-current curves of a thin-film transistor according to the embodiments and comparative examples. Figure 12 The diagram illustrates the degree to which the second pixel driving circuit PDC2 is affected by the first pixel driving circuit PDC1.

[0255] In detail, Figure 12 The curve represents when to Figure 11 A voltage V is applied to the gate electrode G1_1 of the first thin-film transistor TR1_1 in the first pixel driving circuit PDC1 of the display device 400 shown. GS At that time, the drain-source current I of the first thin-film transistor TR1_2 in the second pixel driving circuit PDC2 is... DS . Reference Figure 12 No voltage was applied to the gate electrode G1_2 of the first thin-film transistor TR1_2 of the second pixel driving circuit PDC2.

[0256] exist Figure 12 In this context, "EX.1" refers to Embodiment 1, in which the thickness of the electric field blocking layer 210 is 1.0 μm; "EX.2" refers to Embodiment 2, in which the thickness of the electric field blocking layer 210 is 2.0 μm; and "Comp.1" refers to a comparative example in which the electric field blocking layer 210 is not provided.

[0257] Reference Figure 12 In "Comp.1", note that even if no voltage is applied to the gate electrode G1_2 of the first thin-film transistor TR1_2 of the second pixel driving circuit PDC2, the voltage V applied to the gate electrode G1_1 of the first thin-film transistor TR1_1 of the first pixel driving circuit PDC1 is still present. GS Drain-source current I is also easily generated in the first thin-film transistor TR1_2 of the second pixel driving circuit PDC2. DS .

[0258] Reference Figure 12 In “EX.1”, note that when the voltage V applied to the gate electrode G1_1 of the first thin-film transistor TR1_1 of the first pixel driving circuit PDC1 is... GS When the voltage is 15V or greater than the threshold voltage of 0V, a drain-source current I is generated in the first thin-film transistor TR1_2 of the second pixel driving circuit PDC2. DS .

[0259] Reference Figure 12 In “EX.2”, note that when the voltage V applied to the gate electrode G1_1 of the first thin-film transistor TR1_1 of the first pixel driving circuit PDC1 is... GSWhen the voltage is 30V or greater than the threshold voltage of 0V, a drain-source current I is generated in the first thin-film transistor TR1_2 of the second pixel driving circuit PDC2. DS .

[0260] Thus, when no electric field blocking layer 210 is provided between the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2, it is noted that the second pixel driving circuit PDC2 is easily affected by the first pixel driving circuit PDC1. Furthermore, when the thickness of the electric field blocking layer 210 increases, it is noted that the first pixel driving circuit PDC1 has a smaller influence on the second pixel driving circuit PDC2. Moreover, when the thickness of the electric field blocking layer 210 is 1.0 μm or greater, it is noted that the first pixel driving circuit PDC1 has a small influence on the second pixel driving circuit PDC2, and therefore the influence is negligible.

[0261] Figure 13A This is a plan view illustrating the pixel array of a display device according to another embodiment of the present invention. Figure 13B yes Figure 13A A schematic perspective view.

[0262] Figure 13A and Figure 13B The display device 500 shown includes: a first display unit PU1 having a first pixel P1 and a second pixel P2, and a second display unit PU2 having a third pixel P3 and a fourth pixel P4. Figure 13A and Figure 13B The first pixel P1 and the second pixel P2 can be respectively with Figure 3 or Figure 4 The first pixel P1 and the second pixel P2 shown are the same. Furthermore, Figure 13A and Figure 13B The third pixel P3 and the fourth pixel P4 can be respectively with Figure 3 or Figure 4 The first pixel P1 and the second pixel P2 shown are the same.

[0263] Reference Figure 13A and Figure 13B According to another embodiment of the present invention, the display device 500 includes a first pixel P1, a second pixel P2, a third pixel P3, and a fourth pixel P4.

[0264] The first pixel P1 includes a first pixel driving circuit PDC1 and a first display element DU1 connected to the first pixel driving circuit PDC1. (See reference...) Figure 13B The first display element DU1 and the first pixel driving circuit PDC1 can be connected to each other through the first connecting part CT1.

[0265] The second pixel P2 includes a second pixel driving circuit PDC2 and a second display element DU2 connected to the second pixel driving circuit PDC2. (See reference...) Figure 13B The second display element DU2 and the second pixel driving circuit PDC2 can be connected to each other through the second connecting part CT2.

[0266] The third pixel P3 includes a third pixel driving circuit PDC3 and a third display element DU3 connected to the third pixel driving circuit PDC3. (See reference...) Figure 13B The third display element DU3 and the third pixel driving circuit PDC3 can be connected to each other through the third connecting part CT3.

[0267] The fourth pixel P4 includes a fourth pixel driving circuit PDC4 and a fourth display element DU4 connected to the fourth pixel driving circuit PDC4. (See reference...) Figure 13B The fourth display element DU4 and the fourth pixel driving circuit PDC4 can be connected to each other through the fourth connecting part CT4.

[0268] According to another embodiment of the present invention, the display device 500 may be, for example, a top-emitting display device. In this case, the light generated from the display elements DU1, DU2, DU3 and DU4 may be emitted in a direction opposite to the direction toward the pixel driving circuits PDC1, PDC2, PDC3 and PDC4.

[0269] According to another embodiment of the present invention, such as Figure 13B As shown, the first connecting part CT1, the second connecting part CT2, the third connecting part CT3 and the fourth connecting part CT4 can be configured to overlap with the embankment layer 750.

[0270] An electric field blocking layer 210 is disposed between the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2, and between the third pixel driving circuit PDC3 and the fourth pixel driving circuit PDC4. The electric field blocking layer 210 can extend from the portion between the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2 to the portion between the third pixel driving circuit PDC3 and the fourth pixel driving circuit PDC4, thereby forming a single unit. The electric field blocking layer 210 can be integrally formed on the entire surface of the display device 500.

[0271] According to another embodiment of the present invention, the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2 overlap each other. Furthermore, the third pixel driving circuit PDC3 and the fourth pixel driving circuit PDC4 overlap each other.

[0272] According to another embodiment of the present invention, the first pixel P1 and the second pixel P2 constitute a first display unit PU1, and the third pixel P3 and the fourth pixel P4 constitute a second display unit PU2. According to another embodiment of the present invention, as... Figure 13A and Figure 13B As shown, the first display unit PU1 and the second display unit PU2 are adjacent to each other.

[0273] According to another embodiment of the present invention, the electric field blocking layer 210 may have a thickness of 1 μm or greater. The thickness of the electric field blocking layer 210 may be defined as the distance between the upper surface of the first pixel driving circuit PDC1 and the lower surface of the second pixel driving circuit PDC2.

[0274] The electric field blocking layer 210 may have a dielectric constant of 3.9 or less. The electric field blocking layer 210 may have a dielectric constant of 3.5 or less, 3.0 or less, or 2.5 or less.

[0275] The electric field blocking layer 210 may include a siloxane compound. The electric field blocking layer 210 may be formed of a siloxane compound.

[0276] According to another embodiment of the present invention, each of the first pixel driving circuit PDC1, the second pixel driving circuit PDC2, the third pixel driving circuit PDC3, and the fourth pixel driving circuit PDC4 may include two or more thin-film transistors. Each of the first pixel driving circuit PDC1, the second pixel driving circuit PDC2, the third pixel driving circuit PDC3, and the fourth pixel driving circuit PDC4 may have the same characteristics as... Figure 2 , Figure 9 and Figure 10 The circuit diagram shown is identical to any one of the pixel drive circuits (PDC) in the circuit diagram shown.

[0277] According to another embodiment of the present invention, each of the first pixel driving circuit PDC1, the second pixel driving circuit PDC2, the third pixel driving circuit PDC3, and the fourth pixel driving circuit PDC4 may include four or more thin-film transistors.

[0278] Each of the first pixel P1, the second pixel P2, the third pixel P3, and the fourth pixel P4 can have the same characteristics as... Figure 2 , Figure 9 and Figure 10 The same structure for any of the pixels P shown.

[0279] According to another embodiment of the present invention, a first pixel P1 may display a first color, a second pixel P2 may display a second color, a third pixel P3 may display a third color, and a fourth pixel P4 may display a fourth color. According to another embodiment of the present invention, the first color, second color, third color, and fourth color may be different from each other. For example, one of the first color, second color, third color, and fourth color may be white (W). Furthermore, one of the first color, second color, third color, and fourth color may be red (R), another may be green (G), and yet another may be blue (B).

[0280] Figure 14 This is a plan view illustrating the pixel array of a display device 600 according to another embodiment of the present invention. The display device 600 according to another embodiment of the present invention includes a first pixel P1, a second pixel P2, a third pixel P3, and a fourth pixel P4. (Refer to...) Figure 14 The first display unit PU1 includes a first pixel P1 and a second pixel P2, and the second display unit PU2 includes a third pixel P3 and a fourth pixel P4.

[0281] exist Figure 14 In the display device 600 shown, the deposition structures of the first pixel P1, the second pixel P2, the third pixel P3, and the fourth pixel P4 can be compared with... Figure 13B The depositional structures shown are the same.

[0282] According to another embodiment of the present invention, a first pixel P1 may display a first color, a second pixel P2 may display a second color, a third pixel P3 may display the first color, and a fourth pixel P4 may display a third color. In this case, the first color may be green (G), and one of the second and third colors may be red (R) and the other may be blue (B).

[0283] Reference Figure 14 The first pixel P1, the second pixel P2, the third pixel P3, and the fourth pixel P4 that constitute the first display unit PU1 and the second display unit PU2 can be configured to display colors in, for example, the order of green, red, green, and blue.

[0284] Figure 15 This is a plan view illustrating the pixel array of a display device 700 according to yet another embodiment of the present invention.

[0285] Reference Figure 15According to another embodiment of the present invention, a display device 700 includes light-transmitting portions TP1 and TP2 adjacent to a first display unit PU1 and a second display unit PU2. The light-transmitting portions TP1 and TP2 transmit light. According to another embodiment of the present invention, the light-transmitting portion adjacent to the first display unit PU1 is referred to as the first light-transmitting portion TP1, and the light-transmitting portion adjacent to the second display unit PU2 is referred to as the second light-transmitting portion TP2.

[0286] Figure 15 The display device 700 shown is, for example, a transparent display device. The transparent display device includes light-transmitting portions TP1 and TP2 and pixels P1, P2, P3 and P4, and the light-transmitting portions TP1 and TP2 and the pixel portions P1, P2, P3 and P4 can be alternately arranged on a display panel.

[0287] In detail, according to another embodiment of the present invention, the first display unit PU1 and the first light-transmitting portion TP1 can be alternately arranged. The first display unit PU1 includes a first pixel P1 and a second pixel P2. Furthermore, according to another embodiment of the present invention, the second display unit PU2 and the second light-transmitting portion TP2 can be alternately arranged. The second display unit PU2 includes a third pixel P3 and a fourth pixel P4.

[0288] According to another embodiment of the present invention, the area of ​​each of the light-transmitting portions TP1 and TP2 may be the same as or similar to the area of ​​the first display unit PU1 or the second display unit PU2. As a result, light can pass through the display device 700, and the viewer can see the opposite side of the display device.

[0289] Furthermore, even when displaying colors on pixels P1, P2, P3, and P4 of the display device 700 according to another embodiment of the present invention, light can still pass through the light-transmitting portions TP1 and TP2. Therefore, a transparent display device can be realized.

[0290] Figure 16 This is a plan view illustrating the pixel array of a display device 800 according to yet another embodiment of the present invention. Besides the first display unit PU1 and the second display unit PU2, Figure 16 The display device 800 shown also includes a third display unit PU3.

[0291] In detail, besides the first pixel P1, the second pixel P2, the third pixel P3, and the fourth pixel P4, Figure 16The display device 800 shown further includes a fifth pixel P5 and a sixth pixel P6. The fifth pixel P5 includes a fifth pixel driving circuit and a fifth display element connected to the fifth pixel driving circuit PDC5. The sixth pixel P6 includes a sixth pixel driving circuit and a sixth display element connected to the sixth pixel driving circuit. The fifth pixel driving circuit and the sixth pixel driving circuit overlap each other, and an electric field blocking layer 210 is disposed between the fifth pixel driving circuit and the sixth pixel driving circuit.

[0292] According to another embodiment of the present invention, the fifth pixel P5 and the sixth pixel P6 constitute a third display unit PU3. The third display unit PU3 may be adjacent to at least one of the first display unit PU1 and the second display unit PU2.

[0293] The fifth pixel P5 and the sixth pixel P6 can be with Figure 3 The first pixel P1 and the second pixel P2 shown are set in the same way.

[0294] Furthermore, each of the first pixel P1, the second pixel P2, the third pixel P3, and the fourth pixel P4 may have the same characteristics as... Figure 2 , Figure 9 and Figure 10 The structure is identical to that of any one of the pixels P shown. Each of the fifth and sixth pixel driving circuits may have the same structure as... Figure 2 , Figure 9 and Figure 10 The pixel driving circuit PDC shown has the same circuit construction as any one of them.

[0295] Each of the fifth and sixth display elements can be an organic light-emitting diode (OLED).

[0296] exist Figure 16 In the display device 800 shown, a first pixel P1 can display a first color, a second pixel P2 can display a second color, a third pixel P3 can display a third color, a fourth pixel P4 can display the first color, a fifth pixel P5 can display the second color, and a sixth pixel P6 can display the third color. In this case, the first color, the second color, and the third color can be different from each other. According to another embodiment of the present invention, the first pixel P1 and the fourth pixel P4 can display the same color, the second pixel P2 and the fifth pixel P5 can display the same color, and the third pixel P3 and the sixth pixel P6 can display the same color.

[0297] According to another embodiment of the present invention, the first color can be red (R), the second color can be green (G), and the third color can be blue (B).

[0298] According to another embodiment of the present invention, red pixels, green pixels and blue pixels can form a pixel group, and two pixel groups can be displayed through a first display unit PU1, a second display unit PU2 and a third display unit PU3.

[0299] According to the present invention, the following beneficial effects can be obtained.

[0300] According to one embodiment of the present invention, since multiple pixel driving circuits are arranged overlapping each other, a large number of thin-film transistors can be disposed in a limited area. As a result, according to one embodiment of the present invention, thin-film transistors can be integrated into a display device at high density, enabling the manufacture of high-resolution display devices. Furthermore, according to one embodiment of the present invention, transparent display devices in which pixel driving circuits are disposed only in a limited area can be easily manufactured.

[0301] Furthermore, in one embodiment of the invention, even if multiple thin-film transistors are arranged overlapping each other, no electrical interference between the thin-film transistors will occur. As a result, a high-resolution display device with excellent display performance can be manufactured, and a transparent display device in which the pixel driving circuit is disposed only in a limited area can be easily manufactured.

[0302] It will be apparent to those skilled in the art that the present invention is not limited to the described embodiments and drawings, and various substitutions, modifications, and variations can be made in the present invention without departing from its spirit or scope. Therefore, the scope of the present invention is defined by the appended claims, and all variations or modifications derived from the meaning, scope, and equivalent concepts of the claims fall within the scope of the present invention.

Claims

1. A display device, comprising: First pixel driving circuit; An electric field blocking layer on the first pixel driving circuit; The second pixel driving circuit on the electric field blocking layer; as well as The first display element and the second display element on the second pixel driving circuit Each of the first pixel driving circuit and the second pixel driving circuit includes at least one thin-film transistor. The first pixel driving circuit overlaps with the second pixel driving circuit. The first display element is connected to the first pixel driving circuit, and The second display element is connected to the second pixel driving circuit. Each of the thin-film transistors in the first pixel driving circuit and the second pixel driving circuit includes an active layer and a gate electrode separated from the active layer. The thickness t of the electric field blocking layer satisfies the following equation 1: [Equation 1] t ≥ (V GH / V TH ) ×(κ / 3.9) ×(t GI ), In Equation 1, t is the thickness of the electric field blocking layer, κ is the dielectric constant of the electric field blocking layer, and V... GH It is the on-state voltage of the thin-film transistor applied to the first pixel driving circuit, V TH It is the threshold voltage of the thin-film transistor in the second pixel driving circuit, t GI It is the distance between the gate electrode of the thin-film transistor in the second pixel driving circuit and the active layer.

2. The display device according to claim 1, wherein the first display element overlaps with the first pixel driving circuit and the second pixel driving circuit, and The second display element overlaps with the first pixel driving circuit and the second pixel driving circuit.

3. The display device according to claim 1, The electric field blocking layer has a thickness of 1 μm or greater between the first pixel driving circuit and the second pixel driving circuit. The thickness of the electric field blocking layer is defined as the distance between the upper surface of the first pixel driving circuit and the lower surface of the second pixel driving circuit.

4. The display device according to claim 1, wherein the electric field blocking layer has a dielectric constant of 3.9 or less.

5. The display device according to claim 1, wherein the electric field blocking layer comprises a siloxane compound.

6. The display device of claim 1, wherein each of the first pixel driving circuit and the second pixel driving circuit comprises two or more thin-film transistors.

7. The display device of claim 1, wherein each of the first pixel driving circuit and the second pixel driving circuit comprises four or more thin-film transistors.

8. The display device according to claim 1, wherein any thin-film transistor of the first pixel driving circuit and any thin-film transistor of the second pixel driving circuit overlap each other, and Each of the thin-film transistors of the overlapping first pixel driving circuit and the second pixel driving circuit includes: Active layer; and A gate electrode that is separated from and at least partially overlaps with the active layer, and The separation distance between the gate electrode of the thin-film transistor of the first pixel driving circuit and the active layer of the thin-film transistor of the second pixel driving circuit is 1 μm or greater.

9. The display device according to claim 1, wherein the first display element comprises a first electrode, a first organic light-emitting layer, and a second electrode, and The second display element includes a first electrode, a second organic light-emitting layer, and a second electrode.

10. The display device of claim 9, wherein each of the first electrode of the first display element and the first electrode of the second display element has a reflective layer, and the display device is a top-emitting type in which each of the first display element and the second display element emits light through a second electrode.

11. The display device according to claim 1, further comprising: A dam layer, the dam layer defining the light-emitting area of ​​the first display element and the light-emitting area of ​​the second display element; A first connecting portion connects the first display element to the first pixel driving circuit. and The second connecting part connects the second display element to the second pixel driving circuit. At least one of the first connecting portion and the second connecting portion overlaps with the embankment layer.

12. The display device according to claim 11, wherein at least a portion of the first connecting portion overlaps with the embankment.

13. The display device of claim 11, wherein the first connection includes a first portion passing through the electric field blocking layer, the first portion overlapping the dam layer.

14. The display device according to claim 1, wherein the second pixel driving circuit includes a buffer layer disposed on the electric field blocking layer, the buffer layer being formed of an insulating material.

15. A display device, comprising: The first pixel includes a first pixel driving circuit and a first display element connected to the first pixel driving circuit. The second pixel includes a second pixel driving circuit and a second display element connected to the second pixel driving circuit; The third pixel includes a third pixel driving circuit and a third display element connected to the third pixel driving circuit; The fourth pixel includes a fourth pixel driving circuit and a fourth display element connected to the fourth pixel driving circuit; and An electric field blocking layer is disposed between the first pixel driving circuit and the second pixel driving circuit, and between the third pixel driving circuit and the fourth pixel driving circuit. The first pixel driving circuit and the second pixel driving circuit overlap each other. The third pixel driving circuit and the fourth pixel driving circuit overlap each other. The first pixel and the second pixel constitute the first display unit. The third pixel and the fourth pixel constitute the second display unit, and The first display unit and the second display unit are adjacent to each other. Each of the first pixel driving circuit and the second pixel driving circuit includes at least one thin-film transistor. Each of the thin-film transistors in the first pixel driving circuit and the second pixel driving circuit includes an active layer and a gate electrode separated from the active layer. The thickness t of the electric field blocking layer satisfies the following equation 1: [Equation 1] t ≥ (V GH / V TH )x(κ / 3.9)x(t GI ), In Equation 1, t is the thickness of the electric field blocking layer, κ is the dielectric constant of the electric field blocking layer, and V... GH It is the on-state voltage of the thin-film transistor applied to the first pixel driving circuit, V TH It is the threshold voltage of the thin-film transistor in the second pixel driving circuit, t GI It is the distance between the gate electrode of the thin-film transistor in the second pixel driving circuit and the active layer.

16. The display device of claim 15, wherein the electric field blocking layer has a thickness of 1 μm or greater. The thickness of the electric field blocking layer is defined as the distance between the upper surface of the first pixel driving circuit and the lower surface of the second pixel driving circuit.

17. The display device of claim 15, wherein the electric field blocking layer has a dielectric constant of 3.9 or less.

18. The display device of claim 15, wherein the electric field blocking layer comprises a siloxane compound.

19. The display device of claim 15, wherein each of the first pixel driving circuit, the second pixel driving circuit, the third pixel driving circuit, and the fourth pixel driving circuit comprises two or more thin-film transistors.

20. The display device of claim 15, wherein each of the first pixel driving circuit, the second pixel driving circuit, the third pixel driving circuit, and the fourth pixel driving circuit comprises four or more thin-film transistors.

21. The display device according to claim 15, wherein the display device is a top-emitting type.

22. The display device of claim 15, wherein the first pixel displays a first color. The second pixel displays the second color. The third pixel displays a third color. The fourth pixel displays the fourth color. The first color, the second color, the third color, and the fourth color are different from each other, and Any one of the first color, the second color, the third color, and the fourth color is white.

23. The display device according to claim 22, wherein another of the first color, the second color, the third color, and the fourth color is red, another is green, and the other is blue.

24. The display device according to claim 15, wherein the first pixel displays a first color. The second pixel displays the second color. The third pixel displays the first color. The fourth pixel displays the third color. The first color, the second color, and the third color are different from each other.

25. The display device of claim 24, wherein the first color is green, and either the second color or the third color is red, and the other is blue.

26. The display device according to claim 15 further includes a plurality of light-transmitting portions adjacent to the first display unit and the second display unit, wherein the light-transmitting portions transmit light.

27. The display device according to claim 15, further comprising: The fifth pixel includes a fifth pixel driving circuit and a fifth display element connected to the fifth pixel driving circuit; and The sixth pixel includes a sixth pixel driving circuit and a sixth display element connected to the sixth pixel driving circuit. The fifth pixel driving circuit and the sixth pixel driving circuit overlap each other. The electric field blocking layer is disposed between the fifth pixel driving circuit and the sixth pixel driving circuit. The fifth pixel and the sixth pixel constitute the third display unit, and The third display unit is adjacent to at least one of the first display unit and the second display unit.

28. The display device according to claim 27, The first pixel displays the first color. The second pixel displays the second color. The third pixel displays a third color. The fourth pixel displays the first color. The fifth pixel displays the second color. The sixth pixel displays the third color, and The first color, the second color, and the third color are different from each other.

29. The display device according to claim 28, The first color is red. The second color is green, and The third color is blue.

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