Display device

Abstract

Embodiments of the present disclosure relate to a display device, since a storage capacitor provided on a sub-pixel and an active pattern are arranged by using an active layer in which a semiconductor layer and a conductive layer are stacked, an area of the storage capacitor can be efficiently increased, and a method of using an area overlapping a contact hole located on the active pattern as an area of the storage capacitor can be provided. Further, since a position of the contact hole is easily adjusted, by not providing the contact hole on a region adjacent to a driving transistor, a size of the driving transistor can be increased, and an aperture ratio of the sub-pixel can be improved.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a display device. Background Technology

[0002] The growth of the information society has led to an increased demand for display devices that display images and for various types of display devices (such as liquid crystal displays, organic light-emitting diode displays, etc.).

[0003] Because organic light-emitting display devices use self-emissive organic light-emitting diodes (OLEDs) to display images, they offer advantages such as fast response time, good contrast, and high color performance.

[0004] An organic light-emitting display device may include an organic light-emitting diode disposed in each sub-pixel and a driving transistor that provides driving current to the organic light-emitting diode.

[0005] To enhance the driving performance of organic light-emitting diodes (OLEDs) located in sub-pixels, it is necessary to increase the size of the driving transistors located in the sub-pixels. However, increasing the size of the driving transistors presents many difficulties due to the various lines and circuit elements located in the sub-pixels. Summary of the Invention

[0006] Embodiments of this disclosure provide a method for improving the aperture ratio of sub-pixels while increasing the size of the driving transistors used to drive light-emitting elements disposed in the sub-pixels.

[0007] Embodiments of this disclosure provide a method for increasing the capacity of storage capacitors while efficiently arranging the area occupied by storage capacitors disposed in sub-pixels.

[0008] In one aspect, embodiments of the present disclosure may provide a display device including a display panel having a plurality of sub-pixels, wherein each of the plurality of sub-pixels includes a light-emitting element, a driving transistor electrically connected to the light-emitting element, a storage capacitor electrically connected to the driving transistor, and a first active pattern electrically connected to the storage capacitor.

[0009] The storage capacitor may include a first capacitor electrode, a second capacitor electrode located above the first capacitor electrode, and a third capacitor electrode located above the second capacitor electrode, wherein at least a portion of the third capacitor electrode is located in a region overlapping with the first capacitor electrode.

[0010] The first active pattern can be disposed on the same layer as the layer on which the second capacitor electrode is disposed, and can be electrically connected to the third capacitor electrode through a first contact hole located in the region overlapping with the first capacitor electrode.

[0011] The first active pattern may include a semiconductor layer and a conductive layer disposed on at least a portion of the semiconductor layer, and at least a portion of the conductive layer may be removed in the first contact hole.

[0012] The third capacitor electrode can contact the side surface of the conductive layer and the top surface of the semiconductor layer included in the first active pattern in the first contact hole.

[0013] In another aspect, embodiments of this disclosure may provide a display device comprising a display panel having a plurality of sub-pixels, each of the plurality of sub-pixels comprising a light-emitting element, a driving transistor electrically connected to the light-emitting element, and a storage capacitor electrically connected to the driving transistor. The storage capacitor comprises a first capacitor electrode, a second capacitor electrode located above the first capacitor electrode and on a portion of a region overlapping with the first capacitor electrode, and a third capacitor electrode, the third capacitor electrode being located above the second capacitor electrode, a portion of the third capacitor electrode being located on the region overlapping with the second capacitor electrode, and the remainder of the third capacitor electrode being located in a region overlapping with the first capacitor electrode, excluding the region overlapping with the second capacitor electrode.

[0014] In another aspect, embodiments of this disclosure may provide a display device comprising: a substrate; a first capacitor electrode located above the substrate; a second capacitor electrode located above the first capacitor electrode and disposed on a portion of a region overlapping with the first capacitor electrode and electrically connected to the first capacitor electrode; and a third capacitor electrode located above the second capacitor electrode, at least a portion of the third capacitor electrode being disposed on a region overlapping with the second capacitor electrode in a region other than the region overlapping with the second capacitor electrode.

[0015] According to various embodiments of this disclosure, since the contact hole is not disposed in the region adjacent to the driving transistor disposed on the sub-pixel, the size of the driving transistor can be increased and the aperture ratio of the sub-pixel can be improved.

[0016] According to various embodiments of this disclosure, by using the region overlapping with the contact hole located on the circuit region of the sub-pixel as the region of the storage capacitor, the capacity of the storage capacitor can be increased while effectively increasing the area of ​​the storage capacitor. Attached Figure Description

[0017] The above and other objects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0018] Figure 1This is a diagram schematically illustrating the configuration of a display device according to an embodiment of the present disclosure.

[0019] Figure 2 This is a diagram illustrating an example of a circuit structure for a sub-pixel included in a display device according to an embodiment of the present disclosure.

[0020] Figure 3 This is a diagram illustrating an example of the arrangement structure of the light-emitting region and circuit region of a sub-pixel included in a display device according to an embodiment of the present disclosure.

[0021] Figure 4 This is a diagram illustrating an example of a specific planar structure of a circuit region of a sub-pixel included in a display device according to an embodiment of the present disclosure.

[0022] Figure 5 This is a diagram illustrating an example of the structure of a storage capacitor located on a circuit region of a sub-pixel included in a display device, according to an embodiment of the present disclosure.

[0023] Figure 6 This is a diagram illustrating an example of a cross-sectional structure of a portion A-A' on a circuit region of a sub-pixel included in a display device according to an embodiment of the present disclosure.

[0024] Figure 7 This is a diagram illustrating an example of a cross-sectional structure of a portion B-B' on a circuit region of a sub-pixel included in a display device according to an embodiment of the present disclosure.

[0025] Figure 8 This is a diagram illustrating an example of a cross-sectional structure of a portion C-C' on a circuit region of a sub-pixel included in a display device according to an embodiment of the present disclosure.

[0026] Figure 9 This is a diagram illustrating an example of a cross-sectional structure of a portion D-D' on a circuit region of a sub-pixel included in a display device according to an embodiment of the present disclosure. Detailed Implementation

[0027] In the following description of examples or embodiments of this disclosure, reference will be made to the accompanying drawings, in which specific examples or embodiments that may be implemented are illustrated by way of illustration, and wherein the same reference numerals and symbols may be used to indicate the same or similar components even when shown in different drawings. Furthermore, in the following description of examples or embodiments of this disclosure, a detailed description of well-known functions and components incorporated herein will be omitted where it is determined that such detailed description may make the subject matter of some embodiments of this disclosure considerably unclear. Terms used herein, such as “comprising,” “having,” “containing,” “constituting,” “made of,” and “formed from,” are generally intended to allow for the addition of additional components, unless the term is used in conjunction with the term “only.” As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0028] In this document, terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” may be used to describe elements of this disclosure. Each of these terms is not used to define the nature, order, sequence, or number of elements, but merely to distinguish the corresponding element from other elements.

[0029] When referring to the first element as "connected to or linked to," "in contact with," or "overlapping" with the second element, it should be interpreted as meaning that not only can the first element be "directly connected to or linked to" or "directly in contact with or overlap" the second element, but a third element can also be "inserted" between the first and second elements, or the first and second elements can be "connected to or linked to," "in contact with," or "overlapping" with each other via a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected to or linked to," "in contact with," or "overlap" with each other.

[0030] When time-related terms such as “after,” “following,” “then,” “before,” etc., are used to describe the handling or operation of an element or configuration, or a process or step in an operation, handling, or manufacturing method, these terms may be used to describe non-continuous or non-sequential handling or operation, unless the terms “direct” or “immediate” are used together.

[0031] Furthermore, when referring to any size, relative dimensions, etc., the numerical values ​​or corresponding information of the component or feature (e.g., level, range, etc.) should be considered, including tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external shocks, noise, etc.), even if no relevant description is specified. Additionally, the term "can" fully encompasses all the meanings of the term "able to".

[0032] Figure 1 This is a schematic diagram illustrating the configuration included in a display device 100 according to embodiments of the present disclosure. All components of the display device 100 according to all embodiments of the present disclosure are operatively connected and configured.

[0033] Reference Figure 1 The display device 100 may include a display panel 110, a gate driving circuit 120, a data driving circuit 130, and a controller 140 for driving the display panel 110.

[0034] The display panel 110 may include a display area AA with multiple sub-pixels SP and a non-display area located outside the display area AA.

[0035] Multiple gate lines GL and multiple data lines DL can be arranged on the display panel 110. Multiple sub-pixels SP can be located in the area where the gate lines GL and data lines DL intersect.

[0036] The gate drive circuit 120 is controlled by the controller 140 and sequentially outputs scan signals to multiple gate lines GL disposed on the display panel 110, thereby controlling the driving timing of multiple sub-pixels SP.

[0037] The gate drive circuit 120 may include one or more gate driver integrated circuits (GDICs) and may be located only on one side of the display panel 110, or on both sides, depending on the driving method.

[0038] Each gate driver integrated circuit (GDIC) can be connected to the bonding pads of the display panel 110 via a tape-on-brush (TAB) method or a chip-on-glass (COG) method. Alternatively, each GDIC can be implemented using an in-panel gate-in-patch (GIP) method for subsequent direct placement on the display panel 110. Alternatively, in some cases, each GDIC can be integrated and placed on the display panel 110. Alternatively, each GDIC can be implemented using a chip-on-film (COF) method, where components are mounted on a thin film connected to the display panel 110.

[0039] The data driving circuit 130 receives image data from the controller 140 and converts the image data into an analog data voltage Vdata. The data driving circuit 130 outputs the data voltage Vdata to each data line DL according to the timing of the scan signal applied through the gate line GL, causing each of the plurality of sub-pixels SP to emit light with a brightness according to the image data.

[0040] The data drive circuit 130 may include one or more source driver integrated circuits (SDICs).

[0041] Each source driver integrated circuit (SDIC) may include a shift register, latch circuit, digital-to-analog converter, output buffer, etc.

[0042] Each source driver integrated circuit (SDIC) can be connected to the bonding pads of the display panel 110 via a tape-on-a-brush (TAB) method or a chip-on-glass (COG) method. Alternatively, each source driver integrated circuit can be directly disposed on the display panel 110. In some cases, each source driver integrated circuit (SDIC) can be integrated and arranged on the display panel 110. Alternatively, each source driver integrated circuit (SDIC) can be implemented using a chip-on-film (COF) method. In this case, each source driver integrated circuit (SDIC) can be mounted on a film connected to the display panel 110 and can be electrically connected to the display panel 110 via wires on the film.

[0043] The controller 140 provides various control signals to the gate drive circuit 120 and the data drive circuit 130, and controls the operation of the gate drive circuit 120 and the data drive circuit 130.

[0044] The controller 140 can be mounted on a printed circuit board, flexible printed circuit, etc., and can be electrically connected to the gate drive circuit 120 and the data drive circuit 130 through the printed circuit board, flexible printed circuit, etc.

[0045] The controller 140 allows the gate drive circuit 120 to output a scan signal according to the timing implemented in each frame. The controller 140 can convert data signals received from the outside to conform to the data signal format used in the data drive circuit 130, and then output the converted image data to the data drive circuit 130.

[0046] The controller 140 receives various timing signals from an external source (e.g., a host system), including the vertical synchronization signal VSYNC, the horizontal synchronization signal HSYNC, the input data enable signal DE, the clock signal CLK, and image data.

[0047] The controller 140 can generate various control signals using various timing signals received from the outside, and can output the control signals to the gate drive circuit 120 and the data drive circuit 130.

[0048] For example, in order to control the gate drive circuit 120, the controller 140 can output various gate control signals GCS, including gate start pulse GSP, gate shift clock GSC, gate output enable signal GOE, etc.

[0049] The gate start pulse (GSP) controls the start-up timing of one or more gate driver integrated circuits (GDICs) constituting the gate drive circuit 120. The gate shift clock (GSC), which is typically input to one or more gate driver integrated circuits (GDICs), controls the shift timing of the scan signal. The gate output enable signal (GOE) specifies timing information on one or more gate driver integrated circuits (GDICs).

[0050] In addition, in order to control the data drive circuit 130, the controller 140 can output various data control signals DCS, including source start pulse SSP, source sampling clock SSC, source output enable signal SOE, etc.

[0051] The source start pulse SSP controls the data sampling start timing of one or more source driver integrated circuits (SDICs) constituting the data drive circuit 130. The source sampling clock SSC is a clock signal used to control the timing of the sampled data in each source driver integrated circuit (SDIC). The source output enable signal SOE controls the output timing of the data drive circuit 130.

[0052] The display device 100 may also include a power management integrated circuit for providing various voltages or currents to the display panel 110, gate driving circuit 120, data driving circuit 130, etc., or controlling the various voltages or currents provided thereto.

[0053] Each of the plurality of sub-pixels SP can be a region defined by the intersection of gate line GL and data line DL, and at least one circuit element including a light-emitting element can be disposed on the sub-pixel SP.

[0054] For example, when the display device 100 is an organic light-emitting display device, an organic light-emitting diode (OLED) and multiple circuit elements can be disposed in each of the multiple sub-pixels SP. When the display device 100 drives the multiple circuit elements to control the current supplied to the organic light-emitting diode (OLED) disposed on the sub-pixel SP, the brightness of each sub-pixel SP corresponding to the image data can be controlled.

[0055] Figure 2 This is a diagram illustrating an example of the circuit structure of a sub-pixel SP included in a display device 100 according to an embodiment of the present disclosure.

[0056] Figure 2 An example of the circuit structure of a sub-pixel SP is shown in the case where the display device 100 is an organic light-emitting display device, but the embodiments of this disclosure can be applied to different types of display devices.

[0057] Reference Figure 2The light-emitting element ED and the driving transistor DRT for driving the light-emitting element ED can be disposed on the sub-pixel SP. In addition, at least one circuit element other than the light-emitting element ED and the driving transistor DRT can be further disposed on the sub-pixel SP.

[0058] For example, such as Figure 2 In the example shown, the switching transistor SWT, the sensing transistor SENT, and the storage capacitor Cstg can be further disposed on the sub-pixel SP.

[0059] therefore, Figure 2 The example shown illustrates a 3T1C structure in which, in addition to the light-emitting element ED, three thin-film transistors and one capacitor are disposed on the sub-pixel SP as an example; however, embodiments of this disclosure are not limited thereto. Furthermore, Figure 2 The example shown illustrates the case where all thin-film transistors are N-type, but in some cases, the thin-film transistors set on the sub-pixel SP can be P-type.

[0060] The switching transistor SWT can be electrically connected between the data line DL and the first node N1.

[0061] The data voltage Vdata can be supplied to the sub-pixel SP via the data line DL. The first node N1 can be the gate node of the driving transistor DRT.

[0062] The switching transistor SWT can be controlled by a scan signal provided to the gate line GL. The switching transistor SWT can control the data voltage Vdata provided through the data line DL to be applied to the gate node of the driving transistor DRT.

[0063] The driving transistor DRT can be electrically connected between the driving voltage line DVL and the light-emitting element ED.

[0064] The first drive voltage EVDD can be provided to the third node N3 through the drive voltage line DVL. For example, the first drive voltage EVDD can be a high potential voltage. The third node N3 can be the drain node or source node of the drive transistor DRT.

[0065] The driving transistor DRT can be controlled by the voltage applied to the first node N1. Furthermore, the driving transistor DRT can control the driving current supplied to the light-emitting element ED.

[0066] The sensing transistor SENT can be electrically connected between the reference voltage line RVL and the second node N2.

[0067] The reference voltage Vref can be provided to the second node N2 through the reference voltage line RVL. The second node N2 can be the source node or the drain node of the driving transistor DRT.

[0068] The sensing transistor SENT can be controlled by a scan signal provided to the gate line GL. The gate line GL controlling the sensing transistor SENT can be the same as or different from the gate line GL controlling the switching transistor SWT.

[0069] The sensing transistor SENT can be controlled to apply a reference voltage Vref to the second node N2. Furthermore, in some cases, the sensing transistor SENT can be controlled to sense the voltage of the second node N2 via the reference voltage line RVL.

[0070] The storage capacitor Cstg can be electrically connected between the first node N1 and the second node N2. The storage capacitor Cstg can maintain the data voltage Vdata applied to the first node N1 during one frame.

[0071] The light-emitting element ED can be electrically connected between the second node N2 and the line provided with the second driving voltage EVSS. The second driving voltage EVSS can be, for example, a low potential voltage.

[0072] When a scan signal at the on level is applied to the gate line GL, the switching transistor SWT and the sensing transistor SENT can be turned on. The data voltage Vdata can be applied to the first node N1, and the reference voltage Vref can be applied to the second node N2.

[0073] The drive current provided by the drive transistor DRT can be determined based on the difference between the voltage of the first node N1 and the voltage of the second node N2.

[0074] An ED (Emitting Light) element can represent the brightness based on the drive current provided by the driving transistor DRT.

[0075] To enhance the brightness of the sub-pixel SP, it may be important to increase the area of ​​the light-emitting region in the sub-pixel SP from which light emitted from the light-emitting element ED is output to the outside. In the case of a display device 100 with a bottom light-emitting structure where light emitted from the light-emitting element ED is output to the bottom surface of the substrate, since the light-emitting region can be set in an area other than the circuit region where circuit elements are set, it is necessary to efficiently set the circuit region to increase the light-emitting region.

[0076] Figure 3 This is a diagram illustrating an example of the arrangement structure of the light-emitting region and the circuit region of the sub-pixel SP included in the display device 100 according to an embodiment of the present disclosure.

[0077] Reference Figure 3 This illustrates an example of a structure where four sub-pixels (SPs) are positioned adjacent to each other. For instance, each of the four sub-pixels (SPs) can represent a different color, and the four sub-pixels (SPs) can constitute a single pixel.

[0078] The data line DL, which provides the data voltage Vdata to each of the four sub-pixels SP, can be electrically connected to each of the four sub-pixels SP.

[0079] The first driving voltage EVDD provided by the driving voltage line DVL can be provided to two or more sub-pixels SP positioned in the direction intersecting the driving voltage line DVL. For example, the first driving voltage EVDD can be provided to the sub-pixels SP through a driving voltage line connection pattern DVL_CP electrically connected to the driving voltage line DVL.

[0080] The reference voltage Vref provided by the reference voltage line RVL can be supplied to two or more sub-pixels SP located in the direction intersecting the reference voltage line RVL. For example, the reference voltage Vref can be supplied to the sub-pixels SP through a reference voltage line connection pattern RVL_CP electrically connected to the reference voltage line RVL.

[0081] The gate line GL, which controls the driving timing of the four sub-pixels SP, can be configured to cross the data line DL. The gate line GL can be electrically connected to the switching transistor SWT and the sensing transistor SENT located on each of the four sub-pixels SP.

[0082] The circuit area containing circuit elements such as thin-film transistors can be located in an area other than the light-emitting area on the four sub-pixels SP that outputs light emitted from the light-emitting element ED to the outside.

[0083] The switching transistor SWT and the sensing transistor SENT can be disposed on the circuit area of ​​the sub-pixel SP. Additionally, the driving transistor DRT and the storage capacitor Cstg can be disposed on the circuit area of ​​the sub-pixel SP.

[0084] The luminous efficiency of the subpixel SP can be improved by considering the performance of the driving transistor DRT and the storage capacitor Cstg located in the circuit region of the subpixel SP.

[0085] The display device 100 according to an embodiment of the present disclosure provides a method for improving the aperture ratio of the sub-pixel SP and increasing the luminous efficiency of the light-emitting element ED disposed on the sub-pixel SP by effectively disposing the driving transistor DRT and the storage capacitor Cstg on the circuit region of the sub-pixel SP.

[0086] Figure 4 This is a diagram illustrating an example of a specific planar structure of a circuit region of a sub-pixel SP included in a display device 100 according to an embodiment of the present disclosure.

[0087] Reference Figure 4The circuit elements and lines disposed on the sub-pixel SP can be disposed using two or more metal layers. For example, the circuit elements and lines disposed on the sub-pixel SP can be disposed using a first metal layer M1, an active layer ACT, a second metal layer M2, and a third metal layer M3.

[0088] For example, the first metal layer M1 may be the metal layer most adjacent to the substrate among the metal layers disposed on the substrate. Alternatively, the first metal layer M1 may be a metal layer closer to the substrate than the active layer ACT, the second metal layer M2, and the third metal layer M3.

[0089] For example, the drive voltage line DVL, data line DL, and reference voltage line RVL can be set using the first metal layer M1. Furthermore, the storage capacitor Cstg can be set using the first metal layer M1.

[0090] In addition, in some cases, the repair pattern RP can be set by using the first metal layer M1.

[0091] For example, when a disconnection defect occurs in the gate line GL, a repair pattern RP can be used in the repair process of the gate line GL using the drive voltage line connection pattern DVL_CP.

[0092] When a gate line GL disconnection defect occurs, the pixel at the point where the gate line GL is disconnected may be darkened. The drive voltage line DVL can be cut, and the drive voltage line DVL and the gate line GL can be soldered. By soldering the repair pattern RP and the drive voltage line connection pattern DVL_CP, the scan signal provided to the gate line GL can be transmitted through the cut drive voltage line DVL, the drive voltage line connection pattern DVL_CP, and the repair pattern RP.

[0093] The active layer ACT can be located above the first metal layer M1.

[0094] For example, the channel regions of the switching transistor (SWT), sensing transistor (SENT), and driving transistor (DRT) can be formed using an active layer (ACT). Furthermore, the source and drain electrodes of a thin-film transistor can be formed using an active layer (ACT).

[0095] In addition, active layers (ACTs) can be used to set up lines or active patterns (APs) that are electrically connected to thin-film transistors.

[0096] For example, the reference voltage line connection pattern RVL_CP, which electrically connects the reference voltage line RVL and the sensing transistor SENT, can be set using the active layer ACT.

[0097] Since the reference voltage line connection pattern RVL_CP is set using the active layer ACT, the reference voltage line connection pattern RVL_CP and the sensing transistor SENT can be directly connected. Contact holes for the electrical connection between the reference voltage line connection pattern RVL_CP and the sensing transistor SENT are not required. Therefore, the number of contact holes provided on the sub-pixel SP can be reduced.

[0098] In another example, a first active pattern AP1 can be configured to electrically connect the switching transistor SWT and the storage capacitor Cstg using an active layer ACT. In some cases, the first active pattern AP1 can be considered to include at least a portion of the active layer ACT that constitutes the switching transistor SWT.

[0099] In another example, a second active pattern AP2 can be configured to electrically connect the sensing transistor SENT and the storage capacitor Cstg using an active layer ACT. In some cases, the second active pattern AP2 can be considered to include part of the active layer ACT that constitutes the sensing transistor SENT.

[0100] Furthermore, the storage capacitor Cstg can be set using an active layer ACT. As described above, by using the active layer ACT, the reference voltage line connection pattern RVL_CP, the first active pattern AP1, the second active pattern AP2, and the storage capacitor Cstg can be set. The reference voltage line connection pattern RVL_CP, the second active pattern AP2, and the storage capacitor Cstg can be integrated. The reference voltage line connection pattern RVL_CP, the sensing transistor SENT, and the driving transistor DRT can be a structure connected using the active layer ACT. Therefore, the circuit structure of the sub-pixel SP can be constructed while reducing the contact holes used for electrical connections between the voltage line and the thin-film transistor.

[0101] For example, the active layer ACT can be made of semiconductor material. In this case, lines using the active layer ACT can be fabricated using conductive processes.

[0102] For example, the active layer ACT can be a structure in which a metal material is stacked on a semiconductor material. Furthermore, the semiconductor material and the metal material included in the active layer ACT can be in direct contact with each other. In this case, the metal material of the active layer ACT can be removed in the channel region and can be disposed on portions constituting lines, etc.

[0103] The second metal layer M2 can be located above the active layer ACT.

[0104] For example, the gate line GL can be set using the second metal layer M2. Furthermore, the drive voltage line connection pattern DVL_CP can be set using the second metal layer M2.

[0105] Furthermore, the gate electrode of the driving transistor DRT can be set using a second metal layer M2. The storage capacitor Cstg can also be set using the second metal layer M2.

[0106] Furthermore, in some cases, by using the second metal layer M2, an electrode connection pattern CE_CP that electrically connects the first metal layer M1 and the active layer ACT can be set.

[0107] The third metal layer M3 can be located above the second metal layer M2.

[0108] For example, the pixel electrode PXL can be set using a third metal layer M3. The pixel electrode PXL can be the anode electrode of the light-emitting element ED set on the sub-pixel SP.

[0109] Various types of contact holes used to electrically connect metal layers disposed on different layers to each other can be provided on sub-pixels SP.

[0110] For example, a plurality of contact holes CHa, provided by penetrating at least one insulating layer located between the first metal layer M1 and the second metal layer M2, can be located on the sub-pixel SP.

[0111] Furthermore, multiple contact holes CHb, which are formed by penetrating at least one insulating layer located between the active layer ACT and the second metal layer M2, can be located on the sub-pixel SP.

[0112] Furthermore, multiple contact holes CHc, which are formed by penetrating at least one insulating layer located between the second metal layer M2 and the third metal layer M3, can be located on the sub-pixel SP.

[0113] The display device 100 according to the embodiments of the present disclosure can minimize the number of lines and contact holes provided on the sub-pixel SP in order to improve the aperture ratio of the sub-pixel SP.

[0114] For example, since the switching transistor SWT and the sensing transistor SENT are driven by a single gate line GL, the number of gate lines GL set on the sub-pixel SP can be reduced.

[0115] Furthermore, since only a first contact hole CH1 for connecting the switching transistor SWT and the sensing transistor SENT, and a second contact hole CH2 for connecting the sensing transistor SENT and the storage capacitor Cstg are provided, the number of contact holes provided on the sub-pixel SP can be reduced.

[0116] Furthermore, since the third contact hole CH3, which is used for electrical connection with the pixel electrode PXL, is located in the area overlapping with the second contact hole CH2, the entire area where the contact hole is located can be reduced.

[0117] Furthermore, the storage capacitor Cstg disposed on the sub-pixel SP can be configured using three or more layers. Therefore, the area occupied by the storage capacitor Cstg on the sub-pixel SP can be effectively configured, and the capacity of the storage capacitor Cstg can be increased.

[0118] Figure 5 This is a diagram illustrating an example of the structure of a storage capacitor Cstg located on a circuit region of a sub-pixel SP included in a display device 100, according to an embodiment of the present disclosure.

[0119] Reference Figure 5 The storage capacitor Cstg disposed on the sub-pixel SP may include a first capacitor electrode CE1, a second capacitor electrode CE2, and a third capacitor electrode CE3.

[0120] The first capacitor electrode CE1 can be set using the first metal layer M1.

[0121] A portion of the first capacitor electrode CE1 may overlap with the driving transistor DRT. A portion of the first capacitor electrode CE1 may overlap with the first active pattern AP1.

[0122] The second capacitor electrode CE2 can be set using the active layer ACT.

[0123] The second capacitor electrode CE2 may be located above the first capacitor electrode CE1. The second capacitor electrode CE2 may be located on a portion of the region overlapping with the first capacitor electrode CE1.

[0124] The second capacitor electrode CE2 can be electrically connected to the driving transistor DRT. The second capacitor electrode CE2 can be integrated with the active layer ACT that constitutes the driving transistor DRT.

[0125] The second capacitor electrode CE2 can be electrically connected to the second active pattern AP2. The second capacitor electrode CE2 can be integrated with the second active pattern AP2.

[0126] The second capacitor electrode CE2 can be electrically connected to the first capacitor electrode CE1 via the electrode connection pattern CE_CP. The electrode connection pattern CE_CP can be set using a second metal layer M2.

[0127] The third capacitor electrode CE3 can be set by using the second metal layer M2.

[0128] The third capacitor electrode CE3 can be located above the second capacitor electrode CE2.

[0129] The third capacitor electrode CE3 may be located on at least a portion of the region overlapping with the first capacitor electrode CE1. The third capacitor electrode CE3 may also be located on at least a portion of the region overlapping with the second capacitor electrode CE2.

[0130] A portion of the third capacitor electrode CE3 may overlap with the first capacitor electrode CE1 in a region other than the region overlapping with the second capacitor electrode CE2.

[0131] The third capacitor electrode CE3 can be electrically connected to the gate electrode of the driving transistor DRT. The third capacitor electrode CE3 can be integrated with the gate electrode of the driving transistor DRT.

[0132] The third capacitor electrode CE3 can be electrically connected to the first active pattern AP1.

[0133] The third capacitor electrode CE3 can be electrically connected to the first active pattern AP1 through the first contact hole CH1. The first contact hole CH1 can be located in a region other than the region connected to the gate electrode of the third capacitor electrode CE3 and the driving transistor DRT.

[0134] For example, the third capacitor electrode CE3 can be located between the first contact hole CH1 and the driving transistor DRT.

[0135] Since the contact hole is not located in the area adjacent to the driving transistor DRT, the size of the driving transistor DRT can be easily increased.

[0136] Furthermore, since the third capacitor electrode CE3 together with the second capacitor electrode CE2 forms the storage capacitor Cstg, and together with the first capacitor electrode CE1 in the area that does not overlap with the second capacitor electrode CE2, the capacity of the storage capacitor Cstg can be increased.

[0137] In addition, the pixel electrode PXL can be electrically connected to the first capacitor electrode CE1 and the second capacitor electrode CE2 via the electrode connection pattern CE_CP.

[0138] The pixel electrode PXL can be set using the metal layer M3, and the pixel electrode PXL can be located above the third capacitor electrode CE3.

[0139] Therefore, the third capacitor electrode CE3 can be used together with the pixel electrode PXL to form the storage capacitor Cstg.

[0140] By using multiple layers to set the storage capacitor Cstg, the area where the storage capacitor Cstg is set can be constructed efficiently, and the capacity of the storage capacitor Cstg can be increased.

[0141] Furthermore, since the first capacitor electrode CE1 is located below the contact hole CHb (e.g., the first contact hole CH1) provided by penetrating the insulating layer located between the active layer ACT and the second metal layer M2, the area of ​​the storage capacitor Cstg can be maximized.

[0142] For example, when the first active pattern AP1 is set by using an active layer ACT made of semiconductor and metal materials, the area overlapping with the first contact hole CH1 can be used as the area of ​​the storage capacitor Cstg.

[0143] Furthermore, the metal material included in the active layer ACT may not be disposed on the channel region of the thin-film transistor disposed on the sub-pixel SP.

[0144] Figure 6 This is a diagram illustrating an example of the cross-sectional structure of a portion A-A' on the circuit region of a sub-pixel SP included in a display device 100 according to an embodiment of the present disclosure.

[0145] Reference Figure 6 It shows an example of the cross-sectional structure of the driving transistor DRT disposed on the sub-pixel SP.

[0146] The first capacitor electrode CE1, which is provided by using the first metal layer M1, can be disposed on the substrate SUB.

[0147] The buffer layer BUF can be set on the first capacitor electrode CE1.

[0148] The active layer (ACT) can be set on the buffer layer (BUF).

[0149] For example, the active layer ACT may include a semiconductor layer SEMI and a conductive layer COND disposed on the semiconductor layer SEMI. For example, the conductive layer COND may be disposed on at least a portion of the semiconductor layer SEMI of the active layer ACT.

[0150] The material constituting the semiconductor layer SEMI included in the active layer ACT can be, for example, an oxide semiconductor. The semiconductor layer SEMI can be an oxide of metals such as molybdenum (Mo), zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti). Alternatively, the semiconductor layer SEMI can be made of a combination of metals such as molybdenum (Mo), zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti) and their oxides. Furthermore, the semiconductor layer SEMI can be a semiconductor material other than an oxide semiconductor, but embodiments of this disclosure are not limited to these.

[0151] The conductive layer COND included in the active layer ACT may include, for example, one of a metal or alloy thereof such as aluminum (Al), gold (Au), silver (Ag), copper (Cu), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), and titanium (Ti), but the embodiments of this disclosure are not limited to these.

[0152] In the process of setting the active layer ACT, for example, the conductive layer COND can be set on the channel region of the driving transistor DRT without a halftone exposure process.

[0153] The active layer ACT, which consists only of the semiconductor layer SEMI, can be placed on the channel region of the driving transistor DRT.

[0154] The semiconductor layer SEMI and conductive layer COND included in the active layer ACT can be configured as a stacked structure on the regions corresponding to the source and drain electrodes of the driving transistor DRT.

[0155] The gate insulating layer GI can be disposed on the active layer ACT.

[0156] The gate electrode of the driving transistor DRT can be disposed on the gate insulating layer G1.

[0157] The gate electrode of the driving transistor DRT can be made of a second metal layer M2 and can be integrated with a third capacitor electrode CE3.

[0158] The contact hole may not be located in the area adjacent to the driving transistor DRT.

[0159] Therefore, the size of the driving transistor DRT can be increased. Furthermore, the region adjacent to the driving transistor DRT can be used as the region for the storage capacitor Cstg.

[0160] Figure 7 This is a diagram illustrating an example of the cross-sectional structure of a portion B-B' on the circuit region of a sub-pixel SP included in a display device 100 according to an embodiment of the present disclosure.

[0161] refer to Figure 7 The first capacitor electrode CE1 can be located in the region where the third capacitor electrode CE3 and the gate electrode of the driving transistor DRT are connected.

[0162] The second capacitor electrode CE2 can be located on a portion of the first capacitor electrode CE1.

[0163] The third capacitor electrode CE3 can be located above the second capacitor electrode CE2.

[0164] A portion of the third capacitor electrode CE3 may be disposed in the region overlapping with the second capacitor electrode CE2, and together with the second capacitor electrode CE2, it may form a storage capacitor Cstg.

[0165] The remaining portion of the third capacitor electrode CE3 can be located in the region overlapping with the first capacitor electrode CE1, in the region where the second capacitor electrode CE2 is not provided. Therefore, the remaining portion of the third capacitor electrode CE3 can together with the first capacitor electrode CE1 to form a storage capacitor Cstg.

[0166] Since the storage capacitor Cstg can be placed in the area where the driving transistor DRT and the third capacitor electrode CE3 are connected, and the size of the driving transistor DRT is increased, the capacitance of the storage capacitor Cstg can be increased further.

[0167] Furthermore, since the area where the third capacitor electrode CE3 and the first active pattern AP1 are connected is used as the area of ​​the storage capacitor Cstg, the capacity of the storage capacitor Cstg can be effectively increased.

[0168] Figure 8 This is a diagram illustrating an example of a cross-sectional structure of a portion C-C' on the circuit region of a sub-pixel SP included in a display device 100 according to an embodiment of the present disclosure.

[0169] Reference Figure 8 The buffer layer BUF can be disposed on the first capacitor electrode CE1. The first active pattern AP1 can be disposed on the buffer layer BUF.

[0170] The first active pattern AP1 may include a semiconductor layer SEMI.

[0171] The first active pattern AP1 may include a conductive layer COND disposed on a portion of the semiconductor layer SEMI.

[0172] The conductive layer COND included in the first active pattern AP1 can be a shape that is removed over at least a portion of the region corresponding to the first contact hole CH1. A portion of the conductive layer COND included in the first active pattern AP1 can be removed by a process used to set the first contact hole CH1.

[0173] For example, the active layer ACT, which consists of a semiconductor layer (SEMI) and a conductive layer (COND), can be disposed on the buffer layer (BUF). The gate insulating layer (GI) can be disposed on the active layer ACT.

[0174] A process of etching the gate insulating layer GI can be performed to form the first contact hole CH1. The process of etching the gate insulating layer GI can be a dry etching process, but is not limited to this.

[0175] During the etching of the gate insulating layer GI, the conductive layer COND disposed on the semiconductor layer SEMI of the active layer ACT can be removed. Furthermore, the semiconductor layer SEMI can be retained and not removed during the etching of the gate insulating layer GI.

[0176] Because the semiconductor layer SEMI of the active layer ACT is retained, the buffer layer BUF located below the active layer ACT can be prevented from being damaged during the etching of the gate insulating layer GI.

[0177] Therefore, since the third capacitor electrode CE3 disposed on the gate insulating layer GI can be prevented from penetrating below the buffer layer BUF, the first capacitor electrode CE1 can be disposed below the first contact hole CH1.

[0178] The conductive layer COND included in the active layer ACT can be retained in an area other than the first contact hole CH1. The conductive layer COND can be disposed along the outer edge of the first contact hole CH1. Furthermore, the conductive layer COND can protrude toward the first contact hole CH1 below the gate insulating layer GI.

[0179] The active layer ACT, which is a portion of the conductive layer COND disposed on the semiconductor layer SEMI and has been removed, can become the first active pattern AP1.

[0180] Through the above process, a first active pattern AP1 can be formed, including a semiconductor layer SEMI and a conductive layer COND disposed on a portion of the semiconductor layer SEMI.

[0181] The second metal layer M2 constituting the third capacitor electrode CE3 can be disposed on the gate insulating layer GI and in the first contact hole CH1.

[0182] For example, the third capacitor electrode CE3 may contact the top surface of the semiconductor layer SEMI included in the first active pattern AP1 in the first contact hole CH1. For example, the third capacitor electrode CE3 may contact the side surface of the conductive layer COND included in the first active pattern AP1 in the first contact hole CH1. Furthermore, in some cases, the third capacitor electrode CE3 may contact the top surface of the conductive layer COND included in the first active pattern AP1 in the first contact hole CH1.

[0183] Since the third capacitor electrode CE3 is in contact with the conductive layer COND of the first active pattern AP1, the third capacitor electrode CE3 and the first active pattern AP1 can be electrically connected.

[0184] Therefore, the third capacitor electrode CE3 and the switching transistor SWT can be electrically connected. The data voltage Vdata supplied through the data line DL and the switching transistor SWT can be applied to the third capacitor electrode CE3 and the gate electrode of the drive transistor DRT.

[0185] The first capacitor electrode CE1 can be located below the first contact hole CH1.

[0186] The third capacitor electrode CE3 can form a storage capacitor Cstg together with the first capacitor electrode CE1 in the area where the first contact hole CH1 is provided to be electrically connected to the first active pattern AP1.

[0187] The embodiments of this disclosure can increase the capacity of the storage capacitor Cstg, while effectively increasing the area on which the storage capacitor Cstg can be disposed on the sub-pixel SP.

[0188] Furthermore, embodiments of this disclosure can prevent a reduction in the area of ​​the storage capacitor Cstg due to the contact hole by minimizing the area occupied by the contact hole on the sub-pixel SP.

[0189] Figure 9 This is a diagram illustrating an example of the cross-sectional structure of a portion D-D' on the circuit region of a sub-pixel SP included in a display device 100 according to an embodiment of the present disclosure.

[0190] Reference Figure 9 The first capacitor electrode CE1 and the second capacitor electrode CE2 can be electrically connected through the second contact hole CH2.

[0191] The second contact hole CH2 can be located in the area overlapping with the first capacitor electrode CE1.

[0192] The second contact hole CH2 can be located on the side of the storage capacitor Cstg where the first contact hole CH1 is located. The second capacitor electrode CE2 constituting the storage capacitor Cstg can be located between the second contact hole CH2 and the driving transistor DRT.

[0193] The second contact hole CH2 may include a contact hole CHa formed by penetrating at least one insulating layer located between the first metal layer M1 and the second metal layer M2. Furthermore, the second contact hole CH2 may include a contact hole CHb formed by penetrating at least one insulating layer located between the active layer ACT and the second metal layer M2.

[0194] For example, the buffer layer BUF can be disposed on the first capacitor electrode CE1.

[0195] The active layer ACT can be disposed on a portion of the buffer layer BUF. The active layer ACT may include a semiconductor layer SEMI and a conductive layer COND disposed on the semiconductor layer SEMI.

[0196] A portion of the buffer layer BUF and the gate insulating layer GI disposed on the first capacitor electrode CE1 can be removed by an etching process. Furthermore, a portion of the gate insulating layer GI disposed on the active layer ACT can be removed by an etching process.

[0197] A portion of the gate insulating layer GI disposed on the active layer ACT is removed, and a portion of the conductive layer COND included in the active layer ACT can be removed.

[0198] The active layer ACT, which is formed by removing a portion of the conductive layer COND disposed on the semiconductor layer SEMI, can be transformed into a second active pattern AP2.

[0199] A portion of the conductive layer COND included in the second active pattern AP2 may protrude toward the outside of the gate insulating layer GI.

[0200] The electrode connection pattern CE_CP disposed in the second contact hole CH2 can contact the top surface of the first capacitor electrode CE1. Furthermore, the electrode connection pattern CE_CP can contact the top surface of the semiconductor layer SEMI and the side surface of the conductive layer COND included in the second active pattern AP2.

[0201] Because the electrode connection pattern CE_CP is in contact with the conductive layer COND included in the second active pattern AP2, the second active pattern AP2 and the first capacitor electrode CE1 can be electrically connected. Furthermore, because the second active pattern AP2 is integrated with the second capacitor electrode CE2, the second capacitor electrode CE2 and the first capacitor electrode CE1 can be electrically connected.

[0202] Furthermore, the third contact hole CH3 may be disposed in an area that overlaps with at least a portion of the second contact hole CH2.

[0203] For example, the third contact hole CH3 can be a contact hole CHc formed by penetrating at least one insulating layer located between the second metal layer M2 and the third metal layer M3. The third contact hole CH3 can be disposed in the passivation layer PAS and the cover layer OC, which are disposed on the second metal layer M2.

[0204] The pixel electrode PXL and the electrode connection pattern CE_CP can be electrically connected through the third contact hole CH3.

[0205] Therefore, the pixel electrode PXL can be electrically connected to the storage capacitor Cstg, the sensing transistor SENT, and the driving transistor DRT disposed on the sub-pixel SP through the third contact hole CH3.

[0206] By minimizing the number of contact holes set on the sub-pixel SP, the area of ​​the storage capacitor Cstg can be prevented from decreasing, and the aperture ratio of the sub-pixel SP can be improved.

[0207] According to the embodiments of the present disclosure described above, since the storage capacitor Cstg disposed on the sub-pixel SP is arranged in three or more layers, the capacity of the storage capacitor Cstg can be increased, while the area of ​​the storage capacitor Cstg is effectively set.

[0208] Furthermore, since the active pattern AP disposed on the sub-pixel SP is arranged by using an active layer ACT which is stacked with a semiconductor layer SEMI and a conductive layer COND, the area overlapping with the contact hole disposed on the active pattern AP can be used as the area of ​​the storage capacitor Cstg.

[0209] Furthermore, since the area overlapping with the contact hole can be used as the area of ​​the storage capacitor Cstg, the position of the contact hole can be easily adjusted, so the contact hole does not have to be located in the area adjacent to the driving transistor DRT.

[0210] Therefore, the aperture ratio of the sub-pixel SP can be improved by effectively increasing the size of the driving transistor DRT and the capacity of the storage capacitor Cstg set on the sub-pixel SP.

[0211] The above description is provided to enable those skilled in the art to implement and use the technical ideas of this disclosure, and is given in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this disclosure. The above description and drawings provide examples of the technical ideas of this disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical ideas of this disclosure. Therefore, the scope of this disclosure is not limited to the embodiments shown, but is consistent with the widest scope conforming to the claims. The scope of protection of this disclosure should be interpreted based on the appended claims, and all technical ideas within the scope of their equivalents should be interpreted as being included within the scope of this disclosure.

[0212] Cross-references to related applications

[0213] This application claims priority to Korean Patent Application No. 10-2020-0185418, filed on December 29, 2020, which is incorporated herein by reference for all purposes, as if fully set forth herein.

Claims

1. A display device, the display device comprising: The display panel has multiple sub-pixels, and Each of the plurality of sub-pixels includes: Light-emitting elements; The driving transistor electrically connected to the light-emitting element; The storage capacitor electrically connected to the driving transistor; and The first active pattern electrically connected to the storage capacitor, The storage capacitor includes, First capacitor electrode; The second capacitor electrode is located above the first capacitor electrode; and A third capacitor electrode is located above the second capacitor electrode, and at least a portion of the third capacitor electrode lies in the region overlapping with the first capacitor electrode. The first active pattern is disposed on the same layer as the layer on which the second capacitor electrode is disposed, and is electrically connected to the third capacitor electrode through a first contact hole located in the region overlapping with the first capacitor electrode.

2. The display device according to claim 1, wherein, The first active pattern includes a semiconductor layer and a conductive layer disposed on at least a portion of the semiconductor layer, and At least a portion of the conductive layer is removed in the first contact hole.

3. The display device according to claim 2, wherein, The third capacitor electrode is in contact with the side surface of the conductive layer and the top surface of the semiconductor layer included in the first active pattern in the first contact hole.

4. The display device according to claim 1, wherein, A portion of the third capacitor electrode is located in the region that overlaps with the first capacitor electrode, excluding the region that overlaps with the second capacitor electrode.

5. The display device according to claim 1, wherein, The third capacitor electrode is connected to the gate electrode of the driving transistor.

6. The display device according to claim 5, wherein, The first contact hole is located in a region other than the area where the gate electrode of the driving transistor and the third capacitor electrode are connected.

7. The display device according to claim 1, wherein, The second capacitor electrode includes a semiconductor layer and a conductive layer disposed over the entire area of ​​the semiconductor layer.

8. The display device according to claim 1, wherein, The first capacitor electrode is electrically connected to the second capacitor electrode.

9. The display device according to claim 1, wherein, Each of the plurality of sub-pixels also includes: A second active pattern is disposed on the same layer as the layer on which the second capacitor electrode is disposed, and is connected to the second capacitor electrode; and An electrode connection pattern is disposed on the same layer as the layer on which the third capacitor electrode is disposed, and is electrically connected to the first capacitor electrode and the second active pattern through a second contact hole located in the region overlapping with the first capacitor electrode.

10. The display device according to claim 9, wherein, The second active pattern includes a semiconductor layer and a conductive layer disposed on at least a portion of the semiconductor layer, and At least a portion of the conductive layer is removed in the second contact hole.

11. The display device according to claim 10, wherein, The electrode connection pattern contacts the side surface of the semiconductor layer and the top surface of the conductive layer included in the second active pattern in the second contact hole.

12. The display device according to claim 9, wherein, The electrode connection pattern is electrically connected to the light-emitting element through a third contact hole that overlaps with at least a portion of the second contact hole.

13. The display device according to claim 9, wherein, The second capacitor electrode is located between the second contact hole and the driving transistor.

14. A display device comprising: The display panel has multiple sub-pixels, and Each of the plurality of sub-pixels includes: Light-emitting elements; The driving transistor electrically connected to the light-emitting element; The storage capacitor electrically connected to the driving transistor, The storage capacitor includes, First capacitor electrode; A second capacitor electrode is located above the first capacitor electrode and on a portion of the region overlapping with the first capacitor electrode; and A third capacitor electrode is located above the second capacitor electrode, and a portion of the third capacitor electrode is located in the region overlapping with the second capacitor electrode, while the remaining portion of the third capacitor electrode is located in the region overlapping with the first capacitor electrode, excluding the region overlapping with the second capacitor electrode. At least one contact hole, the at least one contact hole being located in a region overlapping with the first capacitor electrode and in a region overlapping with the third capacitor electrode; and An active pattern comprising a semiconductor layer completely disposed within the at least one contact hole and a conductive layer disposed on the semiconductor layer along the outer edge of the at least one contact hole.

15. The display device according to claim 14, wherein, The second capacitor electrode is located between the at least one contact hole and the driving transistor.

16. The display device according to claim 14, wherein, The active pattern is disposed on the same layer as the layer on which the second capacitor electrode is disposed, and is disposed on a region including the region overlapping with the at least one contact hole.

17. A display device comprising: A substrate having a plurality of sub-pixels, each of the plurality of sub-pixels comprising: Light-emitting elements; The driving transistor electrically connected to the light-emitting element; The storage capacitor electrically connected to the driving transistor, The storage capacitor includes: First capacitor electrode; A second capacitor electrode, located above the first capacitor electrode, disposed on a portion of the region overlapping with the first capacitor electrode, and electrically connected to the first capacitor electrode; and A third capacitor electrode, the third capacitor electrode being located above the second capacitor electrode, and at least a portion of the third capacitor electrode being disposed in the region overlapping the first capacitor electrode, excluding the region overlapping the second capacitor electrode; and An active pattern is electrically connected to the third capacitor electrode through a contact hole located in the region overlapping with the first capacitor electrode.

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