Circuit devices and oscillators

Abstract

A circuit arrangement and an oscillator are provided, enabling multiple outputs of a clock signal and high-precision duty cycle adjustment. The circuit arrangement includes: an oscillator circuit that generates an oscillation signal by oscillating an oscillator; a waveform shaping circuit that takes the oscillation signal as input and outputs a clock signal obtained by waveform shaping the oscillation signal; a first duty cycle adjustment circuit that adjusts the duty cycle of the clock signal; and an output buffer circuit that outputs the first output clock signal and a second output clock signal to the outside based on the clock signal. The output buffer circuit includes a second duty cycle adjustment circuit that adjusts the duty cycle of the second output clock signal.

Description

Technical Field

[0001] This invention relates to circuit devices and oscillators, etc. Background Technology

[0002] Conventionally, circuit devices with oscillation circuits that cause oscillators such as quartz oscillators to oscillate are known. In such circuit devices, it is desirable to achieve high precision in the duty cycle of the clock signal generated based on the oscillation signal. For example, Patent Document 1 discloses a CMOS inverter circuit that, after an input signal is input to the input terminal, a control signal is input to the control terminal of a switch connected to the source of one of the PMOS transistors and NMOS transistors, thereby maintaining the voltage of the input signal and performing duty cycle correction on the output signal.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2013-21388

[0004] However, in the structure of Patent Document 1, it is difficult to perform high-precision duty cycle adjustment of the clock signal. For example, it is difficult to achieve high-precision duty cycle adjustment while realizing the multiple output function of the clock signal. Summary of the Invention

[0005] This disclosure relates to a circuit device comprising: an oscillation circuit electrically connected to a first node electrically connected to one end of an oscillator and a second node electrically connected to the other end of the oscillator, generating an oscillation signal by oscillating the oscillator; a waveform shaping circuit connected to the first node, receiving the oscillation signal from the first node and outputting a clock signal obtained by waveform shaping the oscillation signal; a first duty cycle adjustment circuit for adjusting the duty cycle of the clock signal; and an output buffer circuit for outputting a first output clock signal and a second output clock signal to the outside according to the clock signal, the output buffer circuit including a second duty cycle adjustment circuit for adjusting the duty cycle of the second output clock signal.

[0006] Furthermore, another aspect of this disclosure relates to an oscillator comprising the aforementioned circuitry and the oscillator. Attached Figure Description

[0007] Figure 1 This is an example of the structure of the circuit device in this embodiment.

[0008] Figure 2 This is a detailed structural example of the circuit device in this embodiment.

[0009] Figure 3 This is a structural example of a circuit device that illustrates the details of the first duty cycle adjustment circuit.

[0010] Figure 4It is a chart that shows the relationship between the adjustment value of the adjusted data and the duty cycle.

[0011] Figure 5 It is a chart showing the process variation of the duty cycle of the clock signal.

[0012] Figure 6 It is a chart showing the process variation of the duty cycle when the duty cycle adjustment circuit is used.

[0013] Figure 7 This is a structural example of the circuit device in the first comparative example of this embodiment.

[0014] Figure 8 This is a structural example of the circuit device in the second comparative example of this embodiment.

[0015] Figure 9 This is a structural example of a circuit device that illustrates the details of the second duty cycle adjustment circuit.

[0016] Figure 10 It is a chart that shows the relationship between the adjustment value of the adjusted data and the duty cycle.

[0017] Figure 11 It is a chart that shows the relationship between the adjustment value of the adjusted data and the duty cycle.

[0018] Figure 12 It is a graph representing the process variation of the duty cycle of the output clock signal.

[0019] Figure 13 It is a graph showing the process variation of the output clock signal duty cycle when the duty cycle adjustment circuit has been applied.

[0020] Figure 14 It is a graph showing the process variation of the output clock signal duty cycle when the duty cycle is adjusted by the first duty cycle adjustment circuit and the second duty cycle adjustment circuit.

[0021] Figure 15 This is an example of the structure of the second duty cycle adjustment circuit.

[0022] Figure 16 This is a detailed structural example of the second duty cycle adjustment circuit.

[0023] Figure 17 This is a detailed structural example of the second duty cycle adjustment circuit.

[0024] Figure 18 This is a variation of the circuit device in this embodiment.

[0025] Figure 19 This is a variation of the circuit device in this embodiment.

[0026] Figure 20 This is a variation of the circuit device in this embodiment.

[0027] Figure 21 This is an example of the structure of the first duty cycle adjustment circuit.

[0028] Figure 22 This is an example of an oscillator construction.

[0029] Label Explanation

[0030] 4: Oscillator; 10: Vibrator; 15: Package; 16: Base; 17: Cover; 18: External Terminal; 19: External Terminal; 20: Circuit Device; 30: Oscillator Circuit; 32: Variable Capacitor Circuit; 40: Waveform Shaping Circuit; 50: First Duty Cycle Adjustment Circuit; 52: Voltage Divider Circuit; 54: Selection Circuit; 60: Processing Circuit; 62: Non-Volatile Memory; 70: Output Buffer Circuit; 72: First Buffer Circuit; 74: Second Buffer Circuit; 80: Second Duty Cycle Adjustment Circuit; 82: Reference Inverting Circuit; 84: Inverting Circuit for Duty Cycle Adjustment Path; 84-1~84-n: Inverting circuit for adjusting the first duty cycle to the nth duty cycle; 90: Power supply circuit; 92: Temperature compensation circuit; 94: Temperature sensor circuit; 120: Circuit device; 130: Oscillation circuit; 140: Waveform shaping circuit; 220: Circuit device; 230: Oscillation circuit; 240: Waveform shaping circuit; 250: Bias circuit; 260: Constant current circuit; ADJ: Adjustment data; BF1, BF2: Buffer circuit; BMP: Bump; CB, CF1, CF2, CG: Capacitors; CK: Clock Signals; CKQ1, CKQ2: Output clock signals; CV1: Variable capacitor element; CV2: Variable capacitor element; CX, CX1, CX2: Capacitors; DT1~DTn: Control signals; IS: Current source; IVA1, IVA2, IVB1, IVB2: Inverting circuit; N1: Node 1; N2: Node 2; VCMP: Temperature compensation voltage; R1~Rm-1: Resistors; RB: Feedback resistor; RBS, RCP, RRF, RRFB, RFFC, RX: Resistors; TP01, TP02, TP11, TP 12. TP21, TP22, TPn1, TPn2: ​​P-type transistors; TN01, TN02, TN11, TN12, TN21, TN22, TNn1, TNn2: N-type transistors; TCK1, TCK2: Clock terminals; TGND: Ground terminal; TR: Bipolar transistor; TVDD: Power supply terminal; TXI, TXO: Terminals; VBS: Bias voltage; VDD: Power supply voltage; VR1~VRm-1: Voltage divider voltages; VREF, VREFB, VREFC: Reference voltages; XI, XO: Oscillation signals. Detailed Implementation

[0031] The embodiments will now be described. Furthermore, the embodiments described below do not unduly limit the scope of the claims. Also, not all structures described in these embodiments are necessarily essential structural elements.

[0032] 1. Circuit device

[0033] Figure 1 An example of the structure of the circuit device 20 of this embodiment is shown. The circuit device 20 of this embodiment includes an oscillation circuit 30, a waveform shaping circuit 40, a first duty cycle adjustment circuit 50, and an output buffer circuit 70, the output buffer circuit 70 including a second duty cycle adjustment circuit 80. Furthermore, as will be described later... Figure 22 As described above, the oscillator 4 of this embodiment includes an oscillator 10 and a circuit device 20. The oscillator 10 is electrically connected to the circuit device 20. For example, the oscillator 10 and the circuit device 20 are electrically connected using internal wiring, bonding wires, or metal bumps in a package that houses the oscillator 10 and the circuit device 20.

[0034] The oscillator 10 is a component that generates mechanical vibration through an electrical signal. The oscillator 10 can be implemented, for example, using a quartz resonator or similar vibrating plate. For instance, the oscillator 10 can be implemented using a quartz resonator with a shearing angle of AT or SC, a tuning fork type quartz resonator, or a double tuning fork type quartz resonator. For example, the oscillator 10 can be an oscillator built into a temperature-compensated quartz oscillator (TCXO) without a thermostatic bath, or an oscillator built into a thermostatically controlled quartz oscillator (OCXO) with a thermostatic bath. Alternatively, the oscillator 10 can be an oscillator built into an SPXO (Simple Packaged Crystal Oscillator). Furthermore, the oscillator 10 of this embodiment can also be implemented using various vibrating plates, such as those other than shearing type, tuning fork type, or double tuning fork type, or piezoelectric resonators made of materials other than quartz. For example, as the oscillator 10, a SAW (Surface Acoustic Wave) resonator or a MEMS (Micro ElectroMechanical Systems) oscillator formed using a silicon substrate as a silicon oscillator can also be used.

[0035] Circuit device 20 is an integrated circuit device called an IC (Integrated Circuit). For example, circuit device 20 is an IC manufactured by semiconductor technology, which is a semiconductor chip on a semiconductor substrate on which circuit elements are formed.

[0036] The oscillation circuit 30 is a circuit that causes the oscillator 10 to oscillate. For example, the oscillation circuit 30 is electrically connected to a first node N1 electrically connected to one end of the oscillator 10 and a second node N2 electrically connected to the other end of the oscillator 10, generating oscillation signals XI and XO by causing the oscillator 10 to oscillate. Specifically, the oscillation circuit 30 is electrically connected to a terminal TXI electrically connected to one end of the oscillator 10 and a terminal TXO electrically connected to the other end of the oscillator 10, generating oscillation signals XI and XO by causing the oscillator 10 to oscillate. Terminal TXI is the first terminal, and terminal TXO is the second terminal. Terminals TXI and TXO are, for example, pads of the circuit device 20 of the IC. The oscillation circuit 30 can be implemented, for example, by a drive circuit for oscillation and passive components such as capacitors or resistors provided between terminals TXI and TXO. The drive circuit can be implemented, for example, by a CMOS inverter circuit or a bipolar transistor. The drive circuit is the core circuit of the oscillation circuit 30, and the drive circuit drives the oscillator 10 with voltage or current, thereby causing the oscillator 10 to oscillate. As the oscillation circuit 30, various types of oscillation circuits, such as inverter type, Pierce type, Colpitts type, or Hartley type, can be used. Furthermore, a variable capacitor circuit is provided in the oscillation circuit 30, and the oscillation frequency can be adjusted by adjusting the capacitance of this variable capacitor circuit. The variable capacitor circuit can be implemented, for example, using a variable capacitor element such as a varactor diode. Alternatively, it can be implemented using a capacitor array whose capacitance values ​​are binary-weighted and a switch array connected to the capacitor array. The variable capacitor circuit is electrically connected, for example, to a first signal line connected to terminal TXI. The oscillation circuit 30 may also have: a first variable capacitor circuit electrically connected to the first signal line connected to terminal TXI; and a second variable capacitor circuit electrically connected to a second signal line connected to terminal TXO. In addition, the connection in this embodiment is an electrical connection. An electrical connection is a connection capable of transmitting electrical signals and transmitting information via electrical signals. An electrical connection can also be a connection via passive components, etc.

[0037] The waveform shaping circuit 40 is a circuit that shapes the waveform of the oscillation signal XI. It is a buffer circuit that receives the oscillation signal XI as input and outputs a clock signal CK. For example, the waveform shaping circuit 40 is connected to the first node N1, receives the oscillation signal XI from the first node N1, and outputs a clock signal CK obtained by shaping the oscillation signal XI. For example, the waveform shaping circuit 40 shapes a sinusoidal oscillation signal XI and outputs a rectangular wave clock signal CK. The waveform shaping circuit 40 can be configured, for example, by multiple inverting circuits.

[0038] The first duty cycle adjustment circuit 50 is a circuit that adjusts the duty cycle of the clock signal CK. The first duty cycle adjustment circuit 50 can also be described as a bias voltage adjustment circuit that adjusts the bias voltage VBS. For example, the first duty cycle adjustment circuit 50 adjusts the duty cycle of the clock signal CK by supplying a bias voltage VBS, which is variably adjusted according to the adjustment data ADJ, to the first node N1. By adjusting the duty cycle of the clock signal CK, the following also applies: Figure 2 The duty cycle of the output clock signals CKQ1 and CKQ2 of the circuit device 20. The duty cycle is also called the duty period. In this embodiment, the duty cycle is sometimes simply referred to as the duty period. For example, when the adjustment data ADJ is a first adjustment value, the first duty cycle adjustment circuit 50 generates a bias voltage VBS corresponding to a first voltage value, and when the adjustment data ADJ is a second adjustment value, it generates a bias voltage VBS corresponding to a second voltage value. That is, the first duty cycle adjustment circuit 50 supplies a bias voltage VBS, whose voltage value is variably set according to the adjustment data ADJ, to the first node N1.

[0039] The first duty cycle adjustment circuit 50 supplies a bias voltage VBS to the first node N1, which serves as the output node of the oscillation signal XI, thereby making the oscillation signal XI an AC signal that varies around the bias voltage VBS. For example, the oscillation signal XI becomes an AC signal that is DC cut off by a capacitor (not shown), and the center voltage of this AC signal is set by the bias voltage VBS from the first duty cycle adjustment circuit 50. Moreover, the oscillation signal XI with the bias voltage VBS set in this way is input to the waveform shaping circuit 40 and waveform shaping is performed, thereby generating a rectangular wave clock signal CK.

[0040] In this case, the adjustment data ADJ is set to an adjustment value such that the duty cycle of the clock signal CK is, for example, 50%. For instance, in cases where variations in semiconductor manufacturing processes are typical, the adjustment data ADJ is set to an adjustment value such that the bias voltage VBS is set to approximately half the power supply voltage of the waveform shaping circuit 40. Furthermore, even if the manufacturing process of the P-type or N-type transistors constituting the inverting circuit of the waveform shaping circuit 40 varies rapidly or slowly, the adjustment value of the adjustment data ADJ is set to 50% for the duty cycle of the clock signal CK. Thus, even in cases of manufacturing process variations, a clock signal CK with a duty cycle adjusted to 50% can be generated.

[0041] The output buffer circuit 70 outputs output clock signals CKQ1 and CKQ2 to the outside based on the clock signal CK. For example, the output buffer circuit 70 buffers the clock signal CK and outputs it as output clock signals CKQ1 and CKQ2. CKQ1 is the first output clock signal, and CKQ2 is the second output clock signal. The output clock signals CKQ1 and CKQ2 are, for example, clock signals with different phases, specifically, clock signals with a phase difference of 180 degrees. In this way, the output buffer circuit 70 outputs the output clock signals CKQ1 and CKQ2 based on the oscillation signal XI to the clock terminals TCK1 and TCK2. Moreover, the output clock signals CKQ1 and CKQ2 are output to the outside from the clock terminals TCK1 and TCK2 via the external terminals of the oscillator 4. For example, the output buffer circuit 70 outputs the output clock signals CKQ1 and CKQ2 in the form of single-ended CMOS signals. For example, when the output enable signal input via the output enable terminal (not shown) is valid, the output buffer circuit 70 outputs the output clock signals CKQ1 and CKQ2. On the other hand, when the output enable signal is invalid, the output buffer circuit 70 sets the output clock signals CKQ1 and CKQ2 to a fixed voltage level, such as a low level. Therefore, the voltage levels of the clock terminals TCK1 and TCK2 are set to a fixed voltage level. Furthermore, the output enable can be controlled independently for each of the output clock signals CKQ1 and CKQ2. Additionally, a valid signal is, for example, a high level in positive logic and a low level in negative logic. Conversely, an invalid signal is, for example, a low level in positive logic and a high level in negative logic. Furthermore, in... Figure 2 In this circuit, the output buffer circuit 70 outputs two output clock signals CKQ1 and CKQ2, but it can also output more than three output clock signals by buffering the clock signal CK. Furthermore, the output buffer circuit 70 can also output the output clock signals CKQ1 and CKQ2 in a signal format other than CMOS.

[0042] Furthermore, the output buffer circuit 70 includes a second duty cycle adjustment circuit 80, which adjusts the duty cycle of the output clock signal CKQ2, which serves as the second output clock signal. For example, the output clock signal CKQ1, which serves as the first output clock signal, is output from the output buffer circuit 70 without duty cycle adjustment by the second duty cycle adjustment circuit 80. On the other hand, the output clock signal CKQ2, which serves as the second output clock signal, is output from the output buffer circuit 70 after duty cycle adjustment by the second duty cycle adjustment circuit 80. For example, the second duty cycle adjustment circuit 80 adjusts the duty cycle of the output clock signal CKQ2 based on adjustment data ADJ2, which serves as the second adjustment data.

[0043] Figure 2A detailed structural example of the circuit device 20 in this embodiment is shown. For example... Figure 2 As shown, the circuit device 20, in addition to Figure 1 In addition to its structure, it may also include a processing circuit 60, a non-volatile memory 62, a power supply circuit 90, a temperature compensation circuit 92, and a temperature sensor circuit 94.

[0044] The processing circuit 60 is a control circuit that performs various control processes, for example, implemented through logic circuits. For instance, the processing circuit 60 performs overall control of the circuit device 20, or controls the sequence of actions of the circuit device 20. Furthermore, the processing circuit 60 controls individual circuit modules of the circuit device 20, such as the oscillation circuit 30, the output buffer circuit 70, and the temperature compensation circuit 92. Additionally, the processing circuit 60 performs read / write control of the non-volatile memory 62. The processing circuit 60 can be implemented, for example, using an ASIC (Application Specific Integrated Circuit) circuit based on automatic configuration routing, such as a gate array.

[0045] The non-volatile memory 62 stores various information used in the circuit device 20. The non-volatile memory 62 can be implemented, for example, by an EEPROM such as a FAMOS (Floating Gate Avalanche Injection MOS) memory or a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) memory, but is not limited to these; it can also be an OTP (One Time Programmable) memory or a fuse-type ROM, etc.

[0046] 62 pairs of non-volatile memory Figure 1The adjustment data ADJ and ADJ2 are stored. Furthermore, the adjustment data ADJ read from the non-volatile memory 62 via the processing circuit 60 is input to the first duty cycle adjustment circuit 50, which adjusts the duty cycle of the clock signal CK based on the adjustment data ADJ. For example, the first duty cycle adjustment circuit 50 generates a bias voltage VBS that is variably set according to the adjustment data ADJ and supplies it to the first node N1, thereby adjusting the duty cycle of the clock signal CK. Additionally, the duty cycle of the clock signal CKQ2 is adjusted by the second duty cycle adjustment circuit 80 based on the adjustment data ADJ2 read from the non-volatile memory 62 via the processing circuit 60. For example, the second duty cycle adjustment circuit 80 uses a control signal based on the adjustment data ADJ2 to adjust the duty cycle of the clock signal CKQ2. Thus, the circuit device 20 of this embodiment includes a non-volatile memory 62 storing the adjustment data ADJ and ADJ2. Furthermore, the first duty cycle adjustment circuit 50 adjusts the duty cycle of the clock signal CK based on the adjustment data ADJ stored in the non-volatile memory 62. For example, it adjusts the duty cycle of the output clock signal CKQ1. Additionally, the second duty cycle adjustment circuit 80 adjusts the duty cycle of the output clock signal CKQ2 based on the adjustment data ADJ2 stored in the non-volatile memory 62. Furthermore, as described later, the non-volatile memory 62 also stores information for temperature compensation.

[0047] The power supply circuit 90 is supplied with a power supply voltage VDD from the power supply terminal TVDD and a ground voltage GND from the ground terminal TGND, supplying power supply voltages for each circuit block of the circuit device 20. For example, the power supply circuit 90 includes a regulator that provides an regulated power supply voltage generated based on the power supply voltage VDD to each circuit block of the circuit device 20. For example, the power supply circuit 90 supplies a first regulated power supply voltage to the oscillation circuit 30 and a second regulated power supply voltage different from the first regulated power supply voltage to the waveform shaping circuit 40 or the output buffer circuit 70. Furthermore, the power supply circuit 90 also supplies various regulated power supply voltages to the first duty cycle adjustment circuit 50, the processing circuit 60, the non-volatile memory 62, the temperature compensation circuit 92, and the temperature sensor circuit 94. Additionally, the power supply circuit 90 also includes a reference voltage generation circuit and a reference current generation circuit.

[0048] Temperature compensation circuit 92 performs temperature compensation for the oscillation frequency of oscillation circuit 30. Temperature compensation of the oscillation frequency refers to temperature compensation of the oscillation signals XI and XO of oscillation circuit 30. Specifically, temperature compensation circuit 92 performs temperature compensation based on temperature detection information from temperature sensor circuit 94. For example, temperature compensation circuit 92 generates a temperature compensation voltage based on the temperature detection voltage from temperature sensor circuit 94 and outputs the generated temperature compensation voltage to oscillation circuit 30, thereby performing temperature compensation for the oscillation frequency of oscillation circuit 30. For example, temperature compensation circuit 92 adjusts the capacitance of variable capacitor circuit 32 by outputting a temperature compensation voltage as the capacitor control voltage of variable capacitor circuit 32, thereby performing temperature compensation. In this case, variable capacitor circuit 32 of oscillation circuit 30 is implemented using a variable capacitor element such as a varactor diode. Temperature compensation is a process that suppresses and compensates for oscillation frequency variations caused by temperature changes. For example, temperature compensation circuit 92 performs temperature compensation based on a polynomial approximation analog method. For example, when the temperature compensation voltage for compensating the frequency-temperature characteristics of the oscillator 10 is approximated by a polynomial, the temperature compensation circuit 92 performs analog temperature compensation based on the coefficient information of the polynomial. Analog temperature compensation is achieved, for example, by adding current and voltage signals, which are analog signals. Specifically, the coefficient information of the polynomial used for temperature compensation is stored in the non-volatile memory 62, and the processing circuit 60 reads this coefficient information from the non-volatile memory 62, for example, and sets it in the register of the temperature compensation circuit 92. Furthermore, the temperature compensation circuit 92 performs analog temperature compensation based on the coefficient information set in the register. Alternatively, the temperature compensation circuit 92 can also perform digital temperature compensation. In this case, the temperature compensation circuit 92 performs digital temperature compensation processing based on temperature detection data, which is temperature detection information from the temperature sensor circuit 94. For example, the temperature compensation circuit 92 calculates frequency adjustment data based on the temperature detection data.

[0049] Furthermore, temperature compensation processing of the oscillation frequency of the oscillation circuit 30 is achieved by adjusting the capacitance value of the variable capacitor circuit 32 of the oscillation circuit 30 according to the obtained frequency adjustment data. In this case, the variable capacitor circuit of the oscillation circuit 30 is implemented by a capacitor array having multiple capacitors weighted in a binary manner and a switch array. In addition, the non-volatile memory 62 stores a lookup table representing the correspondence between temperature detection data and frequency adjustment data, and the temperature compensation circuit 92 performs the following temperature compensation processing: using the lookup table read from the non-volatile memory 62 by the processing circuit 60, the frequency adjustment data is obtained according to the temperature data.

[0050] Temperature sensor circuit 94 is a sensor circuit for detecting temperature. Specifically, temperature sensor circuit 94 outputs a temperature-dependent voltage that varies according to the ambient temperature as a temperature detection voltage. For example, temperature sensor circuit 94 uses temperature-dependent circuit elements to generate the temperature detection voltage. Specifically, temperature sensor circuit 94 outputs a temperature detection voltage whose voltage value varies with temperature by utilizing the temperature dependence of the forward voltage of a PN junction. The forward voltage of the PN junction can be, for example, the base-emitter voltage of a bipolar transistor. Furthermore, in the case of digital temperature compensation processing, temperature sensor circuit 94 measures the ambient temperature and other temperatures, and outputs the result as temperature detection data. The temperature detection data is data that increases or decreases monotonically relative to the temperature.

[0051] Furthermore, the first duty cycle adjustment circuit 50 includes a voltage divider circuit 52 and a selection circuit 54. The voltage divider circuit 52 outputs multiple divided voltages by dividing the power supply voltage and the ground voltage. For example, the voltage divider circuit 52 has multiple resistors connected in series between the power supply node and the ground node, outputting multiple divided voltages obtained by dividing the voltage using these resistors. That is, the voltage divider circuit 52 is implemented using a resistor ladder circuit or the like. The power supply node is the node supplied with the power supply voltage, and the ground node is the node supplied with the ground voltage. Moreover, the selection circuit 54 selects the first divided voltage, which is any one of the multiple divided voltages, as the bias voltage VBS. That is, the selection circuit 54 selects the first divided voltage, which is any one of the multiple divided voltages, as the bias voltage VBS according to the adjustment data ADJ. Furthermore, the selection circuit 54 selects the second divided voltage, which is any one of the multiple divided voltages, as the reference voltage VREF, which will be described later.

[0052] 2. First duty cycle adjustment circuit

[0053] Next, the details of the first duty cycle adjustment circuit 50 will be explained. Figure 3 This is a structural example of a circuit device 20 that illustrates the details of the first duty cycle adjustment circuit 50. In Figure 3 In the oscillation circuit 30, a current source IS, a bipolar transistor TR, a resistor RX, and a capacitor CX are included. The current source IS and the bipolar transistor TR are connected in series between the power supply node and the ground node of VRG1. These current sources IS and the bipolar transistor TR constitute the driving circuit of the oscillation circuit 30. The current source IS can be implemented, for example, by a CMOS transistor whose gate is biased by an input voltage. The resistor RX is located between the collector node and the base node of the bipolar transistor TR. The capacitor CX is located between the base node of the bipolar transistor TR and the first node N1.

[0054] In addition, Figure 3In the oscillation circuit 30, variable capacitor elements CV1 and CV2 implemented by varactor diodes, etc., and fixed capacitors CF1 and CF2 with fixed capacitance values ​​are included as follows: Figure 2 The variable capacitor circuit 32. Specifically, the oscillation circuit 30 includes: a fixed capacitor CF1, one end of which is connected to the first node N1; and a variable capacitor element CV1, one end of which is connected to the other end of the fixed capacitor CF1, with a variable capacitance value. Furthermore, the oscillation circuit 30 includes: a fixed capacitor CF2, one end of which is connected to the second node N2; and a variable capacitor element CV2, one end of which is connected to the other end of the fixed capacitor CF2, with a variable capacitance value. A capacitor CG is disposed between the other ends of the variable capacitor elements CV1 and CV2 and the ground node. Moreover, from... Figure 2 The temperature compensation voltage VCMP of the temperature compensation circuit 92 is supplied to one end of the variable capacitor elements CV1 and CV2 via resistor RCP. Furthermore, the reference voltage VREF is supplied to the other end of the variable capacitor elements CV1 and CV2 via resistor RRF. Thus, a voltage corresponding to the voltage difference between the temperature compensation voltage VCMP and the reference voltage VREF is applied to the variable capacitor elements CV1 and CV2. Therefore, the variable capacitor elements CV1 and CV2 are set to the capacitance corresponding to the temperature compensation voltage VCMP, thereby achieving temperature compensation of the oscillation frequency of the oscillation circuit 30. Additionally, in Figure 3 In the circuit, the first duty cycle adjustment circuit 50, which supplies the bias voltage VBS, also supplies the reference voltage VREF.

[0055] The first duty cycle adjustment circuit 50 is implemented by a trapezoidal resistor circuit disposed between the power node and the ground node of VRG1, and outputs a bias voltage VBS as a voltage divider voltage generated by the trapezoidal resistor circuit. Furthermore, the first duty cycle adjustment circuit 50 outputs a reference voltage VREF for temperature compensation as described above. Moreover, the bias voltage VBS is supplied to the first node N1 via a resistor RBS. Using this bias voltage VBS, the center voltage of an oscillation signal XI, which is an AC signal, is set, and an oscillation signal XI, for example a sine wave, varying around the bias voltage VBS, is input to the waveform shaping circuit 40.

[0056] The waveform shaping circuit 40 includes multiple inverting circuits IVA1 and IVA2 as buffer circuits. Inverting circuits IVA1 and IVA2 are respectively composed of a P-type transistor and an N-type transistor connected in series between the power supply node and the ground node of VREG2. Furthermore, an oscillation signal XI, whose bias point is set by a bias voltage VBS, is input as an input signal to the primary inverting circuit IVA1 of the waveform shaping circuit 40. That is, the oscillation signal XI is input to the gates of the P-type transistor and the N-type transistor constituting the inverting circuit IVA1. Moreover, the output signal of the inverting circuit IVA1 is input to the next-stage inverting circuit IVA2, which outputs a clock signal CK. Thus, the waveform shaping circuit 40 outputs a rectangular wave clock signal CK that has shaped the oscillation signal XI. Additionally, as an example, the temperature compensation voltage VCMP is, for example, a voltage centered at 0.9V that varies according to the temperature detection result. The reference voltage VREF is, for example, a voltage of approximately 0.3V to 0.4V. The power supply voltage of VREG1 is, for example, 1.2V, and the power supply voltage of VREG2 is, for example, 1.0V. The bias voltage VBS is, for example, a voltage adjusted within a range of ±0.1V with 0.5V as the center. 0.5V is about half of the power supply voltage of VREG2 of the waveform shaping circuit 40.

[0057] As described above, the circuit device 20 of this embodiment includes: an oscillation circuit 30 connected to a first node N1 and a second node N2 connected to the oscillator 10, generating oscillation signals XI and XO; a waveform shaping circuit 40 that receives the oscillation signal XI from the first node N1 and outputs a clock signal CK; and a first duty cycle adjustment circuit 50 that supplies a bias voltage VBS, which is variably adjusted according to adjustment data ADJ, to the first node N1. Furthermore, the oscillation signal XI, which varies around the bias voltage VBS, which is variably adjusted according to the adjustment data ADJ, is input to the waveform shaping circuit 40 for waveform shaping, thereby adjusting the duty cycle of the clock signal CK. In this way, the duty cycle of the clock signal CK can be adjusted by taking into account process variations such as the threshold voltage of the P-type or N-type transistor constituting the waveform shaping circuit 40, distortion of the oscillation waveform, or deviations in the duty cycle in subsequent circuits. The duty cycles of the output clock signals CKQ1 and CKQ2 from the circuit device 20 can also be adjusted. This allows the duty cycle to approach, for example, 50%, enabling high-precision duty cycle adjustment.

[0058] For example, Figure 4 A chart showing the relationship between the adjustment value and duty cycle of the adjusted data ADJ. Figure 4 For example, by using 5-bit adjustment data ADJ, a duty cycle adjustment of 50% ± 8% is performed in 32 stages, resulting in a duty cycle adjustment with a resolution of 0.4%.

[0059] Figure 5 This is a graph showing the angular simulation results of the duty cycle variation due to process changes without duty cycle adjustment by the first duty cycle adjustment circuit 50. Here, TYP represents the typical case. SF represents the case where the N-type transistor is slow and the P-type transistor is fast; FS represents the case where the N-type transistor is fast and the P-type transistor is slow; SS represents the case where both the N-type and P-type transistors are slow; and FF represents the case where both the N-type and P-type transistors are fast. (The last sentence appears to be a separate, unrelated statement.) Figure 5 As shown, due to variations in semiconductor manufacturing processes, the duty cycle varies within a range of approximately 50% ± 5%.

[0060] on the other hand, Figure 6 This is a graph showing the angular simulation results of the duty cycle variation under the condition that the duty cycle adjustment circuit 50 has been implemented. For example... Figure 6 As shown, the first duty cycle adjustment circuit 50 supplies a bias voltage VBS that is variably set according to the adjustment data ADJ, thereby enabling high-precision duty cycle adjustment, for example, to allow the duty cycle variation to be within a range of 50% ± 1%.

[0061] Figure 7 The circuit arrangement 120 of the first comparative example of this embodiment is shown. In the oscillation circuit 130 of the circuit arrangement 120 of the first comparative example, in addition to the capacitor CX1 between the first node N1 and the base node of the bipolar transistor TR, a capacitor CX2 is also provided between the second node N2 and the collector node of the bipolar transistor TR. Furthermore, one end of the variable capacitor element CV1 is connected to the first node N1, and the other end is connected to the supply node of the temperature compensation voltage VCMP. One end of the variable capacitor element CV2 is connected to the second node N2, and the other end is connected to the supply node of the temperature compensation voltage VCMP. In addition, a reference voltage VREFB is supplied to the node of the oscillation signal XI, i.e., the first node N1, and a reference voltage VREFC is supplied to the node of the oscillation signal XO, i.e., the second node N2. Thus, the oscillation signal XI becomes an oscillation signal that varies around the reference voltage VREFB, and the oscillation signal XO becomes an oscillation signal that varies around the reference voltage VREFC. The reference voltage VREFB is, for example, 0.4V, and the reference voltage VREFC is, for example, 1.2V.

[0062] Moreover, in Figure 7In the first comparative example, a DC cutoff capacitor CB is provided between the first node N1 and the input node of the waveform shaping circuit 140. As a result, the DC component of the oscillation signal XI is cut off, and the AC component is input to the waveform shaping circuit 140. Furthermore, the waveform shaping circuit 140 includes inverting circuits IVB1 and IVB2, with a feedback resistor RB provided between the output node and the input node of the primary inverting circuit IVB1. By providing such a feedback resistor RB, the primary inverting circuit IVB1 sets its bias point through self-biasing.

[0063] Thus, in Figure 7 In the first comparative example, a temperature-compensated reference voltage VREFB is applied to the node N1 of the oscillation signal XI, i.e., the first node. The oscillation signal XI then becomes an oscillation signal that varies around the reference voltage VREFB. Here, the reference voltage VREFB is adjusted, for example, to optimize the sensitivity of the variable capacitor element CV1, and is inconsistent with the threshold voltage of the primary inverting circuit IVB1 of the waveform shaping circuit 140. As an example, in the first comparative example, a power supply voltage of VREG = 1.5V is supplied to the inverting circuit IVB1, therefore the threshold voltage of the inverting circuit IVB1 is approximately VREG / 2 = 0.75V. On the other hand, the reference voltage VREFB is adjusted, for example, to VREFB = 0.4V, to optimize the sensitivity of the variable capacitor element CV1, therefore the threshold voltage of the inverting circuit IVB1 is inconsistent with the reference voltage VREFB, which is the center voltage of the oscillation signal XI. Furthermore, the reference voltage VREFB is adjusted based on manufacturing deviations of the varactor diode, which is a variable capacitor element, rather than on manufacturing deviations of the P-type and N-type transistors that constitute the inverting circuit IVB1.

[0064] Therefore, in Figure 7 In the first comparative example, a capacitor CB for DC cutoff needs to be set at the input node of the inverting circuit IVB1 to cut off the DC component of the oscillation signal XI, allowing only the AC component of the oscillation signal XI to be input to the inverting circuit IVB1. Furthermore, in the primary inverting circuit IVB1, its output and input nodes are connected via a feedback resistor RB, thereby adjusting the bias point through self-biasing. However, in this self-biasing-based bias point adjustment, when nonlinear distortion occurs in the waveform of the oscillation signal XI, the duty cycle of the clock signal CK changes, resulting in a problem where high precision of the duty cycle cannot be achieved. For example, in… Figure 7In the first comparative example, the actual duty cycle deviation was approximately 50% ± 4%, which is insufficient to achieve a high duty cycle precision of, for example, within 50% ± 1%. For example, in applications where an external processing unit processes output clock signals CKQ1 and CKQ2 obtained by buffering the clock signal CK, this processing unit uses both the rising and falling edges of the output clock signals CKQ1 and CKQ2. In such applications, proper processing cannot be performed with a duty cycle of approximately 50% ± 4%, therefore, a high duty cycle precision of within 50% ± 1% is sometimes required. Figure 7 The first comparative example cannot meet such a requirement.

[0065] Regarding this point, Figure 3 In the circuit device 20 of this embodiment, a DC cutoff capacitor CF1 is provided between the first node N1 of the oscillation signal XI and the variable capacitor element CV1. Furthermore, a DC cutoff capacitor CF2 is also provided between the second node N2 of the oscillation signal XO and the variable capacitor element CV2. Therefore, the bias voltage VBS can be set independently of the temperature compensation reference voltage VREF, and the oscillation signal XI can be made into an oscillation signal that varies around the bias voltage VBS.

[0066] For example, by adjusting the reference voltage VREF, the variable capacitor elements CV1 and CV2 can be adjusted to their optimal sensitivity. In this case, the capacitance of node 1 N1 becomes the series capacitance of variable capacitor element CV1 and capacitor CF1, and the capacitance of node 2 N2 becomes the series capacitance of variable capacitor element CV2 and capacitor CF2. However, by making the capacitances of capacitors CF1 and CF2 sufficiently large, the capacitances of node 1 N1 and node 2 N2 can be adjusted to appropriate capacitances corresponding to the ambient temperature using variable capacitor elements CV1 and CV2.

[0067] Furthermore, in this embodiment, the bias voltage VBS can be adjusted using the adjustment data ADJ and through the first duty cycle adjustment circuit 50 to a suitable voltage that makes the duty cycle of the clock signal CK close to 50%, independent of the reference voltage VREF.

[0068] For example, suppose that due to process variations such as the threshold voltage of P-type or N-type transistors, Figure 3The threshold voltage of the primary inverter circuit IVA1 in the waveform shaping circuit 40 becomes lower than half the voltage of VREG2, which is the power supply voltage. For example, when there is a process variation such as N-type transistors becoming faster and P-type transistors becoming slower, the threshold voltage of the inverter circuit IVA1 becomes lower than half the voltage of VREG2. In this case, when the bias voltage VBS is always half the voltage of VREG2, the duty cycle of the clock signal CK will be greater than 50%. In this case, in this embodiment, the first duty cycle adjustment circuit 50 also sets the bias voltage VBS to be lower than half the voltage of VREG2 according to the adjustment data ADJ. In this way, even when the threshold voltage of the inverter circuit IVA1 becomes low due to process variation, the bias voltage VBS, which is the center voltage of the oscillation signal XI, also becomes low, so the duty cycle of the clock signal CK can be made close to 50%. Therefore, high-precision duty cycle adjustment with a duty cycle variation within 50% ± 1% can be achieved.

[0069] On the other hand, suppose that due to process variations such as the threshold voltages of P-type and N-type transistors, the threshold voltage of the primary inverter circuit IVA1 of the waveform shaping circuit 40 becomes higher than half the voltage of VREG2. For example, when there is a process variation such as P-type transistors becoming faster and N-type transistors becoming slower, the threshold voltage of the inverter circuit IVA1 becomes higher than half the voltage of VREG2. In this case, when the bias voltage VBS is always half the voltage of VREG2, the duty cycle of the clock signal CK will be less than 50%. In this case, in this embodiment, the first duty cycle adjustment circuit 50 also sets the bias voltage VBS to be higher than half the voltage of VREG2 according to the adjustment data ADJ. In this way, even if the threshold voltage of the inverter circuit IVA1 becomes high due to process variations, the bias voltage VBS, which is the center voltage of the oscillation signal XI, also becomes higher, and thus, the duty cycle of the clock signal CK can be made close to 50%. Therefore, it can achieve high-precision duty cycle adjustment with a duty cycle variation within 50% ± 1%.

[0070] In addition, Figure 3 In the middle, since it is not necessary to set it Figure 7 The DC cutoff capacitor CB provided in the first comparative example can suppress the attenuation of the oscillation amplitude caused by the voltage division between the DC cutoff capacitor CB and the input capacitor, thus achieving low noise floor. Furthermore, since it is not necessary to... Figure 7 The feedback resistor RB shown can thus prevent abnormal oscillations caused by the feedback resistor RB.

[0071] Figure 8The circuit arrangement 220 of the second comparative example of this embodiment is shown. This second comparative example circuit arrangement 220 includes an oscillation circuit 230, a waveform shaping circuit 240, a bias circuit 250, and a constant current circuit 260. In this second comparative example, the bias circuit 250 is a replica of the waveform shaping circuit 240, and the bias voltage output by the bias circuit 250 depends on the supplied power supply voltage VDD. For example, the bias circuit 250 outputs a bias voltage of approximately half of VDD. However, the duty cycle of the clock signal CK varies not only due to a deviation of approximately ±0.1V in the threshold voltage of the P-type or N-type transistor in the primary inverter circuit, but also due to subsequent circuitry and distortion of the oscillation waveform. Therefore, in Figure 8 In the second comparative example, the following problem exists: it is impossible to achieve high-precision duty cycle adjustment that takes into account all these varying factors. Additionally, in Figure 8 In the second comparative example, the bias circuit 250 only outputs a bias voltage of about 1 / 2 of VDD, and there is no adjustment circuit that adjusts the bias voltage based on the adjustment data.

[0072] Regarding this, in the circuit device 20 of this embodiment, the bias voltage VBS can be variably adjusted according to the adjustment data ADJ. That is, a first duty cycle adjustment circuit 50 is provided to adjust the bias voltage VBS according to the adjustment data ADJ. Therefore, in addition to, for example Figure 3 In addition to considering deviations such as the threshold voltage of the P-type or N-type transistor in the primary inverter circuit IVA1, the bias voltage VBS can also be adjusted by taking into account deviations in the duty cycle of subsequent circuits and distortion of the oscillation waveform, thereby adjusting the duty cycle of the clock signal CK. Figure 8 Compared to the second comparative example, it can achieve high-precision duty cycle adjustment.

[0073] For example, the circuit device 20 of this embodiment includes a non-volatile memory 62 that stores adjustment data ADJ, and a first duty cycle adjustment circuit 50 that generates a bias voltage VBS set according to the adjustment data ADJ stored in the non-volatile memory 62. For example, when the adjustment data ADJ stored in the non-volatile memory 62 is a first adjustment value, the first duty cycle adjustment circuit 50 generates a bias voltage VBS corresponding to a first voltage value corresponding to the first adjustment value, and when the adjustment data ADJ is a second adjustment value, it generates a bias voltage VBS corresponding to a second voltage value corresponding to the second adjustment value. Thus, by storing the adjustment data ADJ, which enables the setting of the optimal duty cycle, in the non-volatile memory 62, and supplying the bias voltage VBS corresponding to the adjustment data ADJ read from the non-volatile memory 62 by the first duty cycle adjustment circuit 50 during actual operation of the circuit device 20, a high-precision duty cycle adjustment of, for example, 50% ± 1% can be achieved. Specifically, during the inspection process such as manufacturing the circuit device 20, the duty cycle of the output clock signal CKQ is measured, and adjustment data ADJ is determined based on the measurement results and written into the non-volatile memory 62. For example, the adjustment data ADJ is determined not only considering deviations such as transistor threshold voltage caused by process variations, but also considering nonlinear distortion of the oscillation waveform. Moreover, during the actual operation of the circuit device 20, by reading the adjustment data ADJ determined based on the measurement results from the non-volatile memory 62 and supplying a bias voltage VBS corresponding to the adjustment data ADJ by the first duty cycle adjustment circuit 50, a high-precision duty cycle adjustment, such as within 50% ± 1%, can be achieved.

[0074] Furthermore, in this embodiment... Figure 3 The power supply voltage of the oscillation circuit 30, i.e., VRG1, becomes a voltage greater than or equal to the power supply voltage of the waveform shaping circuit 40, i.e., VREG2. That is, the relationship VREG1 ≥ VREG2 holds. As an example, VRG1 is 1.2V and VREG2 is 1V.

[0075] On the other hand, Figure 8 In the second comparative example, VREG, the power supply voltage of the oscillation circuit 230, is 1.2V, and VDD, the power supply voltage of the waveform shaping circuit 240 or the bias circuit 250, is 1.8 to 5V, thus the relationship VREG < VDD holds. Therefore, the amplitude voltage of the oscillation signal XI input to the waveform shaping circuit 240 is less than the power supply voltage VDD of the waveform shaping circuit 240, and the rising and falling waveforms of the output signal of the primary inverter circuit of the waveform shaping circuit 240 do not become steep, but become gentle waveforms. Moreover, when the output signal of the primary inverter circuit becomes a gentle waveform, the duty cycle will change due to deviations in the threshold voltages of the P-type or N-type transistors in the next stage inverter circuit.

[0076] In contrast, in this embodiment, VRG1, which serves as the power supply voltage for the oscillation circuit 30, becomes a voltage higher than or equal to VREG2, which serves as the power supply voltage for the waveform shaping circuit 40. Therefore, the amplitude of the oscillation signal XI input to the waveform shaping circuit 40 can be maximized within the driving voltage range of the waveform shaping circuit 40. That is, within the driving voltage range of the waveform shaping circuit 40 set by VREG2, a full-swing oscillation signal XI can be input to the primary inverter circuit IVA1 of the waveform shaping circuit 40. Therefore, the period during which both the P-type and N-type transistors of the primary inverter circuit IVA1 are turned on almost disappears, resulting in steeper rising and falling waveforms of the output signal of the inverter circuit IVA1. As a result, duty cycle deviation caused by deviations in the threshold voltages of the P-type or N-type transistors of the next-stage inverter circuit IVA2 can be reduced. Furthermore, AM noise caused by amplitude fluctuations in the oscillation signal XI is converted into PM noise, which is phase noise, through waveform shaping by the waveform shaping circuit 40. Regarding this point, if VREG1 is set to ≥ VREG2 as in this embodiment, and the amplitude of the oscillation signal XI is increased as much as possible within the driving voltage range of the waveform shaping circuit 40, the degree of conversion from AM noise to PM noise can be reduced, thereby improving the signal quality of the clock signal CK. Furthermore, the waveform shaping circuit 40 and the subsequent output buffer circuit 70 operate with the same VREG2 power supply voltage, but by making the power supply voltage of VREG2 lower than the power supply voltage of the oscillation circuit 30, i.e., VREG1, the power consumption in the output buffer circuit 70 can be reduced. For example, the output buffer circuit 70 consumes more power than other circuit modules because it drives a large external load, but by setting VREG2 to a voltage lower than VREG1, power consumption can be reduced accordingly.

[0077] In addition, such as Figure 3 As shown, in this embodiment, the oscillation circuit 30 includes: a fixed-capacitance capacitor CF1, one end of which is connected to the first node N1, and the capacitance value is fixed; and a variable-capacitance element CV1, one end of which is connected to the other end of the fixed-capacitance capacitor CF1, and the capacitance value is variable. Furthermore, a temperature compensation voltage VCMP is input to one end and the other end of the variable-capacitance element CV1, and a reference voltage VREF is input to the other end. For example, in... Figure 3In this configuration, a temperature compensation voltage VCMP is input to one end of the variable capacitor element CV1, and a reference voltage VREF is input to the other end. Alternatively, the temperature compensation voltage VCMP can be input to the other end of the variable capacitor element CV1, which serves as the ground node, and the reference voltage VREF can be input to one end of the variable capacitor element CV1, which serves as the capacitor CF1. Furthermore, the variable capacitor element CV2 has the same connection structure as the variable capacitor element CV1; detailed explanation is omitted here.

[0078] Based on this structure, a voltage corresponding to the voltage difference between the temperature compensation voltage VCMP and the reference voltage VREF can be applied to the variable capacitor element CV1. By changing the capacitance value of the variable capacitor element CV1 using the temperature compensation voltage VCMP referenced to the reference voltage VREF, temperature compensation of the oscillation frequency of the oscillation circuit 30 can be achieved. Furthermore, by setting a capacitor CF1 with a fixed capacitance, the bias voltage VBS and the reference voltage VREF can be adjusted independently. That is, while adjusting the duty cycle by changing the bias voltage VBS, the reference voltage VREF of the variable capacitor element CV1, such as the varactor diode, can also be adjusted independently. For example, while adjusting the duty cycle of the bias voltage VBS by changing the duty cycle of the clock signal CK to approximately 50%, the reference voltage VREF can be adjusted to ensure that the potential difference across the variable capacitor element CV1 is greater than 0V and the sensitivity is optimal.

[0079] Furthermore, in this embodiment, the first duty cycle adjustment circuit 50 outputs a bias voltage to the first node N1 and outputs a reference voltage VREF to the other end of one and the other ends of the variable capacitor element CV1. For example, in Figure 3 In this circuit, a temperature compensation voltage VCMP is input to one end of the variable capacitor element CV1, and the first duty cycle adjustment circuit 50 outputs a reference voltage VREF to the other end of the variable capacitor element CV1. Alternatively, the temperature compensation voltage VCMP can be input to the other end of the variable capacitor element CV1, and the first duty cycle adjustment circuit 50 can output a reference voltage VREF to one end of the variable capacitor element CV1.

[0080] With this structure, a first duty cycle adjustment circuit 50 can be used to supply a bias voltage VBS to adjust the duty cycle of the clock signal CK, and a reference voltage VREF for temperature compensation can also be supplied to achieve temperature compensation of the oscillation frequency. In other words, the first duty cycle adjustment circuit 50, which supplies the reference voltage VREF for temperature compensation, can effectively utilize the first duty cycle adjustment circuit 50 to supply the bias voltage VBS, thereby adjusting the duty cycle. This enables circuit commonality and miniaturization of the circuit device 20, and also achieves low power consumption of the circuit device 20.

[0081] Specifically, as will be discussed later. Figure 21 As detailed in the description, the first duty cycle adjustment circuit 50 includes: a voltage divider circuit 52 having multiple resistors connected in series between the power supply node and the ground node, outputting multiple divided voltages obtained by dividing the voltages through the multiple resistors; and a selection circuit 54 that selects any one of the multiple divided voltages as the bias voltage VBS. That is, the voltage divider circuit 52 is implemented using a trapezoidal resistor circuit, and the selection circuit 54 selects the bias voltage VBS from the multiple divided voltages generated by the voltage divider circuit 52 (which is a trapezoidal resistor circuit) according to the input adjustment data ADJ, and supplies it to the first node N1. With this structure, for example, multiple divided voltages are generated between the power supply voltage of VREG1 and GND by the voltage divider circuit 52, and the voltage corresponding to the adjustment data ADJ is selected from the generated multiple divided voltages, thereby generating the bias voltage VBS as the center voltage of the oscillation signal XI.

[0082] Furthermore, in this embodiment, the selection circuit 54 selects a first voltage divider, which is any one of the multiple voltage dividers from the voltage divider circuit 52, as the bias voltage VBS, and selects a second voltage divider, which is any one of the multiple voltage dividers, as the reference voltage VREF. Thus, by supplying the first voltage divider selected by the selection circuit 54 from the multiple voltage dividers as the bias voltage VBS to the first node N1, the duty cycle of the clock signal CK can be adjusted. Moreover, by supplying the second voltage divider selected by the selection circuit 54 from the multiple voltage dividers as the reference voltage VREF, the variable capacitor element CV1 operates within an appropriate sensitivity range, thereby achieving temperature compensation of the oscillation frequency. Furthermore, to generate the bias voltage VBS and the reference voltage VREF, only one trapezoidal resistor circuit is needed as the voltage divider circuit 52. Therefore, compared to the case where a first trapezoidal resistor circuit for the bias voltage and a second trapezoidal resistor circuit for the reference voltage are provided, the circuit area of ​​the circuit device 20 can be reduced. Furthermore, compared to the case where a first trapezoidal resistor circuit and a second trapezoidal resistor circuit are provided, the current flowing from the power node to the ground node can be set to, for example, about 1 / 2, thus enabling the circuit device 20 to achieve low power consumption.

[0083] 3. Second duty cycle adjustment circuit

[0084] In recent years, communication terminals have become increasingly complex. For oscillators such as quartz oscillators, there is a demand for multi-output functions that distribute clock signals to chipsets for baseband processing, RF / GPS, WLAN, and Bluetooth (registered trademark). Processing speeds are also trending towards higher speeds, for example, requiring strict performance such as a duty cycle accuracy of RF clock signals within 50% ± 1%. Regarding this, Patent Document 1 discloses a method that involves staggering the input waveforms of an inverting circuit to maintain the voltage of the input signal and correcting the duty cycle of the output signal. However, in the method of Patent Document 1, it is difficult to adjust the delay time between the input signal and the staggered input signal. When attempting to achieve the aforementioned multi-output function, the duty cycle deviates due to subsequent circuitry, resulting in a problem in achieving high duty cycle accuracy.

[0085] As in Figure 1 , Figure 2 As explained in the text, the circuit device 20 of this embodiment, which solves such problems, includes: an oscillation circuit 30 that generates oscillation signals XI and XO; a waveform shaping circuit 40 that outputs a clock signal CK obtained by shaping the waveform of the oscillation signal XI; and a first duty cycle adjustment circuit 50 that adjusts the duty cycle of the clock signal CK. Furthermore, the circuit device 20 includes an output buffer circuit 70 that outputs clock signals CKQ1 and CKQ2 to the outside based on the clock signal CK, and the output buffer circuit 70 includes a second duty cycle adjustment circuit 80 that adjusts the duty cycle of the output clock signal CKQ2.

[0086] Thus, the output buffer circuit 70 outputs multiple output clock signals CKQ1 and CKQ2 based on the clock signal CK, thereby responding to the multi-output function requirements of the clock signal. In this case, the first duty cycle adjustment circuit 50 adjusts the duty cycle of the clock signal CK, thereby achieving high precision in the duty cycle of the clock signal CK. However, when the output buffer circuit 70 buffers the clock signal CK after duty cycle adjustment and outputs the output clock signals CKQ1 and CKQ2 to achieve the multi-output function, the duty cycle precision becomes insufficient, and it may not meet the duty cycle precision requirements of the circuit device 20.

[0087] Therefore, in this embodiment, a second duty cycle adjustment circuit 80 for adjusting the duty cycle of the output clock signal CKQ2 is provided in the output buffer circuit 70 that outputs the output clock signals CKQ1 and CKQ2 according to the clock signal CK. This allows for two-stage duty cycle adjustment, where the first duty cycle adjustment circuit 50 adjusts the duty cycle and the second duty cycle adjustment circuit 80 adjusts the duty cycle. For example, suppose that the output clock signal CKQ1 meets the duty cycle accuracy requirements after the duty cycle adjustment by the first duty cycle adjustment circuit, but the output clock signal CKQ2 does not meet the duty cycle accuracy requirements. For example, this situation occurs when the output clock signal CKQ2, which is the second output clock signal, is a signal with a different phase than the output clock signal CKQ1, which is the first output clock signal. In such a case, the duty cycle adjustment performed by the second duty cycle adjustment circuit 80 provided in the output buffer circuit 70 can also make the output clock signal CKQ2 meet the duty cycle accuracy requirements. Therefore, the output buffer circuit 70 can output multiple output clock signals CKQ1 and CKQ2 that meet the duty cycle accuracy requirements of, for example, 50% ± 1%, thereby enabling the simultaneous realization of multiple clock signal output functions and high-precision duty cycle adjustment.

[0088] For example, Figure 9 This is an example of the structure of the circuit device 20, which explains the details of the second duty cycle adjustment circuit 80. For example... Figure 9 As shown, the first duty cycle adjustment circuit 50 adjusts the duty cycle of the clock signal CK by supplying a bias voltage VBS, which is variably adjusted according to the adjustment data ADJ, to the first node N1. Thus, the clock signal CK with a highly accurate duty cycle adjustment is input from the waveform shaping circuit 40 to the output buffer circuit 70. Then, the output buffer circuit 70 outputs output clock signals CKQ1 and CKQ2 based on the clock signal CK with its duty cycle adjusted by the first duty cycle adjustment circuit 50.

[0089] At this time, for example, if the duty cycle of the output clock signal CKQ1 is measured as described above and the adjustment data ADJ is determined based on the measurement result, the first duty cycle adjustment circuit 50 adjusts the duty cycle based on the adjustment data ADJ, thereby enabling the output clock signal CKQ1 to meet the required duty cycle accuracy specifications. However, the output clock signal CKQ2 may have a different phase than the output clock signal CKQ1, for example. Figure 9The phase difference between the two clock signals is 180 degrees. Therefore, even if the duty cycle of the output clock signal CKQ1 is precisely adjusted to meet the required specifications, the duty cycle of the output clock signal CKQ2 may not meet the required accuracy. For example, when the output clock signal CKQ2 is an inverted clock signal with a phase difference of 180 degrees from CKQ1, an inverting circuit is required to reverse the signal level. In this case, when there is an imbalance between the driving capabilities of the P-type transistor and the N-type transistor constituting the inverting circuit, the duty cycle of the output clock signal CKQ2 will deviate. For example, when the N-type transistor and P-type transistor are slow and fast SF respectively, or when the N-type transistor and P-type transistor are fast and slow FS respectively, the above situation will occur, making it impossible to achieve high-precision duty cycle of the output clock signal CKQ2.

[0090] In this embodiment, a second duty cycle adjustment circuit 80 is provided in the output buffer circuit 70. This second duty cycle adjustment circuit 80 adjusts the duty cycle of the output clock signal CKQ2. For example, the duty cycle of the output clock signal CKQ2 is measured, and adjustment data ADJ2 is determined based on the measurement result. The second duty cycle adjustment circuit 80 adjusts the duty cycle of the output clock signal CKQ2 based on this adjustment data ADJ2. Thus, not only the output clock signal CKQ1 but also the output clock signal CKQ2 are adjusted with high precision and output to the outside. Therefore, multiple clock signal output functions and high-precision duty cycle adjustment can be achieved simultaneously.

[0091] Specifically, in Figure 9 In this circuit, the output buffer circuit 70 includes a first buffer circuit 72 and a second buffer circuit 74. The first buffer circuit 72 buffers the clock signal CK and outputs it as the output clock signal CKQ1. For example, the first buffer circuit 72 has a buffer circuit BF1, which buffers the clock signal CK and outputs the signal obtained by buffering the clock signal CK through the buffer circuit BF1 as the output clock signal CKQ1. In this case, the output clock signal CKQ1 is the positive phase signal of the clock signal CK, and the output clock signal CKQ1 is a clock signal with the same phase as the clock signal CK. Furthermore, the buffer circuit BF1 can be implemented, for example, by using multiple inverting circuits. The buffer circuit BF1 has a high driving capability to drive external loads, for example, a higher driving capability than the waveform shaping circuit 40. Specifically, the buffer circuit BF1 is composed of P-type transistors and N-type transistors that are larger in size than the waveform shaping circuit 40.

[0092] On the other hand, the second buffer circuit 74 has a second duty cycle adjustment circuit 80, which buffers the clock signal CK and outputs an output clock signal CKQ2 with the duty cycle adjusted by the second duty cycle adjustment circuit 80. For example, the clock signal CK from the waveform shaping circuit 40 is input to the second duty cycle adjustment circuit 80, which inverts the signal level of the clock signal CK and adjusts the duty cycle. Moreover, the output signal of the second duty cycle adjustment circuit 80 is buffered by the buffer circuit BF2 and output as the output clock signal CKQ2. In this case, the output clock signal CKQ2 is the inverted signal of the clock signal CK, and the output clock signal CKQ2 is a clock signal with a phase different from the output clock signals CKQ1 and CK. Specifically, the output clock signal CKQ2 is 180 degrees out of phase with the output clock signals CKQ1 and CK. Furthermore, the buffer circuit BF2 can be implemented, for example, by multiple inverting circuits. The buffer circuit BF2 has a high driving capability to drive external loads, for example, a higher driving capability than the second duty cycle adjustment circuit 80 and the waveform shaping circuit 40. Specifically, the buffer circuit BF2 is composed of P-type transistors and N-type transistors that are larger in size compared to the second duty cycle adjustment circuit 80 and the waveform shaping circuit 40.

[0093] Thus, in Figure 9 In the first signal path branching from the intermediate node of the output buffer circuit 70, the clock signal CK is buffered by the first buffer circuit 72 and output as the output clock signal CKQ1. Furthermore, in the second signal path branching from this intermediate node, the clock signal CK is buffered by the second buffer circuit 74, causing the signal level to be inverted and the duty cycle adjusted, and then output as the output clock signal CKQ2. By providing such first buffer circuit 72 and second buffer circuit 74 in the output buffer circuit 70, the buffered clock signal CK can be output as the output clock signal CKQ1, and the buffered clock signal CK with its duty cycle adjusted by the second duty cycle adjustment circuit 80 can be output as the output clock signal CKQ2. Therefore, multiple output clock signals CKQ1 and CKQ2 with high-precision duty cycle adjustment can be output to the outside, simultaneously realizing multi-output clock signals and high-precision duty cycle adjustment.

[0094] Furthermore, in this embodiment, the output clock signals CKQ1 and CKQ2 are clock signals with a phase difference of 180 degrees. For example, the output clock signal CKQ1 is the positive phase signal of the clock signal CK, with the same phase as the clock signal CK, while the output clock signal CKQ2 is the inverted phase signal of the clock signal CK, with a phase difference of 180 degrees from both the clock signal CK and the output clock signal CKQ1. This allows for the output of both the output clock signal CKQ1 and the output clock signal CKQ2 (with a phase difference of 180 degrees) to the outside, achieving a multi-output function. It also allows for the output of multiple output clock signals CKQ1 and CKQ2 with highly precise duty cycle adjustments. Therefore, when the circuit device 20 requires not only an output clock signal CKQ1 with the same phase as the clock signal CK, but also a clock signal with a phase difference of 180 degrees from the output clock signal CKQ1, these output clock signals CKQ1 and CKQ2 with highly precise duty cycle adjustments can be supplied to the outside according to this requirement.

[0095] In addition, Figure 9 In this embodiment, the output clock signals CKQ1 and CKQ2 are 180 degrees out of phase, but this embodiment is not limited to this; for example, various modifications can be implemented, such as making the phase difference 90 degrees. Furthermore, in Figure 9 In the output buffer circuit 70, two output clock signals CKQ1 and CKQ2 are output, but the output buffer circuit 70 can also output more than three output clock signals.

[0096] In addition, such as Figure 9As shown, the first duty cycle adjustment circuit 50 adjusts the duty cycle of the clock signal CK based on the adjustment data ADJ stored in the non-volatile memory 62, and the second duty cycle adjustment circuit 80 adjusts the duty cycle of the output clock signal CKQ2 based on the adjustment data ADJ2 stored in the non-volatile memory 62. Specifically, during the inspection process such as manufacturing the circuit device 20, the duty cycle of the output clock signal CKQ1 is measured, and the adjustment data ADJ is determined based on the measurement result. Furthermore, the duty cycle of the output clock signal CKQ2 is measured, and the adjustment data ADJ2 is determined based on the measurement result. Then, the determined adjustment data ADJ and ADJ2 are written into the non-volatile memory 62. Furthermore, during the actual operation of the circuit device 20, adjustment data ADJ and ADJ2 determined based on the measurement results are read from the non-volatile memory 62. The first duty cycle adjustment circuit 50 performs duty cycle adjustment based on the adjustment data ADJ, and the second duty cycle adjustment circuit 80 performs duty cycle adjustment based on the adjustment data ADJ2. For example, in the second duty cycle adjustment circuit 80, the ratio of the driving capability of the P-type transistor to the driving capability of the N-type transistor in the inverting circuit constituting the second duty cycle adjustment circuit 80 is adjusted according to the adjustment data ADJ2. The ratio adjustment of the driving capability can be achieved by adjusting the ratio of the size of the P-type transistor to the size of the N-type transistor in the inverting circuit, etc. As a result, output clock signals CKQ1 and CKQ2 with high-precision duty cycle adjustment within 50% ± 1% can be output to the outside.

[0097] For example, Figure 10 , Figure 11 A chart showing the relationship between the adjustment values ​​of ADJ and ADJ2 and the duty cycle. Figure 10 In the first level of duty cycle adjustment shown, for example, based on the adjustment data ADJ, a duty cycle adjustment is performed such that 50% ± 8% is divided into 32 levels using 5 bits, resulting in a duty cycle adjustment with a resolution of 0.4%. Figure 11 In the second-level duty cycle adjustment shown, for example, based on the adjustment data ADJ2, a duty cycle adjustment is performed such that 50% ± 4% is divided into 32 levels using 5 bits, resulting in a duty cycle adjustment with a resolution of 0.2%. Thus, in this embodiment, the resolution of the duty cycle adjustment by the second duty cycle adjustment circuit 80 becomes equal to or higher than the resolution of the duty cycle adjustment by the first duty cycle adjustment circuit 50. Furthermore, through... Figure 10 The duty cycle adjustment of the first duty cycle adjustment circuit 50 shown is as follows: Figure 11As shown, the duty cycle adjustment for the output clock signal CKQ1 is performed with a high precision within 50% ± 1%. However, for the output clock signal CKQ2, which has a different phase from CKQ1, the precision of the duty cycle adjustment becomes insufficient. Therefore, the duty cycle is adjusted by the second duty cycle adjustment circuit 80, thereby achieving a high precision duty cycle adjustment of within 50% ± 1% for the output clock signal CKQ2 as well.

[0098] Figure 12 This is the angular simulation result of the process variation of the duty cycle of the output clock signals CKQ1 and CKQ2 without duty cycle adjustment based on the first duty cycle adjustment circuit 50 and the second duty cycle adjustment circuit 80. For example... Figure 12 As shown, in the SF circuit where the N-type transistor is slow and the P-type transistor is fast, the output clock signal CKQ1 shifts towards the side with a duty cycle less than 50%, and the output clock signal CKQ2 shifts towards the side with a duty cycle greater than 50%. In the FS circuit where the N-type transistor is fast and the P-type transistor is slow, the output clock signal CKQ1 shifts towards the side with a duty cycle greater than 50%, and the output clock signal CKQ2 shifts towards the side with a duty cycle less than 50%.

[0099] Figure 13 This is an angular simulation result of the process variation of the duty cycle of the output clock signals CKQ1 and CKQ2 under the condition of duty cycle adjustment based on the first duty cycle adjustment circuit 50. For example... Figure 13 As shown, for the output clock signal CKQ1, a high-precision duty cycle adjustment within 50% ± 1% is achieved. However, for the output clock signal CKQ2, whose phase is different from that of the output clock signal CKQ1, the duty cycle exceeds the range of 50% ± 1%. That is, for the output clock signal CKQ2, the high-precision duty cycle adjustment achieved solely through the first duty cycle adjustment circuit 50 is still insufficient.

[0100] Figure 14 This is a simulation result of the process variation in the duty cycle of the output clock signals CKQ1 and CKQ2 under the condition that the duty cycle of both the first duty cycle adjustment circuit 50 and the second duty cycle adjustment circuit 80 has been adjusted. For example... Figure 14 As shown, by adjusting the duty cycle of both the first duty cycle adjustment circuit 50 and the second duty cycle adjustment circuit 80, high-precision duty cycle adjustment within 50% ± 1% is achieved for the output clock signals CKQ1 and CKQ2. Thus, according to this embodiment, both multi-output clock signal functionality and high-precision duty cycle adjustment can be simultaneously realized.

[0101] Figure 15 An example of the structure of the second duty cycle adjustment circuit 80 is shown. Figure 15In this circuit, the second duty cycle adjustment circuit 80 includes a reference inverting circuit 82 and a duty cycle adjustment inverting circuit 84 connected in parallel. The reference inverting circuit 82 outputs a buffered clock signal CK to the output node NQ. The reference inverting circuit 82 is, for example, an inverting circuit that operates continuously, outputting a signal that inverts the signal level of the clock signal CK input to the input node NQ. The duty cycle adjustment inverting circuit 84 is connected in parallel with the reference inverting circuit 82, and outputs a buffered clock signal CK to the output node NQ. The duty cycle adjustment inverting circuit 84, for example, sets the driving capability of the P-type transistor or the N-type transistor according to the adjustment data ADJ2, and outputs a signal that inverts the signal level of the clock signal CK input to the input node NQ. Furthermore, a buffer circuit BF2, located after the second duty cycle adjustment circuit 80, buffers the signal output to the output node and outputs it as the output clock signal CKQ2. Thus, for example, by connecting a duty cycle adjustment inverting circuit 84 in parallel to a reference inverting circuit 82 that always operates after the power is turned on, the clock signal CK is buffered, and the duty cycle of the output clock signal CKQ2 can be adjusted by the duty cycle adjustment inverting circuit 84.

[0102] For example, the reference inverting circuit 82 is the main inverting circuit of the second duty cycle adjustment circuit 80. Furthermore, as... Figure 9 As shown, by setting a reference inverting circuit 82 of the second duty cycle adjustment circuit 80 on the second signal path of the first signal path branch of the output clock signal CKQ1, and the reference inverting circuit 82 reverses the signal level of the clock signal CK, it is possible to output an output clock signal CKQ2 with a phase difference of 180 degrees from the output clock signal CKQ1.

[0103] In this situation, an imbalance may sometimes occur between the driving capabilities of the P-type transistors and the N-type transistors constituting the reference inverting circuit 82, caused by variations in manufacturing processes. For example, in the case of an SF circuit where the N-type transistor is slow and the P-type transistor is fast, an imbalance may occur where the driving capability of the N-type transistor is lower than that of the P-type transistor. In the case of an FS circuit where the N-type transistor is fast and the P-type transistor is slow, an imbalance may occur where the driving capability of the P-type transistor is lower than that of the N-type transistor. Moreover, when such a driving capability imbalance occurs, the duty cycle of the output clock signal CKQ2 generated by the signal inversion of the reference inverting circuit 82 will change.

[0104] Therefore, in Figure 15The circuit includes a duty cycle adjustment inverter circuit 84 connected in parallel with the main reference inverter circuit 82. The input of the duty cycle adjustment inverter circuit 84 and the reference inverter circuit 82 are connected to a common input node NI, and its output and the reference inverter circuit 82 are connected to a common output node NQ. Furthermore, in the duty cycle adjustment inverter circuit 84, the drive capability of the P-type transistors and the drive capability of the N-type transistors constituting the duty cycle adjustment inverter circuit 84 can be variably adjusted according to the adjustment data ADJ2. For example, the ratio information of the drive capability can be variably adjusted.

[0105] For example, suppose that due to a process variation where N-type transistors are slower and P-type transistors are faster, an imbalance occurs where the driving capability of the N-type transistor in the reference inverter circuit 82 is lower than that of the P-type transistor. In this case, an adjustment is made according to the adjustment data ADJ2 to increase the driving capability of the N-type transistor side of the duty cycle adjustment inverter circuit 84. On the other hand, suppose that due to a process variation where N-type transistors are faster and P-type transistors are slower, an imbalance occurs where the driving capability of the P-type transistor in the reference inverter circuit 82 is lower than that of the N-type transistor. In this case, an adjustment is made according to the adjustment data ADJ2 to increase the driving capability of the P-type transistor side of the duty cycle adjustment inverter circuit 84. In this way, the second duty cycle adjustment circuit 80 can adjust the driving capability of the P-type transistor side of the reference inverter circuit 84. Figure 13 As shown, the duty cycle of the insufficiently high-precision output clock signal CKQ2 can be precisely adjusted solely through the first duty cycle adjustment circuit 50, thereby enabling... Figure 14 As shown, this achieves a high-precision duty cycle adjustment within 50% ± 1%.

[0106] In addition, Figure 15In this circuit, the dimensions of the P-type transistor and N-type transistor constituting the duty cycle adjustment inverting circuit 84 are each less than half the dimensions of the P-type transistor and N-type transistor constituting the reference inverting circuit 82. For example, the size of the P-type transistor constituting the duty cycle adjustment inverting circuit 84 is less than half the size of the P-type transistor constituting the reference inverting circuit 82, and the size of the N-type transistor constituting the duty cycle adjustment inverting circuit 84 is less than half the size of the N-type transistor constituting the reference inverting circuit 82. Here, when the gate width of the transistor is set to W and the gate length is set to L, the size of the transistor can be expressed as W / L, for example. For example, when the gate lengths L of the two transistors are the same, the size of the transistor can also be expressed by the gate width W. In this way, by setting the size of the transistor in the duty cycle adjustment inverter circuit 84 to less than half the size of the transistor in the reference inverter circuit 82, the drive capability of the P-type transistor or N-type transistor in the reference inverter circuit 82 can be used as a reference, and the drive capability of the P-type transistor side and the N-type transistor side can be adjusted by the duty cycle adjustment inverter circuit 84 according to the adjustment data ADJ2. Therefore, even in the event of process variations such as an imbalance in the drive capabilities of the P-type transistor and the N-type transistor, the duty cycle variation of the output clock signal CKQ2 can be suppressed, thereby achieving high-precision duty cycle adjustment. Furthermore, hereafter, the drive capability of the P-type transistor side will be appropriately described as the P-side drive capability, and the drive capability of the N-type transistor side will be appropriately described as the N-side drive capability.

[0107] In addition, such as Figure 16 As shown, the second duty cycle adjustment circuit 80 includes a first duty cycle adjustment inverter circuit 84-1 and a second duty cycle adjustment inverter circuit 84-2. The first duty cycle adjustment inverter circuit 84-1 is connected in parallel with the reference inverter circuit 82, and outputs a buffered clock signal CK to the output node NQ. The second duty cycle adjustment inverter circuit 84-2 is also connected in parallel with the reference inverter circuit 82, and outputs a buffered clock signal CK to the output node NQ. Furthermore, the size of each of the P-type transistor and N-type transistor constituting the second duty cycle adjustment inverter circuit 84-2 is twice the size of each of the P-type transistor and N-type transistor constituting the first duty cycle adjustment inverter circuit 84-1. In this way, the following adjustments can be made: based on the adjustment data ADJ2, the driving capabilities of the P-side and N-side of the first duty cycle adjustment inverting circuit 84-1 and the driving capabilities of the P-side and N-side of the second duty cycle adjustment inverting circuit 84-2 are binary-weighted and added to the driving capabilities of the P-side and N-side of the reference inverting circuit 82. Therefore, higher resolution duty cycle adjustments can be performed, achieving high precision in duty cycle adjustment.

[0108] Furthermore, the adjustment of the driving capability of the P-side and N-side of the first duty cycle adjustment inverting circuit 84-1 and the second duty cycle adjustment inverting circuit 84-2 is an adjustment that increases the driving capability of the P-type transistor side and an adjustment that increases the driving capability of the N-type transistor side. For example, when each bit of the data ADJ2 is, for example, a low level or a first logic level, the adjustment increases the driving capability of the P-type transistor side, while when it is a high level or a second logic level, the adjustment increases the driving capability of the N-type transistor side.

[0109] Furthermore, in Figure 16 In the circuit, the second duty cycle adjustment circuit 80 includes: a first duty cycle adjustment inverter circuit 84-1; and second to nth duty cycle adjustment inverter circuits 84-2 to 84-n, which are connected in parallel with the reference inverter circuit 82, and output the buffered clock signal CK to the output node NQ. Furthermore, as in... Figure 17 As detailed in the description, by means of control signals DT1 to DTn, one of the P-type transistors and N-type transistors in the inverting circuits 84-1 to 84-n for adjusting the duty cycle is controlled to be turned on, and the other is controlled to be turned off. In other words, control signals DT1 to DTn that cause one of the P-type transistors and N-type transistors in each duty cycle adjusting inverting circuit to be turned on and the other to be turned off are input to the inverting circuits 84-1 to 84-n for adjusting the duty cycle. Here, control signals DT1 to DTn are the first to nth control signals, which are signals set based on the adjustment data ADJ2. Figure 2 For example, the processing circuit 60 outputs control signals DT1 to DTn based on the adjustment data ADJ2 read from the non-volatile memory 62.

[0110] Furthermore, in Figure 16 In this circuit, the dimensions of the P-type and N-type transistors constituting the first to nth duty cycle adjustment inverting circuits 84-1 to 84-n are binary-weighted. For example, the dimensions of each P-type and N-type transistor in the second duty cycle adjustment inverting circuit 84-2 are twice the dimensions of each P-type and N-type transistor in the first duty cycle adjustment inverting circuit 84-1. Furthermore, the dimensions of each P-type and N-type transistor in the third duty cycle adjustment inverting circuit 84-3 are twice the dimensions of each P-type and N-type transistor in the second duty cycle adjustment inverting circuit 84-2.

[0111] In this way, the following adjustments can be made: the driving capabilities of the P-side and N-side of the inverting circuits 84-1 to 84-n for adjusting the duty cycle from the 1st to the nth can be binary-weighted and added to the driving capabilities of the P-side and N-side of the reference inverting circuit 82. Therefore, high-resolution duty cycle adjustments can be performed, achieving high precision in duty cycle adjustment.

[0112] Figure 17 A detailed structural example of the second duty cycle adjustment circuit 80 is shown. For example... Figure 17 As shown, the reference inverting circuit 82 of the second duty cycle adjustment circuit 80 includes: P-type transistors TP01 and TP02, which are connected in series between the power supply node and the output node NQ of VREG2; and N-type transistors TN01 and TN02, which are connected in series between the ground node and the output node NQ. Furthermore, a clock signal CK is input to the gates of the P-type transistor TP01 and the N-type transistor TN01. Additionally, the P-type transistor TP02 is always turned on because its gate is connected to the ground node, and the N-type transistor TN02 is always turned on because its gate is connected to the power supply node. Thus, the reference inverting circuit 82 becomes an inverting circuit that is always operating.

[0113] And, as Figure 17 As shown, the first duty cycle adjustment inverter circuit 84-1, which serves as an inverter circuit for duty cycle adjustment, includes: P-type transistors TP11 and TP12, which are connected in series between the power supply node and the output node NQ of VREG2; and N-type transistors TN11 and TN12, which are connected in series between the ground node and the output node NQ. TP11 is a first P-type transistor, and TP12 is a second P-type transistor. TN11 is a first N-type transistor, and TN12 is a second N-type transistor.

[0114] Furthermore, a clock signal CK is input to the gates of TP11, which is a first P-type transistor, and TN11, which is a first N-type transistor. On the other hand, a control signal DT1, which is a common first control signal, is input to the gates of TP12, which is a second P-type transistor, and TN12, which is a second N-type transistor.

[0115] Thus, when the control signal DT1 is at the first logic level (low level), the P-type transistor TP12 is turned on, and the N-type transistor TN12 is turned off. This allows the driving capability of the P-side of the P-type transistors TP11 and TP12 in the first duty cycle adjustment inverter circuit 84-1 to be added to the driving capability of the P-side of the reference inverter circuit 82. Therefore, even if an imbalance occurs due to variations in the manufacturing process of the P-type transistors, resulting in a lower driving capability of the P-side of the reference inverter circuit 82, this imbalance can be eliminated by adding driving capability to the P-side using the first duty cycle adjustment inverter circuit 84-1. This suppresses duty cycle fluctuations in the output clock signal CKQ2 caused by this imbalance, enabling high-precision duty cycle adjustment.

[0116] Furthermore, when the control signal DT1 is at the second logic level (high), the P-type transistor TP12 and the N-type transistor TN12 are turned on. This allows the N-side drive capability of the N-type transistors TN11 and TN12 in the first duty cycle adjustment inverter circuit 84-1 to be added to the N-side drive capability of the reference inverter circuit 82. Therefore, even if an imbalance occurs due to variations in the manufacturing process of N-type transistors, resulting in a lower drive capability on the N-side of the reference inverter circuit 82, this imbalance can be eliminated by adding drive capability to the N-side using the first duty cycle adjustment inverter circuit 84-1. This suppresses duty cycle fluctuations in the output clock signal CKQ2 caused by this imbalance, enabling high-precision duty cycle adjustment.

[0117] In addition, Figure 17 In the circuit, the second duty cycle adjustment circuit 80 includes a second duty cycle adjustment inverting circuit 84-2 connected in parallel with the reference inverting circuit 82 and outputting a buffered clock signal CK to the output node NQ. Furthermore, the second duty cycle adjustment inverting circuit 84-2 includes P-type transistors TP21 and TP22 connected in series between the power supply node and the output node NQ, and N-type transistors TN21 and TN22 connected in series between the ground node and the output node NQ. TP21 is a third P-type transistor, and TP22 is a fourth P-type transistor. TN21 is a third N-type transistor, and TN22 is a fourth N-type transistor.

[0118] Furthermore, a clock signal CK is input to the gates of TP21 (the third P-type transistor) and TN21 (the third N-type transistor). On the other hand, a control signal DT2, serving as a common second control signal, is input to the gates of TP22 (the fourth P-type transistor) and TN22 (the fourth N-type transistor).

[0119] Thus, when the control signal DT2 is low, the P-type transistor TP22 is turned on, and the N-type transistor TN22 is turned off. This allows the driving capability of the P-side of the P-type transistors TP21 and TP22 of the second duty cycle adjustment inverter circuit 84-2 to be added to the driving capability of the P-side of the reference inverter circuit 82. Therefore, even if an imbalance occurs where the driving capability of the P-side of the reference inverter circuit 82 becomes lower, this imbalance can be eliminated by adding driving capability to the P-side using the second duty cycle adjustment inverter circuit 84-2. Furthermore, when the control signal DT2 is high, the P-type transistor TP22 is turned off, and the N-type transistor TN22 is turned on. This allows the driving capability of the N-side of the N-type transistors TN21 and TN22 of the second duty cycle adjustment inverter circuit 84-2 to be added to the driving capability of the N-side of the reference inverter circuit 82. Therefore, even in the event of an imbalance that results in a decrease in the drive capability of the N-side of the reference inverter circuit 82, this imbalance can be eliminated by utilizing the additional drive capability of the N-side using the second duty cycle adjustment inverter circuit 84-2. This suppresses duty cycle variations in the output clock signal CKQ2, enabling high-precision duty cycle adjustment.

[0120] In addition, Figure 17 In this circuit, the second duty cycle adjustment circuit 80 includes an nth duty cycle adjustment inverter circuit 84-n connected in parallel with the reference inverter circuit 82 and outputting a buffered clock signal CK to the output node NQ. The nth duty cycle adjustment inverter circuit 84-n includes P-type transistors TPn1 and TPn2 connected in series between the power supply node and the output node NQ, and N-type transistors TNn1 and TNn2 connected in series between the ground node and the output node NQ. The clock signal CK is input to the gates of the P-type transistors TPn1 and TNn1, and a control signal DTn, serving as a common nth control signal, is input to the gates of the P-type transistors TPn2 and TNn2. When the control signal DTn is low, the driving capability of the P-side of the P-type transistors TPn1 and TPn2 of the nth duty cycle adjustment inverter circuit 84-n can be added to the driving capability of the P-side of the reference inverter circuit 82. Furthermore, when the control signal DTn is high, the driving capability of the N-type transistors TNn1 and TNn2 of the nth duty cycle adjustment inverter circuit 84-2 can be added to the driving capability of the nth side of the reference inverter circuit 82.

[0121] In addition, Figure 17 In this context, the control signals DT1 to DTn, which serve as the 1st to nth control signals, are signals set based on the adjustment data ADJ2. Furthermore, in... Figure 17In this circuit, the dimensions of the P-type and N-type transistors in the first duty cycle adjustment inverting circuit 84-1 are less than 1 / 2, specifically 1 / 3, of the dimensions of the P-type and N-type transistors in the reference inverting circuit 82. Furthermore, the dimensions of the P-type and N-type transistors in the second duty cycle adjustment inverting circuit 84-2 are twice the dimensions of the P-type and N-type transistors in the first duty cycle adjustment inverting circuit 84-1. Specifically, the dimensions of the P-type and N-type transistors in the first to nth duty cycle adjustment inverting circuits 84-1 to 84-n are binary-weighted.

[0122] 4. Variations

[0123] The circuit device 20 of this embodiment is not limited to the structural example described above, and can be modified in various ways. Hereinafter, various modifications of this embodiment will be described.

[0124] For example in Figure 18 In the modified example, the structure of the oscillating circuit 30 is the same as... Figure 3 Different. For example, in Figure 18 In, not set Figure 3 Fixed capacitors CF1 and CF2 are used. Furthermore, one end of variable capacitor element CV1 is connected to node 1 N1, and a temperature compensation voltage VCMP is supplied to the other end of variable capacitor element CV1. Similarly, one end of variable capacitor element CV2 is connected to node 2 N2, and a temperature compensation voltage VCMP is supplied to the other end of variable capacitor element CV2. A reference voltage VREFB is supplied to node 1 N1 from the first duty cycle adjustment circuit 50 via resistor RRFB, and a reference voltage VREFC is supplied to node 2 N2 from the first duty cycle adjustment circuit 50 via resistor RRFC. Thus, a voltage corresponding to the voltage difference between the temperature compensation voltage VCMP and the reference voltage VREFB is applied across variable capacitor element CV1, and a voltage corresponding to the voltage difference between the temperature compensation voltage VCMP and the reference voltage VREFC is applied across variable capacitor element CV2. Additionally, the oscillation signal XI becomes an oscillation signal that varies around the reference voltage VREFB, and the oscillation signal XO becomes an oscillation signal that varies around the reference voltage VREFC. Furthermore, in Figure 18 In this circuit, a DC cutoff capacitor CX2 is provided between the first node N1 and the input node of the waveform shaping circuit 40. By providing such a capacitor CX2, the DC component of the oscillation signal XI is cut off, and only the AC component is transmitted to the waveform shaping circuit 40. Furthermore, for the AC component of the oscillation signal XI, a bias voltage VBS, which serves as the bias point, is set by the first duty cycle adjustment circuit 50, thereby enabling the oscillation signal XI, which varies around the bias voltage VBS, to be input to the waveform shaping circuit 40.

[0125] Furthermore, the structure of the first duty cycle adjustment circuit 50 in this embodiment is not limited to... Figure 3 , Figure 18 The structure shown can be modified in various ways. For example, as the first duty cycle adjustment circuit 50, it can also be used in... Figure 7 , Figure 8 The circuits with the structures described in the first and second comparative examples, etc.

[0126] exist Figure 19 , Figure 20 In this circuit, the circuit device 20 includes an output buffer circuit 70 that buffers the clock signal CK and outputs the output clock signals CKQ1 and CKQ2 to the outside. The output buffer circuit 70, for example, has a buffer circuit with a higher drive capability than the waveform shaping circuit 40. The clock signal CK, buffered by this high-drive-capability buffer circuit, is output as the output clock signals CKQ1 and CKQ2 to the outside of the circuit device 20. Therefore, even under a large external load, the output clock signals CKQ1 and CKQ2 with appropriate drive waveforms can be supplied to the external load for driving.

[0127] In addition, Figure 19 In this circuit, the first duty cycle adjustment circuit 50 supplies a reference voltage VREF where VCMP-VREF is greater than 0V when the temperature compensation voltage is set to VCMP and the reference voltage is set to VREF. For example, the reference voltage VREF is supplied by applying a voltage greater than 0V to the variable capacitor element CV1. Similarly, the reference voltage VREF is supplied by applying a voltage greater than 0V to the variable capacitor element CV2.

[0128] exist Figure 19 In this circuit, the temperature compensation voltage VCMP becomes, for example, a voltage that varies with temperature in a three-fold characteristic, centered at 0.9V. Furthermore, the first duty cycle adjustment circuit 50 adjusts VCMP-VREF to be greater than 0V. Figure 19 A reference voltage VREF of, for example, 0.3V is supplied to the variable capacitor element CV1. This applies a voltage VCMP-VREF greater than 0V to the variable capacitor element CV1. Therefore, the capacitance of the variable capacitor element CV1 varies variablely within an appropriate sensitivity range according to the temperature compensation voltage VCMP. Similarly, a voltage VCMP-VREF greater than 0V is also applied to the variable capacitor element CV2, and the capacitance of the variable capacitor element CV2 varies variablely within an appropriate sensitivity range according to the temperature compensation voltage VCMP. Thus, the circuit device 20 can be used as a circuit device for a TCXO, and an oscillator for the TCXO can be realized.

[0129] On the other hand, Figure 20In this circuit, the first duty cycle adjustment circuit 50 supplies a reference voltage VREF that makes VCMP-VREF below 0V. For example, the reference voltage VREF is supplied by applying a voltage below 0V to the variable capacitor element CV1. Similarly, the reference voltage VREF is supplied by applying a voltage below 0V to the variable capacitor element CV2. Figure 20 In this process, a temperature compensation voltage VCMP of approximately 0.6V is supplied. Therefore, in Figure 20 In this circuit, the first duty cycle adjustment circuit 50 supplies a reference voltage VREF of, for example, 0.9V to the variable capacitor element CV1, so that VCMP-VREF becomes 0V or less. Thus, a voltage VCMP-VREF of 0V or less is applied to the variable capacitor element CV1. Similarly, VCMP-VREF of 0V or less is also applied to the variable capacitor element CV2. Therefore, the circuit arrangement 20 can be used as a circuit arrangement for an SPXO, and an oscillator for the SPXO can be realized.

[0130] For example, the first duty cycle adjustment circuit 50 supplies a voltage of approximately 0.5V ± 0.1V as the bias voltage VBS. Therefore, in implementing the TCXO... Figure 19 In the trapezoidal resistor circuit of voltage divider circuit 52, the voltage-divided tap of the output reference voltage VREF becomes the ground node-side tap compared to the voltage-divided tap of the output bias voltage VBS. On the other hand, in implementing SPXO... Figure 20 In the trapezoidal resistor circuit of the voltage divider circuit 52, the voltage division tap of the output reference voltage VREF becomes the tap on the power node side of VREG1, compared to the voltage division tap of the output bias voltage VBS. Thus, according to this embodiment, by simply switching the position of the voltage division tap of the output bias voltage VBS in the trapezoidal resistor circuit of the voltage divider circuit 52, the same circuit arrangement 20 can be used... Figure 19 That way it can be used as a circuit device for a TCXO, or as... Figure 20 That is, it can be used as a circuit device for SPXO. Therefore, circuit device 20 can be shared in both TCXO and SPXO.

[0131] Figure 21An example of the structure of the first duty cycle adjustment circuit 50 is shown. The first duty cycle adjustment circuit 50 includes a voltage divider circuit 52 and a selection circuit 54. The voltage divider circuit 52 has multiple resistors R1 to Rm connected in series between the power node and the ground node of VREG1, and outputs multiple divided voltages VR1 to VRm-1 obtained by dividing the voltages of the multiple resistors R1 to Rm. Then, the selection circuit 54 selects any one of the multiple divided voltages VR1 to VRm-1 as the bias voltage VBS according to the adjustment data ADJ. This selection circuit 54 can be implemented, for example, by multiple selection circuits that select voltages in a tournament manner. Specifically, the selection circuit 54 selects the first divided voltage, which is any one of the multiple divided voltages VR1 to VRm-1, as the bias voltage VBS and outputs it, and selects the second divided voltage, which is any one of the multiple divided voltages VR1 to VRm-1, as the reference voltage VREF and outputs it. Therefore, a first duty cycle adjustment circuit 50 can be used to supply both the bias voltage VBS for duty cycle adjustment and the reference voltage VREF for temperature compensation, thus achieving circuit sharing.

[0132] 5. Oscillator

[0133] Figure 22 An example of the construction of the oscillator 4 according to this embodiment is shown. The oscillator 4 has an oscillator 10, a circuit device 20, and a package 15 for housing the oscillator 10 and the circuit device 20. The package 15 is formed of, for example, ceramic, and has a housing space inside, in which the oscillator 10 and the circuit device 20 are housed. The housing space is hermetically sealed, preferably in a near-vacuum state, i.e., a depressurized state. Through the package 15, the oscillator 10 and the circuit device 20 can be appropriately protected from the effects of impact, dust, heat, moisture, etc.

[0134] Package 15 includes a base 16 and a cover 17. Specifically, package 15 comprises a base 16 supporting the oscillator 10 and the circuit device 20, and a cover 17 engaged with the upper surface of the base 16 to form a receiving space between the cover and the base 16. The oscillator 10 is supported on a stepped portion provided inside the base 16 via terminal electrodes. The circuit device 20 is disposed on the inner bottom surface of the base 16. Specifically, the circuit device 20 is disposed with its active surface facing the inner bottom surface of the base 16. The active surface is the surface of the circuit device 20 where circuit elements are formed. Furthermore, bumps BMP are formed on the terminals of the circuit device 20. The circuit device 20 is supported on the inner bottom surface of the base 16 via conductive bumps BMP. The conductive bumps BMP are, for example, metal bumps, through which the oscillator 10 and the circuit device 20 are electrically connected. Furthermore, the circuit device 20 is electrically connected to the external terminals 18 and 19 of the oscillator 4 via the bump BMP or the internal wiring of the package 15. The external terminals 18 and 19 are formed on the outer bottom surface of the package 15. The external terminals 18 and 19 are connected to external devices via external wiring. The external wiring is, for example, wiring formed on a circuit board on which the external device is mounted. Thus, clock signals can be output to external devices.

[0135] In addition, Figure 22 In this embodiment, the circuit device 20 is flip-mounted with its active surface facing downwards, but this embodiment is not limited to this mounting. For example, the circuit device 20 can also be mounted with its active surface facing upwards. That is, the circuit device 20 is mounted with its active surface facing the oscillator 10. Alternatively, the oscillator 4 can also be a wafer-level package (WLP) oscillator. In this case, the oscillator 4 includes: a base having a semiconductor substrate and a through electrode penetrating between a first surface and a second surface of the semiconductor substrate; an oscillator 10 fixed to the first surface of the semiconductor substrate via a conductive bonding member such as a metal bump; and an external terminal provided on the second surface side of the semiconductor substrate via an insulating layer such as a reconfigured wiring layer. Furthermore, an integrated circuit that becomes the circuit device 20 is formed on the first or second surface of the semiconductor substrate. In this case, the multiple substrates and multiple covers are joined by bonding a first semiconductor wafer having multiple bases configured with an oscillator 10 and an integrated circuit to a second semiconductor wafer having multiple covers, and then the oscillator 4 is monolithically produced using a dicing machine or the like. In this way, a wafer-level packaged oscillator 4 can be realized, and the oscillator 4 can be manufactured with high productivity and low cost.

[0136] As described above, the circuit arrangement of this embodiment includes: an oscillation circuit electrically connected to a first node electrically connected to one end of an oscillator and a second node electrically connected to the other end of the oscillator, generating an oscillation signal by oscillating the oscillator; a waveform shaping circuit connected to the first node, receiving the oscillation signal from the first node and outputting a clock signal obtained by waveform shaping of the oscillation signal; and a first duty cycle adjustment circuit that adjusts the duty cycle of the clock signal. Furthermore, the circuit arrangement includes an output buffer circuit that outputs a first output clock signal and a second output clock signal to the outside according to the clock signal, and the output buffer circuit includes a second duty cycle adjustment circuit that adjusts the duty cycle of the second output clock signal.

[0137] In this embodiment, the oscillation circuit causes the oscillator, electrically connected via the first and second nodes, to oscillate, thereby generating an oscillation signal. The oscillation signal at the first node is input to the waveform shaping circuit for waveform shaping to generate a clock signal. Furthermore, the output buffer circuit outputs the first and second output clock signals to the outside based on the clock signal. Additionally, the first duty cycle adjustment circuit adjusts the duty cycle of the clock signal, and the second duty cycle adjustment circuit, located in the output buffer circuit, adjusts the duty cycle of the second output clock signal. Thus, duty cycle adjustment can be performed in two stages, with both the first and second duty cycle adjustment circuits performing the adjustment. Therefore, even if the duty cycle adjustment by the first duty cycle adjustment circuit cannot meet the required duty cycle accuracy of the second output clock signal, the second duty cycle adjustment circuit can still ensure that the second output clock signal meets the required duty cycle accuracy. Therefore, multiple clock signal output functionality and high-precision duty cycle adjustment can be achieved simultaneously.

[0138] In addition, in this embodiment, the first output clock signal and the second output clock signal can also be clock signals with a phase difference of 180 degrees.

[0139] In this way, the first output clock signal and the second output clock signal, which are 180 degrees out of phase with the first output clock signal, can be output to the outside to realize the multi-output function, and the first output clock signal and the second output clock signal, which have undergone high-precision duty cycle adjustment, can be output to the outside.

[0140] Alternatively, in this embodiment, the output buffer circuit may also include: a first buffer circuit that buffers the clock signal and outputs it as a first output clock signal; and a second buffer circuit that has a second duty cycle adjustment circuit that buffers the clock signal and outputs a second output clock signal whose duty cycle is adjusted by the second duty cycle adjustment circuit.

[0141] In this way, the first buffer circuit can output the buffered clock signal as the first output clock signal to the outside, and the second buffer circuit can output the buffered clock signal with the duty cycle adjusted by the second duty cycle adjustment circuit as the second output clock signal to the outside.

[0142] In addition, in this embodiment, the first duty cycle adjustment circuit can also supply a bias voltage that has been variably adjusted based on adjustment data to the first node, thereby adjusting the duty cycle of the clock signal.

[0143] Therefore, since the clock signal can be used as the optimal duty cycle, the bias voltage of the oscillation signal can be adjusted according to the adjustment data, and the oscillation signal can be input to the waveform shaping circuit, thus enabling high-precision adjustment of the duty cycle.

[0144] Alternatively, in this embodiment, the second duty cycle adjustment circuit may also include: a reference inverting circuit that outputs a buffered clock signal to the output node; and a duty cycle adjustment inverting circuit connected in parallel with the reference inverting circuit that outputs a buffered clock signal to the output node.

[0145] In this way, the duty cycle adjustment inverter circuit is connected in parallel with the reference inverter circuit and the clock signal is buffered, so that the duty cycle of the second output clock signal can be adjusted using the duty cycle adjustment inverter circuit.

[0146] Furthermore, in this embodiment, the size of each of the P-type transistor and the N-type transistor constituting the duty cycle adjustment inverting circuit can be less than 1 / 2 of the size of each of the P-type transistor and the N-type transistor constituting the reference inverting circuit.

[0147] In this way, the driving capability of the P-type transistor and the N-type transistor of the reference inverting circuit can be used as a reference, and the driving capability of the P-type transistor side and the driving capability of the N-type transistor side can be adjusted by the duty cycle adjustment inverting circuit.

[0148] In this embodiment, the second duty cycle adjustment circuit may also include: a duty cycle adjustment inverting circuit that serves as the inverting circuit for the first duty cycle adjustment; and a second duty cycle adjustment inverting circuit connected in parallel with the reference inverting circuit, which outputs a buffered clock signal to the output node. Furthermore, the dimensions of the P-type transistor and N-type transistor constituting the second duty cycle adjustment inverting circuit may be twice the dimensions of the P-type transistor and N-type transistor constituting the first duty cycle adjustment inverting circuit.

[0149] In this way, the driving capability of the P-type transistor side and N-type transistor side of the reference inverting circuit can be adjusted by adding the driving capability of the P-type transistor side and N-type transistor side of the first duty cycle adjustment inverting circuit and the second duty cycle adjustment inverting circuit, thus enabling higher resolution duty cycle adjustment.

[0150] Furthermore, in this embodiment, the second duty cycle adjustment circuit may include: a duty cycle adjustment inverting circuit serving as the inverting circuit for the first duty cycle adjustment; and second to nth duty cycle adjustment inverting circuits, which are connected in parallel with the reference inverting circuit, outputting a buffered clock signal to the output node, where n is an integer of 3 or more. Moreover, control can be achieved by using the first to nth control signals, such that one of the P-type and N-type transistors in each of the first to nth duty cycle adjustment inverting circuits is turned on while the other is turned off. Furthermore, the dimensions of the P-type and N-type transistors constituting the first to nth duty cycle adjustment inverting circuits can be binary-weighted.

[0151] In this way, the following adjustments can be made: the driving capabilities of the P-type transistor side and N-type transistor side of the inverting circuit for adjusting the duty cycle from the 1st to the nth can be weighted in binary and added to the driving capabilities of the P-type transistor side and N-type transistor side of the reference inverting circuit, thereby enabling duty cycle adjustments with higher resolution.

[0152] Furthermore, in this embodiment, the inverting circuit for duty cycle adjustment may also include: a first P-type transistor and a second P-type transistor connected in series between the power supply node and the output node; and a first N-type transistor and a second N-type transistor connected in series between the ground node and the output node. Moreover, a clock signal may be input to the gates of the first P-type transistor and the first N-type transistor, and a common first control signal may be input to the gates of the second P-type transistor and the second N-type transistor.

[0153] In this way, even in the case of an imbalance where the driving capability of the P-type transistor side and the N-type transistor side of the reference inverting circuit becomes lower, the imbalance can be eliminated by using the inverting circuit for adjusting the first duty cycle to add driving capability to the P-type transistor side and the N-type transistor side, thereby achieving high-precision duty cycle adjustment.

[0154] Furthermore, in this embodiment, the second duty cycle adjustment circuit may include: a duty cycle adjustment inverting circuit that serves as the inverting circuit for the first duty cycle adjustment; and a second duty cycle adjustment inverting circuit connected in parallel with the reference inverting circuit, which outputs a buffered clock signal to the output node. The second duty cycle adjustment inverting circuit may also include: a third P-type transistor and a fourth P-type transistor connected in series between the power supply node and the output node; and a third N-type transistor and a fourth N-type transistor connected in series between the ground node and the output node. Moreover, a clock signal may be input to the gates of the third P-type transistor and the third N-type transistor, and a common second control signal may be input to the gates of the fourth P-type transistor and the fourth N-type transistor.

[0155] In this way, even in the case of an imbalance where the driving capability of the P-type transistor side and the N-type transistor side of the reference inverting circuit decreases, the imbalance can be eliminated by using the first duty cycle adjustment inverting circuit and the second duty cycle adjustment inverting circuit to increase the driving capability of the P-type transistor side and the N-type transistor side, thereby achieving high-precision duty cycle adjustment.

[0156] Furthermore, this embodiment relates to an oscillator that includes the aforementioned circuitry and oscillator.

[0157] Furthermore, while this embodiment has been described in detail above, those skilled in the art should readily understand that various modifications can be made without substantially departing from the new aspects and effects of this disclosure. Therefore, all such modifications are included within the scope of this disclosure. For example, in the specification or drawings, any term that is described at least once with a different term that is more general or synonymous can be replaced with that different term anywhere in the specification or drawings. Additionally, all combinations of this embodiment and its modifications are also included within the scope of this disclosure. Furthermore, the structure and operation of circuit devices, oscillators, etc., are not limited to those described in this embodiment, and various modifications can be made.

Claims

1. A circuit arrangement, characterized by comprises: an oscillation circuit electrically connected to a first node to which one end of a vibrator is electrically connected and a second node to which the other end of the vibrator is electrically connected, which generates an oscillation signal by oscillating the vibrator; a waveform shaping circuit connected to the first node, which inputs the oscillation signal from the first node and outputs a clock signal obtained by waveform shaping the oscillation signal; a first duty adjustment circuit which performs duty adjustment of the clock signal; and an output buffer circuit which outputs a first output clock signal and a second output clock signal to the outside according to the clock signal, the output buffer circuit comprises a second duty adjustment circuit which performs duty adjustment of the second output clock signal, the first duty adjustment circuit supplies a bias voltage which is variably adjusted on the basis of adjustment data to the first node, thereby performing duty adjustment of the clock signal. comprises:

2. A circuit arrangement, characterized by an oscillation circuit electrically connected to a first node to which one end of a vibrator is electrically connected and a second node to which the other end of the vibrator is electrically connected, which generates an oscillation signal by oscillating the vibrator; a waveform shaping circuit connected to the first node, which inputs the oscillation signal from the first node and outputs a clock signal obtained by waveform shaping the oscillation signal; a first duty adjustment circuit which performs duty adjustment of the clock signal; and an output buffer circuit which outputs a first output clock signal and a second output clock signal to the outside according to the clock signal, the output buffer circuit comprises a second duty adjustment circuit which performs duty adjustment of the second output clock signal, the second duty adjustment circuit comprises: a reference inverter circuit which outputs a signal obtained by buffering the clock signal to an output node; and a duty adjustment inverter circuit which is connected in parallel to the reference inverter circuit and outputs a signal obtained by buffering the clock signal to the output node.

3. The circuit device according to claim 1 or 2, wherein the first output clock signal and the second output clock signal are clock signals which are 180 degrees out of phase with each other.

4. The circuit device according to claim 1 or 2, wherein the output buffer circuit comprises: a first buffer circuit which buffers the clock signal and outputs the clock signal as the first output clock signal; and a second buffer circuit which has the second duty adjustment circuit, buffers the clock signal, and outputs the second output clock signal whose duty has been adjusted by the second duty adjustment circuit.

5. The circuit device according to claim 2, wherein the sizes of the P-type transistor and the N-type transistor which constitute the duty adjustment inverter circuit are each 1 / 2 or less of the sizes of the P-type transistor and the N-type transistor which constitute the reference inverter circuit.

6. The circuit device according to claim 2, wherein the second duty adjustment circuit comprises: the duty adjustment inverter circuit as a first duty adjustment inverter circuit; and ​ ​ ​ a second duty cycle adjustment inverter connected in parallel to the reference inverter and outputting a signal in which the clock signal is buffered to the output node, the sizes of the P-type transistor and the N-type transistor constituting the second duty cycle adjustment inverter are twice the sizes of the P-type transistor and the N-type transistor constituting the first duty cycle adjustment inverter.

7. The circuit device according to claim 2, wherein the second duty cycle adjustment circuit includes: the duty cycle adjustment inverter as the first duty cycle adjustment inverter; and second to nth duty cycle adjustment inverters connected in parallel to the reference inverter and outputting a signal in which the clock signal is buffered to the output node, where n is an integer of 3 or more, the first to nth duty cycle adjustment inverters are controlled in such a manner that one of the P-type transistor and the N-type transistor of each of the first to nth duty cycle adjustment inverters is turned on and the other is turned off by the first to nth control signals, the sizes of the P-type transistor and the N-type transistor constituting the first to nth duty cycle adjustment inverters are weighted in binary.

8. The circuit device according to claim 2, wherein the duty cycle adjustment inverter includes: a first P-type transistor and a second P-type transistor connected in series between a power supply node and the output node; and a first N-type transistor and a second N-type transistor connected in series between a ground node and the output node, the clock signal is input to the gates of the first P-type transistor and the first N-type transistor, a common first control signal is input to the gates of the second P-type transistor and the second N-type transistor.

9. The circuit device according to claim 8, wherein the second duty cycle adjustment circuit includes: the duty cycle adjustment inverter as the first duty cycle adjustment inverter; and a second duty cycle adjustment inverter connected in parallel to the reference inverter and outputting a signal in which the clock signal is buffered to the output node, the second duty cycle adjustment inverter includes: a third P-type transistor and a fourth P-type transistor connected in series between the power supply node and the output node; and a third N-type transistor and a fourth N-type transistor connected in series between the ground node and the output node, the clock signal is input to the gates of the third P-type transistor and the third N-type transistor, a common second control signal is input to the gates of the fourth P-type transistor and the fourth N-type transistor.

10. An oscillator characterized by the oscillator includes: the circuit device according to any one of claims 1 to 9; and the oscillator.

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