Data decoding system, method, device and storage medium

Abstract

The present disclosure relates to the field of communication technology, and in particular to a data decoding system, method, device and storage medium. The data decoding system includes multiple first storage modules for storing data to be decoded; a polling module for determining in parallel whether the multiple first storage modules are non-empty, and reading the data to be decoded from the non-empty first storage modules; and multiple decoding modules, each decoding module for decoding the data to be decoded read from the polling module through a decoder. The present disclosure realizes parallel data decoding of multiple groups of data through a multi-module design and a fair polling method, which greatly improves the processing efficiency of data decoding.

Description

Technical Field

[0001] The present disclosure relates to the field of communication technology, and in particular to a data decoding system, method, device and storage medium. Background Art

[0002] In recent years, low-density parity check code (LDPC) has been a hot topic in the field of channel coding. Low-density parity check code is a type of linear block code with a sparse check matrix. It not only has good performance close to the Shannon limit, but also has low decoding complexity and flexible structure. It has been widely used in deep space communication, optical fiber communication, satellite digital video and audio broadcasting and other fields. LDPC code has become a strong competitor for the fourth-generation communication system (4G), and the coding scheme based on LDPC code has been adopted by the next-generation satellite digital video broadcasting standard DVB-S2. Another polar code (Polar Code) is based on the conceptual theory of channel polarization and is the first channel coding method that can be strictly proved to reach the channel capacity. The International Mobile Communications Standardization Organization 3GPP finally determined the channel coding technology solution for the 5G eMBB (enhanced mobile broadband) scenario, in which Polar code is used as the coding scheme for the control channel and LDPC code is used as the coding scheme for the data channel. Summary of the invention

[0003] The inventors found that in the related art, when decoding through POLAR / LDPC, the IP-Core (Intellectual Property Core) supports decoding of one group of user data at a time, so the general design is only a single-user mode, which is inefficient.

[0004] The present disclosure provides a data decoding system, method, device and storage medium to solve the technical problem of low POLAR / LDPC decoding efficiency mentioned in the background technology.

[0005] According to one aspect of an embodiment of the present disclosure, the present disclosure provides a data decoding system, including:

[0006] A plurality of first storage modules, used for storing data to be decoded;

[0007] A polling module, used for determining in parallel whether a plurality of first storage modules are not empty, and reading data to be decoded from the first storage modules that are not empty;

[0008] A plurality of decoding modules, each decoding module is used to decode the to-be-decoded data read from the polling module through a decoder.

[0009] Optionally, the system further comprises:

[0010] A plurality of second storage modules, corresponding one to one with the plurality of decoding modules, each second storage module being used for caching the to-be-decoded data read from the polling module;

[0011] Each decoding module is specifically used to decode the to-be-decoded data read from the corresponding second storage module through a decoder.

[0012] Optionally, the polling module is further configured to transfer the to-be-decoded data in the non-empty first storage module to the non-full second storage module.

[0013] Optionally, data is transmitted between the multiple first storage modules and the polling module, between the polling module and the multiple second storage modules, and between each second storage module and the corresponding decoding module in a first-in-first-out manner.

[0014] Optionally, the system further comprises:

[0015] The data receiving module is used to cache the to-be-decoded data associated with the data packet header to the first storage module when the data packet header is detected. The data receiving module and the plurality of first storage modules are transmitted data in a first-in-first-out manner.

[0016] Optionally, the system further comprises:

[0017] The detection module is used to detect the storage status of multiple second storage modules, and when the storage status of any second storage module is full, call a second storage module in a non-full state to store the data to be decoded read by the polling module.

[0018] Optionally, the system further comprises:

[0019] The sending module is used to send the data decoded by the decoding module.

[0020] According to another aspect of an embodiment of the present disclosure, the present disclosure provides a data decoding method, including:

[0021] Calling a plurality of first storage modules to store data to be decoded;

[0022] Calling the polling module to determine in parallel whether the plurality of first storage modules are not empty, and calling the polling module to read the data to be decoded from the first storage modules that are not empty;

[0023] Multiple decoding modules are called to decode the data to be decoded read from the polling module.

[0024] Optionally, after calling the polling module to read the to-be-decoded data from the non-empty first storage module, the method further comprises:

[0025] Calling the polling module to transfer the data to be decoded to the second storage module corresponding to each decoding module;

[0026] When calling multiple decoding modules to decode the data to be decoded read from the polling module, the decoding module reads the data to be decoded from the corresponding second storage module.

[0027] Optionally, transferring the to-be-decoded data to a second storage module corresponding to each decoding module includes:

[0028] The detection module is called to detect the storage status of the plurality of second storage modules, and when the storage status of any second storage module is full, a second storage module in a non-full state is called to store the to-be-decoded data read by the polling module.

[0029] Optionally, after calling multiple decoding modules to decode the to-be-decoded data read from the polling module, the method further includes:

[0030] The sending module is called to send the data decoded by the decoding module.

[0031] According to another aspect of an embodiment of the present disclosure, the present disclosure provides an electronic device, including a memory, a processor, a communication interface and a communication bus, wherein the memory stores a computer program that can be run on the processor, the memory and the processor communicate through the communication bus and the communication interface, and the processor implements the steps of the above-mentioned data decoding method when executing the computer program.

[0032] According to another aspect of the embodiments of the present disclosure, the present disclosure further provides a computer-readable medium having a non-volatile program code executable by a processor, wherein the program code enables the processor to execute the above-mentioned data decoding method.

[0033] The above technical solution provided by the embodiment of the present disclosure has the following advantages compared with the prior art:

[0034] The disclosed technical solution provides a data decoding system, including multiple first storage modules for storing data to be decoded; a polling module for determining in parallel whether the multiple first storage modules are not empty, and reading the data to be decoded from the non-empty first storage modules; and multiple decoding modules, each decoding module for decoding the data to be decoded read from the polling module through a decoder. The disclosed method realizes parallel data decoding of multiple groups of data through a multi-module design and a fair polling method, which greatly improves the processing efficiency of data decoding. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0036] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0037] Figure 1 A schematic diagram of an optional data decoding system provided in an embodiment of the present disclosure;

[0038] Figure 2 A flow chart of an optional data decoding method provided by an embodiment of the present disclosure;

[0039] Figure 3 A flow chart of an optional data decoding method provided by an embodiment of the present disclosure;

[0040] Figure 4 A schematic diagram of an optional electronic device structure provided for an embodiment of the present disclosure. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0042] In the following description, reference is made to “one specific embodiment”, which describes a subset of all possible embodiments, but it can be understood that “one specific embodiment” describes the same subset or different subsets of all possible embodiments and can be combined with each other without conflict.

[0043] Unless otherwise defined, all technical science and technology used herein have the same meaning as commonly understood by those skilled in the art of the present invention. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present invention.

[0044] Before further describing the embodiments of the present disclosure in detail, the nouns and terms involved in the embodiments of the present disclosure are described. The nouns and terms involved in the embodiments of the present disclosure are subject to the following interpretations.

[0045] FPGA (Field Programmable Gate Array), FPGA is widely used in communication hardware equipment systems with its advantages such as parallel operation of internal logic, high-speed working clock, rich input and output pin resources, integrated high-speed serial transceiver modules, and IP-Core (Intellectual Property Core) resources of specific interface protocols, to complete board-level logic control, interface conversion, data transmission, algorithm processing and other functions.

[0046] In the related art, when decoding through POLAR / LDPC, the IP-Core (Intellectual Property Core) supports decoding of one group of user data at a time, so the general design is only a single-user mode, which is inefficient.

[0047] In order to solve the technical problems mentioned in the background technology, according to one aspect of an embodiment of the present disclosure, an embodiment of a data decoding system is provided.

[0048] In the embodiments of the present disclosure, Figure 1 As shown, the data decoding system comprises:

[0049] A plurality of first storage modules 101, used for storing data to be decoded;

[0050] The polling module 102 is used to determine in parallel whether the plurality of first storage modules 101 are not empty, and read the data to be decoded from the first storage modules 101 that are not empty;

[0051] A plurality of decoding modules 103 , each decoding module 103 is used to decode the to-be-decoded data read from the polling module 102 through a decoder.

[0052] In the embodiment of the present disclosure, the data stream in the communication link is user data, and the communication system encodes and decodes different user data for data transmission. The present disclosure is based on the rich input and output pin resources of FPGA, and integrates a high-speed serial transceiver module to form a polling module 102, which can simultaneously poll multiple first storage modules 101, that is, to judge in parallel whether multiple first storage modules 101 are not empty, and when multiple first storage modules 101 are not empty, read the data to be decoded in multiple first storage modules 101. The above decoder can be an IP-Core (Intellectual Property Core) based on an FPGA specific interface protocol, and each decoding module 103 includes at least one decoder, so that multiple decoding modules 103 are used to decode the data to be decoded read out of the polling module 102 in parallel. It can be understood that when POLAR / LDPC decoding is required to be performed quickly, a decoder related to POLAR / LDPC can be used. For decoding of other coding formats, a decoder of the corresponding format can be used, and there is no limitation here.

[0053] FPGA is widely used in communication hardware equipment systems due to its advantages such as parallel operation of internal logic, high-speed working clock, rich input and output pin resources, integrated high-speed serial transceiver modules, and IP-Core (Intellectual Property Core) resources for specific interface protocols. It completes board-level logic control, interface conversion, data transmission, algorithm processing and other functions.

[0054] In the disclosed embodiment, the first storage module 101 provides a data polling interface and a data reading interface to the polling module 102. The data polling interface is used for the polling module 102 to determine whether the first storage module 101 is not empty, and the data reading interface is used for the polling module 102 to read data from the first storage module 101.

[0055] Optionally, the system further comprises:

[0056] A plurality of second storage modules 104, corresponding one to one with the plurality of decoding modules 103, each second storage module 104 being used for caching the to-be-decoded data read from the polling module 102;

[0057] Each decoding module 103 is specifically configured to decode the to-be-decoded data read from the corresponding second storage module 104 through a decoder.

[0058] In the disclosed embodiment, the second storage module 104 provides a second data cache interface to the polling module 102, which is used to store the data to be decoded read by the polling module 102 through the second data cache interface, and provides a data decoding interface to the decoding module 103, and the data decoding interface is used for the decoding module 103 to read the data to be decoded in the second storage module 104 for decoding.

[0059] Optionally, the polling module 102 is further configured to transfer the to-be-decoded data in the non-empty first storage module 101 to the non-full second storage module 104 .

[0060] In the disclosed embodiment, since the decoder supports decoding of one group of user data at a time, a polling module 102 is designed to perform data scheduling between multiple first storage modules 101 and multiple decoding modules 103, that is, the data to be decoded is transferred from the multiple first storage modules 101 to the multiple second storage modules 104 corresponding to the multiple decoding modules 103 one by one, so that multiple groups of data to be decoded are decoded in parallel by using multiple decoding modules 103, thereby improving decoding efficiency.

[0061] Optionally, data is transmitted between the multiple first storage modules 101 and the polling module 102 , between the polling module 102 and the multiple second storage modules 104 , and between each second storage module 104 and the corresponding decoding module 103 in a first-in, first-out manner.

[0062] In the disclosed embodiment, various levels of the data decoding system are connected via a First Input First Output (FIFO) method.

[0063] In the embodiment of the present disclosure, the polling module 102 distributes and transfers the data to be decoded (frame fifo and data fifo) of the front-end multiple first storage modules 101 to multiple second storage modules 104 (frame fifo and data fifo), wherein the frame fifo represents the address cache and the data fifo represents the data cache. Considering the back-end processing performance, when the block data in a second storage module 104 is small, the corresponding back-end module can be processed quickly. In order to ensure that multiple groups of user data can be processed in the first time, in the entire system design of the present disclosure, each level module adopts a plurality of pairs of FIFOs for docking, which is similar to the design of CPU cache (CPU Cache), so that the speed of the entire system is significantly accelerated. The multi-user polling module design can realize the simultaneous reception and transmission of multiple groups of users. Taking 4 users as an example: data scheduling can be performed through 4 first storage modules 101, polling module 102, and 4 second storage modules 104, and enter 4 decoding modules 103 for parallel decoding.

[0064] In the polling module 102, the user data (i.e., data to be decoded) of the four first storage modules 101 are read out and written into the four non-full second storage modules 104 that are connected one-to-one with multiple decoding modules 103 according to the scheduling rules (data in the non-empty first storage modules 101 are scheduled first, and the first-in-first-out order is followed when all are non-empty). The polling module 102 determines whether the four first storage modules 101 are non-empty at the same time each time to ensure that each user has the same opportunity. The decoding module 103 decodes the data to be decoded in the corresponding second storage modules 104 to ensure decoding efficiency.

[0065] Optionally, the system further comprises:

[0066] The data receiving module 105 is used to cache the to-be-decoded data associated with the data packet header to the first storage module 101 when a data packet header is detected. The data receiving module 105 and the multiple first storage modules 101 use a first-in-first-out method for data transmission.

[0067] In the embodiment of the present disclosure, the data receiving module 105 can be connected to the digital signal processor (DSP) upstream of the communication system. The data receiving module 105 can detect the data packet header and store the data packet associated with the data packet header to multiple first storage modules 101. The first storage module 101 provides a first data cache interface, a data polling interface and a data reading interface. The first storage module 101 stores the data cached by the data receiving module 105 through the first data cache interface. The data polling interface is provided to the polling module 102, and is used for the polling module 102 to determine whether the first storage module 101 is not empty. The data reading interface is used for the polling module 102 to read data from the first storage module 101. Table 1 is an optional data packet structure reference table provided in the present disclosure.

[0068] Table 1

[0069]

[0070] The data stored in the data packet is block data, i.e., block, and the function of pkt_length is to characterize the number of clocks (clk) of the control (ctrl) information of the block + the number of clks of the data data. Each blcok requires a ctrl information, which is 90 bits of data and is composed of blk_ctrl_0, blk_ctrl_1, and blk_ctrl_2 in the above table, i.e., ctrl = {blk_ctrl_0, blk_ctrl_1, blk_ctrl_2}. The ctrl information contains an id number, which represents the block identifier. The data receiving module 105 can also be set in multiple groups. For example, by adopting the design of 4 data receiving modules 105, the data of 4 groups of users can be stored in the cache of 4 first storage modules 101 at the receiving end at the same time.

[0071] Optionally, the system further comprises:

[0072] The detection module 106 is used to detect the storage status of multiple second storage modules 104, and when the storage status of any second storage module 104 is full, call a second storage module 104 that is not full to store the data to be decoded read by the polling module 102.

[0073] The present disclosure dynamically allocates the second storage module 104 for data transfer through the detection module 106. For example, in the process of the data to be decoded in the above four first storage modules 101, the polling module 102 takes out the data to be decoded from the four first storage modules 101 and transfers the data to be decoded to the four second storage modules 104, the detection module 106 simultaneously detects the storage status of the four second storage modules 104, and when it is detected that the storage status of any second storage module 104 is full, other second storage modules 104 in non-full status are called to continue to store the data to be decoded. The full status indicates that the data stored in the second storage module 104 has reached the maximum limit.

[0074] Optionally, the system further comprises:

[0075] The sending module 107 is used to send the data decoded by the decoding module 103.

[0076] In the disclosed embodiment, the data decoded by the decoding module 103 can be sent to the PCIe interface (peripheral component interconnect express) through the sending module 107. PCIe is a high-speed serial point-to-point dual-channel high-bandwidth transmission. The connected devices are allocated exclusive channel bandwidth and do not share bus bandwidth. It mainly supports active power management, error reporting, end-to-end reliable transmission, hot plugging, and quality of service (QOS) and other functions.

[0077] The decoded data is transmitted to the downstream digital signal processor (DSP) through the PCIe interface to achieve data conversion and assign PCIe addresses. When assigning PCIe addresses, the front-end information is read first, and the total amount of data to be read is obtained based on the front-end information. The bit width of the front-end data can be 128 bits, and the data of one PCIe address can be 64 bits * 16 = 1024 bits = 128 bytes. When the data of one PCIe address is written, the PCIe address is increased by 1.

[0078] According to another aspect of the present disclosure, Figure 2 As shown, the present disclosure provides a data decoding method, comprising:

[0079] Step S202, calling multiple first storage modules to store data to be decoded;

[0080] Step S204, calling the polling module to determine in parallel whether the plurality of first storage modules are not empty, and calling the polling module to read the data to be decoded from the first storage modules that are not empty;

[0081] Step S206, calling multiple decoding modules to decode the to-be-decoded data read from the polling module.

[0082] In the disclosed embodiment, the data stream in the communication link can be continuously detected, the data packet header can be identified, and the data to be decoded associated with the data packet header can be extracted, and the data to be decoded can be cached in multiple first storage modules. A fair polling method is used to simultaneously determine whether multiple first storage modules are not empty, and non-empty data is read first. If all first storage modules are not empty, the data to be decoded can be read in a first-in-first-out order, and finally, multiple decoding modules built based on FPGA can be used to decode the data to be decoded in parallel.

[0083] Alternatively, if Figure 3 As shown, after calling the polling module to read the to-be-decoded data from the non-empty first storage module, the method further includes:

[0084] Step S302: calling the polling module to transfer the data to be decoded to the second storage module corresponding to each decoding module.

[0085] In the disclosed embodiment, the first storage module provides a first data cache interface, and the first data cache interface is used to cache the data to be decoded associated with the data packet header to the first storage module through the first data cache interface when the data packet header is detected. The second storage module provides a second data cache interface and a data decoding interface, and the second data cache interface is used to transfer the data to be decoded to the second storage module for data decoding. The data decoding interface is used to read the data to be decoded so as to perform parallel decoding using multiple decoding modules.

[0086] Step S304, when calling multiple decoding modules to decode the data to be decoded read from the polling module, the decoding module reads the data to be decoded from the corresponding second storage module.

[0087] Optionally, transferring the to-be-decoded data to a second storage module corresponding to each decoding module includes:

[0088] The detection module is called to detect the storage status of the plurality of second storage modules, and when the storage status of any second storage module is full, a second storage module in a non-full state is called to store the to-be-decoded data read by the polling module.

[0089] In the disclosed embodiment, a corresponding data cache device, i.e., a second storage module, can be set before decoding, and the storage status of multiple second storage modules can be detected in the process of transferring the data to be decoded from multiple first storage modules to multiple second storage modules, so as to dynamically allocate the second storage modules for data transfer according to the storage status of the second storage modules. For example, there are 4 second storage modules, and the storage status of the 4 second storage modules is detected at the same time. When it is detected that the storage status of any second storage module is full, other second storage modules in non-full status are called to continue to store the data to be decoded.

[0090] Optionally, after calling multiple decoding modules to decode the to-be-decoded data read from the polling module, the method further includes:

[0091] The sending module is called to send the data decoded by the decoding module.

[0092] In the disclosed embodiment, the data decoded by the decoding module can be sent to the PCIe interface (Peripheral Component Interconnect Express) through the sending module. PCIe is a high-speed serial point-to-point dual-channel high-bandwidth transmission. The connected devices are allocated exclusive channel bandwidth and do not share bus bandwidth. It mainly supports active power management, error reporting, end-to-end reliable transmission, hot plugging, and quality of service (QOS) and other functions.

[0093] The decoded data is transmitted to the downstream digital signal processor (DSP) through the PCIe interface to achieve data conversion and assign PCIe addresses. When assigning PCIe addresses, the front-end information is read first, and the total amount of data to be read is obtained based on the front-end information. The bit width of the front-end data can be 128 bits, and the data of one PCIe address can be 64 bits * 16 = 1024 bits = 128 bytes. When the data of one PCIe address is written, the PCIe address is increased by 1.

[0094] According to another aspect of the present disclosure, the present disclosure provides an electronic device, such as Figure 4 As shown, it includes a memory 401, a processor 403, a communication interface 405 and a communication bus 407. The memory 401 stores a computer program that can be run on the processor 403. The memory 401 and the processor 403 communicate through the communication interface 405 and the communication bus 407. When the processor 403 executes the computer program, the steps of the above method are implemented.

[0095] The memory and processor in the above electronic device communicate via a communication bus and a communication interface. The communication bus may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus may be divided into an address bus, a data bus, a control bus, etc.

[0096] The memory may include a random access memory (RAM) or a non-volatile memory, such as at least one disk memory. Optionally, the memory may also be at least one storage device located away from the aforementioned processor.

[0097] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0098] According to another aspect of the embodiments of the present disclosure, a computer-readable medium having a non-volatile program code executable by a processor is provided.

[0099] Optionally, in an embodiment of the present disclosure, the computer-readable medium is configured to store program codes for the processor to execute the following steps:

[0100] Calling a plurality of first storage modules to store data to be decoded;

[0101] Calling the polling module to determine in parallel whether the plurality of first storage modules are not empty, and calling the polling module to read the data to be decoded from the first storage modules that are not empty;

[0102] Multiple decoding modules are called to decode the data to be decoded read from the polling module.

[0103] Optionally, the specific examples in this embodiment may refer to the examples described in the above embodiments, and this embodiment will not be described in detail here.

[0104] When the embodiments of the present disclosure are specifically implemented, reference may be made to the above-mentioned embodiments, and corresponding technical effects are achieved.

[0105] It is understood that the embodiments described herein may be implemented in hardware, software, firmware, middleware, microcode, or a combination thereof. For hardware implementation, the processing unit may be implemented in one or more application specific integrated circuits (ASIC), digital signal processors (DSP), digital signal processing devices (DSPD), programmable logic devices (PLD), field programmable gate arrays (FPGA), general purpose processors, controllers, microcontrollers, microprocessors, other electronic units for performing the functions described in the present disclosure, or a combination thereof.

[0106] For software implementation, the technology described herein can be implemented by a unit that performs the functions described herein. The software code can be stored in a memory and executed by a processor. The memory can be implemented in the processor or outside the processor.

[0107] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this disclosure.

[0108] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0109] In the embodiments provided in the present disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0110] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0111] In addition, each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0112] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the embodiment of the present disclosure is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present disclosure. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a ROM, a RAM, a magnetic disk or an optical disk. It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "includes", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements that are not explicitly listed, or also includes elements inherent to such a process, method, article or device. Without more constraints, an element defined by the phrase "comprising a..." does not exclude the existence of other identical elements in the process, method, article or apparatus comprising the element.

[0113] The foregoing is merely a specific embodiment of the present disclosure, which enables those skilled in the art to understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features applied herein.

Claims

1. A data decoding system, characterized in that: include: A plurality of first storage modules, used for storing data to be decoded; A polling module, used for determining in parallel whether a plurality of the first storage modules are not empty, and reading the to-be-decoded data from the first storage modules that are not empty; A plurality of decoding modules, each of which is used to decode the to-be-decoded data read from the polling module through a decoder; A plurality of second storage modules, corresponding one to one with the plurality of decoding modules, each of the second storage modules being used for caching the to-be-decoded data read from the polling module; Each of the decoding modules is specifically used to decode the to-be-decoded data read from the corresponding second storage module through a decoder; The polling module is further used to transfer the to-be-decoded data in the non-empty first storage module to the non-full second storage module; a detection module, configured to detect the storage status of the plurality of second storage modules, and, if the storage status of any of the second storage modules is full, call a second storage module in a non-full state to store the to-be-decoded data read by the polling module; The polling module is formed by integrating a high-speed serial transceiver module; In the polling module, the data to be decoded of the four first storage modules are read out through scheduling rules and written into four non-full second storage modules that are connected one-to-one with multiple decoding modules; the detection module simultaneously detects the storage status of the four second storage modules, and when it is detected that the storage status of any second storage module is full, other non-full second storage modules are called to continue storing the data to be decoded, and the full status indicates that the data stored in the second storage module has reached the maximum limit.

2. The system according to claim 1, characterized in that Data is transmitted between the first storage modules and the polling module, between the polling module and the second storage modules, and between each second storage module and the corresponding decoding module in a first-in-first-out manner.

3. The system according to claim 1, characterized in that The system further comprises: The data receiving module is used to cache the to-be-decoded data associated with the data packet header to the first storage module when a data packet header is detected, and the data receiving module and the plurality of the first storage modules are transmitted data in a first-in-first-out manner.

4. The system according to any one of claims 1 to 3, characterized in that: The system further comprises: The sending module is used to send the data decoded by the decoding module.

5. A data decoding method, characterized in that: include: Calling a plurality of first storage modules to store data to be decoded; Calling a polling module to determine in parallel whether a plurality of the first storage modules are not empty, and calling the polling module to read the to-be-decoded data from the first storage modules that are not empty; Calling multiple decoding modules to decode the to-be-decoded data read from the polling module through a decoder; Calling a plurality of second storage modules, corresponding one-to-one to the plurality of decoding modules, and calling the second storage modules to cache the to-be-decoded data read from the polling module; Calling the decoding module to decode the to-be-decoded data read from the corresponding second storage module through a decoder; Calling the polling module to transfer the to-be-decoded data in the non-empty first storage module to the non-full second storage module; Calling a detection module to detect storage status of a plurality of second storage modules, and when the storage status of any second storage module is full, calling a second storage module in a non-full state to store the to-be-decoded data read by the polling module; The polling module is formed by integrating a high-speed serial transceiver module; The polling module is called to read the data to be decoded of the four first storage modules and write them into four non-full second storage modules that are connected one-to-one with multiple decoding modules through scheduling rules; the detection module simultaneously detects the storage status of the four second storage modules, and when it is detected that the storage status of any second storage module is full, other non-full second storage modules are called to continue storing the data to be decoded, and the full status indicates that the data stored in the second storage module has reached the maximum limit.

6. The method according to claim 5, characterized in that After calling the polling module to read the to-be-decoded data from the non-empty first storage module, the method further includes: Calling the polling module to transfer the data to be decoded to the second storage module corresponding to each decoding module; When calling the plurality of decoding modules to decode the data to be decoded read from the polling module, the decoding module reads the data to be decoded from the corresponding second storage module.

7. The method according to claim 6, characterized in that Transferring the to-be-decoded data to a second storage module corresponding to each of the decoding modules comprises: The detection module is called to detect the storage status of multiple second storage modules, and when the storage status of any second storage module is full, the second storage module in a non-full state is called to store the data to be decoded read by the polling module.

8. An electronic device, comprising a memory, a processor, a communication interface and a communication bus, wherein the memory stores a computer program that can be run on the processor, and the memory and the processor communicate through the communication bus and the communication interface, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 5 to 7 are implemented.

9. A computer-readable medium having a non-volatile program code executable by a processor, characterized in that: The program code enables the processor to execute the method according to any one of claims 5 to 7.

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