Apparatus and associated method for a receiver with carrier frequency offset correction using frequency information

Abstract

The present application discloses an apparatus and associated method for a receiver with carrier frequency offset correction using frequency information. An apparatus includes an RF receiver for receiving radio frequency (RF) signals using multiple antennas. The RF receiver includes a demodulator to provide a switching signal so that the RF receiver uses an antenna from the multiple antennas. The RF receiver further includes a carrier frequency offset correction circuit that estimates and removes a carrier frequency offset (CFO).

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is related to U.S. patent application serial number 17 / 138,846, which was filed on December 30, 2020 and is titled "Apparatus for Receiver with Carrier Frequency Offset Correction Using Phase and Frequency Information and Associated Methods." Technical Field

[0003] The present disclosure relates generally to communication devices and associated methods. More particularly, the present disclosure relates to devices for radio frequency (RF), such as RF receivers, with carrier frequency offset (CFO) correction, and associated methods. Background Art

[0004] As technology advances, more and more circuit elements have been integrated into devices such as integrated circuits (ICs). In addition, more and more devices, such as ICs, or subsystems, have been integrated into products. With the development of things such as the Internet of Things (IoT), this trend is expected to continue.

[0005] Some devices, such as IoT devices, operate at least partially wirelessly. In other words, such devices use a radio frequency (RF) receiver (RX) and / or transmitter (TX). As those of ordinary skill in the art will appreciate, RF receivers are often affected by carrier frequency offset (CFO).

[0006] Figure 1 A conventional RF receiver including CFO estimation and removal is shown. Figure 2 Details of a conventional CFO estimation circuit and a conventional CFO removal circuit are shown. Figure 1 and Figure 2 The circuit systems in the embodiment are known to those skilled in the art. Therefore, the details of their operation are understood by those skilled in the art and are therefore not further described herein.

[0007] The description in this section and any corresponding figure(s) are included as background information material. The inclusion of the materials in this section should not be construed as an admission that such materials constitute prior art to the present patent application. Summary of the invention

[0008] According to exemplary embodiments, various devices and associated methods for RF devices are contemplated. According to an exemplary embodiment, a device includes an RF receiver for receiving RF signals using multiple antennas. The RF receiver includes a demodulator to provide a switching signal so that the RF receiver uses one of the multiple antennas. The RF receiver further includes a CFO correction circuit that estimates and removes a carrier frequency offset.

[0009] According to another exemplary embodiment, a device includes an RF receiver for receiving RF signals using multiple antennas. The RF receiver includes a demodulator to provide a switching signal so that the RF receiver uses an antenna from the multiple antennas. The RF receiver further includes: a CFO estimation circuit that uses the switching signal to provide an estimate of a carrier frequency offset; a phase difference removal (PDR) circuit coupled to the CFO estimation circuit; and a CFO removal circuit coupled to the CFO estimation circuit that uses the estimate of the carrier frequency offset to remove the carrier frequency offset.

[0010] According to another exemplary embodiment, a method of correcting CFO in a radio frequency (RF) receiver using multiple antennas includes using a demodulator to provide a switching signal to cause the RF receiver to use an antenna among the multiple antennas, and using a CFO correction circuit to estimate and remove a carrier frequency offset. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings illustrate only exemplary embodiments and should not be considered to limit the scope of the present application or the claimed subject matter. It will be appreciated by those skilled in the art that the disclosed concepts lend themselves to other equivalent embodiments. In the accompanying drawings, the same numerical designations used in more than one figure represent the same, similar or equivalent functions, components or blocks.

[0012] Figure 1 A conventional RF receiver is shown.

[0013] Figure 2 Shows Figure 1 Details of conventional CFO estimation and CFO removal circuitry in conventional RF receivers.

[0014] Figure 3 A graph of the chip phase for a receiver without antenna diversity (single antenna) is shown.

[0015] Figure 4-Figure 5 A graph of chip phase for an RF receiver with antenna diversity is shown in accordance with an exemplary embodiment.

[0016] Figure 6 A circuit arrangement of an RF receiver according to an exemplary embodiment is shown.

[0017] Figure 7A circuit arrangement for CFO correction according to an exemplary embodiment is shown.

[0018] Figure 8A-8B A flow chart for a CFO correction method according to an exemplary embodiment is shown.

[0019] Fig. 9 A graph showing chip phase in an RF receiver according to an exemplary embodiment is shown.

[0020] Fig.10 A circuit arrangement for an RF receiver according to an exemplary embodiment is shown.

[0021] Fig.11 A circuit arrangement for CFO correction according to an exemplary embodiment is shown.

[0022] Figure 12A-12C A flow chart for a CFO correction method according to an exemplary embodiment is shown.

[0023] Fig.13 A circuit arrangement for CFO correction according to an exemplary embodiment is shown.

[0024] Figure 14A-Figure 14C A flow chart for a CFO correction method according to an exemplary embodiment is shown.

[0025] Fig.15 A circuit arrangement for an RF receiver according to an exemplary embodiment is shown.

[0026] Fig.16 A circuit arrangement for CFO correction according to an exemplary embodiment is shown.

[0027] Figure 17A-Figure 17C A flow chart for a CFO correction method according to an exemplary embodiment is shown.

[0028] Fig.18 A system for radio communications according to an exemplary embodiment is shown.

[0029] Fig.19 A circuit arrangement for an IC including an RF receiver is shown according to an exemplary embodiment.

[0030] Fig. 20 A circuit arrangement for an IC including an RF receiver and an RF transmitter is shown according to an exemplary embodiment. DETAILED DESCRIPTION

[0031] The present disclosure generally relates to communication devices and associated methods. More specifically, the present disclosure relates to devices for RF communication, such as RF receivers, with CFO correction, and associated methods related to such devices. In an exemplary embodiment, CFO correction is provided for an RF receiver and / or transceiver using antenna diversity.

[0032] As known to those of ordinary skill in the art, antenna diversity allows a receiver to use more than one antenna. Based on one or more criteria, such as one or more quality metrics or indicators related to the signals received by the RF receiver, the RF receiver may use one antenna from a group of antennas at any given time. As also known to those of ordinary skill in the art, the selection of antennas for the RF receiver may change over time, for example, in response to changes in the one or more quality metrics or indicators described above.

[0033] Conventional RF receivers use a single antenna, e.g. Figure 1 as shown, i.e. they do not use antenna diversity. Figure 3 A graph showing the chip time for such a receiver is shown. Fig.10 More specifically, the curve Fig.10 The receiver's chip phase is shown as a linear function of time, with no discontinuities or "jumps." CFO estimation and removal circuitry can exploit the linear phase as a function of time in a single antenna receiver. The result is a relatively simple CFO estimation and removal scheme.

[0034] However, when two or more antennas are used, i.e., antenna diversity, non-contiguous "segments" of data for each antenna result in a plot of chip phase versus time. (A chip, sometimes called a sample, is a component or segment of a symbol. For example, a symbol consisting of 1010 has four chips of alternating 1s and 0s.) Because multiple antennas are used, there are discontinuities in the chip (or sample) phase versus time function.

[0035] Figure 4-Figure 5 FIG. 1 shows a graph of chip phase for an RF receiver with antenna diversity according to an exemplary embodiment. For example, the RF receiver may be configured Figure 6 , which uses two antennas: antenna 23 and antenna 26. Depending on one or more measures of received signal quality, such as a received signal strength indication (RSSI), receiver 20 may use antenna 23 or antenna 26. In other words, as one or more measures of received signal quality using one antenna decrease, receiver 20 switches to using another antenna, such as antenna 26. Switching between antennas may occur multiple times as a function of time.

[0036] refer to Figure 4, the graph of chip phase as a function of time includes segment 13 and segment 16. Segment 13 corresponds to the chip phase using one antenna (e.g., antenna 23), and segment 16 corresponds to the chip phase using another antenna (e.g., antenna 26). As part of the CFO correction, RF receiver 20 uses the segment from the antenna that provides the better metric(s) of received signal quality.

[0037] For example, Figure 5 As shown, segment 16 may be used. Figure 5 A graph of the chip phase as a function of the splicing time for segment 16 is shown. In other words, Figure 4 Segment 13 is removed and segment 16 is joined to obtain Figure 5 The chip phase curve in Figure 1 is shown in Figure 2. The splicing (removing segment 13 and joining segments 16 together) causes Figure 5 The term "antenna switch" refers to switching relative to the splicing time rather than the normal time. In other words, Figure 5 In FIG. 1 , two such switches / switches are shown, which correspond to chip phase discontinuities, ie two discontinuities between segments 16 .

[0038] Since frequency is the derivative of phase with respect to time, differences in the characteristics of the reference crystal and other non-idealities can cause carrier frequency offset (CFO). This phenomenon is further exacerbated in the presence of noisy phase values. CFO can cause various undesirable results. For example, CFO can cause the +1 symbol, which is normally at the +1 point on the unit circle, to rotate around the unit circle. Other effects of CFO are understood by those of ordinary skill in the art and will not be discussed further.

[0039] When switching antennas in an antenna diversity receiver, as described above, the multi-symbol sequence of a chip consists of multiple discontinuous intervals. To correct the CFO in this case, in an exemplary embodiment, the CFO parameters are calculated relatively reliably. Ideally, the CFO calculation accuracy will not be a limiting factor in the sensitivity of the RF receiver. In the case of antenna diversity, these CFO correction techniques provide sensitivity vs. frequency offset curves within a fraction of a decibel of the ideal non-CFO case.

[0040] Devices and methods according to various embodiments provide CFO correction, as described above. CFO correction according to exemplary embodiments is effective when the phase measurements for each in-phase (I) and quadrature (Q) sample in the RF receiver are noisy. In such cases, simpler schemes (e.g., those for single antenna systems) may fail completely, or may not work, or may not work well with a phase-locked loop (PLL) with an accuracy or precision of 20 parts per million (20 ppm) or worse.

[0041] The noise phase value is often significant in some special applications, such as Internet of Things (IoT) devices (e.g., ICs) and systems. Such systems often have relatively strict constraints on both power consumption and cost. Using CFO correction techniques according to various embodiments in such systems provides advantages over traditional methods.

[0042] In an exemplary embodiment, the discontinuity of the phase is estimated and removed separately. Thus, the CFO correction in such an embodiment uses two separate loops, rather than one loop as conventionally used. The following description provides an example of such an embodiment.

[0043] Figure 6 A circuit arrangement for an RF receiver 20 according to an exemplary embodiment is shown. The RF receiver 20 includes a CFO correction circuit system, as described in detail below. The RF receiver 20 uses two antennas 23 and 26 respectively via a switch / switch 29. The switch 29 is controlled by a demodulator circuit 59, i.e., via a control signal provided by the demodulator 59, the switch 29 provides a signal received by the antenna 23 or the antenna 26 to a low noise amplifier (LNA) 32. The selection of the antenna can be made as described above, i.e., based on one or more criteria, such as one or more quality metrics or indicators related to the signal received by the RF receiver.

[0044] LNA 32 amplifies the signal received by switch 29. The amount of amplification depends on a gain signal provided by automatic gain control (AGC) circuit 62. LNA 32 provides the amplified signal to IQ mixer 38. The IQ mixer mixes the amplified signal with a local oscillator (LO) signal from LO circuit 35 to generate a down-converted signal.

[0045] The down-converted signal is provided to a programmable gain amplifier (PGA) circuit 41. In response to a gain signal from an AGC circuit 62, the PGA circuit 41 amplifies the down-converted signal to generate an input signal for an IQ analog-to-digital converter (ADC) circuit 44.

[0046] The ADC circuit 44 converts the IQ signal from the PGA circuit 41 into a digital IQ signal. The digital IQ signal is provided to the decimation, filtering and sample rate conversion (SRC) circuit 50, which, as the name implies, performs decimation, filtering and SRC operations on the signal received from the ADC circuit 44. The details of the decimation, filtering and SRC operations depend on various factors, such as the design and operating specifications of a given application, cost, complexity, modulation scheme, frequency plan, etc., as will be understood by those of ordinary skill in the art.

[0047] The CFO correction circuit 52 in the RF receiver 20 includes a CFO estimation circuit 53 and a CFO removal circuit 56. The output of the decimation, filtering and SRC (DFS) circuit 50 feeds the input of the CFO correction circuit 52. The output of the CFO estimation circuit 53 feeds the input of the CFO removal circuit 56, and the output of the CFO removal circuit 56 drives the input of the demodulator circuit 59 (as described in detail below).

[0048] As described below, CFO estimation circuit 53 provides an estimate of the CFO to CFO removal circuit 56 in response to a control signal from demodulator 59. The control signal provides the antenna or chip phase switching point (see Figure 4-Figure 5 ).

[0049] CFO removal circuit 56 removes (or nearly removes, in a practical implementation with non-ideal circuitry, as will be appreciated by one of ordinary skill in the art) the CFO. In other words, one of the design goals of CFO estimation circuit 53 and CFO removal circuit is to make the multi-antenna case (see Figure 5 ) looks similar to the single antenna case (see Figure 3 )similar.

[0050] Figure 7 1 shows a circuit arrangement for a CFO correction circuit 52 according to an exemplary embodiment. More specifically, the diagram shows Figure 6 The CFO estimation circuit 53 and CFO removal circuit 56 used in the receiver of FIG. 5 make the multi-antenna case look similar to the single antenna case by removing the "jumps" or discontinuities (see, for example, Figure 5 ).

[0051] Reference again Figure 7 , CFO removal circuit 80 includes a multiplier 80 that receives I and Q (IQ_IN) signals provided from decimation, filtering and SRC (DFS) circuit 50 to CFO correction circuit 52. Multiplier 80 multiplies the output of D-latch 98 (described below) with the IQ_IN signal to generate an output I and Q (IQ_OUT) signal. The IQ_OUT signal is provided to demodulator 59 (see Figure 6 ).

[0052] Reference again Figure 7 , the demodulator 59 provides control signals to various blocks in the CFO correction circuit 52 via the register block 137. For example, the demodulator 59 provides control signals to the derotator 83, the demultiplexer (DeMUX) 86, and the averaging circuit 128 via the register block 137. The control signal from the demodulator 59 indicates, for example, a switching point from one antenna to another, for example, from antenna 23 to antenna 26 (see Figure 6 ). Note that averaging refers to the sum of the N elements divided by N, where N represents a positive integer greater than 1. The derotator essentially adds / subtracts a fixed sequence of phases (determined by the specifications of a given wireless standard or protocol under which the RF receiver operates) so that all chips have ideally the same phase.

[0053] Reference again Figure 7 , the output of multiplier 80 is fed to derotator 83 in CFO estimation circuit 53. Derotator 83 ensures that all chips have the same phase (or nearly the same phase in actual real-life implementations) regardless of the effects of CFO. In response to a control signal from demodulator 59 (provided via register block circuit 137), DeMUX 86 provides the output of derotator 83 to averaging circuit 89, averaging circuit 107, or averaging circuit 116, depending on which bin the CFO estimation is performed for using a particular antenna. The register block holds configuration information and control signals from demodulator 59 and provides those signals to various blocks in CFO estimation circuit 53.

[0054] Averaging circuits 89, 107, and 116 are part of three branches or loops in CFO estimation circuit 53, each of which includes phase averaging, followed by phase-to-frequency conversion, followed by frequency averaging. In the first branch, averaging circuit 89 averages the phase output signal of derotator 83 and provides the resulting signal to multiplier 95.

[0055] The averaging performed by averaging circuit 89 (and similarly by averaging circuits 107 and 116) improves the signal-to-noise ratio (SNR) of the phase samples. Multiplier 95, together with delay circuit 92, provides phase to frequency conversion. The frequency output signal of multiplier 95 is provided to averaging circuit 101. Averaging circuit 101 provides averaging of the frequency values ​​and provides a CFO value, CFO1.

[0056] The second branch (phase averaging circuit 107, phase to frequency converter (multiplier 110 and delay circuit 104), and frequency averaging circuit 113 operate similarly to provide a CFO value, CFO2. Finally, the third branch (phase averaging circuit 116, phase to frequency converter (multiplier 122 and delay circuit 119), and frequency averaging circuit 125 operate similarly to provide a CFO value, CFO3.

[0057] The CFO1, CFO2, and CFO3 values ​​correspond to the time period when a particular antenna is used. Fig. 9 Again, refer to Figure 7 , the number of phase and / or frequency samples averaged by the averaging circuit in three branches, for example, can be configured or programmed by the demodulator 59 or a controller, etc. As will be appreciated by one of ordinary skill in the art, other numbers of circuit branches, such as two or more than three, may be used depending on factors such as design and performance specifications, cost, target performance, target market, etc.

[0058] The outputs of the three branches, ie the outputs of frequency averaging circuits 101, 113 and 123, are respectively provided as inputs to an averaging circuit 128. Under the control of the demodulator 59, via a register block 137, the averaging circuit 128 improves the SNR of the frequency samples.

[0059] A coordinate rotation digital computer (Cordic) 131 converts the IQ samples from the averaging circuit 128 into frequency samples and then creates IQ samples with an estimated constant frequency. The exponentiation block 134 converts the phase increment received from the CORDIC 131 into a complex vector of phase increments. As desired, the exponentiation block 134 can be implemented using a CORDIC. In other words, for each phase Ph, the CORDIC calculates Exp(i*Ph)=cos(Ph)+i*sin(Ph), where i is an imaginary unit or the square root of -1. In an exemplary embodiment, as desired, the exponentiation block 134 can be implemented using a CORDIC.

[0060] The output of the exponentiation block 134 (the rotation coefficient) is provided to the D-latch 98. A clock signal labeled "iteration CLK" clocks the latch 98 (a demodulator or controller (not shown) may provide a clock signal to the latch 98). The output of the latch 98 is provided as an input to the multiplier 80. Before each latch 98 is clocked, the demodulator 59, via the register block 137, increases the level of filtering by increasing the number of averaging operations performed by the averaging circuit 128, i.e., by increasing N.

[0061] Figure 8A-B A flow chart of a CFO correction method according to an exemplary embodiment is shown. More specifically, Figure 8A-8BExplained Figure 6-Figure 7 Flowchart of an exemplary embodiment of Fig. 8A , at 153, by an RF receiver (e.g., Figure 6 At 156, the CFO is estimated and stored (e.g., Fig. 9 CFO1 in.

[0062] At 159, a check is made as to whether the antenna switch count exceeds a threshold value N, where N represents a positive integer. If not, control returns to 156. However, if the count exceeds N, the CFO is averaged at 162 and removed at 165. Note that the number of antenna switches multiplied by the switch time cannot exceed the preamble time. Thus, just as an example, in the case of the Zigbee specification, there are 8 zero symbols in the preamble. If each switch duration is 1 symbol, then 8 / (number of antennas) is the absolute maximum value of N, and the switch counter will determine when to exit the loop.

[0063] Figure 8B Shown in Fig. 8A The CFO details are estimated and stored at 156. Figure 8B At 156A, IQ symbol derotation is performed. At 156B, fixed phase averaging is performed. At 156C, frequency is derived from the phase samples. At 156D, frequency averaging is performed.

[0064] Fig.10 A circuit arrangement for an RF receiver 20 according to an exemplary embodiment is shown. Fig.10 The RF receiver 20 in the Figure 6 The RF receiver 20 in FIG. 1 is different from the RF receiver 20 in FIG. 1 , but is different in the CFO correction circuit 52. Fig.10 The CFO correction circuit includes a CFO estimation circuit 53, a CFO removal circuit 56 and a phase increment (delta) removal or phase difference removal (PDR) circuit 175.

[0065] Fig.11 A circuit arrangement for CFO correction according to an exemplary embodiment is shown. More specifically, Fig.11 Shows Fig.10 The details of the CFO correction circuit 52 in FIG. Fig.11 , CFO removal circuit 56 and Figure 7 Same as shown.

[0066] also, Fig.11 The CFO estimation circuit 53 in is similar to Figure 7 However, in Fig.11 In the embodiment, a branch or loop is used (rather than Figure 7More specifically, Fig.11 The examples in this paper use Figure 7 In the first branch shown in FIG. 1 , the averaging circuit 101 is omitted.

[0067] In addition, like Figure 7 The exponentiation circuit 134 is used as in FIG. Figure 7 The embodiments in the examples are different. Fig.11 The output of CORDIC 131 drives the input of PDR circuit 175 .

[0068] The PDR circuit 175 includes a DeMUX 178 that receives the output of the CORDIC 131. The DeMUX 176 provides its input signal to a multiplier 178 or a multiplexer (MUX) 181 in response to a control signal provided via a register block 137 from a demodulator (not shown).

[0069] If the input signal of DeMUX 176 is provided to multiplier 178, then multiplier 178 multiplies the frequency samples by 32, which represents the number of chips per symbol. However, as will be appreciated by one of ordinary skill in the art, in other embodiments, the number of chips per symbol may be different than 32, depending on factors such as design and performance specifications. Furthermore, the multiplication by 32 assumes that the antenna is switched for each symbol, so in the case of the Zigbee example discussed above, every 32 chips.

[0070] As another option, DeMUX 176 provides its input signal to MUX 181 without modification, depending on the control signal from register block 137. In practice, DeMUX circuit 176 determines whether to use the unmodified frequency samples or the frequency samples that have been multiplied by the number of chips per symbol.

[0071] In response to a control signal from a demodulator (not shown) provided via register block 137, MUX 181 provides one of its input signals to exponentiation circuit 134. As described above, exponentiation block 134 may be implemented using a CORDIC as desired.

[0072] Figure 12A-12C A flow chart of a CFO correction method according to an exemplary embodiment is shown. More specifically, Figure 12A-12C Shown for Figure 10-11 Flowchart of CFO correction in an exemplary embodiment of the present invention.

[0073] refer to Fig. 12A , at 153, by an RF receiver (e.g., Fig.10 At 203, the CFO is estimated and stored (e.g., Fig. 9At 206, the phase difference is removed. At 209, non-constant frequency removal is performed. At 212, it is checked whether the iteration count exceeds a threshold value N, where N represents a positive integer. If not, control returns to 203. However, if the count exceeds N, the CFO correction ends.

[0074] Fig. 12B Shown in Fig. 12A The details of the CFO are estimated and stored at 203. Fig. 12B At 203A, IQ symbol derotation is performed. At 203B, fixed phase averaging is performed. At 203C, frequency is derived from the phase samples. At 203D, frequency averaging is performed. Fig. 12C Shown in Fig. 12A The details of the phase difference are removed at 206.

[0075] At 206A, a check is made as to whether the iteration count is equal to the number of chips per antenna switching time, i.e., (32) in the case of a switch per symbol for the Zigbee example. If so, the frequency samples are multiplied by the number of chips per symbol (e.g., 32). If not, control passes to 206C, where the results are combined. At 206D, a check is made as to whether the iteration count exceeds the total number of chips. If so, the process continues (e.g., to Fig. 12A 209 in the example), otherwise control returns to 206A.

[0076] Fig.10 The RF receiver 20 shown in FIG. Fig.11 0047] The CFO correction circuit 52 other than the exemplary embodiment shown in FIG. Fig.13 A block diagram of such an alternative CFO correction circuit 52 is shown. Fig.13 The CFO removal circuit in Fig.11 The same as shown in and described above.

[0077] The CFO estimation circuit 53 is similar to Fig.11 The corresponding circuit shown in Fig.13 In the embodiment of FIG. 1 , a PDR circuit 175 (described in detail below) is coupled between the output of multiplier 95 and the input of averaging circuit 128. More specifically, the output of multiplier 95 feeds the input of PDR circuit 175, and the output of PDR circuit 175 feeds the input of averaging circuit 128.

[0078] Although the PDR circuit 175 operates on frequency samples, functionally, the PDR circuit 175 performs phase difference removal. Phase difference removal includes zeroing some frequency samples (via binary 0 inputs to MUX 220). The PDR circuit 175 includes a counter 223 and a MUX 220. One input of the MUX 220 receives a binary logic 0 level. Another input of the MUX 220 receives the output of the multiplier 95.

[0079] Counter 223 provides a selection or control signal for MUX 220. More specifically, counter 223 counts in response to a clock signal labeled "Sample CLK" under the control of demodulator 59 via register block 137. Counter 223 is programmed by register block 134, since the position at which Sample is zeroed (set to zero by virtue of a binary 0 input to MUX 220) depends on the antenna switch (e.g., Fig.10 The position of switch 29 in the CFO correction circuit 52 and the current iteration number (the number of times the information has been processed by the loop in the CFO correction circuit 52).

[0080] Basically, the PDR circuit 175 zeroes some of the frequency samples (by virtue of a binary 0 being applied to the input of the MUX 220). More specifically, via a select signal from the demodulator 59 (provided via register block 134), the MUX 220 provides a binary 0 as its output when there is a "jump" or discontinuity. The counter 223 is programmed by the register block 137, as the position at which the samples are zeroed depends on the position of the antenna switch, and the number of iterations (how many cycles of the "iteration CLK" signal have been applied to the latch 98). The demodulator 59 provides both of these quantities to the register block 137.

[0081] Figure 14A-Figure 14C A flow chart of a CFO correction method according to an exemplary embodiment is shown. More specifically, Figure 14A-Figure 14C Shown for Fig.10 and Fig.13 Flowchart of CFO correction in an exemplary embodiment of the present invention.

[0082] refer to Fig.14A , at 153, by an RF receiver (e.g., Fig.10 The receiver in the receiver detects the packet. At 223, an initial frequency calculation is performed. At 236, the antenna switch value is zeroed (set to 0, as described above). More specifically, the differential phase value (frequency value) is calculated, and the value corresponding to the transition is zeroed. At 239, the CFO is estimated and stored.

[0083] At 242, it is checked whether the iteration count exceeds a threshold value N, where N represents a positive integer. If so, the CFO correction ends. Otherwise, control is passed to 248, where the zero point is changed. Thereafter, at 245, the number of averaging operations M is increased, where M represents a positive integer, and control returns to 233.

[0084] Fig. 14B Shown in Fig.14A Details of the initial frequency calculations performed at 233 in . Fig. 14B At 233A, the chips are derotated. At 233B, an M-sample phase averaging operation is performed. At 233C, a frequency value is derived from the phase samples.

[0085] Fig. 14C Shown in Fig.14A Detail of the CFO estimation and removal performed at 239 in FIG. 2. At 239A, frequency averaging is performed. At 239B, constant frequency removal is performed.

[0086] Fig.15 A circuit arrangement for an RF receiver 20 according to an exemplary embodiment is shown. Fig.15 The RF receiver 20 in the Fig.10 The RF receiver 20 in FIG. 1 is different from the RF receiver 20 in FIG. 1 , but is different in the CFO correction circuit 52. Fig.15 The CFO correction circuit includes a CFO estimation circuit 53, a CFO removal circuit 56, a PDR circuit 262 and a phase increment estimation or phase difference estimation (PDE) circuit 260.

[0087] Fig.16 A circuit arrangement for CFO correction according to an exemplary embodiment is shown. More specifically, Fig.16 Shows Fig.15 The details of the CFO correction circuit 52 in FIG. Fig.16 , CFO removal circuit 56 and Figure 7 Same as shown.

[0088] also, Fig.16 The CFO estimation circuit 53 in is similar to Figure 7 However, in Fig.16 In the embodiment, a branch or loop is used (rather than Figure 7 More specifically, Fig.16 The examples in this paper use Figure 7 The first branch shown in FIG. 1 omits the averaging circuit 101, the derotator 83 and the DeMUX 86. Therefore, Fig.16The CFO estimation circuit 53 in EMBODIMENT 1 includes a phase averaging circuit 279 , a phase-to-frequency converter circuit (including a multiplier 285 and a delay circuit 282 ), a frequency averaging circuit 288 , a CORDIC 131 , and an exponentiation circuit 134 .

[0089] Reference again Fig.16 , PDE circuit 260 is similar to CFO estimation circuit 53, but has the following differences. First, the second averaging circuit (averaging circuit 288 in CFO estimation circuit 53) is not used. Second, instead of one branch or loop in CFO estimation circuit 53, PDE circuit 260 uses two branches or loops, i.e., two circuit branches, which operate and modify the output of derotator 83 provided by MUX 86 (in response to control signals from register block 137) and provide the result to PDR circuit 262. MUX 86 also provides the output of derotator 83 to PDR circuit 262 (in response to control signals from register block 137). The first branch includes averaging circuit 89A, multiplier 95A, delay circuit 92A, CORDIC 131A, and exponentiation circuit 134A. The second branch includes averaging circuit 89B, multiplier 95B, delay circuit 92B, CORDIC 131B, and exponentiation circuit 134B.

[0090] Third, DeMUX 86 receives the output of derotator 83 and provides it to one of the two branches (via register block 134) under the control of demodulator 59. Derotator 83 receives its input from the output of multiplier 80. Fourth, the phase-to-frequency converter in each of the first branch and the second branch operates on k samples rather than a fixed number of samples (hence the use of notation Zk for delay circuits 92A and 92B) in response to control signals 137D and 137C, respectively (provided by demodulator 59 via register block 137).

[0091] PDR circuit 262 is similar to CFO removal circuit 56 , but with the following differences: First, PDR circuit 262 uses MUX 276 , which provides one of its three input signals to CFO estimation circuit 53 under the control of demodulator 59 (via register block 134 ).

[0092] Second, the two multipliers, 273A and 273B, of PDR circuit 262. Multiplier 273A multiplies the output of exponentiation circuit 134A with the output of multiplier 273B and provides the resulting output to MUX 276. Multiplier 273B multiplies the output of exponentiation circuit 134B with the output of derotator 83 (as provided by DeMUX 86) and provides the resulting output to MUX 276 as a second input.

[0093] Finally, the output of derotator 83 (as provided by DeMUX 86) drives the third input of MUX 276. The three inputs of MUX 276 correspond to three intervals, the first interval corresponds to the output of derotator 83 without any modification, the second interval has been rotated once (the output of multiplier 273B), and the third interval has been rotated twice (the output of multiplier 273A). As will be appreciated by those of ordinary skill in the art, other numbers of circuit branches may be used, depending on factors such as design and performance specifications, cost, target performance, target market, etc.

[0094] Figure 17A-Figure 17C A flow chart of a CFO correction method according to an exemplary embodiment is shown. More specifically, Figure 17A-Figure 17C Shown for Figure 15-16 Flowchart of CFO correction in an exemplary embodiment of the present invention.

[0095] refer to Fig.17A , at 153, by an RF receiver (e.g., Fig.15 The receiver in the receiver detects the packet. At 303, IQ symbol derotation is performed. At 309, the phase difference is estimated and removed. At 312, the CFO is estimated and stored.

[0096] At 315 , it is checked whether the iteration count exceeds a threshold value N, where N represents a positive integer. If so, the CFO correction ends. Otherwise, control is passed to 306 , where the number of averaging operations (M and N) is increased, and control is passed to 303 .

[0097] Fig. 17B Shown in Fig.17A Details of the estimation and removal of the phase difference performed at 309 are shown in FIG. Fig. 17B At 309A, the phase difference is calculated as the mean (or average) phase of the N samples after the antenna switching point minus the mean (or average) phase of the N samples before the antenna switching point.

[0098] At 309B, a constant phase removal operation is performed. At 309C, a check is performed to see if the iteration count exceeds the number of antenna switches. If so, control is passed to 312 (see Fig.17A ), otherwise, control returns to 309A (ie, another iteration is performed).

[0099] Fig. 17C Shown in Fig.17A Details of the estimation and removal of CFO performed at 312 are provided in FIG. Fig. 17B At 312A, M sample phase averaging is performed. At 312B, a frequency value is derived from the averaged phase value. At 312C, an averaging operation is performed on the frequency value. At 312D, constant frequency removal is performed.

[0100] Receivers according to example embodiments may be used in various communication arrangements, systems, subsystems, networks, etc., as desired. Fig.18 A system 500 for radio communication according to an exemplary embodiment is shown. The system comprises an RF receiver 5, as described above.

[0101] System 500 includes a transmitter 515 coupled to antenna 10A. Via antenna 10A, transmitter 515 transmits an RF signal. The RF signal may be received by receiver 20B via antenna 10B. Additionally or alternatively, transceiver 520A and / or transceiver 520B may receive the transmitted RF signal (via receivers 20C and 20D, respectively).

[0102] In addition to the receiving capability, transceiver 520A and transceiver 520B may also transmit RF signals. The transmitted RF signals may be received by receiver 20, either in a separate receiver (20B) or via the receiver circuitry of a non-transmitting transceiver (20C or 20D).

[0103] Other systems or subsystems having different configurations and / or capabilities are also contemplated. For example, in some exemplary embodiments, two or more transceivers (e.g., transceiver 520A and transceiver 520B) may form a network, such as an ad-hoc network or a mesh network. As another example, in some exemplary embodiments, transceiver 520A and transceiver 520B may form part of a network, e.g., in conjunction with transmitter 515.

[0104] RF receivers, such as the RF receiver 20 described above, can be used in various circuits, blocks, subsystems and / or systems. For example, in some embodiments, such RF receivers can be integrated in an IC, such as a microcontroller unit (MCU). Fig.19 A block diagram of IC 550 is shown according to an exemplary embodiment.

[0105] Fig. 20 Similar to Fig.19 , and shows an IC 550 which includes an RF transmitter 515 in addition to the RF receiver 5. Thus, Fig. 20 The embodiments in have RF transceiver capability.

[0106] refer to Fig.19, IC 550 constitutes or includes an MCU. IC 550 includes several blocks (e.g., processor(s) 565, data converter 605, I / O circuitry 585, etc.) that communicate with each other using link 560. In an exemplary embodiment, link 560 may constitute a coupling mechanism, such as a bus, a set of conductors or semiconductor elements (e.g., traces, devices, etc.), for transmitting information, such as data, commands, status information, etc.

[0107] IC 550 may include a link 560 coupled to one or more processors 565, clock circuitry 575, and power management circuitry or power management unit (PMU) 580. In some embodiments, processor(s) 565 may include circuitry or blocks for providing information processing (or data processing or computing) functions, such as a central processing unit (CPU), an arithmetic logic unit (ALU), etc. In some embodiments, in addition, or as an alternative, processor(s) 565 may include one or more DSPs. The DSP may provide various signal processing functions, such as arithmetic functions, filtering, delay blocks, etc., as desired.

[0108] Clock circuitry 575 may generate one or more clock signals that facilitate or control the timing of operations of one or more blocks in IC 550. Clock circuitry 575 may also desirably control the timing of operations using link 560. In some embodiments, clock circuitry 575 may provide one or more clock signals to other blocks in IC 550 via link 560.

[0109] In some embodiments, PMU 580 may reduce the clock speed, shut down the clock, reduce power, shut down the power supply, disable (or power off or put in a lower power consumption or sleep or inactive or idle state), enable (or power on or put in a higher power consumption or normal or active state), or any combination of the above for a device (e.g., IC 550) with respect to a portion of or all components of a circuit, such as one or more blocks in IC 550. In addition, PMU 580 may turn on the clock, increase the clock rate, turn on the power supply, increase the power, or any combination of the above in response to a transition from an inactive state to an active state, including but not limited to when (one or more) processors 565 transition from a low power or idle or sleep state to a normal operating state.

[0110] Link 560 may be coupled to one or more circuits 600 via serial interface 595. One or more circuits or blocks coupled to link 560 may communicate with circuit 600 via serial interface 595. Circuit 600 may communicate using one or more serial protocols, such as SMBUS, I 2 C, SPI, etc., as will be understood by one of ordinary skill in the art.

[0111] Link 560 may be coupled to one or more peripherals 590 through I / O circuitry 585. Through I / O circuitry 585, one or more peripherals 590 may be coupled to link 560 and may therefore communicate with one or more blocks coupled to link 560, e.g., processor(s) 565, memory circuitry 625, etc.

[0112] In an exemplary embodiment, peripherals 590 may include various circuit systems, blocks, etc. Examples include I / O devices (keypads, keyboards, speakers, display devices, storage devices, timers, sensors, etc.) Note that in some embodiments, some peripherals 590 may be external to IC 550. Examples include keypads, speakers, etc.

[0113] In some embodiments, I / O circuitry 585 may be bypassed with respect to some peripherals. In such embodiments, some peripherals 590 may be coupled to link 560 and communicate therewith without using I / O circuitry 585. In some embodiments, such peripherals may be external to IC 550, as described above.

[0114] Link 560 may be coupled to analog circuitry 620 via data converter(s) 605. Data converter(s) 605 may include one or more ADCs 605A and / or one or more DACs 605B.

[0115] ADC(s) 605A receive(s) analog signal(s) from analog circuitry 620 and convert the analog signal(s) to digital format, which they pass to one or more blocks coupled to link 560. Conversely, DAC(s) 605B receive(s) digital signal(s) from one or more blocks coupled to link 560 and convert the digital signal(s) to analog format, which they pass to analog circuitry 620.

[0116] Analog circuitry 620 may include various circuitry that provides and / or receives analog signals. Examples include sensors, transducers, etc., as will be understood by one of ordinary skill in the art. In some embodiments, analog circuitry 620 may communicate with circuitry external to IC 550 to form more complex systems, subsystems, control blocks or systems, feedback systems, and information processing blocks as desired.

[0117] Control circuitry 570 is coupled to link 560. Thus, control circuitry 570 can communicate with and / or control the operation of various blocks coupled to link 560 by providing control information or signals. In some embodiments, control circuitry 570 also receives status information or signals from various blocks coupled to link 560. Furthermore, in some embodiments, control circuitry 570 facilitates (or controls or supervises) communication or cooperation between various blocks coupled to link 560.

[0118] In some embodiments, control circuit system 570 may initiate or respond to a reset operation or signal. The reset operation may cause a reset of one or more blocks of IC 550 coupled to link 560, etc., as will be understood by one of ordinary skill in the art. For example, control circuit system 570 may cause PMU 580, as well as circuit systems such as RF receiver 5 or its various blocks, circuits or components, to reset to an initial or known state.

[0119] In an exemplary embodiment, control circuitry 570 may include circuitry of various types and blocks. In some embodiments, control circuitry 570 may include logic circuitry, a finite state machine (FSM), or other circuitry to perform operations such as those described above.

[0120] Communications circuitry 640 is coupled to link 560 and also to circuitry or blocks (not shown) external to IC 550. Through communications circuitry 640, various blocks coupled to link 560 (or IC 550, generally) can communicate with external circuitry or blocks (not shown) via one or more communications protocols. Examples of communications include USB, Ethernet, etc. In exemplary embodiments, other communications protocols may be used, depending on factors such as design or performance specifications for a given application, as will be understood by one of ordinary skill in the art.

[0121] As described above, memory circuit 625 is coupled to link 560. Thus, memory circuit 625 may communicate with one or more blocks coupled to link 560, such as processor(s) 565, control circuitry 570, I / O circuitry 585, and the like.

[0122] Memory circuit 625 provides storage for various information or data in IC 550, such as operands, flags, data, instructions, etc., as will be understood by one of ordinary skill in the art. Memory circuit 625 may support various protocols as desired, such as double data rate (DDR), DDR2, DDR3, DDR4, etc.

[0123] In some embodiments, memory read and / or write operations through memory circuit 625 involve the use of one or more blocks in IC 550, such as (one or more) processors 565. A direct memory access (DMA) arrangement (not shown) allows for improved performance of memory operations in some cases. More specifically, DMA (not shown) provides a mechanism for performing memory read and write operations directly between the source or destination of data and memory circuit 625, rather than through a block, such as (one or more) processor 565.

[0124] The memory circuit 625 may include various memory circuits or blocks. In the illustrated embodiment, the memory circuit 625 includes a non-volatile (NV) memory 635. In addition or in lieu thereof, the memory circuit 625 may include a volatile memory (not shown), such as a random access memory (RAM). The NV memory 635 may be used to store information related to the performance, control, or configuration of one or more blocks in the IC 550. For example, the NV memory 635 may store configuration information related to the operation of the RF receiver 20, such as configuration information for various blocks, circuits, components, etc. of the RF receiver 20.

[0125] RF receiver 20 is coupled to link 560. Through link 560, RF receiver 20 may receive control and / or status information from one or more blocks in IC 550. Conversely, through link 560, RF receiver 20 may provide information, such as control and / or status information, as well as information received via RF signals via antenna 10.

[0126] The various circuits and blocks including the digital and / or mixed signal circuit systems described above and used in the exemplary embodiments may be implemented in various ways and using various circuit elements or blocks. For example, the ADC 35, the decimation, filtering and SRC (DFS) circuit 50, the CFO correction circuit system 52 (including the CFO estimation circuit, the CFO removal circuit, the PDE circuit and the PDR circuit), the demodulator 59, etc. may generally be implemented using digital circuit systems. As desired and as will be understood by one of ordinary skill in the art, the digital circuit system may include circuit elements or blocks such as gates, digital multiplexers (MUXs), latches, flip-flops, registers, finite state machines (FSMs), processors, programmable logic (e.g., field programmable gate arrays (FPGAs) or other types of programmable logic), arithmetic logic units (ALUs), standard cells, custom cells, custom analog cells, etc. In addition, as desired, analog circuit systems or mixed signal circuit systems or both may be included, such as power converters, discrete devices (transistors, capacitors, resistors, inductors, diodes, etc.), etc. As desired and as will be understood by one of ordinary skill in the art, analog circuitry may include bias circuits, decoupling circuits, coupling circuits, power supply circuits, current mirrors, current and / or voltage sources, filters, amplifiers, converters, signal processing circuits (e.g., multipliers), detectors, transducers, discrete components (transistors, diodes, resistors, capacitors, inductors), analog MUXs, etc. As described above and as will be understood by one of ordinary skill in the art, in addition to analog circuitry and digital circuitry, mixed signal circuitry may include analog-to-digital converters (ADCs), digital-to-analog converters (DACs), etc. For a given implementation, the selection of circuitry depends on various factors, as will be understood by one of ordinary skill in the art. Such factors include design specifications, performance specifications, cost, IC or device area, available technology such as semiconductor manufacturing technology, target market, target end user, etc.

[0127] Various circuits and blocks including the analog circuitry described above and used in the exemplary embodiments may be implemented in various ways and using various circuit elements or blocks. For example, LNA 32, mixer 38, LO 35, and PGA 41 may generally be implemented using analog circuitry. As desired and as will be understood by one of ordinary skill in the art, the analog circuitry may include bias circuits, decoupling circuits, coupling circuits, power supply circuits, current mirrors, current and / or voltage sources, filters, amplifiers, converters, signal processing circuits (e.g., multipliers), sensors or detectors, transducers, discrete components (transistors, diodes, resistors, capacitors, inductors), analog MUXs, etc. In addition, digital circuitry or mixed signal circuitry or both may be included. As desired and as will be understood by one of ordinary skill in the art, the digital circuitry may include circuit elements or blocks such as gates, digital multiplexers (MUXs), latches, flip-flops, registers, finite state machines (FSMs), processors, programmable logic (e.g., field programmable gate arrays (FPGAs) or other types of programmable logic), arithmetic logic units (ALUs), standard cells, custom cells, custom analog cells, etc. As described above and as will be understood by one of ordinary skill in the art, in addition to analog circuitry and digital circuitry, mixed signal circuitry may include analog-to-digital converters (ADCs), digital-to-analog converters (DACs), etc. For a given implementation, the selection of circuitry depends on various factors, as will be understood by one of ordinary skill in the art. Such factors include design specifications, performance specifications, cost, IC or device area, available technology such as semiconductor manufacturing technology, target market, target end user, etc.

[0128] With reference to the accompanying drawings, those of ordinary skill in the art will note that the various blocks shown may primarily depict conceptual functions and signal flows. Actual circuit implementations may or may not include individually identifiable hardware for various functional blocks, and may or may not use the specific circuit systems shown. For example, one may combine the functions of various blocks into one circuit block as desired. In addition, one may implement the functions of a single block in several circuit blocks as desired. For a given implementation, the choice of circuit implementation depends on various factors, such as specific design and performance specifications. In addition to the embodiments in the present disclosure, other modifications and alternative embodiments will be apparent to those of ordinary skill in the art. Therefore, the present disclosure teaches those skilled in the art how to perform the disclosed concepts according to exemplary embodiments, and should be understood to be merely illustrative. Where applicable, the drawings may or may not be drawn to scale, as will be understood by those of ordinary skill in the art.

[0129] The specific forms and embodiments shown and described constitute exemplary embodiments only. Those skilled in the art may make various changes to the shape, size, and arrangement of parts without departing from the scope of the present disclosure. For example, those skilled in the art may replace the elements shown and described with equivalent elements. In addition, those skilled in the art may use certain features of the disclosed concepts independently of the use of other features without departing from the scope of the present disclosure.

Claims

1. A communication device, comprising: An RF receiver for receiving radio frequency signals (RF signals) using multiple antennas, the RF receiver comprising: a demodulator to provide a switch signal to cause the RF receiver to use an antenna from the plurality of antennas in an antenna diversity configuration; and A carrier frequency offset correction circuit, i.e., a CFO correction circuit, estimates and removes a carrier frequency offset, i.e., a CFO correction circuit, wherein the CFO correction circuit comprises a CFO estimation circuit, wherein the CFO estimation circuit comprises a demultiplexer, i.e., a DeMUX, coupled to a plurality of circuit branches, wherein each of the plurality of circuit branches comprises a first averaging circuit, a phase-to-frequency converter circuit, and a second averaging circuit.

2. The apparatus of claim 1, wherein the CFO correction circuit comprises a CFO removal circuit.

3. The apparatus of claim 2, wherein the CFO removal circuit comprises a multiplier that multiplies an in-phase input signal (I input signal) and a quadrature input signal (Q input signal) with the output of the CFO estimation circuit.

4. The apparatus according to claim 1, wherein the CFO estimation circuit further comprises a third averaging circuit, a coordinate rotation digital computer (Cordic), and an exponentiation circuit.

5. The apparatus of claim 2, wherein the CFO estimation circuit comprises a derotator coupled to a first averaging circuit, a phase-to-frequency converter circuit coupled to the first averaging circuit, a second averaging circuit coupled to the phase-to-frequency converter circuit, and a coordinate rotation digital computer (Cordic) coupled to the second averaging circuit.

6. The apparatus of claim 2, wherein the CFO correction circuit comprises a phase difference removal circuit (PDR) circuit coupled to an output of a coordinate rotation digital computer (Cordic).

7. The apparatus of claim 6, wherein the PDR circuit comprises a demultiplexer (DeMUX) coupled to receive the output of the Cordic, a multiplier coupled to the output of the DeMUX, and a multiplexer (MUX) coupled to the multiplier and the DeMUX.

8. The apparatus of claim 7, wherein an output of the MUX drives an input of an exponentiation circuit in the CFO estimation circuit.

9. A communication device, comprising: An RF receiver for receiving radio frequency signals (RF signals) using multiple antennas, the RF receiver comprising: a demodulator to provide a switch signal to cause the RF receiver to use an antenna from the plurality of antennas in an antenna diversity configuration; and A carrier frequency offset estimation circuit, i.e., a CFO estimation circuit, for using the switch signal to provide an estimate of the carrier frequency offset; a phase difference removal circuit (PDR circuit) coupled to the CFO estimation circuit, wherein the PDR circuit includes a multiplexer (MUX) and a counter; and A CFO removal circuit, coupled to the CFO estimation circuit, removes the carrier frequency offset using the estimate of the carrier frequency offset.

10. The apparatus of claim 9, wherein the CFO removal circuit comprises a multiplier that multiplies an in-phase input signal (I input signal) and a quadrature input signal (Q input signal) with the output of the CFO estimation circuit.

11. The apparatus of claim 9, wherein the CFO estimation circuit comprises a derotator, a first averaging circuit, a phase to frequency converter circuit, a multiplier, a second averaging circuit, a coordinate rotation digital computer (Cordic), and an exponentiation circuit.

12. The apparatus of claim 11, wherein the CFO estimation circuit further comprises a third averaging circuit.

13. The apparatus of claim 11, wherein the multiplexer (MUX) is coupled to the multiplier and the counter provides a selection signal to the MUX, wherein in response to the selection signal, the MUX provides either a binary zero or the output of the multiplier to the second averaging circuit.

14. A method for correcting carrier frequency offset (CFO) in a radio frequency receiver (RF receiver) using multiple antennas, the method comprising: providing a switch signal using a demodulator to cause the RF receiver to use an antenna from the plurality of antennas in an antenna diversity configuration; as well as The carrier frequency offset is estimated and removed using a CFO correction circuit, wherein using the CFO correction circuit includes using a phase difference removal circuit (PDR circuit) by selectively multiplying the output of the CFO estimation circuit by the number of chips per symbol of the received RF signal.

15. The method of claim 14, wherein estimating and removing the carrier frequency offset using the CFO correction circuit further comprises using a CFO removal circuit.

16. The method of claim 15, wherein using the CFO removal circuit further comprises multiplying an in-phase input signal (I input signal) and a quadrature input signal (Q input signal) with an output of the CFO estimation circuit.

17. The method of claim 15, wherein using the CFO estimation circuit comprises estimating and storing CFO values, and averaging the CFO values.

18. The method according to claim 14, wherein: The CFO estimation circuit includes a demultiplexer or DeMUX coupled to a plurality of circuit branches, wherein each of the plurality of circuit branches includes a first averaging circuit, a phase-to-frequency converter circuit, and a second averaging circuit.

19. The method according to claim 18, wherein: The CFO estimation circuit further includes a third averaging circuit, a coordinate rotation digital computer (Cordic), and an exponentiation circuit.

20. The method according to claim 14, wherein: The CFO correction circuit includes a phase difference removal circuit (PDR circuit) coupled to the output end of a coordinate rotation digital computer (Cordic).

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