Control module and control method for synchronous dynamic random access memory

Abstract

This application discloses a control module for an SDRAM and a control method thereof. The control module includes at least one register and a controller. The controller is configured to: control the SDRAM to switch from a bus data access mode to a dynamic pin (DPIN) operation mode; set a value in at least one register in the DPIN operation mode; and control the SDRAM based on the value in the at least one register.

Description

Technical Field

[0001] The present invention relates to a memory control module and a control method, and more particularly to a control module and a control method for synchronous dynamic random access memory. Background Art

[0002] Synchronous Dynamic Random Access Memory (SDRAM) architectures rely on an SDRAM controller to execute commands and control data channels. Conventional SDRAM controllers are typically developed specifically for the commands and functions they are designed to execute. However, in completed SDRAM controllers, any defects, flaws, or errors in SDRAM operations (especially those involving specialized functions) are difficult to verify or otherwise correct. Summary of the Invention

[0003] The present invention provides a control method for a synchronous dynamic random access memory (SDRAM), comprising: controlling the SDRAM to switch from a bus data access mode to a dynamic pin (DPIN) operation mode; setting a value of at least one register in the DPIN mode; and controlling the SDRAM according to the value of the at least one register.

[0004] The present invention further provides a control module for an SDRAM, comprising at least one register and a controller. The at least one register is electrically connected to the SDRAM. The controller is electrically connected to the SDRAM and the at least one register and is configured to: control the SDRAM to switch from a bus data access mode to a dynamic pin (DPIN) operation mode; set a value in the at least one register in the DPIN mode; and control the SDRAM based on the value in the at least one register. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The embodiments of the present invention will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that the various features may not be drawn to scale. In fact, the sizes of the various features may be arbitrarily increased or reduced for the sake of clarity of discussion.

[0006] Figure 1 FIG. 4 is a block diagram of a control module according to some embodiments of the present invention.

[0007] Figure 2A FIG. 4 is a block diagram of a control module according to some embodiments of the present invention.

[0008] Figure 2B FIG. 4 is a block diagram of a control module according to some embodiments of the present invention.

[0009] Figure 3 Flowchart of a control method according to some embodiments of the present invention.

[0010] Figure 4 Flowchart of a control method according to some embodiments of the present invention.

[0011] Figures 5A to 5C Flowchart of a control method according to some embodiments of the present invention.

[0012] Figures 6A to 6C Flowchart of a control method according to some embodiments of the present invention.

[0013] Figures 7A to 7C Flowchart of a control method according to some embodiments of the present invention.

[0014] Explanation of symbols:

[0015] 1: Control module

[0016] 11: Register

[0017] 13: Controller

[0018] 2: Control module

[0019] 21A~21E: register

[0020] 23: Controller

[0021] 7: Decoder

[0022] 8:SDRAM

[0023] 9:SDRAM

[0024] S301~S303: Steps

[0025] S401~S406: Steps

[0026] S501~S508: Steps

[0027] S601~S608: Steps

[0028] S701~S708: Steps DETAILED DESCRIPTION

[0029] Embodiments of the present invention are discussed in detail below. However, it should be understood that the present invention provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of the present invention.

[0030] Conventional synchronous dynamic random access memory (SDRAM) architectures lack operational flexibility. Any defects, flaws, or errors in SDRAM operations are difficult to verify or correct. To increase the operational flexibility of the SDRAM architecture, the present invention provides a control module and a control method thereof.

[0031] See also Figure 1 , which is a block diagram of a control module 1 according to some embodiments of the present invention. Control module 1 includes at least one register 11 and a controller 13, with register 11 electrically connected to controller 13. Control module 1 is electrically connected to a synchronous dynamic random access memory (SDRAM) 9. Data and signals are transmitted between components via this electrical connection. Related control operations are further described below.

[0032] In some embodiments, the SDRAM 9 is in a bus data access mode. In other words, the SDRAM 9 exchanges data with a device (e.g., a computer host) via a standard bus. When special operations (e.g., debugging, special command control, etc.) are required for the SDRAM 9, the controller 13 switches the SDRAM 9 from the bus data access mode to a dynamic pin (DPIN) operation mode based on user commands.

[0033] In the DPIN operating mode, a user can set the value of at least one register 11 via the controller 13. After the value of the at least one register 11 is set, the controller 13 controls the SDRAM 9 based on the value of the at least one register 11. Specifically, when a user wishes to execute a special command on the SDRAM 9, this special command typically corresponds to at least one pin of the SDRAM 9. In other words, when the at least one pin corresponding to the special command is triggered, the special command is executed on the SDRAM 9.

[0034] Because different values in the at least one register 11 correspond to different pins or combinations of pins of the SDRAM 9, the user can first enter the corresponding value into the at least one register 11 for the at least one pin of the SDRAM 9 corresponding to the special instruction. In this way, after the value of the at least one register 11 is set, the controller 13 can trigger the pin of the SDRAM 9 according to the value of the at least one register 11, thereby completing the execution of the special instruction on the SDRAM 9.

[0035] See also Figure 2A, which is a block diagram of a control module 2 according to some embodiments of the present invention. Control module 2 includes a plurality of registers 21A to 21D and a controller 23. Registers 21A to 21D are electrically connected to controller 23. In some embodiments, register 21A stores values corresponding to pins associated with Tied Commands of SDRAM 8, register 21B stores values corresponding to pins associated with Synchronous Commands of SDRAM 8, register 21C stores values corresponding to data to be written to SDRAM 8, and register 21D stores data read from SDRAM 8.

[0036] Control module 2 is electrically connected to an SDRAM 8 via a decoder 7. Multiple outputs of decoder 7 correspond to multiple pins of SDRAM 8. Decoder 7 decodes the values provided by control module 2 and triggers corresponding pins of SDRAM 8 based on the decoded values. Data and signals are transmitted between components via electrical connections. Related control operations are further described below.

[0037] In some embodiments, the SDRAM 8 is in a bus data access mode. In other words, the SDRAM 8 exchanges data with a device (e.g., a computer host) via a general bus. When special operations (e.g., debugging, special command control, etc.) are required for the SDRAM 8, the controller 23 switches the SDRAM 8 from the bus data access mode to a DPIN operation mode based on user commands.

[0038] In DPIN operating mode, the user can set the values in registers 21A and 21B via controller 23. After the values in registers 21A and 21B are set, controller 23 controls SDRAM 8 based on the values in registers 21A and 21B. Furthermore, when a user needs to execute a special command on SDRAM 8, this special command typically corresponds to at least one pin of SDRAM 8. In other words, when the at least one pin corresponding to the special command is triggered, the special command is executed on SDRAM 8. Because different values in register 21 correspond to different pins or different combinations of pins on SDRAM 8, the user can first enter the corresponding value in registers 21A and 21B for the at least one pin of SDRAM 8 corresponding to the special command. In this way, after the values in registers 21A and 21B are set, controller 23 can trigger the pin of SDRAM 8 based on the values in registers 21A and 21B to execute the special command on SDRAM 8. The technology of the present invention will be further illustrated below through various examples.

[0039] In some examples, the value in register 21A corresponds to a pin of the SDRAM 8 associated with a binding instruction (e.g., the reset pin RST, the clock enable pin CKE, the on-die termination (ODT) pin, etc.). For at least one pin of the SDRAM 8 (excluding the CKE pin), the user can set a corresponding value in register 21A via controller 23. In other words, the value set in register 21A is used to trigger at least one pin of the SDRAM 8 (excluding the CKE pin). Once the setting is complete, controller 23 directly controls the SDRAM 8 based on the value in register 21A.

[0040] On the other hand, the user can set a corresponding value for at least one pin (including the CKE pin) of SDRAM 8 via register 21A of controller 23. In other words, the value set in register 21A is used to trigger at least one pin (including the CKE pin) of SDRAM 8 accordingly. Once the setting is complete, controller 23 triggers a DPIN operation to synchronously control SDRAM 8 based on the values in registers 21A and 21B. In this example, controller 23 triggers the DPIN operation to control SDRAM 8 based on the value in register 21A.

[0041] In some examples, the value in register 21A corresponds to pins of SDRAM 8 associated with binding instructions (e.g., the reset pin RST, the clock enable pin CKE, the on-die termination pin ODT, etc.), and the value in register 21B corresponds to pins of SDRAM 8 associated with synchronization instructions (e.g., the CS, RAS, CAS, WEN, ACT, CA, etc.). For at least one pin of SDRAM 8 (excluding the CKE, RST, and ODT pins), the user can set corresponding values in registers 21A and 21B via controller 23. In other words, the values set in registers 21A and 21B are used to trigger at least one pin of SDRAM 8 (excluding the CKE, RST, and ODT pins). Once set, controller 23 directly controls SDRAM 8 based on the value in register 21A and triggers a DPIN operation to control SDRAM 8 based on the value in register 21B.

[0042] On the other hand, for at least one pin of SDRAM 8 (including the CKE, RST, and ODT pins), the user can use controller 23 to set corresponding values in registers 21A and 21B. In other words, the values set in registers 21A and 21B are used to trigger at least one pin of SDRAM 8 (including the CKE, RST, and ODT pins). Once the settings are complete, controller 23 triggers a DPIN operation to synchronously control SDRAM 8 based on the values in registers 21A and 21B. In this example, controller 23 triggers a DPIN operation to control SDRAM 8 based on the values in registers 21A and 21B.

[0043] In some examples, the value of register 21A corresponds to the pins related to the binding instructions of SDRAM 8 (for example, the reset pin RST, the clock enable pin CKE, the on-die terminal pin ODT, etc.), the value of register 21B corresponds to the pins related to the synchronization instructions of SDRAM 8 (for example, the CS, RAS, CAS, WEN, ACT, CA, etc.), and the value of register 21C corresponds to the data to be written to SDRAM 8.

[0044] For at least one pin of SDRAM 8 (excluding the CKE, RST, and ODT pins), the user can set corresponding values in registers 21A, 21B, and 21C through controller 23. In other words, the values set in registers 21A and 21B are used to trigger at least one pin of SDRAM 8 (excluding the CKE, RST, and ODT pins), and the value set in register 21C is the data to be written to SDRAM 8. After the setting is completed, controller 23 directly controls SDRAM 8 according to the value in register 21A and triggers the DPIN operation to: (1) control SDRAM 8 according to the value in register 21B and write the value in register 21C to SDRAM 8.

[0045] On the other hand, for at least one pin of SDRAM 8 (including the CKE, RST, and ODT pins), the user can set corresponding values in registers 21A, 21B, and 21C via controller 23. In other words, the values set in registers 21A and 21B are used to trigger at least one pin of SDRAM 8 (including the CKE, RST, and ODT pins), and the value set in register 21C is the data to be written to SDRAM 8. After the settings are completed, controller 23 triggers a DPIN operation to control SDRAM 8 according to the values in registers 21A and 21B and writes the value in register 21C to SDRAM 8. In this example, controller 23 triggers a DPIN operation to control SDRAM 8 according to the values in registers 21A and 21B.

[0046] In some examples, the value of register 21A corresponds to the pins related to the binding instructions of SDRAM 8 (for example, the reset pin RST, the clock enable pin CKE, the on-die terminal pin ODT, etc.), the value of register 21B corresponds to the pins related to the synchronization instructions of SDRAM 8 (for example, the CS, RAS, CAS, WEN, ACT, CA, etc.), and the value of register 21C corresponds to the data to be written to SDRAM 8.

[0047] For at least one pin of the SDRAM 8 (excluding the CKE, RST, and ODT pins), the user can set the corresponding value in registers 21A and 21B through the controller 23. In other words, the values set in registers 21A and 21B are used to trigger at least one pin of the SDRAM 8 (excluding the CKE, RST, and ODT pins). After the setting is completed, the controller 23 directly controls the SDRAM 8 according to the value in register 21A and triggers the DPIN operation to: (1) control the SDRAM 8 according to the value in register 21B and store the data read from the SDRAM 8 in register 21D.

[0048] On the other hand, for at least one pin of SDRAM 8 (including the CKE, RST, and ODT pins), the user can use controller 23 to set corresponding values in registers 21A and 21B. In other words, the values set in registers 21A and 21B are used to trigger at least one pin of SDRAM 8 (including the CKE, RST, and ODT pins). After the settings are completed, controller 23 triggers the DPIN operation to synchronously control SDRAM 8 according to the values in registers 21A and 21B and stores the data read from SDRAM 8 in register 21D. In this example, controller 23 triggers the DPIN operation to control SDRAM 8 according to the values in registers 21A and 21B.

[0049] It should be noted that the aforementioned DPIN operation can synchronize the access of registers 21A to 21C. In some embodiments, an additional synchronization control register can be used to determine the execution of the aforementioned DPIN operation. Figure 2B , which is another block diagram of the control module 2 according to some embodiments of the present invention. The control module 2 further includes a synchronous control register 21E for: (1) marking whether the SDRAM 8 switches to the DPIN operation mode; (2) synchronizing access to registers 21A to 21C; and (3) marking the DPIN status.

[0050] Some embodiments of the present invention include a method for controlling SDRAM, the flow chart of which is as follows: Figure 3The image capture methods of these embodiments are implemented by a control module (such as the control module of the aforementioned embodiments). The detailed operations of the method are as follows. First, step S301 is executed to control the SDRAM to switch from a bus data access mode to a DPIN operation mode. Step S302 is executed to set the value of at least one register in the DPIN mode. Step S303 is executed to control the SDRAM based on the value of the at least one register.

[0051] Some embodiments of the present invention include a method for controlling SDRAM, the flow chart of which is as follows: Figure 4 The image capture methods of these embodiments are implemented by a control module (such as the control module of the aforementioned embodiments), and the detailed operations of the methods are as follows.

[0052] First, step S401 is executed to control the SDRAM to switch from a bus data access mode to a DPIN operation mode. When the CKE pin of the SDRAM needs to be controlled, step S402 is executed to set a value in a first register in the DPIN mode so that the value in the first register corresponds to at least one pin (including the CKE pin) associated with the SDRAM binding instruction. Step S403 is executed to trigger a DPIN operation to control the SDRAM based on the value in the first register.

[0053] On the other hand, when controlling non-CKE pins of the SDRAM, step S404 is executed to set the value of the first register in the DPIN mode so that the value of the first register corresponds to at least one pin (excluding the CKE pin) associated with the binding instruction of the SDRAM, and the SDRAM is directly controlled according to the value of the constraint value register.

[0054] In some embodiments, step S405 is executed to determine whether the DPIN mode needs to be terminated. If so, step S406 is executed to control the SDRAM to switch from the DPIN operation mode to the bus data access mode. If not, steps S402 to S405 are repeated.

[0055] Some embodiments of the present invention include a method for controlling SDRAM, the flow chart of which is as follows: Figures 5A to 5C The image capture methods of these embodiments are implemented by a control module (such as the control module of the aforementioned embodiments), and the detailed operations of the methods are as follows.

[0056] First, step S501 is executed to control the SDRAM to switch from a bus data access mode to a DPIN operation mode. When the CKE, RST, and ODT pins of the SDRAM need to be controlled, step S502 is executed to set the values of a first register and a second register in the DPIN mode. The value of the first register corresponds to at least one pin associated with the SDRAM binding instruction (including the CKE, RST, and ODT pins), and the value of the second register corresponds to at least one pin associated with the SDRAM synchronization instruction (for example, the CS, RAS, CAS, WEN, ACT, and CA pins). Step S503 is executed to trigger a DPIN operation to control the SDRAM based on the values of the first and second registers.

[0057] On the other hand, when controlling SDRAM pins other than CKE, RST, and ODT, step S504 is executed to set the value of the second register in DPIN mode so that the value of the second register corresponds to at least one SDRAM pin. Step S505 is executed to trigger the DPIN function to control the SDRAM based on the value of the second register. It should be noted that step S506 can be executed in parallel with steps S504 and S505 to set the value of the first register in DPIN mode and directly control the SDRAM based on the value of the first register.

[0058] In some embodiments, step S507 is executed to determine whether the DPIN mode needs to be terminated. If so, step S508 is executed to control the SDRAM to switch from the DPIN operation mode to the bus data access mode. If not, steps S502 to S506 are repeated.

[0059] Some embodiments of the present invention include a method for controlling SDRAM, the flow chart of which is as follows: Figures 6A to 6C The image capture methods of these embodiments are implemented by a control module (such as the control module of the aforementioned embodiments), and the detailed operations of the methods are as follows.

[0060] First, step S601 is executed to control the SDRAM to switch from a bus data access mode to a DPIN operation mode. When it is necessary to control the CKE, RST, and ODT pins of the SDRAM, step S602 is executed to set the values of a first register, a second register, and a third register in the DPIN mode so that: (1) the value of the first register corresponds to at least one pin related to the SDRAM binding instruction (including the CKE, RST, and ODT pins); (2) the value of the second register corresponds to at least one pin related to the SDRAM synchronization instruction (for example, the CS, RAS, CAS, WEN, ACT, and CA pins); and (3) the value of the third register corresponds to the data to be written into the SDRAM. Step S603 is executed to trigger a DPIN operation to control the SDRAM according to the values of the first register and the second register, and write the value of the third register into the SDRAM.

[0061] On the other hand, when controlling SDRAM pins other than CKE, RST, and ODT, step S604 is executed to set the values of the second and third registers in DPIN mode, such that the value of the second register corresponds to at least one SDRAM pin and the value of the third register corresponds to the data to be written to the SDRAM. Step S605 is executed to trigger a DPIN operation, thereby controlling the SDRAM based on the value in the second register and writing the data in the third register to the SDRAM. It should be noted that step S606 can be executed in parallel with steps S604 and S605, setting the value of the first register in DPIN mode and directly controlling the SDRAM based on the value in the first register.

[0062] In some embodiments, step S607 is executed to determine whether the DPIN mode needs to be terminated. If so, step S608 is executed to control the SDRAM to switch from the DPIN operation mode to the bus data access mode. If not, steps S602 to S606 are repeated.

[0063] Some embodiments of the present invention include a method for controlling SDRAM, the flow chart of which is as follows: Figures 7A to 7C The image capture methods of these embodiments are implemented by a control module (such as the control module of the aforementioned embodiments), and the detailed operations of the methods are as follows.

[0064] First, step S701 is executed to control the SDRAM to switch from a bus data access mode to a DPIN operation mode. When the CKE, RST, and ODT pins of the SDRAM need to be controlled, step S702 is executed to set the values of a first register and a second register in the DPIN mode so that the value of the first register corresponds to at least one pin associated with the SDRAM binding instruction (including the CKE, RST, and ODT pins), and the value of the second register corresponds to at least one pin associated with the SDRAM synchronization instruction (for example, the CS, RAS, CAS, WEN, ACT, and CA pins). Step S703 is executed to trigger a DPIN operation to control the SDRAM based on the values of the first and second registers and store data read from the SDRAM in a third register.

[0065] On the other hand, when controlling SDRAM pins other than CKE, RST, and ODT, step S704 is executed to set the value of the second register in DPIN mode so that the value of the second register corresponds to at least one SDRAM pin. Step S705 is executed to trigger a DPIN operation to control the SDRAM based on the value of the second register and store data read from the SDRAM in the third register. It should be noted that step S706 can be executed in parallel with steps S704 and S705 to set the value of the first register in DPIN mode and directly control the SDRAM based on the value of the first register.

[0066] In some embodiments, step S707 is executed to determine whether the DPIN mode needs to be terminated. If so, step S708 is executed to control the SDRAM to switch from the DPIN operation mode to the bus data access mode. If not, steps S702 to S706 are repeated.

[0067] In summary, the SDRAM control module and control method provided by the present invention can control the SDRAM through additional registers and control circuits to verify or correct defects, flaws, or errors in the SDRAM's operational design (especially operations with special functions). It should be noted that in some embodiments, the controller includes logic circuits capable of executing operations and instructions, but this is not intended to limit the implementation of the present invention to hardware components.

[0068] The above description briefly introduces the features of certain embodiments of the present invention, so that those with ordinary knowledge in the technical field to which the present invention belongs can more fully understand the various implementation methods of the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs should understand that they can easily use the present invention as a basis to design or modify other processes and structures to achieve the same purpose and / or achieve the same advantages as the implementation methods described herein. Those with ordinary knowledge in the technical field to which the present invention belongs should understand that these equivalent implementation methods still fall within the spirit and scope of the present invention, and various changes, substitutions and modifications can be made thereto without departing from the spirit and scope of the present invention.

Claims

1. A control method for a synchronous dynamic random access memory (SDRAM), characterized in that: Include: Controlling the SDRAM to switch from a bus data access mode to a dynamic pin DPIN operation mode; Setting the value of at least one register in the DPIN operation mode; and Controlling the SDRAM according to the value of the at least one register; The at least one register includes a first register, the value of the first register corresponds to a clock enable pin associated with a binding instruction of the SDRAM, and the step of controlling the SDRAM according to the value of the at least one register further includes: A DPIN operation is triggered to control the SDRAM according to the value of the first register.

2. The control method according to claim 1, wherein: The at least one register includes a first register and a second register. The value of the first register corresponds to a clock enable pin, a reset pin, and an on-die terminal pin associated with a bind instruction of the SDRAM. The value of the second register corresponds to a pin associated with a synchronization instruction of the SDRAM. The step of controlling the SDRAM according to the value of the at least one register further includes: A DPIN operation is triggered to control the SDRAM according to the values of the first register and the second register.

3. The control method according to claim 2, wherein: The at least one register further includes a third register, and the step of triggering the DPIN operation further includes: The DPIN operation is triggered to control the SDRAM according to the values in the first register and the second register, and to write the value in the third register into the SDRAM.

4. The control method according to claim 2, wherein: The at least one register further includes a third register, and the step of triggering the DPIN operation further includes: The DPIN operation is triggered to control the SDRAM according to the values in the first register and the second register, and the value read from the SDRAM is stored in the third register.

5. A control module for a synchronous dynamic random access memory (SDRAM), characterized in that: Include: At least one register electrically connected to the SDRAM; a controller electrically connected to the SDRAM and the at least one register, for: Controlling the SDRAM to switch from a bus data access mode to a dynamic pin DPIN operation mode; Setting the value of the at least one register in the DPIN operation mode; and Controlling the SDRAM according to the value of the at least one register; The at least one register includes a first register and a second register. The value of the first register corresponds to a clock enable pin, a reset pin, and an on-die terminal pin associated with a bind instruction of the SDRAM. The value of the second register corresponds to a pin associated with a synchronization instruction of the SDRAM. The controller is further configured to: A DPIN operation is triggered to control the SDRAM according to the values of the first register and the second register.

6. The control module according to claim 5, wherein: The at least one register further includes a third register, and the controller is further configured to: The DPIN operation is triggered to write the value of the third register into the SDRAM.

7. The control module according to claim 5, wherein: The at least one register further includes a third register, and the controller is further configured to: The DPIN operation is triggered to store the value read from the SDRAM into the third register.

8. The control module according to claim 5, wherein: The at least one register includes a first register and a second register. The value of the first register corresponds to at least one pin associated with a bind instruction of the SDRAM, the at least one pin excluding a clock enable pin, a reset pin, and an on-die terminal pin. The value of the second register corresponds to a pin associated with a synchronization instruction of the SDRAM. The controller is further configured to: A DPIN operation is triggered to control the SDRAM according to the value of the second register.

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