A copper interconnection layer and a damascene process method for the copper interconnection layer

Abstract

The application provides a copper interconnection layer and a damascene process method of the copper interconnection layer. The side wall and bottom of a via and a trench for forming a copper interconnection line are formed with a barrier layer, which comprises a metal crystal adhesion layer or a graphene layer. The metal crystal adhesion layer can be a crystal Co layer, a crystal Ru layer or a crystal Os layer. The metal crystal adhesion layer can enhance the adhesion with Cu, effectively inhibit the diffusion of Cu into a dielectric layer and be beneficial to improving the electron migration performance of Cu. The formation of the metal crystal adhesion layer can effectively reduce the total thickness of the barrier layer and a first barrier layer and effectively reduce the resistance of the via. The graphene layer is an amorphous carbon / graphene composite layer. Due to the formation of the graphene layer, the copper interconnection layer has a lower resistivity. The formation of the graphene layer can also effectively reduce the total thickness of the barrier layer or the barrier layer and the first barrier layer and effectively reduce the resistance of the via.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices, and in particular to a copper interconnect layer and a damascus process for the copper interconnect layer. Background Technology

[0002] The resistance-capacitance (RC) delay of interconnect circuits is a major factor affecting the speed performance of logic circuits. Since the 0.13μm CMOS technology node, copper (Cu) has been used as an interconnect material due to its low resistivity. However, Cu readily diffuses into low-k dielectrics and also degrades Cu's electron-migration (EM) performance.

[0003] In traditional processes, Ta / TaN is typically used as a barrier layer for Cu interconnects in dual damascene (DD) architectures to prevent Cu diffusion. However, with the continuous shrinking of CMOS in BEOLs, the conventional Ta / TaN pads and barrier layers used for copper interconnects in DD structures are ineffective in preventing Cu diffusion, reducing via resistance, and improving adhesion to Cu to achieve electron migration (EM) performance. Therefore, better materials are needed for interconnect layers to enhance or replace conventional Ta / TaN stacks. Summary of the Invention

[0004] In view of the aforementioned problems and defects in the copper interconnect layer of the double damascus process, this invention provides a copper interconnect layer and a method for applying a copper interconnect layer to a damascus process. A barrier layer is formed on the sidewalls and bottom of the vias and grooves forming the copper interconnect layer. This barrier layer includes a metal crystal adhesion layer or a graphene layer. The metal crystal adhesion layer can be a crystalline Co layer, a crystalline Ru layer, or a crystalline Os layer, and the metal crystals are in a hexagonal close-packed or face-centered cubic structure. The graphene layer is a composite layer of amorphous carbon and graphene. Both the aforementioned metal crystal adhesion layer and graphene layer can enhance adhesion to Cu, effectively suppressing Cu diffusion into the dielectric layer, especially the k-th dielectric layer, thereby improving the electron mobility of Cu.

[0005] To achieve the above and other related objectives, the present invention provides a damascus process method for copper interconnect layers, the method comprising:

[0006] A dielectric layer is formed on the substrate;

[0007] Through-holes and trenches are formed in the dielectric layer;

[0008] A barrier layer is formed on the sidewalls and bottom of the through hole and the sidewalls and bottom of the trench. The barrier layer includes a metal crystal adhesion layer or a graphene layer.

[0009] Copper is filled into the through holes and trenches to form a copper interconnect layer.

[0010] Optionally, when the barrier layer comprises a metal crystal adhesion layer, forming the barrier layer on the sidewalls and bottom of the through-hole and the sidewalls and bottom of the trench further includes the following steps:

[0011] A metal and / or metal compound is formed as a first barrier layer on the sidewalls and bottom of the through hole and the sidewalls and bottom of the trench;

[0012] A metal crystal adhesion layer is formed over the first barrier layer on the sidewalls of the through hole and the sidewalls of the trench by physical vapor deposition.

[0013] Optionally, when the barrier layer comprises a metal crystal adhesion layer, forming the barrier layer on the sidewalls and bottom of the through-hole and the sidewalls and bottom of the trench further includes the following steps:

[0014] A metal and / or metal compound is formed as a first barrier layer on the sidewalls and bottom of the through hole and the sidewalls and bottom of the trench;

[0015] An amorphous metal liner layer is formed over the first barrier layer on the sidewalls of the through hole and the sidewalls of the trench by chemical vapor deposition.

[0016] A metal crystal adhesion layer is formed on top of the amorphous metal backing layer by physical vapor deposition.

[0017] Optionally, the metal crystal adhesion layer is a crystalline Co layer, a crystalline Ru layer, or a crystalline Os layer.

[0018] Optionally, the amorphous metal backing layer is an amorphous Co layer, an amorphous Ru layer, or an amorphous Os layer.

[0019] Optionally, the thickness of the amorphous metal backing layer is between 1 nm and 3 nm, and the thickness of the metal crystal adhesion layer is between 1 nm and 2 nm.

[0020] Optionally, the thickness of the metal crystal adhesion layer is between 1 nm and 5 nm.

[0021] Optionally, the metal crystals in the metal crystal adhesion layer have a hexagonal close-packed structure or a face-centered cubic structure.

[0022] Optionally, when the barrier layer comprises a graphene layer, forming the barrier layer on the sidewalls and bottom of the via and the sidewalls and bottom of the trench further includes the following steps:

[0023] Amorphous carbon is formed by chemical vapor deposition on the sidewalls and bottom of the through holes and the sidewalls and bottom of the trenches. A graphene layer is formed at the interface between the amorphous carbon and the dielectric layer. The barrier layer is an amorphous carbon / graphene composite layer.

[0024] Optionally, when the barrier layer comprises a graphene layer, forming the barrier layer on the sidewalls and bottom of the via and the sidewalls and bottom of the trench further includes the following steps:

[0025] An amorphous carbon layer is formed by chemical vapor deposition on the sidewalls and bottom of the through hole and the sidewalls and bottom of the trench. A graphene layer is formed at the interface between the amorphous carbon and the dielectric layer. The barrier layer is an amorphous carbon / graphene composite layer.

[0026] A metal and / or metal compound is deposited as a first barrier layer over the amorphous carbon / graphene composite layer on the sidewalls of the through-hole and the sidewalls of the trench.

[0027] Optionally, the temperature for chemical vapor deposition is between 300°C and 400°C.

[0028] Optionally, the thickness of the graphene layer is less than 1 nm.

[0029] Optionally, the first barrier layer is a TaN layer or a TaN / Ta stack.

[0030] According to another aspect of the present invention, a copper interconnect layer is provided, the copper interconnect layer being formed in vias and trenches in a dielectric layer of a substrate, the copper interconnect layer comprising: a barrier layer formed on the sidewalls and bottom of the vias and the sidewalls and bottom of the trenches, and copper interconnects formed above the barrier layer filling the vias and trenches, the barrier layer comprising a metal crystal adhesion layer or comprising a graphene layer.

[0031] Optionally, the metal crystal adhesion layer is a crystalline Co layer, a crystalline Ru layer, or a crystalline Os layer.

[0032] Optionally, the thickness of the metal crystal adhesion layer is between 1 nm and 5 nm.

[0033] Optionally, the metal crystals in the metal crystal adhesion layer have a hexagonal close-packed structure or a face-centered cubic structure.

[0034] Optionally, a first barrier layer is further formed between the metal crystal adhesion layer and the through hole and the trench.

[0035] Optionally, an amorphous metal pad layer may be formed between the metal crystal adhesion layer and the first barrier layer.

[0036] Optionally, the amorphous metal backing layer is an amorphous Co layer, an amorphous Ru layer, or an amorphous Os layer.

[0037] Optionally, the thickness of the amorphous metal backing layer is between 1 nm and 3 nm, and the thickness of the metal crystal adhesion layer is between 1 nm and 2 nm.

[0038] Optionally, the thickness of the metal crystal adhesion layer is between 1 nm and 5 nm.

[0039] Optionally, the metal crystals in the metal crystal adhesion layer have a hexagonal close-packed structure or a face-centered cubic structure.

[0040] Optionally, the graphene layer is an amorphous carbon layer / graphene composite layer, and the graphene layer is formed at the interface between the amorphous carbon layer and the through holes and the trenches.

[0041] Optionally, a first barrier layer is also formed above the amorphous carbon layer / graphene composite layer.

[0042] Optionally, the thickness of the graphene layer is less than 1 nm.

[0043] Optionally, the first barrier layer is a TaN layer or a TaN / Ta stack.

[0044] As described above, the copper interconnect layer and the damascus steel process method for the copper interconnect layer provided by the present invention have at least the following beneficial technical effects:

[0045] When forming the copper interconnect layer, a barrier layer is first formed on the sidewalls and bottom of the vias and trenches in the dielectric layer. This barrier layer includes a metal crystal adhesion layer or a graphene layer. The metal crystal adhesion layer can be a crystalline Co layer, a crystalline Ru layer, or a crystalline Os layer. In this invention, a first barrier layer can be formed first on the sidewalls and bottom of the vias and trenches, and then the metal crystal adhesion layer can be directly formed by physical vapor deposition. The first barrier layer effectively eliminates the influence of impurity elements in the dielectric layer on the formation of the metal crystal. The metal crystal adhesion layer formed by physical vapor deposition has high crystal material purity and high energy, resulting in a crystal with a tendency towards order. Alternatively, an amorphous metal backing layer can be first formed on the sidewalls and bottom of the vias and trenches by chemical vapor deposition, and then the metal crystal adhesion layer can be formed by physical vapor deposition. The aforementioned metal crystal adhesion layer enhances adhesion to Cu, effectively inhibits Cu diffusion into the dielectric layer, and improves the electron migration performance of Cu. The formation of the aforementioned metal crystal adhesion layer effectively reduces the overall thickness of the barrier layer and the first barrier layer, effectively reducing the via resistance.

[0046] In various embodiments, the barrier layer comprises a graphene layer, which is a composite layer of amorphous carbon and graphene. Amorphous carbon is formed on the sidewalls and bottom of the vias and trenches at a temperature of 300°C to 400°C. During this process, a thin graphene layer is formed at the interface between the amorphous carbon and the dielectric layer. A first barrier layer may or may not be formed between the amorphous carbon layer and the graphene layer and Cu. The formation of the graphene layer results in a lower resistivity for the Cu interconnect layer; the improved interface between the graphene layer and Cu leads to a higher breakdown current density and a longer electron migration lifetime for the Cu interconnect layer, thereby improving the reliability of the interconnect layer. The formation of the graphene layer also effectively reduces the overall thickness of the barrier layer or the barrier layer and the first barrier layer, effectively reducing the via resistance. Attached Figure Description

[0047] Figure 1 The diagram shown is a flowchart of the copper interconnect layer damascus process method provided in Embodiment 1 of the present invention.

[0048] Figure 2 The diagram shows a structure of vias and trenches formed in a dielectric layer above a substrate.

[0049] Figure 3 The diagram shows a structure in which a first barrier layer is formed on the sidewalls and bottom of the through-hole and trench.

[0050] Figure 4 The diagram shows a structure in which a metal crystal adhesion layer is formed above the first barrier layer.

[0051] Figure 5 Displayed as in Figure 4 The diagram shows a structure in which copper is filled to form a copper interconnect layer.

[0052] Figure 6 The diagram shows a structural schematic of an amorphous metal liner layer formed above a first barrier layer in an alternative embodiment of the example.

[0053] Figure 7 Displayed as in Figure 6 The diagram shows a structure in which a metal crystal adhesion layer is formed on top of an amorphous metal backing layer.

[0054] Figure 8 Displayed as in Figure 7 The diagram shows a structure in which copper is filled to form a copper interconnect layer.

[0055] Figure 9 The diagram shown is a flowchart of the copper interconnect layer damascus process method provided in Embodiment 2 of the present invention.

[0056] Figure 10The diagram shows a structure in which graphene layers are formed on the sidewalls and bottom of the vias and trenches in the substrate dielectric layer.

[0057] Figure 11 Displayed as in Figure 10 The diagram shows a structure in which copper is filled to form a copper interconnect layer.

[0058] Figure 12 Displayed as in Figure 10 The diagram shows a structure in which a first barrier layer is formed on top of the graphene layer.

[0059] Figure 13 Displayed as in Figure 12 The diagram shows a structure in which copper is filled to form a copper interconnect layer.

[0060] Figure 14 The diagram shows a schematic of the Cu interconnect layer in the prior art.

[0061] List of reference numerals

[0062] 100 Substrate 110 Copper

[0063] 101 First dielectric layer 201 Graphene layer

[0064] 102 First Etching Stop Layer 202 Copper

[0065] 103 Second Etching Stop Layer 203 First Barrier Layer

[0066] 104 Second dielectric layer 01 Substrate

[0067] 105 Through-hole 02 Dielectric layer

[0068] 106 Trench 03 Barrier Layer

[0069] 107 First Barrier Layer 04 Copper

[0070] 108 Metal crystal adhesion layer 05 Top barrier layer

[0071] 109 Amorphous Metal Backing Layer Detailed Implementation

[0072] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0073] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components, the shape, quantity, positional relationship and proportion of each component can be arbitrarily changed under the premise of realizing the technical solution of this invention, and the layout of the components may also be more complex.

[0074] Example 1

[0075] In the process of forming copper interconnect layers using the Damascus process, such as Figure 14 As shown, a copper interconnect layer is formed in a dielectric layer 02 above the substrate 01. This dielectric layer is typically a low-k dielectric layer, and the copper 04 in the copper interconnect layer readily migrates or diffuses into the surrounding low-k dielectric layer, thereby reducing the electron mobility of copper. To prevent the migration or diffusion of copper into the dielectric layer, in the prior art, a barrier layer 03 is typically formed on the sidewalls of the vias or trenches forming the interconnect layer. Figure 14 As shown, taking a via as an example, a metal barrier layer 03 is formed on the sidewalls and bottom of the via. This barrier layer is typically a Ta, TaN, or a Ta and TaN stack. In traditional interconnect layers, the aforementioned metal barrier layer can effectively suppress copper migration or diffusion. However, as the size of CMOS devices continues to shrink, the thickness of the Ta, TaN, or Ta and TaN stack also decreases accordingly. At this point, the role of the aforementioned metal barrier layer in reducing via resistance, adhesion to copper, and ensuring the electron migration performance of copper is greatly reduced, failing to meet the requirements of the device. Therefore, it is necessary to find alternative materials to meet the barrier layer performance requirements of increasingly smaller CMOS devices.

[0076] In view of the above requirements, this embodiment provides a damascus process for copper interconnect layers, in which a barrier layer including a metal crystal adhesion layer is formed on the sidewalls and bottom of the vias and trenches forming the copper interconnect layer to effectively suppress the migration and diffusion of copper into the surrounding dielectric layer. Figure 1 As shown, the method includes the following steps:

[0077] Step S101: Form a dielectric layer on the substrate;

[0078] The substrate in this embodiment can be selected according to the actual needs of the device. For example, it can include a silicon substrate, a germanium (Ge) substrate, a germanium-silicon (SiGe) substrate, an SOI (Silicon-on-Insulator) substrate, or a GOI (Germanium-on-Insulator) substrate, etc. Figure 2As shown, in a preferred embodiment of this example, the substrate 100 is a silicon substrate. This substrate can be a substrate 100 without a device layer formed, or a substrate 100 with a semiconductor device formed on it. A dielectric layer is formed over the substrate, which may include a first dielectric layer 101 for forming vias and a second dielectric layer 104 for forming trenches. A first etch stop layer 102 may also be formed between the first dielectric layer 101 and the substrate 100, and a second etch stop layer 103 may be formed between the second dielectric layer 104 and the first dielectric layer 101. The aforementioned dielectric layers (the first and second dielectric layers) are the k-th dielectric layer, and may be, for example, SiCOH or SiOF. The first and second etch stop layers may be silicon nitride layers.

[0079] Step S102: Form through holes and trenches in the dielectric layer;

[0080] like Figure 3 As shown, vias 105 and trenches 106 are formed in the first dielectric layer 101 and the second dielectric layer 104, respectively. The via 105 penetrates the first dielectric layer and the first etch stop layer, communicating with the substrate. In a substrate on which a device is formed, the via communicates with the device in the substrate. The trench penetrates the second dielectric layer and the second etch stop layer, communicating with the via. In a dual damascene process, the via 105 can be formed first, followed by the trench 106; alternatively, the trench 106 can be formed first, followed by the via 105; or both via 105 and trench 106 can be formed simultaneously.

[0081] Step S103: A barrier layer is formed on the sidewall and bottom of the through hole and the sidewall and bottom of the trench, the barrier layer comprising a metal crystal adhesion layer;

[0082] The formation of the aforementioned metal crystal adhesion layer requires two conditions: the presence of a metal or metal compound as a barrier layer to eliminate the influence of impurity elements in the dielectric layer on the formation of the metal crystal; and the acquisition of the metal crystal material through physical vapor deposition (PVD) technology, as PVD technology yields materials with high purity and high energy, enabling the production of crystals with a tendency towards order. Based on this, in this embodiment, firstly, as... Figure 3 As shown, a metal layer or metal compound layer is formed on the sidewalls and bottom of the through-hole 105 and the trench 106 as a first barrier layer 107. In an optional embodiment, the first barrier layer 107 may be a metal Ta layer, a TaN layer, or a stack of Ta and TaN.

[0083] Then, as Figure 4As shown, a metal crystal adhesion layer 108 is deposited above the first barrier layer using PVD technology. Preferably, the metal crystal adhesion layer is formed above the first barrier layer on the sidewalls of the vias and trenches. This metal crystal adhesion layer can be a crystalline Co layer, a crystalline Ru layer, or a crystalline Os layer. In optional embodiments, the metal crystal adhesion layer can be formed using ultra-high frequency sputtering (VHF sputter), radio frequency sputtering (RF sputter), pulse sputtering, or DC sputtering. The thickness of the formed metal crystal adhesion layer 108 is approximately 1 nm to 5 nm.

[0084] In the metal crystal adhesion layer, the metal crystals have a hexagonal close-packed or face-centered cubic structure. This close-packed structure gives the metal leaching a lower surface energy, thus resulting in higher adhesion.

[0085] Step S104: Fill the vias and trenches with copper to form a copper interconnect layer.

[0086] After the above-mentioned metal crystal adhesion layer 108 is formed, as Figure 5 As shown, copper 110 is filled into vias and trenches to form a copper interconnect layer. For example, copper is first filled into vias and trenches, and then chemical mechanical polishing is performed to obtain the desired result. Figure 5 The copper interconnect layer shown.

[0087] In one optional embodiment of this example, such as Figure 6 As shown, after forming a first barrier layer 107 on the sidewalls and bottom of the through-hole 105 and trench 106, an amorphous metal backing layer 109 is first formed above the first barrier layer using chemical vapor deposition (CVD) technology. This amorphous metal backing layer has the same metal element as the subsequently formed metal crystal adhesion layer. Preferably, the amorphous metal backing layer 109 is formed above the first barrier layer on the sidewalls of the through-hole and trench. This amorphous metal backing layer can improve the upper and lower coverage of the trench and through-hole. Then, as... Figure 7 As shown, a metal crystal adhesion layer 108 is also formed on top of the amorphous metal backing layer 109 using PVD technology. The thickness of the amorphous metal backing layer can be 1 nm to 3 nm, and the thickness of the metal crystal adhesion layer 108 is approximately 1 nm to 2 nm.

[0088] The method described in this embodiment can form a high-purity, high-energy, and long-range ordered metal crystal adhesion layer. In this layer, the metal crystals have a hexagonal close-packed or face-centered cubic structure. This close-packed structure results in lower surface energy for metal extraction, thus enhancing adhesion. This metal crystal adhesion layer strengthens adhesion to copper, effectively suppressing copper diffusion into the dielectric layer and improving copper's electron migration performance. Simultaneously, it reduces the overall thickness of the barrier layer, effectively lowering via resistance.

[0089] This embodiment also provides a copper interconnect layer obtained by the above method. (See also...) Figure 5 The copper interconnect layer is formed in a dielectric layer above the substrate. The copper interconnect layer includes a barrier layer on the sidewalls and bottom of the vias and the sidewalls and bottom of the trenches, and copper interconnect lines formed above the barrier layer to fill the vias and trenches. The barrier layer includes a metal crystal adhesion layer 108, which is a crystalline Co layer, a crystalline Ru layer, or a crystalline Os layer. Preferably, the metal crystal adhesion layer 108 is formed on the sidewalls of the vias and trenches. In the metal crystal adhesion layer, the metal crystals have a hexagonal close-packed or face-centered cubic structure. This close-packed structure results in lower surface energy for metal extraction, thus providing higher adhesion. The thickness of the metal crystal adhesion layer is between 1 nm and 5 nm, which can reduce the overall thickness of the barrier layer and effectively reduce the via resistance.

[0090] A first barrier layer 107 is also formed between the metal crystal adhesion layer and the through-hole and the trench. This first barrier layer is formed on the sidewalls and bottom of the through-hole and the trench. This first barrier layer 107 can effectively suppress the influence of impurity elements in the dielectric layer on the metal crystal adhesion layer.

[0091] In an optional embodiment of this example, an amorphous metal backing layer 109 is further formed between the metal crystal adhesion layer 108 and the copper 110. This amorphous metal backing layer 109 can be an amorphous Co layer, an amorphous Ru layer, or an amorphous Os layer. Furthermore, the metal element forming this amorphous metal backing layer is the same as that forming the metal crystal adhesion layer. The formation of the amorphous metal backing layer helps improve the uniformity of the upper and lower coverage of the vias and trenches. In this optional embodiment, the thickness of the amorphous metal backing layer can be 1 nm to 3 nm, and the thickness of the metal crystal adhesion layer 108 is approximately 1 nm to 2 nm. In this optional embodiment, the overall thickness of the barrier layer does not increase, while also improving the uniformity of the upper and lower coverage of the vias and trenches.

[0092] Example 2

[0093] This embodiment also provides a damascus process for copper interconnect layers, in which a barrier layer including a metal crystal adhesion layer is formed on the sidewalls and bottom of the vias and trenches forming the copper interconnect layer to effectively suppress the migration and diffusion of copper into the surrounding dielectric layer. Figure 9 As shown, the method includes the following steps:

[0094] Step S201: Form a dielectric layer on the substrate;

[0095] Step S202: Forming through holes and trenches in the dielectric layer;

[0096] Step S203: A barrier layer is formed on the sidewalls and bottom of the through-hole and the sidewalls and bottom of the trench, the barrier layer comprising a graphene layer; and

[0097] Step S204: Fill the vias and trenches with copper to form a copper interconnect layer.

[0098] Steps S201, S202, and S204 described above are the same as steps S101, S102, and S104 in Embodiment 1, and will not be repeated here. The main difference between this embodiment and Embodiment 1 lies in step S203, as follows:

[0099] In this embodiment, the formation Figure 2 After the through hole 105 and groove 106 shown, as Figure 10 As shown, an amorphous carbon layer is deposited on the sidewalls and bottom of the vias and trenches. Specifically, the amorphous carbon layer is deposited using CVD technology at a temperature of 300℃ to 400℃. During the deposition of the amorphous carbon, a thin graphene layer is formed at the interface between the amorphous carbon and the dielectric layer forming the vias and trenches. Therefore, in this embodiment, the graphene layer is actually formed as an amorphous carbon / graphene composite layer 201. The overall thickness of the amorphous carbon / graphene composite layer 201 is between 1 nm and 5 nm, and the thickness of the formed graphene layer is less than 1 nm.

[0100] After forming the above graphene layer, proceed to step S204, as follows: Figure 11 As shown, copper 202 is filled into the vias and trenches to form copper interconnects. In this embodiment, the amorphous carbon / graphene composite layer serves alone as a barrier layer between the copper and the dielectric layer. Due to the excellent interfacial properties of graphene and amorphous carbon, it can effectively suppress the migration or diffusion of copper. Simultaneously, it helps to reduce the thickness of the barrier layer and lower the via resistance.

[0101] In an optional embodiment of this example, after forming the above-mentioned graphene layer, as follows: Figure 12As shown, it also includes forming a metal and / or metal compound layer above the graphene layer as a first barrier layer 203. This first barrier layer can also be a metal Ta layer, a TaN layer, or a stack of Ta and TaN. Preferably, the first barrier layer is formed above the graphene layer on the sidewalls of the vias and trenches.

[0102] After the above graphene layer and the first barrier layer are formed, as follows: Figure 13 As shown, copper 202 is filled into the trenches and vias to form a copper interconnect layer. In this optional embodiment, due to the excellent barrier effect of the graphene layer, the thickness of the first barrier layer can be minimized, thereby achieving a better barrier effect without increasing the overall thickness of the barrier layer, while reducing the via resistance.

[0103] The copper interconnect layer obtained by the above method. Also refer to... Figure 11 The copper interconnect layer is formed in a dielectric layer above the substrate. The copper interconnect layer includes barrier layers on the sidewalls and bottom of the vias and the sidewalls and bottom of the trenches, and copper interconnects formed above the barrier layers to fill the vias and trenches. The barrier layer includes a graphene layer 201, which in this embodiment is actually an amorphous carbon / graphene composite layer. The overall thickness of the amorphous carbon / graphene composite layer 201 is between 1 nm and 5 nm, and the thickness of the formed graphene layer is less than 1 nm. The amorphous carbon / graphene composite layer, acting alone as a barrier layer between copper and the dielectric layer, effectively suppresses copper migration or diffusion due to the excellent interfacial properties of graphene and amorphous carbon. It also helps to reduce the thickness of the barrier layer and lower the via resistance.

[0104] In an optional embodiment of this example, a first barrier layer 203 is further formed between the graphene layer and the copper. Preferably, the first barrier layer is formed above the graphene layer on the sidewall of the via and trench. This first barrier layer can also be a metal Ta layer, a TaN layer, or a stack of Ta and TaN. In this optional embodiment, due to the excellent barrier effect of the graphene layer, the thickness of the first barrier layer can be minimized, thereby achieving a better barrier effect without increasing the overall thickness of the barrier layer, while simultaneously reducing the via resistance.

[0105] As described above, the copper interconnect layer and the damascus steel process method for the copper interconnect layer provided by the present invention have at least the following beneficial technical effects:

[0106] When forming the copper interconnect layer, a barrier layer is first formed on the sidewalls and bottom of the vias and trenches in the dielectric layer. This barrier layer includes a metal crystal adhesion layer or a graphene layer. The metal crystal adhesion layer can be a crystalline Co layer, a crystalline Ru layer, or a crystalline Os layer. In this invention, a first barrier layer can be formed first on the sidewalls and bottom of the vias and trenches, and then the metal crystal adhesion layer can be directly formed by physical vapor deposition. The first barrier layer effectively eliminates the influence of impurity elements in the dielectric layer on the formation of the metal crystal. The metal crystal adhesion layer formed by physical vapor deposition has high crystal material purity and high energy, resulting in a crystal with a tendency towards order. Alternatively, an amorphous metal backing layer can be first formed on the sidewalls and bottom of the vias and trenches by chemical vapor deposition, and then the metal crystal adhesion layer can be formed by physical vapor deposition. The aforementioned metal crystal adhesion layer enhances adhesion to Cu, effectively inhibits Cu diffusion into the dielectric layer, and improves the electron migration performance of Cu. The formation of the aforementioned metal crystal adhesion layer effectively reduces the overall thickness of the barrier layer and the first barrier layer, effectively reducing the via resistance.

[0107] In various embodiments, the barrier layer comprises a graphene layer, which is a composite layer of amorphous carbon and graphene. Amorphous carbon is formed on the sidewalls and bottom of the vias and trenches at a temperature of 300°C to 400°C. During this process, a thin graphene layer is formed at the interface between the amorphous carbon and the dielectric layer. A first barrier layer may or may not be formed between the amorphous carbon layer and the graphene layer and Cu. The formation of the graphene layer results in a lower resistivity for the Cu interconnect layer; the improved interface between the graphene layer and Cu leads to a higher breakdown current density and a longer electron migration lifetime for the Cu interconnect layer, thereby improving the reliability of the interconnect layer. The formation of the graphene layer also effectively reduces the overall thickness of the barrier layer or the barrier layer and the first barrier layer, effectively reducing the via resistance.

[0108] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A damascus steel process for copper interconnect layers, characterized in that, include: A dielectric layer is formed on the substrate; Through-holes and trenches are formed in the dielectric layer; A barrier layer is formed on the sidewalls and bottom of the via and the sidewalls and bottom of the trench. The barrier layer comprises a metal crystal adhesion layer, a first barrier layer, and an amorphous metal pad layer. The amorphous metal pad layer is located between the metal crystal adhesion layer and the first barrier layer, or between the metal crystal adhesion layer and the copper interconnects in the via and trench. The metal crystal adhesion layer is a crystalline Co layer, a crystalline Ru layer, or a crystalline Os layer. The amorphous metal pad layer is an amorphous Co layer, an amorphous Ru layer, or an amorphous Os layer. The metal crystal adhesion layer and the amorphous metal pad layer have the same metal element. Copper is filled into the through holes and trenches to form a copper interconnect layer.

2. The copper interconnect layer damascus process method according to claim 1, characterized in that, Forming a barrier layer on the sidewalls and bottom of the through hole and the sidewalls and bottom of the trench further includes the following steps: A metal and / or metal compound is formed as a first barrier layer on the sidewalls and bottom of the through hole and the sidewalls and bottom of the trench; A metal crystal adhesion layer is formed over the first barrier layer on the sidewall of the through hole and the sidewall of the trench by physical vapor deposition; The amorphous metal liner layer is formed over the metal crystal adhesion layer by chemical vapor deposition.

3. The copper interconnect layer damascus process method according to claim 1, characterized in that, Forming a barrier layer on the sidewalls and bottom of the through hole and the sidewalls and bottom of the trench further includes the following steps: A metal and / or metal compound is formed as a first barrier layer on the sidewalls and bottom of the through hole and the sidewalls and bottom of the trench; The amorphous metal liner layer is formed by chemical vapor deposition over the first barrier layer on the sidewalls of the through hole and the sidewalls of the trench. The metal crystal adhesion layer is formed over the amorphous metal backing layer by physical vapor deposition.

4. The copper interconnect layer damascus process method according to claim 3, characterized in that, The thickness of the amorphous metal backing layer is between 1 nm and 3 nm, and the thickness of the metal crystal adhesion layer is between 1 nm and 2 nm.

5. The damascus process for copper interconnect layers according to claim 1, characterized in that, The metal crystals in the metal crystal adhesion layer have a hexagonal close-packed structure or a face-centered cubic structure.

6. The copper interconnect layer damascus process method according to claim 1, characterized in that, The first barrier layer is a TaN layer or a TaN / Ta stack.

7. A copper interconnect layer, said copper interconnect layer being formed in vias and trenches in a dielectric layer of a substrate, characterized in that, The copper interconnect layer includes a barrier layer formed on the sidewalls and bottom of the via and the sidewalls and bottom of the trench, and copper interconnects formed above the barrier layer to fill the via and trench. The barrier layer includes a first barrier layer, a metal crystal adhesion layer, and an amorphous metal pad layer. The amorphous metal pad layer is located between the metal crystal adhesion layer and the first barrier layer, or between the metal crystal adhesion layer and the copper interconnects in the via and trench. The metal crystal adhesion layer is a crystalline Co layer, a crystalline Ru layer, or a crystalline Os layer. The amorphous metal pad layer is an amorphous Co layer, an amorphous Ru layer, or an amorphous Os layer, and the metal crystal adhesion layer and the amorphous metal pad layer have the same metal element.

8. The copper interconnect layer according to claim 7, characterized in that, The metal crystals in the metal crystal adhesion layer have a hexagonal close-packed structure or a face-centered cubic structure.

9. The copper interconnect layer according to claim 7, characterized in that, The thickness of the amorphous metal backing layer is between 1 nm and 3 nm, and the thickness of the metal crystal adhesion layer is between 1 nm and 2 nm.

10. The copper interconnect layer according to claim 7, characterized in that, The first barrier layer is a TaN layer or a TaN / Ta stack.

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