Display substrate, display panel and device

Abstract

The present application discloses a display substrate, a display panel and a device, belonging to the field of display technology. The display substrate includes: a source-drain layer, a planarization layer and an anode layer stacked in sequence; the source-drain layer includes at least one pair of signal lines; the anode layer includes a common power line, and the common power line has a vent hole; the overlapping area between the two signal lines in any pair of signal lines and the projection pattern of the vent hole is equal, and the projection pattern of the vent hole is the positive projection pattern of the vent hole on the common power line on the source-drain layer. The overlapping area between the common power line and the two signal lines in a pair of signal lines is equal, so that the parasitic capacitance between the common power line and the two signal lines in a pair of signal lines is the same, so that the signals transmitted by the pair of signal lines are matched, that is, the rising edge duration and the falling edge duration of the signals transmitted by the two signal lines in a pair of signal lines are equal, ensuring the uniformity of the display screen.

Description

[0001] This application is a divisional application of the Chinese application with application number 201911189833.6, application date November 28, 2019, and invention name “Organic light-emitting diode display substrate, display panel and device”. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a display substrate, a display panel and a device. Background Art

[0003] In an organic light emitting diode (OLED) display panel, the anode layer is disposed on a planarization layer (PLN). Gas is generated during the preparation of the PLN. To discharge the gas smoothly, exhaust holes are provided on the common power supply (VSS) line in the peripheral area of ​​the anode layer. Summary of the invention

[0004] The embodiments of the present disclosure provide a display substrate, a display panel and a device, which can alleviate the problem of uneven display images. The technical solution is as follows:

[0005] In one aspect, the present disclosure provides a display substrate, the display substrate having a display area and a peripheral area arranged around the display area, the display substrate comprising:

[0006] A source-drain layer, a planarization layer and an anode layer stacked in sequence;

[0007] In the peripheral region, the source-drain electrode layer includes at least one pair of signal lines, the signal lines are signal lines of the gate circuit, the anode layer includes a common power line, and the common power line has a vent hole;

[0008] The overlapping areas of the two signal lines in the at least one pair of signal lines and the vent hole projection pattern are equal, and the vent hole projection pattern is a pattern of the positive projection of the vent holes on the common power line on the source and drain electrode layer.

[0009] Optionally, both signal lines in one pair of the at least one pair of signal lines overlap with projections of the same column of air vents in the air vent projection pattern, and overlapping areas between the two signal lines and the projection of the same air vent are equal.

[0010] Optionally, each of the air venting holes in the row of air venting holes is a centrally symmetrical pattern, and the center of the projection of the air venting hole is located in the middle of two signal lines in the pair of signal lines.

[0011] Optionally, the distances from the center of the projection of the vent hole to the sides of two signal lines in the pair of signal lines are equal.

[0012] Optionally, a maximum dimension of the vent hole in a width direction of the signal line is greater than a width of any one of the signal lines.

[0013] Optionally, an overlapping area between two signal lines in a pair of signal lines in the at least one pair of signal lines and the projection pattern of the air release hole is zero.

[0014] Optionally, two signal lines in one pair of the at least one pair of signal lines overlap with projections of a column of air vents in the air vent projection pattern respectively, and the two columns of air vents have the same number of air vents and the areas of the air vents are the same.

[0015] Optionally, the vent hole is square or circular.

[0016] Optionally, the source-drain electrode layer includes a plurality of pairs of signal lines, and overlapping areas between any two pairs of signal lines and the projection patterns of the air release holes are equal or unequal.

[0017] Optionally, one pair of signal lines in the at least one pair of signal lines includes a high-level clock signal line and a low-level clock signal line.

[0018] Optionally, one pair of signal lines in the at least one pair of signal lines includes a gate high level line and a gate low level line.

[0019] In one aspect, the present disclosure provides a display panel, comprising: the display substrate as described above.

[0020] In one aspect, the present disclosure provides a display device, the display device comprising: a display panel as described above

[0021] The technical solution provided by the embodiments of the present disclosure brings the following beneficial effects:

[0022] In the embodiment of the present disclosure, the overlapping area between the common power line and the two signal lines in a pair of signal lines is designed so that the overlapping area between the common power line and the two signal lines in a pair of signal lines are equal, thereby making the parasitic capacitance between the common power line and the two signal lines in a pair of signal lines the same, thereby making the signals transmitted by the pair of signal lines match, that is, the rising edge duration and the falling edge duration of the signals transmitted by the two signal lines in a pair of signal lines are equal, thereby ensuring the uniformity of the displayed picture. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0024] Figure 1 is a layer diagram of an OLED display substrate provided by an embodiment of the present disclosure;

[0025] Figure 2 is a regional schematic diagram of an OLED display substrate provided by an embodiment of the present disclosure;

[0026] Figure 3 is a schematic diagram of a membrane layer in a related technology provided by an embodiment of the present disclosure;

[0027] Figure 4 is a timing diagram of a clock signal in a related technology provided by an embodiment of the present disclosure;

[0028] Figure 5 is a structural schematic diagram of an organic light emitting diode display substrate provided by an embodiment of the present disclosure;

[0029] Figure 6 is a timing diagram of a clock signal provided by an embodiment of the present disclosure;

[0030] Figure 7 It is a schematic structural diagram of another organic light emitting diode display substrate provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0032] Organic light emitting diode (OLED) display panels can be divided into two types according to the driving mode: passive matrix driving OLED (PMOLED) and active matrix driving OLED (AMOLED). The solution provided in this application is mainly applied to AMOLED display panels.

[0033] Figure 1 is a layer diagram of an OLED display substrate provided by an embodiment of the present disclosure. Figure 1The OLED display substrate includes a substrate 100 and a first gate layer 104, a gate insulating layer (GI) 105, a second gate layer 106, an interlayer insulating layer 107, a source drain (SD) layer 101, a planarization layer (PLN) 102, an anode layer 103, a pixel definition layer (PDL) 108, an organic light emitting layer 109 and a cathode layer 1010 stacked on the substrate 100.

[0034] Exemplarily, the substrate 100 may be a transparent substrate, such as a glass substrate. The gate insulating layer 105 and the interlayer insulating layer 107 may be silicon nitride insulating layers, or other organic or inorganic insulating layers. The planarization layer 102 may be a resin layer, or other organic material layers. The two first gate layers 104, the second gate layer 106, and the source and drain layer 101 may be metal layers or indium tin oxide thin film layers. The anode layer 103 may be a metal layer. The cathode layer 1010 may be an indium tin oxide thin film layer. The pixel defining layer 108 may be a liquid-repellent material layer, such as a fluorinated polyimide or a fluorinated polymethyl methacrylate layer. The organic light-emitting layer 109 may include a hole transport layer, a light-emitting layer, and an electron transport layer, etc., which are stacked.

[0035] Figure 2 is a regional schematic diagram of an OLED display substrate provided by an embodiment of the present disclosure. Figure 2 The OLED display substrate has a display area 10 and a peripheral area 20 arranged around the display area 10 .

[0036] See again Figure 1 In the peripheral region 20, the anode layer 103 is provided with a common power supply (VSS) line 130, and the source-drain layer 101 is provided with a signal line 110 for driving the circuit. For example, the signal line 110 generally provided in the source-drain layer 101 is a signal line of a gate on array (GOA) circuit, a clock signal line (a high-level clock signal line CK, a low-level clock signal line CB), and a gate driving line (a gate high-level line VGH, a gate low-level line VGL) provided in pairs.

[0037] There is a large parasitic capacitance between the VSS line of the anode layer and the wiring of the source and drain layers. Figure 3 Schematic diagram of a membrane layer in a related technology provided by an embodiment of the present disclosure. Figure 3, the overlapping area between the exhaust hole 131 on the VSS line and the two signal lines of a pair of signal lines 110 is different. For example, the overlapping area between the exhaust hole 131 and CK1 and CB1 is different. This situation will cause the overlapping area between the VSS line 130 and the two signal lines 110 in a pair of signal lines 110 to be different, which will lead to different parasitic capacitances between the VSS line 130 and the two signal lines 110. The signals transmitted by a pair of signal lines do not match (that is, the rising edge duration and falling edge duration of the signals transmitted by the two signal lines in a pair of signal lines are not equal), resulting in uneven display images. It is worth noting that Figure 3 Only the circuit layout diagram of the peripheral area on one side of the display area is used. For example, the structure of the peripheral area on the left side of the display area and the peripheral area on the right side of the display area is the same as that on the left side, and the VSS line passes through the peripheral areas on the left, top and right sides of the display area. Therefore, the signal lines 110 on the left and right sides of the display area will be affected by the uneven parasitic capacitance.

[0038] The following table shows Figure 3 The parasitic capacitance between the VSS line and CK1 and CB1.

[0039]

[0040] It can be seen from the table that the parasitic capacitance between CK1 and VSS lines differs from the parasitic capacitance between CB1 and VSS lines by at least 10fF.

[0041] Figure 4 is a timing diagram of a clock signal in a related technology provided by an embodiment of the present disclosure. Figure 4 Since the parasitic capacitance between CK1 and VSS line differs by 10fF from that between CB1 and VSS line, the duration of rising edge x1 (or falling edge) of CK1 and CB1 is inconsistent ( Figure 4 As can be seen from the above, the rising and falling slopes of CK1 and CB1 are different). Due to the different durations of the rising and falling edges of the two signals, the high and low level lengths of the two signals are inconsistent, which in turn causes output mismatch and leads to display abnormality. The higher the frequency, the greater the impact of the different rising and falling times. Therefore, in the high frequency state, the display abnormality is more serious.

[0042] Figure 5 Schematic diagram of the structure of an organic light emitting diode display substrate provided by an embodiment of the present disclosure. Figure 5 The source-drain electrode layer 101 includes at least one pair of signal lines 110 ; the anode layer 103 includes a common power line 130 , and the common power line 130 has a venting hole 131 .

[0043] The overlapping areas of the two signal lines 110 in any pair of signal lines 110 and the vent hole projection pattern are equal. The vent hole projection pattern is a pattern of the orthographic projection of the vent hole 131 on the common power line 130 on the source and drain layer 101 .

[0044] In the embodiment of the present disclosure, the overlapping area between the common power line and the two signal lines in a pair of signal lines is designed so that the overlapping area between the common power line and the two signal lines in a pair of signal lines are equal, thereby making the parasitic capacitance between the common power line and the two signal lines in a pair of signal lines the same, thereby making the signals transmitted by the pair of signal lines match, that is, the rising edge duration and the falling edge duration of the signals transmitted by the two signal lines in a pair of signal lines are equal, thereby ensuring the uniformity of the displayed picture.

[0045] The following table shows Figure 5 The parasitic capacitance between the VSS line and CK1 and CB1.

[0046]

[0047] It can be seen from the table that the difference between the parasitic capacitance between CK1 and VSS lines and the parasitic capacitance between CB1 and VSS lines is only about 1fF.

[0048] Figure 6 is a timing diagram of a clock signal provided by an embodiment of the present disclosure. Figure 6 Since the difference between the parasitic capacitance between CK1 and VSS line and the parasitic capacitance between CB1 and VSS line is small, in this case, the rising edge x1 (or falling edge) time of CK1 and CB1 is consistent ( Figure 6 From the above, we can see that the rising and falling slopes of CK1 and CB1 are the same. Since the rising (or falling) time of the two signals is the same, the high and low level lengths of the two signals are consistent, which makes the outputs match and ensures display uniformity. Even in high-frequency display products, this rise time and fall time will not affect display uniformity, ensuring the display effect.

[0049] In the embodiment of the present disclosure, there are many ways to achieve that the overlapping areas between the two signal lines 110 in a pair of signal lines 110 and the projection pattern of the venting holes are equal.

[0050] In one possible implementation, both signal lines 110 in at least one pair of signal lines 110 overlap with the projections of the same column of vent holes 131 in the projection pattern of the vent holes 131 , and the overlapping areas of the two signal lines 110 and the projections of the same vent hole 131 are equal.

[0051] In this manner, both signal lines 110 in a pair of signal lines 110 overlap with the projections of the same column of the vent holes 131 in the projection pattern of the vent holes 131, so that it is sufficient that the overlapping area between the projection of each vent hole 131 and the two signal lines 110 is equal. Since there is a certain distance between the two signal lines, if one vent hole 131 overlaps with two signal lines at the same time, in this case, a larger vent hole 131 can be designed to facilitate the patterning of the common power line.

[0052] like Figure 5 As shown, CK1 and CB1 overlap with the projections of the same row of vent holes 131, and the overlapping areas of the projections of the same vent hole 131 are equal. VGH and VGL overlap with the projections of the same row of vent holes 131, and the overlapping areas of the projections of the same vent hole 131 are equal.

[0053] Exemplarily, each vent hole 131 in a row of vent holes 131 is a centrally symmetrical pattern, and the center of the projection of the vent hole 131 is located in the middle of two signal lines 110 in a pair of signal lines 110 .

[0054] like Figure 5 As shown, the center O of the projection of the vent hole 131 is located in the middle of the two signal lines 110 , that is, the distance a from the center O to the sides of the two signal lines 110 is equal.

[0055] like Figure 5 As shown, the vent hole 131 may be square; in other implementations, the vent hole 131 may also be circular. The square or circular vent hole 131 is convenient for design and production. In other implementations, the vent hole 131 may also be other regular or irregular shapes.

[0056] In this implementation, the maximum dimension of the vent hole 131 in the width direction of the signal line 110 may be greater than the width of any signal line 110. Figure 5 As shown, the side length d of the vent hole 131 is greater than the width w of the signal line 110 .

[0057] In a possible implementation, the overlapped area between two signal lines 110 in at least one pair of signal lines 110 and the projection pattern of the air release hole is 0, that is, there is no overlap.

[0058] Since the vent holes 131 can be distributed at intervals and do not need to be arranged in an array, no vent holes 131 need to be arranged above a pair of signal lines 110 to ensure that the overlapping areas of the two signal lines 110 in a pair of signal lines 110 and the projection patterns of the vent holes are equal.

[0059] like Figure 5As shown, neither CK2 nor CB2 overlaps with the projection of the vent hole 131 , that is, the overlapping portions of CK2 and CB2 with the vent hole projection pattern are outside the projection of the vent hole 131 .

[0060] In a possible implementation, two signal lines 110 in at least one pair of signal lines 110 overlap with the projections of a column of air vents 131 in the air vent projection pattern, respectively, and the two columns of air vents 131 have the same number of air vents 131 and the same area of ​​each air vent 131.

[0061] In this manner, two signal lines 110 in a pair of signal lines 110 overlap with the projection patterns of two columns of air release holes 131 , respectively. Thus, it is only necessary that the areas of the air release holes 131 are the same.

[0062] Exemplarily, the shapes of the exhaust holes 131 are the same. Figure 7 is a schematic diagram of the structure of another organic light emitting diode display substrate provided by an embodiment of the present disclosure. Figure 7 , the vent hole 131 may be square; in other implementations, the vent hole 131 may also be circular. The square or circular vent hole 131 is convenient for design and production. In other implementations, the vent hole 131 may also be other regular or irregular shapes.

[0063] Since the distance between the two signal lines is not large, in order to avoid the two rows of vent holes 131 being too close to each other and being unfavorable for patterning, the size of the vent holes 131 can be appropriately reduced and the distance between the two rows of vent holes 131 can be increased. For example, the maximum size of the vent holes 131 in the width direction of the signal line 110 can be smaller than the width of any signal line 110. Figure 7 As shown, the side length or diameter of the vent hole 131 may be smaller than the width of the signal line 110 .

[0064] Of course, in addition to Figure 7 In this way, one signal line 110 can also overlap with multiple columns of vent holes.

[0065] Since the signal lines 110 are arranged along the column direction of the display substrate, the vent holes 131 in the present application are also arranged along the column direction for the convenience of design and production. In other implementations, the vent holes can also be arranged along other directions, which is not limited in the present application.

[0066] See again Figure 5 and Figure 7 The source-drain electrode layer 101 includes a plurality of pairs of signal lines 110 , and the overlapping areas of any two pairs of signal lines 110 and the projection patterns of the vent holes are equal or unequal.

[0067] That is, in the embodiment of the present disclosure, different pairs of signal lines 110 can be implemented in different ways, and the parasitic capacitance balance between a pair of signal lines and the common power line does not need to be achieved in the same way for each pair, which provides a higher degree of freedom in design.

[0068] For example, Figure 5 In the figure, the leftmost pair of signal lines 110 and the rightmost pair of signal lines 110 both overlap with the projections of the same column of vent holes 131 , and the middle pair of signal lines 110 does not overlap with the projections of the vent holes 131 . Figure 7 In the figure, the leftmost pair of signal lines 110 and the rightmost pair of signal lines 110 are overlapped with the projections of a column of vent holes 131, respectively, and the middle pair of signal lines 110 are not overlapped with the projections of the vent holes 131. In other implementations, each pair of signal lines 110 may overlap with the projections of the vent holes 131 in the same manner, or may overlap with the projections of the vent holes 131 in three manners, which is not limited in the present application.

[0069] The present disclosure provides a display panel, which includes a display substrate as shown in any of the previous drawings.

[0070] In the embodiment of the present disclosure, the overlapping area between the common power line and the two signal lines in a pair of signal lines is designed so that the overlapping area between the common power line and the two signal lines in a pair of signal lines are equal, thereby making the parasitic capacitance between the common power line and the two signal lines in a pair of signal lines the same, thereby making the signals transmitted by the pair of signal lines match, that is, the rising edge duration and the falling edge duration of the signals transmitted by the two signal lines in a pair of signal lines are equal, thereby ensuring the uniformity of the displayed picture.

[0071] The present disclosure provides a display device, which includes the display panel as described above.

[0072] In specific implementation, the display device provided in the embodiment of the present disclosure can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.

[0073] In the embodiment of the present disclosure, the overlapping area between the common power line and the two signal lines in a pair of signal lines is designed so that the overlapping area between the common power line and the two signal lines in a pair of signal lines are equal, thereby making the parasitic capacitance between the common power line and the two signal lines in a pair of signal lines the same, thereby making the signals transmitted by the pair of signal lines match, that is, the rising edge duration and the falling edge duration of the signals transmitted by the two signal lines in a pair of signal lines are equal, thereby ensuring the uniformity of the displayed picture.

[0074] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A display substrate, characterized in that: The display substrate has a display area (10) and a peripheral area (20) arranged around the display area (10), and the display substrate comprises: A source-drain electrode layer (101), a planarization layer (102), and an anode layer (103) stacked in sequence; In the peripheral region (20), the source-drain electrode layer (101) comprises at least one pair of signal lines (110), the signal lines (110) are signal lines of a gate circuit, the anode layer (103) comprises a common power line (130), and the common power line (130) has a venting hole (131); The overlapping areas of two signal lines (110) in the at least one pair of signal lines (110) and the projection pattern of the air vents are equal, and the projection pattern of the air vents is a pattern of the orthographic projection of the air vents (131) on the common power line (130) on the source-drain electrode layer (101); One pair of signal lines in the at least one pair of signal lines (110) includes a high-level clock signal line and a low-level clock signal line, and / or one pair of signal lines in the at least one pair of signal lines (110) includes a gate high-level line and a gate low-level line.

2. The display substrate according to claim 1, characterized in that: Both signal lines (110) in a pair of signal lines (110) in the at least one pair of signal lines (110) overlap with projections of the same column of air release holes (131) in the projection pattern of the air release holes (131), and overlapping areas of the projections of the two signal lines (110) and the same air release hole (131) are equal.

3. The display substrate according to claim 2, characterized in that: Each of the air release holes (131) in the row of air release holes (131) is a centrally symmetrical figure, and the center of the projection of the air release hole (131) is located in the middle of two signal lines (110) in the pair of signal lines (110).

4. The display substrate according to claim 3, characterized in that: The distances from the center of the projection of the vent hole (131) to the sides of two signal lines (110) in the pair of signal lines (110) are equal.

5. The display substrate according to claim 2, characterized in that: The maximum dimension of the vent hole (131) in the width direction of the signal line (110) is greater than the width of any one of the signal lines (110).

6. The display substrate according to claim 1, characterized in that: The area in which two signal lines (110) in a pair of signal lines (110) of the at least one pair of signal lines (110) overlap with the projection pattern of the air release hole is zero.

7. The display substrate according to claim 1, characterized in that: Two signal lines (110) in a pair of signal lines (110) in the at least one pair of signal lines (110) respectively overlap with the projections of a column of air release holes (131) in the air release hole projection pattern, the number of air release holes (131) in the two columns of air release holes (131) is the same, and the area of ​​each air release hole (131) is the same.

8. The display substrate according to any one of claims 1 to 7, characterized in that: The venting hole (131) is square or circular.

9. The display substrate according to any one of claims 1 to 7, characterized in that: The source-drain electrode layer (101) comprises a plurality of pairs of signal lines (110), and the overlapping areas of any two pairs of signal lines (110) and the projection patterns of the air release holes are equal or unequal.

10. A display panel, characterized in that: The display panel comprises: a display substrate as claimed in any one of claims 1 to 9.

11. A display device, characterized in that: The display device comprises: the display panel as claimed in claim 10.

Images