Wideband voltage controlled oscillator circuit

Abstract

This disclosure relates to a wideband voltage-controlled oscillator (VCO) circuit. Electronic devices may include a transceiver with mixer circuitry that up-converts or down-converts a signal based on a voltage-controlled oscillator (VCO) signal. The transceiver circuitry may include a first VCO, a second VCO, a third VCO, and a fourth VCO. Each VCO may include a VCO core that receives a control voltage and an inductor coupled to the VCO core. Fixed linear capacitors may be coupled between the VCO cores. A switching network may be coupled between the VCOs. Control circuitry may place the VCO circuitry in one of four different operating modes and may switch between operating modes to selectively control the current direction in each of the inductors. The VCO circuitry may generate a VCO signal within a corresponding frequency range in each operating mode. The VCO circuitry may exhibit a relatively wide frequency range across all operating modes while introducing minimal phase noise into the system.

Description

[0001] This application claims priority to U.S. Patent Application No. 17 / 131,168, filed December 22, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates in general to electronic devices, and more specifically to electronic devices having wireless circuitry. Background Technology

[0003] Electronic devices often possess wireless communication capabilities. This invention discloses an electronic device with wireless communication capabilities, which includes a wireless communication circuit having one or more antennas. The wireless transceiver circuit in the wireless communication circuit uses the antennas to transmit or receive radio frequency signals.

[0004] Wireless transceiver circuits typically include mixers for up-converting or down-converting input signals based on local oscillator signals. These local oscillator signals are often generated using voltage-controlled oscillator circuits. Designing satisfactory voltage-controlled oscillator circuits for electronic devices can be challenging. Summary of the Invention

[0005] Electronic devices may include wireless circuitry. The wireless circuitry may include transceiver circuitry that transmits radio frequency signals via an antenna. The transceiver circuitry may include mixer circuitry. The mixer circuitry may up-convert or down-convert the transceiver signal based on the output signal of a voltage-controlled oscillator (VCO). The transceiver circuitry may include VCO circuitry that generates the VCO output signal. The VCO circuitry may include a first VCO, a second VCO, a third VCO, and a fourth VCO. Each VCO may include a VCO core that receives a control voltage and an inductor coupled between a first terminal and a second terminal of the VCO core. A fixed linear capacitor may be coupled between the VCO cores. A switching network may be coupled between the first VCO, the second VCO, the third VCO, and the fourth VCO. The switching network may include, for example, a butterfly switch coupled in parallel with the capacitor between different pairs of VCO cores.

[0006] The electronic device may include control circuitry. The control circuitry provides control signals to the switching network to place the VCO circuitry into one of four different operating modes. The control circuitry can switch between operating modes to selectively control the current direction in each of the inductors. The VCO circuitry can generate a VCO output signal within the corresponding frequency range in each operating mode. The VCO circuitry can exhibit a relatively wide frequency range across all operating modes while introducing minimal phase noise into the system.

[0007] One aspect of this disclosure provides a voltage-controlled oscillator (VCO) circuit. The VCO circuit may have multiple VCOs, including a first VCO having a first inductor, a second VCO having a second inductor, a third VCO having a third inductor, and a fourth VCO having a fourth inductor. The VCO circuit may have a first pair of capacitors coupled between the first VCO and the second VCO. The VCO circuit may have a second pair of capacitors coupled between the second VCO and the third VCO. The VCO circuit may have a third pair of capacitors coupled between the third VCO and the fourth VCO. The VCO circuit may have a fourth pair of capacitors coupled between the fourth VCO and the first VCO. The VCO circuit may have a switching network communicatively coupled to the multiple VCOs, the switching network being configured to selectively control the current direction in the first, second, third, and fourth inductors to generate a VCO output signal across a frequency range in at least four operating modes of the VCO circuit.

[0008] One aspect of this disclosure provides a voltage-controlled oscillator (VCO) circuit. The VCO circuit may include a first VCO having a first VCO core and a first inductor coupled to the first VCO core. The VCO circuit may include a second VCO having a second VCO core and a second inductor coupled to the second VCO core. The VCO circuit may include a first pair of fixed capacitors coupled between the first VCO core and the second VCO core. The VCO circuit may include a first switching circuit coupled in parallel with the first pair of fixed capacitors between the first VCO core and the second VCO core.

[0009] One aspect of this disclosure provides an electronic device. The electronic device may have a baseband processor circuit configured to generate a baseband signal. The electronic device may have a mixer circuit configured to generate a radio frequency (RF) signal based on the baseband signal and a voltage-controlled oscillator (VCO) output signal. The electronic device may have an antenna configured to transmit the RF signal. The electronic device may have a VCO circuit configured to generate a VCO output signal. The VCO circuit may have a first VCO core with a first terminal and a second terminal. The VCO circuit may have a first inductor coupled between the first and second terminals. The VCO circuit may have a second VCO core with a third and a fourth terminal. The VCO circuit may have a second inductor coupled between the third and fourth terminals. The VCO circuit may have a first fixed capacitor that couples the first terminal to the fourth terminal. The VCO circuit may have a second fixed capacitor that couples the second terminal to the third terminal. The VCO circuit may have a switching circuit that couples the first and second terminals in parallel with the first and second fixed capacitors to the third and fourth terminals. The switching circuit has a first state and a second state. In the first state, the switching circuit couples the first terminal to the fourth terminal and the second terminal to the third terminal. In the second state, the switching circuit couples the first terminal to the third terminal and the second terminal to the fourth terminal. Attached Figure Description

[0010] Figure 1 This is a functional block diagram of an exemplary electronic device with a transceiver circuit having a voltage-controlled oscillator (VCO) according to some implementation schemes.

[0011] Figure 2 This is a diagram of an exemplary VCO circuit according to some implementation schemes, which has multiple VCOs coupled together using fixed capacitors and a switching network for extending the frequency range of the VCO circuit.

[0012] Figure 3 This is a circuit diagram of an exemplary VCO core based on some implementation schemes.

[0013] Figure 4 This is a circuit diagram of an exemplary butterfly switch that can be formed in a switching network coupled between VCOs according to some implementation schemes.

[0014] Figure 5 It is a flowchart illustrating exemplary operations that can be performed in generating VCO output signals using a VCO circuit, according to some implementation schemes.

[0015] Figures 6 to 9This is a diagram illustrating how an exemplary VCO circuit, according to some implementation schemes, can be used to generate VCO signals in corresponding first, second, third, and fourth operating modes.

[0016] Figure 10 This illustrates the implementation scheme in some ways. Figures 6 to 9 The graph illustrates how the VCO circuit can be used to maximize the frequency range of the VCO circuit in the first, second, third, and fourth operating modes. Detailed Implementation

[0017] Figure 1 The electronic device 10 may be: a computing device, such as a laptop computer, desktop computer, computer monitor containing an embedded computer, tablet computer, cellular phone, media player, or other handheld or portable electronic device; a smaller device, such as a wristwatch, a wristband, a headset or handset, a device embedded in glasses; or other equipment worn on a user's head; or other wearable or micro-devices, televisions, computer monitors without an embedded computer, gaming devices, navigation devices, embedded systems (such as systems in which electronic equipment with a display is installed in a kiosk or vehicle), voice-controlled speakers connected to the wireless Internet, home entertainment devices, remote control devices, game controllers, peripheral user input devices, wireless base stations or access points, equipment that enables the functions of two or more of these devices; or other electronic equipment.

[0018] like Figure 1 As shown in the functional block diagram, device 10 may include components located on or within an electronic device housing, such as housing 12. Housing 12 (sometimes referred to as a shell) may be formed of plastic, glass, ceramic, fiber composite material, metal (e.g., stainless steel, aluminum, metal alloys, etc.), other suitable materials, or combinations of these materials. In some cases, housing 12 may be partially or entirely formed of dielectric or other low-conductivity materials (e.g., glass, ceramic, plastic, sapphire, etc.). In other cases, housing 12 or at least some of the structures constituting housing 12 may be formed of metallic elements.

[0019] Device 10 may include control circuitry 14. Control circuitry 14 may include storage devices, such as storage circuitry 16. Storage circuitry 16 may include hard disk drive storage devices, non-volatile memory (e.g., flash memory configured to form a solid-state drive or other electrically programmable read-only memory), volatile memory (e.g., static random access memory or dynamic random access memory), etc. Storage circuitry 16 may include storage devices and / or removable storage media integrated within device 10.

[0020] Control circuitry 14 may include processing circuitry, such as processing circuitry 18. Processing circuitry 18 may be used to control the operation of device 10. Processing circuitry 18 may include one or more microprocessors, microcontrollers, digital signal processors, host processors, baseband processor integrated circuits, application-specific integrated circuits, central processing units (CPUs), etc. Control circuitry 14 may be configured to perform operations in device 10 using hardware (e.g., dedicated hardware or circuitry), firmware, and / or software. Software code for performing operations in device 10 may be stored on storage circuitry 16 (e.g., storage circuitry 16 may include a non-transitory (tangible) computer-readable storage medium storing software code). This software code may sometimes be referred to as program instructions, software, data, commands, or code. The software code stored on storage circuitry 16 may be executed by processing circuitry 18.

[0021] Control circuitry 14 can be used to run software on device 10, such as satellite navigation applications, internet browsing applications, Voice over Internet Protocol (VoIP) telephone calling applications, email applications, media playback applications, operating system functions, etc. To support interaction with external equipment, control circuitry 14 can be used to implement communication protocols. Communication protocols that can be implemented using control circuitry 14 include: Internet Protocol, Wireless Local Area Network (WLAN) protocols (e.g., IEEE 802.11 protocol—sometimes referred to as...). Protocols for other short-range wireless communication links, such as This protocol may be any of the following: wireless personal area network (WPAN) protocols, IEEE 802.11ad protocols (e.g., ultra-wideband protocols), cellular phone protocols (e.g., 3G, 4G (LTE), 5G, etc.), antenna diversity protocols, satellite navigation system protocols (e.g., Global Positioning System (GPS), Global Navigation Satellite System (GLONASS), etc.), antenna-based spatial ranging protocols (e.g., radio detection and ranging (RADAR) protocols for signals transmitted at millimeter and centimeter wave frequencies or other desired distance detection protocols), or any other desired communication protocol. Each communication protocol may be associated with a corresponding radio access technology (RAT), which specifies the physical connection method used to implement the protocol.

[0022] Device 10 may include input-output circuitry 20. Input-output circuitry 20 may include input-output devices 22. Input-output devices 22 may be used to allow data to be supplied to device 10 and to allow data to be supplied from device 10 to external devices. Input-output devices 22 may include user interface devices, data port devices, and other input-output components. For example, input-output devices 22 may include touch sensors, displays (e.g., touch-sensitive displays and / or force-sensitive displays), light-emitting components such as displays without touch sensor capability, buttons (mechanical, capacitive, optical, etc.), scroll wheels, touchpads, keypads, keyboards, microphones, cameras, buttons, speakers, status indicators, audio jacks and other audio port components, digital data port devices, motion sensors (accelerometers, gyroscopes, and / or compasses for detecting motion), capacitive sensors, proximity sensors, magnetic sensors, force sensors (e.g., force sensors coupled to a display to detect pressure applied to the display), etc. In some configurations, keyboards, headphones, displays, pointing devices such as touchpads, mice and joysticks, and other input-output devices may be coupled to device 10 via wired or wireless connections (e.g., some of the input-output devices 22 may be peripherals coupled to the main processing unit or other parts of device 10 via wired or wireless links).

[0023] Input-output circuitry 20 may include wireless circuitry 24 to support wireless communication. Wireless circuitry 24 (sometimes referred to herein as wireless communication circuitry 24) may include one or more antennas 40. Wireless circuitry 24 may also include baseband processor circuitry, transceiver circuitry, amplifier circuitry, filter circuitry, switching circuitry, RF transmission lines, and / or any other circuitry for transmitting and / or receiving RF signals using antennas 40.

[0024] For example, such as Figure 1 As shown, wireless circuit 24 may include radio frequency transceiver circuitry, such as transceiver circuitry 28, which transmits and / or receives radio frequency signals within a corresponding frequency band of a radio frequency (sometimes referred to herein as a communication band or simply a "band"). For example, transceiver circuitry 28 may handle a wireless local area network (WLAN) band (e.g., (IEEE 802.11) or other WLAN communication bands, such as the 2.4 GHz WLAN band (e.g., 2400 MHz to 2480 MHz), the 5 GHz WLAN band (e.g., 5180 MHz to 5825 MHz), 6E band (e.g., 5925MHz to 7125MHz) and / or others Frequency bands (e.g., 1875MHz to 5160MHz); Wireless Personal Area Network (WPAN) frequency bands such as 2.4GHz Frequency bands or other WPAN communication bands; cellular telephone bands (e.g., bands from about 600 MHz to about 5 GHz, 3G bands, 4G LTE bands, 5G New Radio Frequency Range 1 (FR1) band below 10 GHz, 5G New Radio Frequency Range 2 (FR2) band between 20 GHz and 60 GHz, etc.); other centimeter or millimeter wave bands between 10 GHz and 300 GHz; near-field communication bands (e.g., 13.56 MHz); satellite navigation bands (e.g., GPS bands from 1565 MHz to 1610 MHz, Global Navigation Satellite System (GLONASS) bands, BeiDou Navigation Satellite System (BDS) bands, etc.); ultra-wideband (UWB) bands operating under the IEEE 802.15.4 protocol and / or other ultra-wideband communication protocols; communication bands under the 3GPP wireless communication standard family; communication bands under the IEEE 802.XX standard family; and / or any other desired bands of interest. The transceiver circuit 28 may sometimes be referred to as transceiver 28 in this article.

[0025] The transceiver circuit 28 can be coupled to one or more antennas 40 via one or more radio frequency (RF) transmission lines, such as RF transmission line 36. The transmission lines in device 10, such as RF transmission line 36, may include coaxial cables, microstrip transmission lines, stripline transmission lines, edge-coupled microstrip transmission lines, edge-coupled stripline transmission lines, transmission lines formed by combinations of these types of transmission lines, etc. Antenna 40 can be formed using any desired antenna structure. For example, antenna 40 may include an antenna with resonant elements, formed by a loop antenna structure, patch antenna structure, inverted F-shaped antenna structure, slot antenna structure, planar inverted F-shaped antenna structure, helical antenna structure, monopole antenna, dipole, a mixture of these designs, etc. Adjustable filter circuitry, switching circuitry, impedance matching circuitry, and / or other antenna tuning components can be used to adjust the frequency response and wireless performance of antenna 40 over time.

[0026] Wireless circuit 24 may also include baseband processor circuitry, such as baseband processor 26. Baseband processor 26 can be coupled to transceiver circuitry 28 via baseband path 30. Although for clarity, in Figure 1 In the example, control circuitry 14 is shown as separate from wireless circuitry 24, but wireless circuitry 24 may include processing circuitry and / or storage circuitry, the processing circuitry forming part of processing circuitry 18 and the storage circuitry forming part of storage circuitry 16 of control circuitry 14 (e.g., portions of control circuitry 14 may be implemented on wireless circuitry 24, baseband processor 26, etc.).

[0027] Figure 1The examples provided are merely illustrative. Generally, wireless circuitry 24 may include any desired number of baseband processors 26, any desired number of transceivers, and any desired number of antennas 40. Each baseband processor 26 may be coupled to one or more transceivers via a corresponding baseband path 30. Each transceiver may include transmitter circuitry that outputs uplink signals to antenna 40, and / or may include receiver circuitry that receives downlink signals from antenna 40. Each transceiver may be coupled to one or more antennas 40 via a corresponding RF transmission line 36. One or more of the RF transmission lines may have an RF front-end module inserted thereon. The RF front-end module may include RF front-end components mounted to a common package, chip, or substrate, such as filters, switches, impedance matching circuitry, antenna tuning components, amplifier circuitry, RF couplers, sensors, etc.

[0028] During wireless transmission, baseband processor 26 can provide baseband signal BB to transceiver circuitry 28 via baseband path 30. Transceiver circuitry 28 may include circuitry for converting the baseband signal BB received from baseband processor 26 into a corresponding radio frequency (RF) signal. For example, transceiver circuitry 28 may include mixer circuitry, such as one or more mixers 34, for up-converting (or modulating) the baseband signal BB to a radio frequency before transmission via antenna 40 (e.g., as the RF signal SIGRF). Transceiver circuitry 28 may also include digital-to-analog converter (DAC) circuitry and / or analog-to-digital converter (ADC) circuitry for converting signals between the digital and analog domains (for clarity, in...). Figure 1 (Not shown in the image). Antenna 40 can transmit radio frequency signals to external wireless equipment by radiating the radio frequency signal SIGRF into free space.

[0029] During wireless reception, antenna 40 can receive a radio frequency (RF) signal SIGRF from an external wireless device. The received RF signal SIGRF can be transmitted to transceiver circuitry 28 via RF transmission line 36. Transceiver circuitry 28 may include circuitry for converting the received RF signal into a corresponding baseband signal. For example, transceiver circuitry 28 may use one or more mixers 34 to downconvert (or demodulate) the received RF signal SIGRF to a baseband frequency before transmitting the received signal through baseband path 30 to baseband processor 26 (e.g., as baseband signal BB).

[0030] To perform upconversion, mixer 34 can mix a local oscillator (LO) signal, such as the local oscillator signal LO received via path 38, with an input signal, such as the baseband signal BB. If desired, the local oscillator signal LO can include multiple local oscillator signals, which are provided to different mixers 34 for upconversion to different frequencies. For example, the local oscillator signal LO can include a radio frequency local oscillator (RFLO) signal for upconverting the signal from baseband to a radio frequency or for upconverting the signal from an intermediate frequency (IF) to a radio frequency (e.g., as the radio frequency signal SIGRF). In examples using an intermediate frequency, the local oscillator signal LO can also include an intermediate frequency local oscillator (IFLO) signal for upconverting the signal from baseband to the intermediate frequency. In examples where the radio frequency is greater than 10 GHz (e.g., exceeding 20 GHz, exceeding 30 GHz, etc.), the intermediate frequency may, for example, be between approximately 100 MHz and 10 GHz. Using an intermediate frequency in scenarios with radio frequencies greater than 10 GHz allows signals to be transmitted over relatively large distances within device 10 with minimal signal attenuation, because high frequencies such as those exceeding 10 GHz are particularly prone to attenuation. Similarly, to perform downconversion, mixer 34 can mix the local oscillator signal LO with an input signal such as the RF signal SIGRF to generate an intermediate frequency signal or a baseband signal BB.

[0031] Transceiver circuit 28 may include local oscillator circuitry, such as local oscillator 32, for generating a local oscillator signal LO. In a specific implementation described herein by way of example, local oscillator 32 may include voltage-controlled oscillator circuitry, such as voltage-controlled oscillator (VCO) circuitry 42. VCO circuitry 42 may be based on a control voltage, such as control voltage V, received on control path 44 (e.g., from control circuitry 14). CTRL A periodic signal, sometimes referred to herein as the VCO output signal OSC, is output on path 38. Local oscillator 32 can generate a local oscillator signal LO based on the VCO output signal OSC. For example, local oscillator 32 may include a phase-locked loop (PLL), a digital trigger, a buffer circuit, and / or any other desired circuitry (e.g., a clock circuit) that uses the VCO output signal OSC generated by VCO circuit 42 to produce the local oscillator signal LO. Figure 1 The example is merely illustrative. VCO circuit 42 need not be formed as part of local oscillator 32. Generally, VCO output signal OSC can be used to perform any desired function of device 10 that would otherwise require a VCO output signal such as VCO output signal OSC.

[0032] Control voltage V CTRLThis can be used to control the frequency of the VCO output signal OSC, and thus the frequency of the local oscillator signal LO (e.g., to control mixer 34 to down-convert or up-convert the input signal to a desired frequency). In the specific implementation described herein as an example, the VCO circuit 42 includes multiple voltage-controlled oscillators (VCOs). Forming the VCO circuit 42 with multiple VCOs can be used to extend the total frequency range that mixer 34 can produce compared to scenarios where the VCO circuit includes only a single VCO.

[0033] In some cases, switched capacitors (e.g., series-coupled switches and capacitors) are coupled between different pairs of VCOs. However, in practice, the ratio C of the switched capacitors is... ON / C OFF The switched capacitor serves as a bottleneck in the frequency range that the VCO circuit 42 can generate. Furthermore, the switched capacitor can exhibit a relatively low Q factor and can introduce undesirable phase noise into the system. To further extend the frequency range that the VCO circuit 42 can generate while mitigating these problems, the VCO circuit 42 can be configured without a switched capacitor between the VCOs. Instead, the VCO circuit 42 may include a fixed linear capacitor and a separate parallel-coupled switching network coupled between the VCOs. The control circuit 14 can provide a switching control signal SW via control path 44. CTRL The state of the switching network can be controlled to place the VCO circuit 42 into one of several different operating modes. In an example where the VCO circuit 42 includes four VCOs, the switching network can be controlled to place the VCO circuit 42 into one of four different operating modes. Each operating mode can be associated with a different corresponding frequency range that can be generated using the VCO circuit 42. Forming the VCO circuit 42 in this way can be used to maximize the frequency range that can be generated using the VCO circuit 42. Furthermore, compared to the case where switched capacitors are coupled between VCOs, fixed linear capacitors can exhibit greater linearity and a larger Q factor, thereby introducing less phase noise.

[0034] Figure 2 This is an illustration of a VCO circuit 42 that includes four VCOs for generating the VCO output signal OSC. This example is merely illustrative, and in general, the VCO circuit 42 may include two VCOs, six VCOs, more than six VCOs, or any other desired number of VCOs.

[0035] like Figure 2As shown, the VCO circuit 42 may include four VCOs 50, such as a first VCO 50A, a second VCO 50B, a third VCO 50C, and a fourth VCO 50D. Each VCO 50 may be formed on a common substrate such as a flexible or rigid printed circuit board substrate. Each VCO 50 may include a corresponding VCO core 54 having a first terminal N and a second terminal P. The VCO circuit 42 may have taps (output terminals) at each terminal N and P of the VCO cores 54A, 54B, 54C, and 54D (e.g., for output). Figure 1 The VCO output signal OSC). Each VCO core 54 can receive control voltage V. CTRL Used to tune the frequency of the VCO output signal OSC. Terminals N and P can be, for example, the corresponding negative and positive signal terminals of the VCO core. In this example, the VCO output signal OSC can be a differential signal formed by a differential signal pair output from the VCO circuit 42 at terminals N and P (e.g., where the differential signal pair includes a negative signal output at terminal N and a corresponding positive signal output at terminal P).

[0036] Each VCO 50 may also include a corresponding inductor 52 coupled between terminals N and P of the corresponding VCO core 54. Each inductor 52 may have one or more loops or coils of conductive material, such as conductive traces on the underlying substrate. For example, VCO 50A may have an inductor 52A coupled between terminals N and P of VCO core 54A, VCO 50B may have an inductor 52B coupled between terminals N and P of VCO core 54B, VCO 50C may have an inductor 52C coupled between terminals N and P of VCO core 54C, and so on. When the VCO circuit 42 generates the VCO output signal OSC, current may flow around the inductor 52.

[0037] VCO circuit 42 may have a capacitor 56 coupled between pairs of VCOs 50. Capacitor 56 may be a fixed linear capacitor. In some embodiments, capacitor 56 may be a variable capacitor. Capacitor 56 may be coupled in parallel between adjacent pairs of VCOs 50 in VCO circuit 42. For example, as... Figure 2As shown, a first pair of capacitors 56-1 can be coupled in parallel between VCOs 50A and 50B. Capacitor 56-1 may include a first capacitor coupled between terminal P on VCO core 54A and terminal P on VCO core 54B, and may also include a second capacitor coupled between terminal N on VCO core 54A and terminal N on VCO core 54B. Furthermore, a second pair of capacitors 56-2 can be coupled in parallel between VCOs 50B and 50C. Capacitor 56-2 may include a first capacitor coupled between terminal P on VCO core 54B and terminal P on VCO core 54C, and may also include a second capacitor coupled between terminal N on VCO core 54B and terminal N on VCO core 54C. Similarly, a third pair of capacitors 56-3 can be coupled in parallel between VCOs 50C and 50D. Capacitor 56-3 may include a first capacitor coupled between terminal P on VCO core 54C and terminal P on VCO core 54D, and may include a second capacitor coupled between terminal N on VCO core 54C and terminal N on VCO core 54D. Finally, a fourth pair of capacitors 56-4 may be coupled in parallel between VCO 50D and 50A. Capacitor 56-4 may include a first capacitor coupled between terminal P on VCO core 54D and terminal P on VCO core 54A, and may include a second capacitor coupled between terminal N on VCO core 54D and terminal N on VCO core 54A. Although Figure 2 Each of the 56 capacitors in the diagram is illustrated as a single capacitor, but if needed, Figure 2 Each of the capacitors 56 shown may include a plurality of fixed linear capacitors. If desired, the capacitors 56 may be formed as metal-oxide-metal (MOM) capacitors on the underlying substrate used to form the VCO circuit 42.

[0038] VCO circuit 42 may also include switching circuitry, such as a switch network 58, coupled between each of the VCOs 50 in VCO circuit 42. Switch network 58 may be coupled to terminals N and P of each of the VCO cores 54 in VCO circuit 42. In a specific implementation described herein as an example, switch network 58 may include four switching circuits 70 (e.g., butterfly switches), each switching circuit 70 being coupled in parallel with a capacitor 56 between a corresponding pair of VCOs 50 in VCO circuit 42. For example, the switching network 58 may include (e.g., in parallel with capacitor 56-1) a switching circuit 70 (e.g., a butterfly switch) coupled between terminals P and N on VCO cores 54A and 54B, a second switching circuit 70 coupled between terminals P and N on VCO cores 54B and 54C (e.g., in parallel with capacitor 56-2), a third switching circuit 70 coupled between terminals P and N on VCO cores 54C and 54D (e.g., in parallel with capacitor 56-3), and a fourth switching circuit 70 coupled between terminals P and N on VCO cores 54D and 54A (e.g., in parallel with capacitor 56-4).

[0039] Control circuit 14 ( Figure 1 ) can provide switch control signal SW CTRL ( Figure 1 The switching network 58 is configured to control the state of the switching circuit 70 (e.g., a butterfly switch) within it. The switching circuit 70 in the switching network 58 can be adjusted to switch the VCO circuit 42 between different operating modes. Figure 2 In this example, the VCO circuit 42 may have four different operating modes. This is merely illustrative, and in general, the VCO circuit 42 may have any desired number of operating modes. Each operating mode may be associated with a different corresponding frequency range of the VCO output signal OSC, and thus with different corresponding frequency ranges that can be generated at the mixer 34 (e.g., using the local oscillator signal LO generated using the VCO output signal OSC). The control circuit 14 can be controlled by utilizing the switch control signal SW. CTRL The control switch network 58 places the VCO circuit 42 into one of the four operating modes at a given time. The control circuit 14 can also use the control voltage V supplied to the VCO core 54. CTRL The frequency generated by the VCO circuit 42 is tuned. Interconnecting the VCO 50 in the VCO circuit 42 using fixed linear capacitors such as capacitor 56 and parallel-coupled switching networks such as switching network 58 can maximize the frequency range that can be generated using the VCO circuit 54, while minimizing phase noise due to the high Q factor and linearity of capacitor 56.

[0040] Figure 3This is a circuit diagram of a given VCO core 54 in an exemplary specific implementation. Figure 3 The VCO core 54 can be used to form one, more than one, or each of the VCO cores 54A, 54B, 54C, and 54D in the VCO circuit 42. For example... Figure 3 As shown, the VCO core 54 may have a first set of cross-coupled transistors M1 and M2 and a second set of cross-coupled transistors M3 and M4 coupled between terminals P and N. The VCO core 54 may also have one or more varactor diodes, such as varactor diode 60, coupled in parallel with the cross-coupled transistors between terminals P and N. Additionally, one or more switched capacitors 62 may be coupled in parallel between terminals P and N (e.g., in parallel with the cross-coupled transistors and varactor diodes 60). Each switched capacitor 62 may include one or more capacitors coupled in series with a switch.

[0041] Control voltage V CTRL ( Figure 1 and 2 This may include the control voltage V supplied to the varactor diode 60. a and V b And control signals for controlling the switch in the switched capacitor 62. The VCO output signal OSC generated by the corresponding VCO 50 can be output at the tap points coupled to terminals P and N (e.g., as a differential signal pair). The control circuit 14 can use the control voltage V a and V b And the frequency of the VCO output signal OSC generated at terminals P and N is controlled (fine-tuned) by using the control signal of the switch in the control switching capacitor 62. Figure 3 The examples provided are merely illustrative, and in general, any desired VCO core architecture can be used to implement VCO core 54.

[0042] Figure 4 yes Figure 2 A circuit diagram of a given switching circuit 70 in the switching network 58. The switching circuit 70 can be, for example, a butterfly switch. Therefore, the switching circuit 70 may sometimes be referred to herein as a butterfly switch 70. The switching circuit 70 can be used to couple terminals P and N of VCO core 54A to terminals P and N of VCO core 54B, terminals P and N of VCO core 54B to terminals P and N of VCO core 54C, terminals P and N of VCO core 54C to terminals P and N of VCO core 54D, or terminals P and N of VCO core 54D to terminals P and N of VCO core 54A. In other words, the switching network 58 may include... Figure 4 The four switching circuits 70 are coupled between a corresponding pair of adjacent VCO cores 54.

[0043] like Figure 4 As shown, the switching circuit 70 can be used with a pair of capacitors 56 (e.g., Figure 2 Capacitors 56-1, 56-2, 56-3, or 56-4 are coupled in parallel between terminals P1, P2, N1, and N2. For example, in switching circuit 70, terminals P and N of VCO core 54A (e.g., with...) are used to couple... Figure 2 When capacitors 56-1 (in parallel) are coupled to terminals P and N of VCO core 54B, terminal P1 forms terminal P of VCO core 54A, terminal P2 forms terminal P of VCO core 54B, terminal N1 forms terminal N of VCO core 54A, and terminal N2 forms terminal N of VCO core 54B. Similarly, in the switching circuit 70 used to couple terminals P and N of VCO core 54B (e.g., with...) Figure 2 When capacitors 56-2 are coupled in parallel to terminals P and N of VCO core 54C, terminal P1 forms terminal P of VCO core 54B, terminal P2 forms terminal P of VCO core 54C, terminal N1 forms terminal N of VCO core 54B, and terminal N2 forms terminal N of VCO core 54C. Furthermore, in the switching circuit 70 used to switch terminals P and N of VCO core 54C (e.g., with...) Figure 2 When capacitors 56-3 are coupled in parallel to terminals P and N of VCO core 54D, terminal P1 forms terminal P of VCO core 54C, terminal P2 forms terminal P of VCO core 54D, terminal N1 forms terminal N of VCO core 54C, and terminal N2 forms terminal N of VCO core 54D. Finally, in the switching circuit 70, terminals P and N of VCO core 54D (e.g., with...) are... Figure 2 When capacitors 56-4 are coupled in parallel to terminals P and N of VCO core 54A, terminal P1 forms terminal P of VCO core 54D, terminal P2 forms terminal P of VCO core 54A, terminal N1 forms terminal N of VCO core 54D, and terminal N2 forms terminal N of VCO core 54A.

[0044] The switching circuit 70 may include a first switch 72 coupling terminal P1 to terminal P2 and a second switch 72 (e.g., in parallel with the first switch 72 and capacitor 56) coupling terminal N1 to terminal N2. The switching circuit 70 may also include cross switches, such as a first switch 74 coupling terminal P1 to terminal N2 and a second switch 74 coupling terminal N1 to terminal P2. As an example, each switch 72 and each switch 74 may be a single-pole single-throw (SPST) switch. This is merely illustrative. In general, switches 72 and 74 may be formed using any type of switch architecture. If desired, the switching circuit 70 may include any desired number of switches arranged in other ways between terminals P1, P2, N1, and N2.

[0045] Switch control signal SW CTRL ( Figure 2 The states of switches 72 and 74 can be controlled. In the specific implementation described herein as an example, the switching circuit 70 may have a first state and a second state (sometimes referred to herein as a first switching state and a second switching state). In the first state, switch 72 is closed and switch 74 is open, thereby coupling terminal P1 to terminal P2 and terminal N1 to terminal N2 (e.g., while decoupling terminal P1 from terminal N2 and decoupling terminal N1 from terminal P2). In the second state, switch 74 is closed and switch 72 is open, thereby coupling terminal P1 to terminal N2 and terminal N1 to terminal P2 (e.g., while decoupling terminal P1 from terminal P2 and decoupling terminal N1 from terminal N2).

[0046] When open, each switch 72 or 74 can create a very high impedance or a very low transconductance g. m By means of a switch (e.g., an impedance exceeding a threshold impedance value or a transconductance below a threshold transconductance value). When closed, each switch 72 or 74 can form a very low impedance or a very high transconductance g. m Switches are used (e.g., impedance exceeding a threshold impedance value or transconductance less than a threshold transconductance value). For example, switches such as switches 72 and 74 can each be formed using transistors having a source terminal, a drain terminal, and a gate terminal. Each switch can be closed or “on” by enabling a gate voltage supplied to the gate terminal to provide an electrical connection between its source and drain terminals. Similarly, each switch can be opened or “off” by disabling a gate voltage to provide electrical isolation between its source and drain terminals. Switching circuit 70 can selectively couple ports P1 and N1 to ports P2 and N2 without introducing losses or nonlinearities into the system. Switching circuit 70 may sometimes be referred to herein as phase exchanger 70.

[0047] Each switching circuit 70 in the switching network 58 ( Figure 2 The VCO circuit 42 can be placed in one of the first and second states to operate in one of the first, second, third, or fourth operating modes. The control circuit 14 can place the VCO circuit 42 in one of the first, second, third, or fourth operating modes based on the frequency generated by the mixer 34. Figure 5 It can be generated by the control circuit 14 and the VCO circuit 42. Figure 1 The flowchart illustrates the exemplary operation of the VCO output signal OSC.

[0048] In operation 76, control circuitry 14 may identify the frequency of the VCO output signal OSC. The frequency of the VCO output signal OSC may be, for example, the VCO output signal frequency, which corresponds to the desired radio, intermediate, or baseband frequency that mixer 34 will utilize to output the VCO output signal OSC (e.g., when mixing an input signal with a local oscillator signal LO generated using the VCO output signal OSC). As an example, the frequency of the VCO output signal OSC may be identified using software running on control circuitry 14 and / or using control signals received from external communication circuitry such as a wireless access point or base station.

[0049] In operation 78, control circuit 14 can place VCO circuit 42 in a selected operating mode corresponding to the identified frequency (e.g., one of the first, second, third, or fourth operating modes, in which the identified frequency can be generated using VCO circuit 42). Control circuit 14 can utilize the control signal SW provided to switching network 58. CTRL VCO circuit 42 is placed in the selected operating mode. Control circuit 14 can, for example, place each of the four switching circuits 70 in the switching network 58 into the corresponding one of the first and second states (e.g., as described above). Figure 3 (As described) Place the VCO circuit 42 in the selected operating mode.

[0050] In addition, the VCO circuit 42 can utilize the control voltage V provided to the VCO core 54 CTRL The frequency generated by the VCO circuit 42 is fine-tuned (e.g., within the frequency range associated with the selected operating mode). The VCO circuit 42 can generate a corresponding VCO output signal OSC, which is output through path 38. Figure 1 Mixer 34 can use the VCO output signal OSC (e.g., a local oscillator signal LO generated on path 38 using the VCO output signal OSC) to down-convert or up-convert the input signal to a frequency corresponding to the VCO output signal frequency identified during processing operation 76. Processing can then loop back to operation 76 via path 79 to update the VCO output signal frequency as needed over time.

[0051] Figures 6 to 9 This is a diagram depicting different operating modes of the VCO circuit 42. For example, the VCO circuit 42 can operate in each of the first, second, third, and fourth operating modes. Figures 6 to 9 In the example, switch network 58 ( Figure 2 This includes a first switching circuit 70 coupled in parallel with capacitor 56-1 between VCO 50A and 50B. Figure 4The second switching circuit 70 is coupled in parallel with capacitor 56-2 between VCO 50B and 50C. Figure 4 The third switching circuit 70 is coupled in parallel with capacitor 56-3 between VCO 50C and 50D. Figure 4 ), and a fourth switching circuit 70 coupled in parallel with capacitor 56-4 between VCO 50D and 50A. Figure 4 However, in Figures 6 to 9 The switch network 58 and its four switching circuits 70 are not shown in the figure to avoid unnecessarily obscuring the drawing.

[0052] In each of the first, second, third, and fourth operating modes, the switching network 58 is adjusted to selectively control the direction of current in each of the inductors 52 of the VCO circuit 42 (e.g., such that the current flows clockwise or counterclockwise when viewed in the plane of the page). The direction of current between adjacent VCOs 50 makes some capacitors 56 effectively invisible or visible to the system in each operating mode. This allows the VCO circuit 42 to generate the VCO output signal OSC with a linearly distributed frequency across all four operating modes, an extended frequency range across all four operating modes, and minimal phase noise. When the current in adjacent VCOs flows in opposite directions (e.g., when the current and voltage distribution between adjacent VCOs exhibits mirror symmetry about an axis extending vertically between adjacent VCOs), the capacitors 56 coupled between adjacent VCOs can effectively appear invisible to the system. On the other hand, when the current in adjacent VCOs flows in the same direction (e.g., when the current and voltage distribution between adjacent VCOs exhibits symmetry about an axis extending vertically between adjacent VCOs), the capacitor 56 coupled between adjacent VCOs can be effectively seen to the system.

[0053] Figure 6 This is a diagram illustrating how the VCO circuit 42 can operate in a first operating mode. In the first operating mode (sometimes referred to herein as "MODE0"), the VCO circuit 42 can generate a VCO output signal OSC within a first frequency range. The switching network 58 can (utilize...) Figure 2 Switch control signal SW CTRL The switching circuit 70 coupled between VCOs 50A and 50B, the switching circuit 70 coupled between VCOs 50B and 50C, the switching circuit 70 coupled between VCOs 50C and 50D, and the switching circuit 70 coupled between VCOs 50D and 50A are each in a first state (i.e., Figure 4 The switch 72 is closed and Figure 4 (Switch 74 is turned on).

[0054] This configuration of the switching network 58 allows the current in the inductor 52 of each VCO 50 to flow in the opposite direction to the current in the two adjacent VCOs 50. Each VCO 50 is adjacent to one VCO 50 about the horizontal axis 82 and to another VCO 50 about the vertical axis 80. Figure 6 As shown, current I will flow through each inductor 52 between terminals N and P of the corresponding VCO core 54 in the direction indicated by "-" to "+". In the first operating mode, the switching network 58 configures the voltages at terminals P and N of VCO core 54A to change directly with the voltages at terminals P and N of VCO core 54B (e.g., because the switches 72 in the switching circuit 70 coupled between VCOs 50A and 50B short terminals P together and N together). In other words, current IA will flow from terminal N to terminal P of VCO core 54A (e.g., clockwise), while the opposite current IB will flow from terminal N to terminal P of VCO core 54B (e.g., counterclockwise). This current and voltage mirror symmetry between VCOs 50A and 50B about the vertical axis 80 effectively makes capacitor 56-1 (and the switches in the parallel-coupled switching circuit 70) invisible to the system.

[0055] Similarly, the switching network 58 configures the voltages at terminals P and N of the VCO core 54B to change directly with the voltages at terminals P and N of the VCO core 54C, respectively (e.g., because the switch 72 in the switching circuit 70 coupled between VCOs 50B and 50C shorts terminals P together and terminals N together). In other words, current IC will flow from terminal N of the VCO core 54C to terminal P (e.g., clockwise), opposite to the direction of current IB in the VCO 50B. This current and voltage mirror symmetry about the horizontal axis 82 effectively makes capacitor 56-2 (and the switches in the parallel-coupled switching circuit 70) invisible to the system.

[0056] Furthermore, the switching network 58 configures the voltages at terminals P and N of the VCO core 54C to change directly with the voltages at terminals P and N of the VCO core 54D, respectively (e.g., because switch 72 in the switching circuit 70 coupled between VCOs 50C and 50D shorts terminals P together and terminals N together). In other words, current ID will flow from terminal N of VCO core 54D to terminal P (e.g., counterclockwise), opposite to the direction of current IC in VCO 50C. This current and voltage mirror symmetry about the vertical axis 80 effectively makes capacitor 56-3 (and the switches in the parallel-coupled switching circuit 70) invisible to the system.

[0057] Finally, the switching network 58 configures the voltages at terminals P and N of the VCO core 54D to change directly with the voltages at terminals P and N of the VCO core 54A, respectively (e.g., because the switch 72 in the switching circuit 70 coupled between VCOs 50D and 50A shorts terminals P together and terminals N together). Therefore, the current ID flows in the opposite direction to the current IA in VCO 50A. This current and voltage mirror symmetry about the horizontal axis 82 effectively makes capacitors 56-4 (and the switches in the parallel-coupled switching circuit 70) invisible to the system. When configured in this way (in the first operating mode MODE0), the VCO circuit 42 can output the VCO output signal OSC within a first frequency range. The control voltage V supplied to the VCO core 54... CTRL The frequency of the VCO output signal OSC can also be tuned within the first frequency range.

[0058] Figure 7 This is a diagram illustrating how the VCO circuit 42 can operate in a second operating mode. In the second operating mode (sometimes referred to herein as "MODE1"), the VCO circuit 42 can generate a VCO output signal OSC within a second frequency range (e.g., at a frequency lower than the first frequency range). The switching network 58 can be configured such that the switching circuit 70 coupled between VCOs 50A and 50B and the switching circuit 70 coupled between VCOs 50C and 50D are each in a second state (i.e., where...). Figure 4 Switch 72 is turned on and Figure 4 (Switch 74 is closed). Simultaneously, the switch network 58 can be configured such that the switching circuit 70 coupled between VCOs 50B and 50C and the switching circuit 70 coupled between VCOs 50D and 50A are each in a first state (i.e., where...). Figure 4 The switch 72 is closed and Figure 4 (Switch 74 is turned on).

[0059] Configuring the switch network 58 in this way allows the current in the inductor 52 of each VCO 50 to flow in the same direction as the VCO 50 adjacent to the vertical axis 80, but in the opposite direction to the VCO 50 adjacent to the horizontal axis 82. For example, as Figure 7As shown, the switching network 58 configures the voltages at terminals P and N of VCO core 54A to vary in opposite (reverse) directions to the voltages at terminals P and N of VCO core 54B (e.g., because switch 74 in the switching circuit 70 coupled between VCOs 50A and 50B shorts terminal P in VCO 50A to terminal N in VCO 50B, and shorts terminal N in VCO 50A to terminal P in VCO 50B). In other words, current IA flows from terminal N to terminal P of VCO core 54A (e.g., clockwise), while current IB flows in the same direction from terminal P to terminal N of VCO core 54B (e.g., clockwise). This current and voltage symmetry between VCOs 50A and 50B about the vertical axis 80 makes capacitor 56-1 effectively visible to the system.

[0060] Similarly, the switching network 58 configures the voltages at terminals P and N of VCO core 54C to vary in opposite (reverse) directions to the voltages at terminals P and N of VCO core 54BD (e.g., because switch 74 in the switching circuit 70 coupled between VCOs 50C and 50D shorts terminal P in VCO 50C to terminal N in VCO 50D, and shorts terminal N in VCO 50C to terminal P in VCO 50D). In other words, current IC will flow from terminal P to terminal N of VCO core 54C (e.g., counterclockwise), while current ID will flow in the same direction from terminal N to terminal P of VCO core 54B (e.g., counterclockwise). This current and voltage symmetry between VCOs 50C and 50D about the vertical axis 80 makes capacitor 56-3 effectively visible to the system.

[0061] Simultaneously, the switching network 58 configures the voltages at terminals P and N of the VCO core 54B to change directly with the voltages at terminals P and N of the VCO core 54C, respectively (e.g., because the switch 72 in the switching circuit 70 coupled between VCOs 50B and 50C shorts terminals P together and terminals N together). Therefore, the current IC flows in the opposite direction to the current IB in VCO 50B. This current and voltage mirror symmetry about the horizontal axis 82 makes capacitor 56-2 (and the switches in the parallel-coupled switching circuit 70) invisible to the system.

[0062] Similarly, the switching network 58 configures the voltages at terminals P and N of the VCO core 54D to change directly with the voltages at terminals P and N of the VCO core 54A, respectively (e.g., because the switch 72 in the switching circuit 70 coupled between VCOs 50D and 50A shorts terminals P together and terminals N together). Therefore, the current ID flows in the opposite direction to the current IA in VCO 50A. This current and voltage mirror symmetry about the horizontal axis 82 makes capacitors 56-4 (and the switches in the parallel-coupled switching circuit 70) invisible to the system. When configured in this way (in the second operating mode MODE1), the VCO circuit 42 can output the VCO output signal OSC in the second frequency range. The control voltage V supplied to the VCO core 54... CTRL The frequency of the VCO output signal OSC can also be tuned within the second frequency range.

[0063] Figure 8 This is a diagram illustrating how the VCO circuit 42 can operate in a third operating mode. In the third operating mode (sometimes referred to herein as "MODE2"), the VCO circuit 42 can generate a VCO output signal OSC within a third frequency range (e.g., at a frequency lower than the second frequency range). The switching network 58 can be configured such that the switching circuit 70 coupled between VCOs 50A and 50B and the switching circuit 70 coupled between VCOs 50C and 50D are each in a first state (i.e., where...). Figure 4 Switch 74 is turned on and Figure 4 (Switch 72 is closed). Simultaneously, the switch network 58 can be configured such that the switching circuit 70 coupled between VCOs 50B and 50C and the switching circuit 70 coupled between VCOs 50D and 50A are each in a second state (i.e., where...). Figure 4 Switch 72 is turned on and Figure 4 (Switch 74 closed).

[0064] Configuring the switch network 58 in this way allows the current in the inductor 52 of each VCO 50 to flow in the same direction as the VCO 50 adjacent to the horizontal axis 82, but in the opposite direction to the VCO 50 adjacent to the vertical axis 80. For example, as Figure 8As shown, the switching network 58 configures the voltages at terminals P and N of VCO core 54B to vary in opposite (reverse) directions to the voltages at terminals P and N of VCO core 54C (e.g., because switch 74 in the switching circuit 70 coupled between VCOs 50B and 50C shorts terminal P in VCO 50B to terminal N in VCO 50C, and shorts terminal N in VCO 50B to terminal P in VCO 50C). In other words, current IB will flow from terminal N to terminal P of VCO core 54B (e.g., counterclockwise), while current IC will flow in the same direction from terminal P to terminal N of VCO core 54C (e.g., counterclockwise). This current and voltage symmetry between VCOs 50B and 50C about the horizontal axis 82 makes capacitor 56-2 effectively visible to the system.

[0065] Similarly, the switching network 58 configures the voltages at terminals P and N of VCO core 54D to vary in opposite (reverse) directions to the voltages at terminals P and N of VCO core 54BA (e.g., because switch 74 in the switching circuit 70 coupled between VCOs 50D and 50A shorts terminal P in VCO 50D to terminal N in VCO 50A, and shorts terminal N in VCO 50D to terminal P in VCO 50A). In other words, current ID will flow from terminal P to terminal N of VCO core 54D (e.g., clockwise), while current IA will flow in the same direction from terminal N to terminal P of VCO core 54A (e.g., clockwise). This current and voltage symmetry between VCOs 50D and 50A about the horizontal axis 82 makes capacitor 56-4 effectively visible to the system.

[0066] Simultaneously, the switching network 58 configures the voltages at terminals P and N of the VCO core 54A to change directly with the voltages at terminals P and N of the VCO core 54B, respectively (e.g., because the switch 72 in the switching circuit 70 coupled between VCOs 50A and 50B shorts terminals P together and terminals N together). Therefore, the current IB flows in the opposite direction to the current IA in VCO 50A. This mirror symmetry of current and voltage with respect to the vertical axis 80 makes capacitor 56-1 (and the switches in the parallel-coupled switching circuit 70) invisible to the system.

[0067] Similarly, the switching network 58 configures the voltages at terminals P and N of the VCO core 54C to change directly with the voltages at terminals P and N of the VCO core 54D, respectively (e.g., because the switch 72 in the switching circuit 70 coupled between VCOs 50C and 50D shorts terminals P together and terminals N together). Therefore, the current ID flows in the opposite direction to the current IC in VCO 50C. This current and voltage mirror symmetry about the vertical axis 80 makes capacitors 56-3 (and the switches in the parallel-coupled switching circuit 70) invisible to the system. When configured in this way (in the third operating mode MODE2), the VCO circuit 42 can output the VCO output signal OSC in the third frequency range. The control voltage V supplied to the VCO core 54... CTRL The frequency of the VCO output signal OSC can also be tuned within the third frequency range.

[0068] Figure 9 This is a diagram illustrating how VCO circuit 42 can operate in a fourth operating mode. In the fourth operating mode (sometimes referred to herein as "MODE3"), VCO circuit 42 can generate a VCO output signal OSC within a fourth frequency range (e.g., at frequencies lower than the third frequency range). Switching network 58 can be configured such that switching circuits 70 coupled between VCOs 50A and 50B, 50C and 50D, 50B and 50C, and 50D and 50A are each in a second state (i.e., Figure 4 Switch 72 is turned on and Figure 4 (Switch 74 closed).

[0069] Configuring the switching network 58 in this way allows the current in the inductor 52 of each VCO 50 to flow in the same direction as all other VCOs 50 in the VCO circuit 42. For example, as Figure 9As shown, the switching network 58 configures the voltages at terminals P and N of VCO core 54A to vary in opposite (reverse) directions to the voltages at terminals P and N of VCO core 54B (e.g., because switch 74 in the switching circuit 70 coupled between VCOs 50A and 50B shorts terminal P in VCO 50A to terminal N in VCO 50B, and shorts terminal N in VCO 50A to terminal P in VCO 50B). In other words, current IA flows from terminal N to terminal P of VCO core 54A (e.g., clockwise), while current IB flows in the same direction from terminal P to terminal N of VCO core 54B (e.g., clockwise). This current and voltage symmetry between VCOs 50A and 50B about the vertical axis 80 makes capacitor 56-1 effectively visible to the system.

[0070] Similarly, the switching network 58 configures the voltages at terminals P and N of VCO core 54B to vary in opposite (reverse) directions to the voltages at terminals P and N of VCO core 54C (e.g., because switch 74 in the switching circuit 70 coupled between VCOs 50B and 50C shorts terminal P in VCO 50B to terminal N in VCO 50C, and shorts terminal N in VCO 50B to terminal P in VCO 50C). In other words, current IB will flow from terminal P to terminal N of VCO core 54B (e.g., clockwise), while current IC will flow in the same direction from terminal N to terminal P of VCO core 54C (e.g., clockwise). This current and voltage symmetry between VCOs 50B and 50C about the horizontal axis 82 makes capacitor 56-2 effectively visible to the system.

[0071] Furthermore, the switching network 58 configures the voltages at terminals P and N of the VCO core 54C to vary in opposite (reverse) directions to the voltages at terminals P and N of the VCO core 54D (e.g., because switch 74 in the switching circuit 70 coupled between VCOs 50C and 50D shorts terminal P in VCO 50C to terminal N in VCO 50D, and shorts terminal N in VCO 50C to terminal P in VCO 50D). In other words, current IC will flow from terminal N of VCO core 54C to terminal P (e.g., clockwise), while current ID will flow in the same direction from terminal P of VCO core 54D to terminal N (e.g., clockwise). This current and voltage symmetry between VCOs 50C and 50D about the vertical axis 80 makes capacitor 56-3 effectively visible to the system.

[0072] Finally, the switching network 58 also configures the voltages at terminals P and N of the VCO core 54D to vary in opposite (reverse) directions to the voltages at terminals P and N of the VCO core 54A, respectively (e.g., because switch 74 in the switching circuit 70 coupled between VCOs 50D and 50A shorts terminal P in VCO 50D to terminal N in VCO 50A, and shorts terminal N in VCO 50D to terminal P in VCO 50A). Therefore, current ID flows from terminal P to terminal N of the VCO core 54D (e.g., clockwise), while current IA flows in the same direction from terminal N to terminal P of the VCO core 54A (e.g., clockwise). This current and voltage symmetry between VCOs 50D and 50A about the horizontal axis 82 makes capacitor 56-4 effectively visible to the system. When configured in this way (in the fourth operating mode MODE3), the VCO circuit 42 can output the VCO output signal OSC in the fourth frequency range. The control voltage V supplied to the VCO core 54 CTRL The frequency of the VCO output signal OSC can also be tuned within the third frequency range.

[0073] Figure 10 It is shown in Figures 6 to 9 The graph shows how the VCO circuit 42 can be used to extend the frequency range of the VCO circuit 42 in the first, second, third and fourth operating modes. Figure 10 The curve 100 plots the frequency of the VCO output signal based on the active VCO in a scenario where switched capacitors are coupled between each of the four VCOs and only one VCO is actively used to generate the VCO output signal at any given time. As shown by line 106 in curve 100, each VCO can generate a corresponding frequency range, with a relatively large overlap 104 between each VCO. The overlap 104 between each VCO limits the total frequency range across all four VCOs to a total frequency range R1.

[0074] Figure 10 The curve 102 plots the frequency of the VCO output signal OSC according to the operating modes of the VCO circuit 42. As shown by line 110 in curve 102, the first operating mode MODE0 generates a first frequency range, the second operating mode MODE1 generates a second frequency range covering frequencies lower than the first frequency range, the third operating mode MODE2 generates a third frequency range covering frequencies lower than the second frequency range, and the fourth operating mode MODE3 generates a fourth frequency range covering frequencies lower than the third frequency range. The control circuit 14 can utilize the control voltage V CTRL ( Figure 2 The frequency of the VCO output signal OSC is tuned within each frequency range.

[0075] As shown in curve 110, the frequency response of VCO circuit 42 is linear across all four operating modes, with an overlap 108 between each mode, which is significantly smaller than the overlap 104 associated with curve 100. This allows VCO circuit 42 to exhibit a wider total frequency range R2 across all four operating modes than the frequency range R1 associated with curve 100.

[0076] Figures 2 to 10 The examples provided are merely illustrative. VCO circuit 42 may have fewer than four operating modes (e.g., two or three operating modes), more than four operating modes (e.g., six or more operating modes), and may include only two VCOs 50 coupled together by a single switching circuit 70 and a single pair of capacitors 56, or may include more than four VCOs 50. The inductor 52, sometimes referred to herein as a coil, may have an octagonal shape (e.g., as shown in the image). Figure 2 and Figures 6 to 9 (as shown) or may have other shapes (e.g., circular, elliptical, or any other shape with any desired number of bends and / or straight segments).

[0077] The above combination Figures 1 to 10 The described methods and operations can be performed by components of device 10 using software, firmware, and / or hardware (e.g., dedicated circuitry or hardware). The software code for performing these operations can be stored on a non-transitory computer-readable storage medium (e.g., a tangible computer-readable storage medium) stored on one or more components of device 10 (e.g., ...). Figure 1 The storage circuit 16). This software code may sometimes be referred to as software, data, instructions, program instructions, or code. Non-transitory computer-readable storage media may include drives, non-volatile memory such as non-volatile random access memory (NVRAM), removable flash drives or other removable media, other types of random access memory, etc. The software stored on the non-transitory computer-readable storage medium may be processed by processing circuitry on one or more components of device 10 (e.g., Figure 1 The processing circuitry (e.g., 18) performs the execution. This processing circuitry may include a microprocessor, a central processing unit (CPU), an application-specific integrated circuit (ASIC) with processing circuitry, or other processing circuitry.

[0078] According to one embodiment, a voltage-controlled oscillator (VCO) circuit is provided, comprising: a plurality of VCOs including a first VCO having a first inductor, a second VCO having a second inductor, a third VCO having a third inductor, and a fourth VCO having a fourth inductor; a first pair of capacitors coupled between the first VCO and the second VCO, a second pair of capacitors coupled between the second VCO and the third VCO, a third pair of capacitors coupled between the third VCO and the fourth VCO, and a fourth pair of capacitors coupled between the fourth VCO and the first VCO; and a switching network communicatively coupled to the plurality of VCOs, the switching network being configured to selectively control the current direction in the first, second, third, and fourth inductors to generate a VCO output signal in a frequency range across at least four operating modes of the VCO circuit.

[0079] According to another embodiment, one or more of the first pair of capacitors, the second pair of capacitors, the third pair of capacitors, and the fourth pair of capacitors include fixed linear capacitors.

[0080] According to another embodiment, the first VCO includes a first VCO core coupled to a first inductor, the second VCO includes a second VCO core coupled to a second inductor, the third VCO includes a third VCO core coupled to a third inductor, and the fourth VCO includes a fourth VCO core coupled to a fourth inductor.

[0081] According to another embodiment, the first VCO core, the second VCO core, the third VCO core and the fourth VCO core each include a cross-coupled transistor, at least one varactor diode and at least one switched capacitor.

[0082] According to another embodiment, the switching network includes a first switching circuit coupled in parallel with a first pair of capacitors between a first VCO and a second VCO, a second switching circuit coupled in parallel with a second pair of capacitors between a second VCO and a third VCO, a third switching circuit coupled in parallel with a third pair of capacitors between a third VCO and a fourth VCO, and a fourth switching circuit coupled in parallel with a fourth pair of capacitors between a fourth VCO and a first VCO.

[0083] According to another implementation, the switching network includes multiple butterfly switches.

[0084] According to another embodiment, the switching network selectively enables a first current in a first inductor, a second current in a second inductor, a third current in a third inductor, and a fourth current in a fourth inductor, and in a first operating mode, the first current and the third current flow in a first direction, and the second current and the fourth current flow in a second direction opposite to the first direction, thereby generating a VCO output signal in a first frequency range.

[0085] According to another embodiment, in the second operating mode, the first current and the second current flow in the first direction and the third current and the fourth current flow in the second direction, thereby generating a VCO output signal in a second frequency range that includes frequencies lower than the first frequency range.

[0086] According to another embodiment, in the third operating mode, the first current and the fourth current flow in the first direction and the second current and the third current flow in the second direction, thereby generating a VCO output signal in a third frequency range that includes frequencies lower than the second frequency range.

[0087] According to another embodiment, in the fourth operating mode, the first current, the second current, the third current and the fourth current flow in the first direction, thereby generating a VCO output signal in a fourth frequency range that includes frequencies lower than the third frequency range.

[0088] According to one embodiment, a voltage-controlled oscillator (VCO) circuit is provided, comprising a first VCO having a first VCO core and a first inductor coupled to the first VCO core, a second VCO having a second VCO core and a second inductor coupled to the second VCO core, a first pair of fixed capacitors coupled between the first VCO core and the second VCO core, and a first switching circuit coupled in parallel with the first pair of fixed capacitors between the first VCO core and the second VCO core.

[0089] According to another embodiment, the VCO circuit includes: a third VCO having a third VCO core and a third inductor coupled to the third VCO core; a fourth VCO having a fourth VCO core and a fourth inductor coupled to the fourth VCO core, wherein the first VCO, second VCO, third VCO, and fourth VCO are configured to generate a VCO output signal based on a control voltage; a second pair of fixed capacitors coupled between the second VCO core and the third VCO core; a third pair of fixed capacitors coupled between the third VCO core and the fourth VCO core; a fourth pair of fixed capacitors coupled between the fourth VCO core and the first VCO core; a second switching circuit coupled in parallel with the second pair of fixed capacitors between the second VCO core and the third VCO core; a third switching circuit coupled in parallel with the third pair of fixed capacitors between the third VCO core and the fourth VCO core; and a fourth switching circuit coupled in parallel with the fourth pair of fixed capacitors between the fourth VCO core and the first VCO core.

[0090] According to another embodiment, a first VCO core has a first terminal and a second terminal, and a first inductor is coupled between the first terminal and the second terminal. A second VCO core has a third terminal and a fourth terminal, and a second inductor is coupled between the third terminal and the fourth terminal. A third VCO core has a fifth terminal and a sixth terminal, and a third inductor is coupled between the fifth terminal and the sixth terminal. A fourth VCO core has a seventh terminal and an eighth terminal, and a fourth inductor is coupled between the seventh terminal and the eighth terminal. A first switching circuit and a first pair of capacitors couple the first terminal and the second terminal to the third terminal and the fourth terminal. A second switching circuit and a second pair of capacitors couple the third terminal and the fourth terminal to the fifth terminal and the sixth terminal. A third switching circuit and a third pair of capacitors couple the fifth terminal and the sixth terminal to the seventh terminal and the eighth terminal. A fourth switching circuit and a fourth pair of capacitors couple the seventh terminal and the eighth terminal to the first terminal and the second terminal.

[0091] According to another embodiment, the first switching circuit has a first state in which a first terminal is coupled to a fourth terminal and a second terminal is coupled to a third terminal; the first switching circuit has a second state in which a first terminal is coupled to a third terminal and a second terminal is coupled to a fourth terminal; the second switching circuit has a first state in which a third terminal is coupled to a sixth terminal and a fourth terminal is coupled to a fifth terminal; and the second switching circuit has a second state in which a third terminal is coupled to a fifth terminal and a fourth terminal is coupled to a sixth terminal.

[0092] According to another embodiment, the third switching circuit has a first state in which the fifth terminal is coupled to the eighth terminal and the sixth terminal is coupled to the seventh terminal; the third switching circuit has a second state in which the fifth terminal is coupled to the seventh terminal and the sixth terminal is coupled to the eighth terminal; the fourth switching circuit has a first state in which the eighth terminal is coupled to the first terminal and the seventh terminal is coupled to the second terminal; and the fourth switching circuit has a second state in which the eighth terminal is coupled to the second terminal and the seventh terminal is coupled to the first terminal.

[0093] According to another embodiment, the first pair of fixed capacitors includes a first fixed capacitor and a second fixed capacitor, the first fixed capacitor being coupled between a second terminal and a third terminal, and the second fixed capacitor being coupled between a first terminal and a fourth terminal. The second pair of fixed capacitors includes a third fixed capacitor and a fourth fixed capacitor, the third fixed capacitor being coupled between a third terminal and a sixth terminal, and the fourth fixed capacitor being coupled between a fourth terminal and a fifth terminal. The third pair of fixed capacitors includes a fifth fixed capacitor and a sixth fixed capacitor, the fifth fixed capacitor being coupled between a fifth terminal and an eighth terminal, and the sixth fixed capacitor being coupled between a sixth terminal and a seventh terminal. The fourth pair of fixed capacitors includes a seventh fixed capacitor and an eighth fixed capacitor, the seventh fixed capacitor being coupled between a seventh terminal and a second terminal, and the eighth fixed capacitor being coupled between an eighth terminal and a first terminal.

[0094] According to another embodiment, the first switching circuit, the second switching circuit, the third switching circuit, and the fourth switching circuit are configured to receive a switch control signal that places the VCO circuit in one of a first operating mode, a second operating mode, a third operating mode, and a fourth operating mode. In the first operating mode, the VCO output signal is in a first frequency range; in the second operating mode, the VCO output signal is in a second frequency range; in the third operating mode, the VCO output signal is in a third frequency range; and in the fourth operating mode, the VCO output signal is in a fourth frequency range.

[0095] According to another embodiment, in a first operating mode, the first switching circuit, the second switching circuit, the third switching circuit, and the fourth switching circuit are in a first state; in a second operating mode, the second switching circuit and the fourth switching circuit are in the first state and the first switching circuit and the third switching circuit are in the second state; in a third operating mode, the first switching circuit and the third switching circuit are in the first state and the second switching circuit and the fourth switching circuit are in the second state; and in a fourth operating mode, the first switching circuit, the second switching circuit, the third switching circuit, and the fourth switching circuit are in the second state.

[0096] According to one embodiment, an electronic device is provided, comprising a baseband processor circuit configured to generate a baseband signal, a mixer circuit configured to generate a radio frequency (RF) signal based on the baseband signal and a voltage-controlled oscillator (VCO) output signal, an antenna configured to transmit the RF signal, and a VCO circuit configured to generate the VCO output signal. The VCO circuit has a first VCO core with a first terminal and a second terminal, a first inductor coupled between the first and second terminals, a second VCO core with a third terminal and a fourth terminal, a second inductor coupled between the third and fourth terminals, a first fixed capacitor coupling the first terminal to the fourth terminal, a second fixed capacitor coupling the second terminal to the third terminal, and a switching circuit that couples the first and second terminals to the third and fourth terminals in parallel with the first and second fixed capacitors. The switching circuit has a first state and a second state, wherein in the first state, the switching circuit couples the first terminal to the fourth terminal and the second terminal to the third terminal, and in the second state, the switching circuit couples the first terminal to the third terminal and the second terminal to the fourth terminal.

[0097] According to another embodiment, the VCO circuit includes a third VCO core having a fifth terminal and a sixth terminal, a third inductor coupled between the fifth terminal and the sixth terminal, a fourth VCO core having a seventh terminal and an eighth terminal, a fourth inductor coupled between the seventh terminal and the eighth terminal, a third fixed capacitor coupling the third terminal to the sixth terminal, a fourth fixed capacitor coupling the fourth terminal to the fifth terminal, a fifth fixed capacitor coupling the fifth terminal to the eighth terminal, a sixth fixed capacitor coupling the sixth terminal to the seventh terminal, a seventh fixed capacitor coupling the seventh terminal to the second terminal, and an eighth fixed capacitor coupling the eighth terminal to the first terminal.

[0098] The foregoing description is merely illustrative and various modifications can be made to the described implementation scheme. The described implementation scheme can be implemented independently or in any combination.

Claims

1. Voltage-controlled oscillator (VCO) circuit, including: A plurality of VCOs, the plurality of VCOs including a first VCO having a first inductor, a second VCO having a second inductor, a third VCO having a third inductor, and a fourth VCO having a fourth inductor; The first pair of capacitors is coupled between the first VCO and the second VCO; The second pair of capacitors is coupled between the second VCO and the third VCO; The third pair of capacitors is coupled between the third VCO and the fourth VCO; A fourth pair of capacitors is coupled between the fourth VCO and the first VCO; as well as A switching network, communicatively coupled to the plurality of VCOs and configured to selectively control the current direction in the first, second, third, and fourth inductors to generate VCO output signals in a frequency range across at least four operating modes of the VCO circuit.

2. The VCO circuit according to claim 1, wherein one or more of the first pair of capacitors, the second pair of capacitors, the third pair of capacitors, and the fourth pair of capacitors comprise fixed linear capacitors.

3. The VCO circuit according to claim 1, wherein the first VCO includes a first VCO core coupled to the first inductor, the second VCO includes a second VCO core coupled to the second inductor, the third VCO includes a third VCO core coupled to the third inductor, and the fourth VCO includes a fourth VCO core coupled to the fourth inductor.

4. The VCO circuit according to claim 3, wherein the first VCO core, the second VCO core, the third VCO core and the fourth VCO core each include a cross-coupled transistor, at least one varactor diode and at least one switched capacitor.

5. The VCO circuit according to claim 1, wherein the switching network comprises: A first switching circuit is coupled in parallel with the first pair of capacitors between the first VCO and the second VCO. A second switching circuit is coupled in parallel with the second pair of capacitors between the second VCO and the third VCO. A third switching circuit is coupled in parallel with the third pair of capacitors between the third VCO and the fourth VCO; as well as A fourth switching circuit is coupled in parallel with the fourth pair of capacitors between the fourth VCO and the first VCO.

6. The VCO circuit according to claim 1, wherein the switching network comprises a plurality of butterfly switches.

7. The VCO circuit of claim 1, wherein the switching network selectively enables a first current in the first inductor, a second current in the second inductor, a third current in the third inductor, and a fourth current in the fourth inductor, and wherein in a first operating mode, the first current and the third current flow in a first direction, and the second current and the fourth current flow in a second direction opposite to the first direction, thereby generating the VCO output signal in a first frequency range.

8. The VCO circuit of claim 7, wherein in the second operating mode, the first current and the second current flow along the first direction and the third current and the fourth current flow along the second direction, thereby generating the VCO output signal in a second frequency range including frequencies lower than the first frequency range.

9. The VCO circuit of claim 8, wherein in the third operating mode, the first current and the fourth current flow along the first direction and the second current and the third current flow along the second direction, thereby generating the VCO output signal in a third frequency range including frequencies lower than the second frequency range.

10. The VCO circuit of claim 9, wherein in a fourth operating mode, the first current, the second current, the third current, and the fourth current flow along the first direction, thereby generating the VCO output signal in a fourth frequency range including frequencies lower than the third frequency range.

11. A voltage-controlled oscillator (VCO) circuit, including: A first VCO, the first VCO having a first VCO core and a first inductor coupled to the first VCO core; The second VCO has a second VCO core and a second inductor coupled to the second VCO core; The third VCO has a third VCO core and a third inductor coupled to the third VCO core. A fourth VCO, the fourth VCO having a fourth VCO core and a fourth inductor coupled to the fourth VCO core; The first pair of fixed capacitors is coupled between the first VCO core and the second VCO core. as well as A switching network, communicatively coupled to the first VCO, the second VCO, the third VCO, and the fourth VCO, is configured to selectively control the current direction in the first inductor, the second inductor, the third inductor, and the fourth inductor to generate a VCO output signal in a frequency range across at least four operating modes of the VCO circuit. The switching network includes a first switching circuit, which is coupled in parallel with the first pair of fixed capacitors between the first VCO core and the second VC core.

12. The VCO circuit according to claim 11, further comprising: The first VCO, the second VCO, the third VCO, and the fourth VCO are configured to generate VCO output signals based on control voltage; The second pair of fixed capacitors is coupled between the second VCO core and the third VCO core. The third pair of fixed capacitors is coupled between the third VCO core and the fourth VCO core. The fourth pair of fixed capacitors is coupled between the fourth VCO core and the first VCO core. The second switching circuit is coupled in parallel with the second pair of fixed capacitors between the second VCO core and the third VCO core. The third switching circuit is coupled in parallel with the third pair of fixed capacitors between the third VCO core and the fourth VCO core. as well as A fourth switching circuit is coupled in parallel with the fourth pair of fixed capacitors between the fourth VCO core and the first VCO core.

13. The VCO circuit of claim 12, wherein the first VCO core has a first terminal and a second terminal, the first inductor is coupled between the first terminal and the second terminal, the second VCO core has a third terminal and a fourth terminal, the second inductor is coupled between the third terminal and the fourth terminal, the third VCO core has a fifth terminal and a sixth terminal, the third inductor is coupled between the fifth terminal and the sixth terminal, the fourth VCO core has a seventh terminal and an eighth terminal, and the fourth inductor is coupled between the seventh terminal and the eighth terminal, wherein the first switching circuit and the first pair of fixed capacitors couple the first terminal and the second terminal to the third terminal and the fourth terminal, the second switching circuit and the second pair of fixed capacitors couple the third terminal and the fourth terminal to the fifth terminal and the sixth terminal, the third switching circuit and the third pair of fixed capacitors couple the fifth terminal and the sixth terminal to the seventh terminal and the eighth terminal, and the fourth switching circuit and the fourth pair of fixed capacitors couple the seventh terminal and the eighth terminal to the first terminal and the second terminal.

14. The VCO circuit of claim 13, wherein the first switching circuit has a first state in which the first terminal is coupled to the fourth terminal and the second terminal is coupled to the third terminal, the first switching circuit has a second state in which the first terminal is coupled to the third terminal and the second terminal is coupled to the fourth terminal, the second switching circuit has a first state in which the third terminal is coupled to the sixth terminal and the fourth terminal is coupled to the fifth terminal, and the second switching circuit has a second state in which the third terminal is coupled to the fifth terminal and the fourth terminal is coupled to the sixth terminal.

15. The VCO circuit of claim 14, wherein the third switching circuit has a first state in which the fifth terminal is coupled to the eighth terminal and the sixth terminal is coupled to the seventh terminal, the third switching circuit has a second state in which the fifth terminal is coupled to the seventh terminal and the sixth terminal is coupled to the eighth terminal, the fourth switching circuit has a first state in which the eighth terminal is coupled to the first terminal and the seventh terminal is coupled to the second terminal, and the fourth switching circuit has a second state in which the eighth terminal is coupled to the second terminal and the seventh terminal is coupled to the first terminal.

16. The VCO circuit of claim 15, wherein the first pair of fixed capacitors comprises a first fixed capacitor and a second fixed capacitor, the first fixed capacitor being coupled between the second terminal and the third terminal, the second fixed capacitor being coupled between the first terminal and the fourth terminal, the second pair of fixed capacitors comprising a third fixed capacitor and a fourth fixed capacitor, the third fixed capacitor being coupled between the third terminal and the sixth terminal, the fourth fixed capacitor being coupled between the fourth terminal and the fifth terminal, the third pair of fixed capacitors comprising a fifth fixed capacitor and a sixth fixed capacitor, the fifth fixed capacitor being coupled between the fifth terminal and the eighth terminal, the sixth fixed capacitor being coupled between the sixth terminal and the seventh terminal, the fourth pair of fixed capacitors comprising a seventh fixed capacitor and an eighth fixed capacitor, the seventh fixed capacitor being coupled between the seventh terminal and the second terminal, and the eighth fixed capacitor being coupled between the eighth terminal and the first terminal.

17. The VCO circuit of claim 15, wherein the first switching circuit, the second switching circuit, the third switching circuit, and the fourth switching circuit are configured to receive a switch control signal, the switch control signal placing the VCO circuit in one of a first operating mode, a second operating mode, a third operating mode, and a fourth operating mode, wherein in the first operating mode the VCO output signal is within a first frequency range, in the second operating mode the VCO output signal is within a second frequency range, in the third operating mode the VCO output signal is within a third frequency range, and in the fourth operating mode the VCO output signal is within a fourth frequency range.

18. The VCO circuit of claim 17, wherein in the first operating mode, the first switching circuit, the second switching circuit, the third switching circuit, and the fourth switching circuit are in the first state; in the second operating mode, the second switching circuit and the fourth switching circuit are in the first state and the first switching circuit and the third switching circuit are in the second state; in the third operating mode, the first switching circuit and the third switching circuit are in the first state and the second switching circuit and the fourth switching circuit are in the second state; and in the fourth operating mode, the first switching circuit, the second switching circuit, the third switching circuit, and the fourth switching circuit are in the second state.

19. An electronic device, the electronic device comprising: A baseband processor circuit, the baseband processor circuit being configured to generate baseband signals; A mixer circuit configured to generate an radio frequency signal based on the baseband signal and the output signal of a voltage-controlled oscillator (VCO); Antenna, the antenna being configured to transmit the radio frequency signal; as well as A VCO circuit, configured to generate the VCO output signal, the VCO circuit having A first VCO core having a first terminal and a second terminal; A first inductor is coupled between the first terminal and the second terminal; The second VCO core has a third terminal and a fourth terminal; A second inductor is coupled between the third terminal and the fourth terminal; The third VCO core has a fifth terminal and a sixth terminal; A third inductor is coupled between the fifth terminal and the sixth terminal; The fourth VCO core has a seventh terminal and an eighth terminal; A fourth inductor is coupled between the seventh terminal and the eighth terminal; A first fixed capacitor, wherein the first fixed capacitor couples the first terminal to the fourth terminal; A second fixed capacitor, wherein the second fixed capacitor couples the second terminal to the third terminal; as well as A switching network, communicatively coupled to the first VCO, the second VCO, the third VCO, and the fourth VCO, is configured to selectively control the current direction in the first inductor, the second inductor, the third inductor, and the fourth inductor to generate a VCO output signal in a frequency range across at least four operating modes of the VCO circuit. The switching network includes a switching circuit that couples the first terminal and the second terminal to the third terminal and the fourth terminal in parallel with the first fixed capacitor and the second fixed capacitor. The switching circuit has a first state and a second state. In the first state, the switching circuit couples the first terminal to the fourth terminal and the second terminal to the third terminal. In the second state, the switching circuit couples the first terminal to the third terminal and the second terminal to the fourth terminal.

20. The electronic device of claim 19, wherein the VCO circuit comprises: A third fixed capacitor, wherein the third fixed capacitor couples the third terminal to the sixth terminal; A fourth fixed capacitor, wherein the fourth fixed capacitor couples the fourth terminal to the fifth terminal; A fifth fixed capacitor, wherein the fifth fixed capacitor couples the fifth terminal to the eighth terminal; A sixth fixed capacitor, wherein the sixth fixed capacitor couples the sixth terminal to the seventh terminal; A seventh fixed capacitor, wherein the seventh terminal is coupled to the second terminal; as well as An eighth fixed capacitor, wherein the eighth fixed capacitor couples the eighth terminal to the first terminal.

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