Rate limiting for partition transition to open

Abstract

The present disclosure generally relates to a method of operating a storage device. The storage device includes a controller that includes a first random access memory (RAM1), a second random access memory (RAM2), and a storage unit divided into a plurality of zones. The controller localizes a host to a maximum number of zones that can be in an open and active state at a time. An open zone can be switched to a closed state after a predetermined amount of time expires and vice versa. The maximum number of open zones is based on an amount of space in a temporary RAM1 buffer and one or more amounts of time for generating parity data, copying the parity data from the RAM2 to the RAM1, updating the parity data, switching a zone from the open and active state to the closed state.

Description

[0001] Cross Reference to Related Applications

[0002] This patent application claims priority to U.S. Application No. 16 / 885,073, filed May 27, 2020, which is incorporated by reference herein in its entirety. BACKGROUND TECHNICAL FIELD

[0004] Embodiments of the present disclosure generally relate to storage devices, such as solid state drives (SSDs).

[0005] Description of the Related Art

[0006] Storage devices, such as SSDs, can be used in computers in applications that require relatively low latency and high capacity storage. For example, SSDs can exhibit lower latency than hard disk drives (HDDs), especially for random reads and writes. Generally, a controller of an SSD receives commands to read or write data from a host device to a memory device. The data is read and written to one or more erase blocks in the memory device. Each of these erase blocks is associated with a logical block address, such that the SSD and / or the host device knows where the data is stored. One or more erase blocks can be grouped together by their respective logical block addresses to form a plurality of zones.

[0007] As a storage device receives a command to write data to a particular zone, the data associated with the command is written to the memory device and parity data is simultaneously generated for the data to protect the data. The parity data is then stored in volatile memory within the storage device. However, because volatile memory is expensive, storage devices generally include a very limited amount of volatile memory, such as SRAM and DRAM. Because multiple zones can be open at the same time, the data written to volatile memory can take up many valuable volatile memory spaces, which can reduce the amount of volatile memory available for other data or can require a greater amount of volatile memory to be included in the storage device. Additionally, transferring data between various volatile memories can take a long time, resulting in write latency for the storage device.

[0008] Accordingly, there is a need for a new method of generating and storing data in a storage device. SUMMARY

[0009] The present disclosure generally relates to methods of operating a storage device. The storage device includes a controller that includes a first random access memory (RAM1), a second random access memory (RAM2), and a storage unit divided into a plurality of zones. The controller localizes a host to a maximum number of zones that can be in an open and active state at a time. An open zone can be switched to a closed state after a predetermined amount of time expires, and vice versa. The maximum number of open zones is based on an amount of space in a temporary RAM1 buffer and one or more amounts of time for generating parity data, copying the parity data from the RAM2 to the RAM1, updating the parity data, switching a zone from the open and active state to the closed state.

[0010] In one embodiment, a storage device includes a non-volatile storage unit, where a capacity of the non-volatile storage unit is divided into a plurality of zones. The non-volatile storage unit includes a plurality of dies, and each die of the plurality of dies includes a plurality of erase blocks. The storage device also includes a first volatile memory unit and a controller coupled to the non-volatile storage unit and the first volatile memory unit. The controller includes a second volatile memory unit, where the controller is configured to set a maximum number of open and active zones and receive one or more first commands to write data to one or more open and active zones of the plurality of zones. The controller is further configured to receive one or more second commands to write data to a first zone, where the first zone is in a closed or resource-sparing lower performance internal state, change a least recently used open and active zone to the closed or resource-sparing lower performance internal state, and change the first zone to an open and active state.

[0011] In another embodiment, a storage device includes a non-volatile storage unit, where a capacity of the non-volatile storage unit is divided into a plurality of zones. The non-volatile storage unit includes a plurality of dies, and each of the plurality of dies includes a plurality of erase blocks. The storage device also includes a first volatile memory unit and a controller coupled to the non-volatile storage unit and the first volatile memory unit. The controller includes a second volatile memory unit, where the controller is configured to: set a maximum number of open and active zones; receive one or more commands to write data to one or more open and active zones of the plurality of zones; and generate new first parity data for a first open and active zone in a temporary location of one or more temporary locations in the second volatile memory unit. The controller is further configured to copy previous first parity data for the first open and active zone from the first volatile memory unit to a first location in the second volatile memory unit. The controller is also configured to update the previous first parity data with the new first parity data in the second volatile memory unit, where an amount of time taken to generate the new first parity data, copy the previous first parity data, and update the previous first parity data determines the maximum number of open and active zones.

[0012] In another embodiment, a storage device includes a non-volatile storage unit, where a capacity of the non-volatile storage unit is divided into a plurality of zones. The non-volatile storage unit includes a plurality of dies, and each of the plurality of dies includes a plurality of erase blocks. The storage device also includes a first volatile memory unit and a controller coupled to the non-volatile storage unit and the first volatile memory unit. The controller includes a second volatile memory unit, where the second volatile memory includes one or more temporary locations. The controller is configured to: set a maximum number of open and active zones, where the maximum number of open and active zones is determined based on a number of temporary locations in the second volatile memory; and receive one or more first commands to write data to one or more open and active zones of the plurality of zones. The controller is further configured to: generate new first parity data for a first open and active zone in a first temporary location in the second volatile memory unit; change a second open and active zone to a closed or resource saving lower performance internal state upon receiving one or more second commands to write data to a closed zone; and change the closed zone to an open and active state. BRIEF DESCRIPTION OF DRAWINGS

[0013] Therefore, by reference to the embodiments, which follow, a manner of obtaining a detailed understanding of the above features of the present disclosure, a more particular description of the application, the above general description of the application, and the above brief description of the drawings, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings show only typical embodiments of the application and should not be considered as limiting its scope, as the application can admit other equally effective embodiments.

[0014] Figure 1 is a schematic block diagram illustrating a storage system according to one embodiment.

[0015] Figure 2A illustrates a partitioned namespace utilized in a storage device according to one embodiment.

[0016] Figure 2B illustrates a state diagram for a partitioned namespace of a storage device according to one embodiment. Figure 2A

[0017] Figures 3A-3D illustrates a schematic block diagram of generating and / or updating data corresponding to various partitions in volatile memory according to various embodiments.

[0018] Figure 4 illustrates a schematic diagram of updating in-flight data in a storage device over time according to various embodiments.

[0019] To facilitate an understanding of this application, like reference characters are used throughout the various embodiments disclosed. It should be noted that, in one embodiment, elements disclosed in one embodiment can be advantageously used in other embodiments without specific recitation. DETAILED DESCRIPTION

[0020] In the following, reference is made to embodiments of the present disclosure. However, it should be understood that the present disclosure is not limited to the particularly described embodiments. On the contrary, any combination of the following features and elements, whether related to different embodiments or not, can be utilized to realize and practice the present disclosure. In addition, although embodiments of the present disclosure can achieve advantages over other possible solutions and / or over the prior art, whether or not a particular advantage is achieved by a given embodiment is not limiting of the present disclosure. Thus, the following aspects, features, embodiments and advantages are merely illustrative and are not considered elements or limitations of the appended claims unless explicitly recited in a claim. Likewise, reference to "the present disclosure" should not be construed as an identification of any one invention or generally precluding its use in combination with other inventions.

[0021] ​The present disclosure generally relates to methods of operating a storage device. The storage device includes a controller that includes a first random access memory (RAM1), a second random access memory (RAM2), and a storage unit divided into a plurality of zones. The controller confines a host to a maximum number of zones that can be in an open and active state at a time. An open zone can be switched to a closed state after a predetermined amount of time expires, and vice versa. The maximum number of open zones is based on an amount of space in a temporary RAM1 buffer and one or more amounts of time for generating parity data, copying the parity data from the RAM2 to the RAM1, updating the parity data, switching a zone from the open and active state to the closed state.

[0022] Figure 1 is a schematic block diagram illustrating a storage system 100 in accordance with one or more techniques of the present disclosure, in which a storage device 106 can serve as a storage device for a host device 104. For example, the host device 104 can utilize storage units 110 (such as non-volatile memory) included in the storage device 106 to store and retrieve data. For example, the storage units 110 can be any type of non-volatile memory, such as MRAM, NAND, NOR, or HDD. In the following description, the storage units 110 are referred to as non-volatile memory (NVM) 110 for simplicity and exemplary purposes. The host device 104 includes a host DRAM 138. In some examples, the storage system 100 can include multiple storage devices, such as the storage device 106, that can operate as a storage array. For example, the storage system 100 can include multiple storage devices 106 that are configured as a redundant array of inexpensive / independent disks (RAID) that collectively serve as a mass storage device for the host device 104.

[0023] The storage system 100 includes a host device 104 that can store data to and / or retrieve data from one or more storage devices, such as the storage device 106. As shown, the host device 104 can communicate with the storage device 106 via an interface 114. The host device 104 can include any of a variety of devices, including a computer server, a network-attached storage (NAS) unit, a desktop computer, a notebook (i.e., laptop) computer, a tablet computer, a set-top box, a telephone handset such as a so-called "smart" phone, a so-called "smart" tablet, a television, a camera, a display device, a digital media player, a video gaming console, a video streaming device, etc. Figure 1

[0024] ​Storage device 106 includes a controller 108, an NVM 110, a power supply 111, a first random access memory (RAM) or volatile memory 112, such as dynamic random access memory (DRAM), and an interface 114. The controller 108 may include a parity check engine or XOR engine 124 and a second RAM or volatile memory 118, such as static random access memory (SRAM). The XOR engine 124 is a parity check engine and is referred to as an XOR engine for illustrative purposes. However, the XOR engine 124 may include other embodiments of the parity check engine. In the following description, for simplicity and illustrative purposes, the first RAM or volatile memory 112 is referred to as DRAM, and the second RAM or volatile memory 118 is referred to as SRAM. In some examples, for clarity, storage device 106 may include... Figure 1 Additional components not shown. For example, storage device 106 may include a printed circuit board (PCB) to which components of storage device 106 are mechanically attached, and the PCB includes conductive traces for electrically interconnecting components of storage device 106, etc. In some examples, the physical dimensions and connector configuration of storage device 106 may conform to one or more standard form factors. Some exemplary standard form factors include, but are not limited to, 2.5” data storage devices (e.g., HDDs or SSDs), 1.8” data storage devices, peripheral component interconnects (PCI), PCI expansion (PCI-X), PCI Express (PCIe) (e.g., PCIe x1, x4, x8, x16, PCIe Mini cards, MiniPCI, etc.). In some examples, storage device 106 may be directly coupled (e.g., directly soldered) to the motherboard of host device 104.

[0025] The interface 114 of the storage device 106 can include one or both of a data bus for exchanging data with the host device 104 and a control bus for exchanging commands with the host device 104. The interface 114 can operate according to any suitable protocol. For example, the interface 114 can operate according to one or more of the following protocols: Advanced Technology Attachment (ATA) (e.g., Serial ATA (SATA) and Parallel ATA (PATA)), Fibre Channel Protocol (FCP), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), PCI, PCIe, Non-Volatile Memory Standard (NVMe), OpenCAPI, GenZ, Cache Coherent Interface Accelerator (CCIX), Compute Express Link (CXL), Open Channel SSD (OCSSD), etc. Electrical connections of the interface 114 (e.g., data bus, control bus, or both) are electrically connected to the controller 108, providing electrical connections between the host device 104 and the controller 108, allowing data to be exchanged between the host device 104 and the controller 108. In some examples, the electrical connections of the interface 114 can also allow the storage device 106 to receive power from the host device 104. For example, as shown in FIG. 1, the power supply 111 can receive power from the host device 104 via the interface 114. Figure 1

[0026] The storage device 106 includes the NVM 110, which can include a plurality of memory devices or memory units. The NVM 110 can be configured to store and / or retrieve data. For example, a storage unit of the NVM 110 can receive data and receive a message from the controller 108 instructing the storage unit to store the data. Similarly, a storage unit of the NVM 110 can receive a message from the controller 108 instructing the storage unit to retrieve data. In some examples, each of the storage units can be referred to as a die. In some examples, a single physical chip can include multiple dies (i.e., multiple storage units). In some examples, each storage unit can be configured to store a relatively large amount of data (e.g., 128 MB, 256 MB, 512 MB, 1 GB, 2 GB, 4 GB, 8 GB, 16 GB, 32 GB, 64 GB, 128 GB, 256 GB, 512 GB, 1 TB, etc.).

[0027] In some examples, each storage unit of the NVM 110 can include any type of non-volatile memory device, such as a flash memory device, a phase change memory (PCM) device, a resistive random access memory (ReRAM) device, a magnetoresistive random access memory (MRAM) device, a ferroelectric random access memory (F-RAM), a holographic memory device, and any other type of non-volatile memory device.

[0028] ​The NVM 110 can include a plurality of flash memory devices or storage units. The flash memory devices can include NAND or NOR based flash memory devices and can store data based on charge contained in a floating gate of a transistor for each flash memory cell. In a NAND flash memory device, the flash memory device can be divided into a plurality of blocks, which can be divided into a plurality of pages. Each block of the plurality of blocks within a particular memory device can include a plurality of NAND cells. Rows of NAND cells can be electrically connected using word lines to define a page of the plurality of pages. Respective cells in each page of the plurality of pages can be electrically connected to a respective bit line. Further, the NAND flash memory device can be a 2D or 3D device and can be single level cell (SLC), multi-level cell (MLC), triple level cell (TLC), or quad level cell (QLC). The controller 108 can write data to and read data from the NAND flash memory device at a page level and erase data from the NAND flash memory device at a block level.

[0029] A portion of the NVM 110 can be formatted as a logical block such that a capacity of the NVM 110 is divided into a plurality of zones. Each of the zones includes a plurality of physical or erase blocks of the NVM 110 and each of the erase blocks is associated with a plurality of logical blocks. Each of the logical blocks is associated with a unique LBA or sector. Each of the zones can have a size that is aligned with a capacity of one or more erase blocks of the NVM 110. When the controller 108 receives a command from, such as, the host device 104, the controller 108 can read data from and write data to a plurality of logical blocks associated with a plurality of erase blocks of the NVM 110.

[0030] The storage device 106 includes a power source 111, which can provide power to one or more components of the storage device 106. When operating in a standard mode, the power source 111 can power the one or more components using power provided by an external device, such as the host device 104. For example, the power source 111 can power the one or more components using power received from the host device 104 via the interface 114. In some examples, the power source 111 can include one or more power storage components configured to power the one or more components when operating in an off mode, such as in the event that power is stopped being received from the external device. In this way, the power source 111 can act as an on-board backup power source. Some examples of the one or more power storage components include, but are not limited to, capacitors, supercapacitors, batteries, and the like. In some examples, the amount of power that can be stored by the one or more power storage components can be a function of the cost and / or size (e.g., area / volume) of the one or more power storage components. In other words, as the amount of power stored by the one or more power storage components increases, the cost and / or size of the one or more power storage components also increases.

[0031] The storage device 106 also includes a volatile memory 112, which can be used by the controller 108 to store information. The volatile memory 112 can include one or more volatile memory devices. In some examples, the controller 108 can use the volatile memory 112 as a cache. For example, the controller 108 can store cached information in the volatile memory 112 until the cached information is written to the non-volatile memory 110. As shown, the volatile memory 112 can consume power received from the power source 111. Examples of the volatile memory 112 include, but are not limited to, RAM, DRAM, SRAM, and synchronous dynamic RAM (SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, LPDDR4, DDR5, LPDDR5, etc.)). As shown, the volatile memory can consume power received from the power source 111. Figure 1 Figure 1 As shown, the volatile memory can consume power received from the power source 111.

[0032] ​Various types of volatile memory can be used for different access attributes. For example, DRAM 112 can be arranged for longer burst accesses to improve bandwidth (BW) of the same access bus. Alternatively, DRAM 112 can be used for smaller accesses so that random small accesses can have better latency. Controller 108 includes additional optional SRAM and / or embedded MRAM 126. Embedded MRAM 126 is another alternative memory that can be used in another embodiment. Similarly, access to MRAM 126 can be optimized for different design purposes, but the number of embedded MRAM 126 in SSD controller 108 can be cost sensitive. Thus, how much data and which data goes into advanced non-volatile memory and advanced volatile memory will be subject to system tradeoffs.

[0033] Storage device 106 includes controller 108, which can manage one or more operations of storage device 106. For example, controller 108 can manage reading data from NVM 110 and / or writing data to the NVM via a toggle mode (TM) bus 128. In some embodiments, when storage device 106 receives a write command from host device 104, controller 108 can initiate a data storage command to store data to the NVM 110 and monitor progress of the data storage command. Controller 108 can determine at least one operational characteristic of storage system 100 and store the at least one operational characteristic to the NVM 110. In some embodiments, when storage device 106 receives a write command from host device 104, controller 108 temporarily stores data associated with the write command in an internal memory or buffer (not shown) before sending the data to NVM 110.

[0034] Controller 108 can include an XOR engine 124 having logic and / or features to generate XOR parity information. Exclusive OR (XOR) parity information can be used to improve reliability of storage device 106, such as enabling it to perform data recovery for data that fails to write or read to and from the NVM, or to perform data recovery in the event of a power loss. Reliability can be provided by using XOR parity information that is generated or calculated based on data stored to storage device 106. Data can be written to NVM 110 through XOR engine 124. XOR engine 124 can generate a parity stream to be written to SRAM 118. SRAM 118 and DRAM 112 can each contain a plurality of regions to which data can be written. Data associated with a partition can be copied from SRAM regions 122a-122n in SRAM 118 to DRAM regions 116a-116n in DRAM 112, and vice versa.

[0035] SRAM 118 and DRAM 112 each individually comprise one or more dies. Each of the one or more dies comprises one or more banks of memory, which are comprised of one or more storage banks. The storage banks are comprised of rows and pages. SRAM 118 in controller 108 can be logically or physically divided into different SRAM zones or regions 122a-122n for use by controller 108. Similarly, DRAM 112 can be logically or physically divided into different DRAM zones or regions 116a-116n for use by controller 108. MRAM within controller 108 can be logically or physically divided into different MRAM zones or regions (not shown). The external attachment for MRAM typically has vendor-specific structure and access, which is not described here.

[0036] Figure 2A A zoned namespace (ZNS) 202 view used in a storage device 200 is shown in accordance with one embodiment. Storage device 200 can present ZNS 202 view to a host device. Figure 2B A state 250 of ZNS 202 of storage device 200 is shown in accordance with one embodiment. Storage device 200 can be Figure 1 storage system 100. Storage device 200 can have one or more ZNS 202, and each ZNS 202 can be a different size. In addition to one or more zoned namespaces 202, storage device 200 can also include one or more regular namespaces. Further, ZNS 202 can be zoned block commands (ZBC) for SAS and / or zoned device ATA command set (ZAC) for SATA. Host-side zoning activity can be more directly related to media activity in the zoning drive due to the relationship between possible logical and physical activity.

[0037] In storage device 200, ZNS 202 is a quantity of NVM that can be formatted into logical blocks such that the capacity is divided into a plurality of zones 206a-206n (collectively, zones 206). NVM can be Figure 1 storage cells or NVM 110. Each of zones 206 includes a plurality of physical blocks or erase blocks (not shown) of memory cells or NVM 204, and each of the erase blocks is associated with a plurality of logical blocks (not shown). Each of zones 206 can have a size that is aligned with the capacity of one or more erase blocks of NVM or NAND devices. When controller 208 receives a command from, such as, a host device (not shown) or a submission queue of a host device, controller 208 can read data from and write data to a plurality of logical blocks associated with a plurality of erase blocks (EBs) of ZNS 202. Each of the logical blocks is associated with a unique LBA or sector.

[0038] In one embodiment, NVM 204 is a NAND device. The NAND device includes one or more dies. Each of the one or more dies includes one or more planes. Each of the one or more planes includes one or more erase blocks. Each of the one or more erase blocks includes one or more word lines (e.g., 256 word lines). Each of the one or more word lines can be addressed in one or more pages. For example, an MLC NAND die can use upper and lower pages to reach two bits in each cell of the entire word line (e.g., 16 KiB per page). Further, each page can be accessed at a granularity equal to or less than a full page. A controller can access the NAND frequently at a user data granularity logical block address (LBA) size of 512 bytes. Thus, as referenced in the description below, a NAND location is equal to a granularity of 512 bytes. Thus, the LBA size is 512 bytes and the page size of two pages of MLC NAND is 16 KiB, which results in 32 LBAs per word line. However, the NAND location size is not intended to be limiting and is used as an example only.

[0039] When data is written to an erase block, one or more logical blocks are updated correspondingly within the partition 206 to track the location of the data within NVM 204. Data can be written one partition 206 at a time until the partition 206 becomes full, or to multiple partitions 206 so that multiple partitions 206 can become partially full. Similarly, when data is written to a particular partition 206, the data can be written one block at a time in order of NAND locations, page by page or word line by word line, to multiple erase blocks until moving to an adjacent block (i.e., writing to a first erase block until the first erase block becomes full before moving to a second erase block), or can be written multiple blocks at a time in order of NAND locations, page by page or word line by word line, to partially fill each block in a parallel manner (i.e., writing a first NAND location or page of each erase block before writing a second NAND location or page of each erase block). This sequential programming of each NAND location is a typical, non-limiting requirement of many NAND EBs.

[0040] When the controller 208 selects the erase block in which to store the data of each partition, the controller 208 will be able to select the erase block at the time of partition opening, or can select the erase block when the need to fill the first word line of that particular erase block is reached. This can be more differentiated when utilizing the above-described method of completely filling one erase block before starting the next. The controller 208 can use the time differential to select a more desirable erase block on an on-the-fly basis. The decision of which erase block to allocate and assign to each partition and its contiguous LBAs can be happening within the controller 208 for zero or multiple parallel partitions at a time.

[0041] Each of the partitions 206 is associated with a zone start logical block address (ZSLBA) or zone start sector. The ZSLBA is the first available LBA in the partition 206. For example, the first partition 206a is associated with a ZSLBA, the second partition 206b is associated with a ZSLBA, the third partition 206c is associated with a ZSLBA, the fourth partition 206d is associated with a ZSLBA, and the nth partition 206n (i.e., the last partition) is associated with a ZSLBA. Each partition 206 is identified by its ZSLBA and is configured to receive sequential writes (i.e., data is written to the NVM 110 in the order in which the write commands are received). a b c d n Each partition 206 is identified by its ZSLBA and is configured to receive sequential writes (i.e., data is written to the NVM 110 in the order in which the write commands are received).

[0042] When data is written to a partition 206, the write pointer 210 is advanced or updated to point to or indicate the next available block in the partition 206 to track the next write start point (i.e., the completion point of a previous write equals the start point of a subsequent write). Thus, the write pointer 210 indicates where a subsequent write to the partition 206 will start. The subsequent write command is a “zone append” command in which the data associated with the subsequent write command is appended to the partition 206 at the location indicated by the write pointer 210 as the next start point. An ordered list of LBAs within the partition 206 can be stored for write ordering. Each partition 206 can have its own write pointer 210. Thus, when a write command is received, the partition is identified by its ZSLBA and the write pointer 210 determines the location within the identified partition where the write of data starts.

[0043] Figure 2B A state 250 of the ZNS 202 is shown for Figure 2A In the state 250, each partition can be in a different state, such as empty, active, full, or offline. When a partition is empty, the partition contains no data (i.e., none of the erased blocks in the partition currently store data) and the write pointer is at the ZSLBA (i.e., WP = 0). An empty partition will switch to an open and active partition once a write is scheduled to the partition or an open partition command is issued by the host. Zone management (ZM) commands can be used to move a partition between the open partition and the closed partition states (both active states). If a partition is active, the partition includes open blocks that can be written to and a description of the recommended time in active state can be provided to the host. The controller 208 includes the ZM. Zone metadata can be stored in the ZM and / or the controller 208.

[0044] ​​​​The term "write" includes programming user data on 0 or more NAND locations in an erase block and / or partially filled NAND locations in an erase block when user data has not yet filled all available NAND locations. The term "write" can also include moving a partition to full due to internal drive processing needs (open block data retention issues due to error bits accumulating faster on open erase blocks), the storage device 200 shutting down or filling partitions due to resource limitations (like too many open partitions to track or defect status found), or the host device shutting down a partition due to issues such as no more data to send to the drive, computer shutdown, error handling on the host, limited host resources for tracking, and the like.

[0045] An active partition can be open or closed. An open partition is an empty or partially filled partition that is ready to be written to and has currently allocated resources. Data received from the host device with a write command or a partition append command can be programmed to an open erase block that is not currently filled with previous data. A closed partition is an empty or partially filled partition that is not currently receiving writes from the host on a continuous basis. The closed state of a partition is a resource conserving, lower performance internal state. Moving a partition from an open to a closed state allows the controller 308 to reallocate resources to other tasks. These tasks can include, but are not limited to, other open partitions, other regular non-partition areas, or other controller needs.

[0046] In open and closed partitions, the write pointer points to some location in the partition between the ZSLBA and the end of the last LBA of the partition (i.e., WP > 0). An active partition can be switched between open and closed states as specified by the ZM or when a write is scheduled to the partition. Additionally, the ZM can reset an active partition to clear or erase the data stored in the partition so that the partition switches back to an empty partition. Once an active partition is full, the partition switches to a full state. A full partition is a partition that is completely filled with data and has no more available sectors or LBAs for writing data (i.e., WP = ZCAP). In a full partition, the write pointer points to the end of the writeable capacity of the partition. Read commands of the data stored in a full partition can still be executed.

[0047] A zone can have any total capacity, such as 256 MiB or 512 MiB. However, a small portion of each zone can not be accessible to write data to, but can still be read, such as a portion of each zone storing parity data and one or more excluded erase blocks. For example, if the total capacity of zone 206 is 512 MiB, then the ZCAP can be 470 MiB, which is the capacity available to write data to, and 42 MiB is not available to write data to. The writeable capacity of a zone (ZCAP) is equal to or less than the total zone storage capacity. Storage device 200 can determine the ZCAP of each zone after a zone reset. For example, controller 208 or ZM can determine the ZCAP of each zone. Storage device 200 can determine the ZCAP of a zone at the time of a zone reset.

[0048] A ZM can reset a full zone, scheduling erasure of data stored in the zone, causing the zone to switch back to an empty zone. At the time of resetting a full zone, although the zone can be marked as an empty zone available to write to, the data of the zone can not be immediately purged. However, the reset zone must be erased before switching to open and active. A zone can be erased at any time between ZM reset and ZM open. At the time of resetting a zone, storage device 200 can determine the new ZCAP of the reset zone and update the writeable ZCAP attribute in the zone metadata. An offline zone is a zone to which data cannot be written. An offline zone can be in a full state, an empty state, or in a partially full state without being in an active state.

[0049] Since resetting a zone purges or schedules erasure of all data stored in the zone, the need for garbage collection of individual erase blocks is eliminated, improving the overall garbage collection process of storage device 200. Storage device 200 can mark one or more erase blocks for erasure. When a new zone is to be formed and storage device 200 anticipates ZM open, then the one or more erase blocks marked for erasure can be erased. Storage device 200 can also decide and create the physical backing of the zone after erasing the erase blocks. Thus, once the new zone is open and an erase block is selected to form the zone, the erase block will be erased. In addition, each time a zone is reset, a new order of LBAs and write pointers 210 of zone 206 can be selected, enabling zone 206 to tolerate out-of-order command reception. Write pointers 210 can optionally be turned off, such that commands can be written to any starting LBA indicated by the command.

[0050] Referring back to Figure 2AWhen the host sends a write command to write data to the partition 206, the controller 208 pulls in the write command and identifies the write command as a write to the newly open partition 206. The controller 208 selects a set of EBs to store the data associated with the write command to the newly open partition 206 and the newly open partition 206 switches to the active partition 206. The write command can be a command to write new data or a command to move valid data to another partition for garbage collection purposes. The controller 208 is configured to DMA read new commands from a submission queue populated by the host device.

[0051] In the empty partition 206 that just switched to active, data is assigned to the partition 206 and a set of associated sequential LBAs of the partition 206 starting at the ZSLBA because the write pointer 210 indicates the logical block associated with the ZSLBA as the first available logical block. The data can be written to one or more erase blocks or NAND locations already allocated for the physical location of the partition 206. After the data associated with the write command has been written to the partition 206, the write pointer 210 is updated to point to the next LBA available for host writes (i.e., the completion point of the first write). The write data from the host write command is sequentially programmed into the next available NAND location in the physical support selected for the partition in the erase block.

[0052] For example, the controller 208 can receive a first write command, or first partition append command, to the third partition 206c. The host identifies which logical block of the partition 206 to use to write the data associated with the first command in order. The data associated with the first command is then written to the first or next available LBA in the third partition 206c as indicated by the write pointer 210 and the write pointer 210 is advanced or updated to point to the next available LBA available for host writes (i.e., WP > 0). If the controller 208 receives a second write command, or second partition append command, to the third partition 206c, the data associated with the second write command is written to the next available LBA in the third partition 206c identified by the write pointer 210. Once the data associated with the second command is written to the third partition 206c, the write pointer 210 is again advanced or updated to point to the next available LBA available for host writes. Resetting the third partition 206c moves the write pointer 210 back to the ZSLBA (i.e., WP = 0) and the third partition 206c switches to the empty partition. c

[0053] Figures 3A-3D schematic block diagrams of generating and / or updating data corresponding to various partitions in volatile memory, in accordance with various embodiments. Figure 1 Aspects of the system 100 will be described in accordance with Figures 3A-3D ​The following description is provided for the purpose of illustrating the subject matter. It is not intended to limit the scope of the subject matter. The subject matter is described herein with reference to particular embodiments. Various modifications to these particular embodiments can and will be implemented by one skilled in the art. However, without departing from the spirit and scope of the subject matter, the subject matter can be implemented in other embodiments and implemented with both software and hardware aspects. For example, it will be appreciated that a storage device, such as the storage device 106 described in the following description, can be implemented as the storage device 200 described in the following description. Furthermore, the non-volatile memory (NVM) 306 described in the following description can be the non-volatile memory (NVM) 110 described in the system 100 described in the following description. The term NAND can be used throughout to describe the non-volatile memory 110. Such term is not intended to be limiting, but to provide an example of a possible implementation for reference. The controller 302 described in the following description can be the controller 108 described in the system 100 described in the following description. The XOR engine 304 described in the following description can be the XOR engine 124 described in the system 100 described in the following description. The SRAM 308 described in the following description can be the SRAM 118 described in the system 100 described in the following description. The DRAM 312 described in the following description can be the DRAM 112 described in the system 100 described in the following description.

[0054] The data storage device 300 can be the storage device 106 described in the following description or the storage device 200 described in the following description, and the non-volatile memory (NVM) 306 can be the non-volatile memory 110 described in the system 100 described in the following description. The term NAND can be used throughout to describe the non-volatile memory 110. Such term is not intended to be limiting, but to provide an example of a possible implementation for reference. The controller 302 described in the following description can be the controller 108 described in the system 100 described in the following description. The XOR engine 304 described in the following description can be the XOR engine 124 described in the system 100 described in the following description. The SRAM 308 described in the following description can be the SRAM 118 described in the system 100 described in the following description. The DRAM 312 described in the following description can be the DRAM 112 described in the system 100 described in the following description. Figure 1 Figure 2A The data storage device 300 can be the storage device 106 described in the following description or the storage device 200 described in the following description, and the non-volatile memory (NVM) 306 can be the non-volatile memory 110 described in the system 100 described in the following description. The term NAND can be used throughout to describe the non-volatile memory 110. Such term is not intended to be limiting, but to provide an example of a possible implementation for reference. The controller 302 described in the following description can be the controller 108 described in the system 100 described in the following description. The XOR engine 304 described in the following description can be the XOR engine 124 described in the system 100 described in the following description. The SRAM 308 described in the following description can be the SRAM 118 described in the system 100 described in the following description. The DRAM 312 described in the following description can be the DRAM 112 described in the system 100 described in the following description. Figure 1 Figure 1 The data storage device 300 can be the storage device 106 described in the following description or the storage device 200 described in the following description, and the non-volatile memory (NVM) 306 can be the non-volatile memory 110 described in the system 100 described in the following description. The term NAND can be used throughout to describe the non-volatile memory 110. Such term is not intended to be limiting, but to provide an example of a possible implementation for reference. The controller 302 described in the following description can be the controller 108 described in the system 100 described in the following description. The XOR engine 304 described in the following description can be the XOR engine 124 described in the system 100 described in the following description. The SRAM 308 described in the following description can be the SRAM 118 described in the system 100 described in the following description. The DRAM 312 described in the following description can be the DRAM 112 described in the system 100 described in the following description. Figure 1 Figure 1 The data storage device 300 can be the storage device 106 described in the following description or the storage device 200 described in the following description, and the non-volatile memory (NVM) 306 can be the non-volatile memory 110 described in the system 100 described in the following description. The term NAND can be used throughout to describe the non-volatile memory 110. Such term is not intended to be limiting, but to provide an example of a possible implementation for reference. The controller 302 described in the following description can be the controller 108 described in the system 100 described in the following description. The XOR engine 304 described in the following description can be the XOR engine 124 described in the system 100 described in the following description. The SRAM 308 described in the following description can be the SRAM 118 described in the system 100 described in the following description. The DRAM 312 described in the following description can be the DRAM 112 described in the system 100 described in the following description. Figure 1

[0055] The data storage device 300 can be the storage device 106 described in the following description or the storage device 200 described in the following description, and the non-volatile memory (NVM) 306 can be the non-volatile memory 110 described in the system 100 described in the following description. The term NAND can be used throughout to describe the non-volatile memory 110. Such term is not intended to be limiting, but to provide an example of a possible implementation for reference. The controller 302 described in the following description can be the controller 108 described in the system 100 described in the following description. The XOR engine 304 described in the following description can be the XOR engine 124 described in the system 100 described in the following description. The SRAM 308 described in the following description can be the SRAM 118 described in the system 100 described in the following description. The DRAM 312 described in the following description can be the DRAM 112 described in the system 100 described in the following description.

[0056] The data storage device 300 can be the storage device 106 described in the following description or the storage device 200 described in the following description, and the non-volatile memory (NVM) 306 can be the non-volatile memory 110 described in the system 100 described in the following description. The term NAND can be used throughout to describe the non-volatile memory 110. Such term is not intended to be limiting, but to provide an example of a possible implementation for reference. The controller 302 described in the following description can be the controller 108 described in the system 100 described in the following description. The XOR engine 304 described in the following description can be the XOR engine 124 described in the system 100 described in the following description. The SRAM 308 described in the following description can be the SRAM 118 described in the system 100 described in the following description. The DRAM 312 described in the following description can be the DRAM 112 described in the system 100 described in the following description. Figure 3A-3D ​​​​​

[0057] In Figure 1 In the SRAM regions 310a-310n, the use of "Wxx" qualifying the partition ID indicates that the controller 302 has received a write command to write data to the partition and will update the parity data for the corresponding partition. However, in the DRAM regions 314a-314n, the use of "Wxx" qualifying the partition ID indicates that the parity data has been successfully updated in the SRAM regions 310a-310n and has been written from the relevant SRAM regions 310a-310n to the DRAM regions 314a-314n. The SRAM regions 310a-310n and the DRAM regions 314a-314n can be any suitable size related to the partition, as described above.

[0058] Further, in the embodiments discussed below, the SRAM 308 can include an amount of space dedicated to temporary buffers or "high-speed staging areas" of parity data for a partition associated with a write command. In some embodiments, the temporary buffers can include from about one SRAM region 310n to about five SRAM regions 310n-4-310n or more than five SRAM regions 310n-4-310n. The data stored in the temporary SRAM regions 310n-4-310n can be stored for a short time. The SRAM 308 also includes a plurality of non-temporary SRAM regions 310a-310f in which data can be stored for a long time. The number of temporary and non-temporary SRAM regions 310a-310n listed is not intended to be limiting, but rather to provide examples of possible embodiments.

[0059] The parity data for a partition can also be represented by an asterisk (*) or a single quote or angle quote symbol ('). The asterisk (*) indicates that new parity data for a partition has been programmed from the XOR engine 304 to the temporary buffers in the SRAM 118, but the SRAM regions 310a-310n storing the relevant parity data for the partition copied from the DRAM regions 314a-314n have not yet been updated. The single quote or angle quote symbol (' ) refers to the partition that includes updated parity data associated with a write command to the temporary buffers of the SRAM 308.

[0060] The data storage device 300 can limit or restrict the host, such as the host device 104 of Figure 2B The maximum number of parallel partitions in an open and active state can be limited to about 128 partitions to about 1024 partitions. An active partition refers to a partition that has been programmed with data and has parity data associated with the data. For example, the maximum number of partitions in an open and active state can be limited to about 128 partitions to about 1024 partitions. An active partition refers to a partition that has been programmed with data and has parity data associated with the data. Figures 2A-2BThe open state describes a partition that is receiving write commands, while the closed state or resource-sparing lower performance internal state describes a partition that is not currently receiving write commands. The closed state of a partition is the resource-sparing lower performance internal state.

[0061] After a predetermined amount of time has expired since the last time the state of a partition was switched, such as about 0.5 seconds to about 1 second, 1 second to about 5 seconds, or about 0.5 seconds to about 5 seconds, the controller 302 allows the host to send a write command to write data to a closed partition. The controller 302 then switches the identified closed partition to the open and active state, and switches the least recently used open partition (e.g., the partition that has not received a write command for the longest amount of time). Thus, the maximum number of parallel partitions in the open and active state is not exceeded. The predetermined amount of time listed above and the maximum number of partitions in the open and active state are not intended to be limiting, but rather provide examples of possible implementations.

[0062] Switching between the open state and the closed or resource-sparing lower performance internal state for a partition requires ZNS, as discussed in Figure 3A The maximum number of open and active partitions of the NVM 306 can be equal to the number of SRAM 308 temporary buffer locations. If an interrupt is received that is associated with a current write command for an open partition or a write command with a higher priority than the current write command, or if the predetermined amount of time has expired or elapsed, the controller 302 can swap the active and open partition to a closed partition.

[0063] Generally, as further discussed below, a command to write data to a partition is received by the controller 302, and the XOR engine 304 generates parity data for the command in the temporary SRAM area 310a-310n. At the same time, if previous parity data for the partition exists in the DRAM 312, the previous parity data is copied to the SRAM area 310a-310f (e.g., data can be stored in a non-temporary SRAM area for a long period of time). Once the previous parity data is in the SRAM area 310a-310f, the previous parity data is updated with the new parity data stored in the temporary SRAM area 310n-4-310n. The updated parity data is then copied from the SRAM 308 to the DRAM area 314a-314n.

[0064] The data transfer rate from DRAM regions 314a-314n to SRAM regions 310a-310n can be slower than the write rate from XOR engine 304 to the temporary buffer of SRAM 308, or vice versa. The amount of space in the temporary buffer and the amount of time used to perform the following operations determine the maximum number of open and active partitions: generating new parity data for write commands in the temporary buffer locations of SRAM 308, copying previous parity data from DRAM 312 to SRAM 308, updating previous parity data with new parity data in SRAM 308, and switching partitions from open and active states to closed or resource-saving, lower-performance internal states. Therefore, the amount of time required to perform the following operations can be proportionally matched to the amount of time spent switching a partition from an open and active state to a closed or resource-saving, lower-performance internal state: generating new parity data for a write command in the temporary buffer location of SRAM 308, copying previous parity data from DRAM 312 to SRAM 308, and / or updating the previous parity data with the new parity data in SRAM 308. In the embodiment described herein, the temporary buffer consists of five SRAM regions 310n-4-310n, and the maximum number of open and active partitions is five.

[0065] like Figure 3A As shown, after receiving one or more commands to write data to the second partition and the fifth partition, new parity data for the second partition W02* and the fifth partition W05* are written to the second temporary SRAM area 310n-3 and the fifth temporary SRAM area 310n, respectively. Figure 3A The updated parity or parity data for the second partition W02' is also shown, stored in both SRAM 308 and DRAM 312. In other words, the previous parity data for the second partition is updated with the new parity data for the second partition W02* in SRAM 308 and copied to DRAM 312 as the updated second parity or parity data W02'. After updating the previous parity data for the partition, the new parity data for that partition can be erased from the temporary SRAM area. Therefore, the updated parity or parity data for the first partition W01' is stored in the first SRAM area 310a and DRAM 312; however, the corresponding new parity data for the first partition has been erased from the temporary SRAM area (e.g., the first temporary SRAM area 310n-4).

[0066] When controller 302 receives a first write command to write data to the third partition, XOR engine 304 writes new parity data associated with the third partition W03* for the first write command to the third temporary SRAM region 310n-2 or a first temporary buffer location available. Controller 302 simultaneously copies previous parity data for the third partition W03 from DRAM region 314c to an available SRAM region 310c, as shown by the arrow between 314c and 310c. Figure 3A

[0067] When controller 302 receives a second write command to write data to the fourth partition, XOR engine 304 writes new parity data associated with the fourth partition W04* for the second write command to the fourth SRAM region 310n-1 or a first temporary buffer location available. Controller 302 simultaneously copies previous parity data for the fourth partition W04 from DRAM region 314d to an available SRAM region 310d, as shown by the arrow between 314d and 310d. Thus, as shown by Figure 3A Figure 3B the first partition through the fifth partition are currently in an open and active state. Because the first partition through the fifth partition are currently in an open and active state, the host can send the host’s desired number of commands to write data to the first partition through the fifth partition at the host’s desired speed and order.

[0068] In Figure 3B the previous parity data associated with the third partition W03 is updated with the new parity associated with the third partition W03* to updated third parity data W03’ in the third SRAM region 310c. After the previous parity data for the third partition W03’ is updated with the new parity data for the first write command, the new parity data associated with the third partition W03* for the first command can be erased from the third temporary SRAM region 310n-2. The previous parity data for a partition can be updated in any of the SRAM regions 310a-310n.

[0069] ​​The previous parity data associated with the fourth partition W04 is updated with the new parity associated with the fourth partition W04* to updated fourth parity data W04' in the fourth SRAM region 310d. After the previous parity data for the fourth partition W04' is updated with the new parity data for the second write command, the new parity data associated with the fourth partition W04* for the second command can be erased from the fourth temporary SRAM region 310n-1 or the available first temporary buffer location. At the same time, the updated parity data associated with the fifth partition W05' stored in the fifth SRAM region 310e is copied to the fifth DRAM region 314e as fifth updated parity data W05'.

[0070] The controller 302 then receives a third write command to write data to a closed sixth partition. Since the open state and the maximum number of active partitions (i.e., the first partition through the fifth partition) are currently satisfied, the controller 302 closes the first partition because the first partition is the least recently used partition, the third write command is received to write to a closed partition, and a predetermined amount of time has expired since the last time the state of a partition was switched. After closing the first partition (i.e., switching the first partition to the resource-sparing lower performance internal state), the parity data associated with the first partition can be erased from the SRAM 308. The XOR engine 304 generates parity data for the third command associated with the sixth partition W06* and writes the generated parity data associated with the sixth partition W06* to the first temporary SRAM region 310n-4 or the available first temporary buffer location. If previous parity data associated with the sixth partition is stored in the DRAM 312, then this previous parity data associated with the sixth partition is copied from the DRAM 312 to the SRAM 308.

[0071] If the parity data stored in the temporary SRAM area 310n-4-310n has not been erased, the fourth write command received by the controller 302 to write data to the closed seventh zone can be held in a buffer (not shown) within the controller 302 until the temporary SRAM area 310n-4-310n is available. After a predetermined amount of time of about 0.5 seconds to about 5 seconds has elapsed, the controller switches the least recently used zone, which is the second zone, from the open and active state to the closed or resource-conserving lower performance internal state and switches the seventh zone to the open and active state. After closing the second zone, the parity data associated with the second zone can be erased from the SRAM 308. New parity data associated with the seventh zone W07* for the fourth command is generated by the XOR engine 304 and written to the second temporary SRAM area 310n-3. If previous parity data associated with the seventh zone is stored in the DRAM 312, then this previous parity data associated with the seventh zone is copied from the DRAM 312 to the SRAM 308.

[0072] Thus, as shown, the third zone to the seventh zone are currently in the open and active state. Since the third zone to the seventh zone are currently in the open and active state, the host can send the host's desired number of commands to write data to the third zone to the seventh zone at the host's desired speed and order. Figure 3C

[0073] In the example shown in FIG. 6, the first zone W01* to the seventh zone W07* are in the open and active state. The first zone W01* to the seventh zone W07* are in the open and active state because the first zone W01* to the seventh zone W07* have not been closed. The first zone W01* to the seventh zone W07* have not been closed because the host has not sent a command to close the first zone W01* to the seventh zone W07*. Figure 3D

[0074] ​​The previous parity data associated with the seventh partition W07 is updated with the corresponding new parity data W07* to updated seventh parity data W07' in the second SRAM region 310b. After the previous parity data for the seventh partition W07' is updated with the new parity data for the fourth write command, the new parity data associated with the seventh partition W07* for the fourth command can be erased from the second temporary SRAM region 310n-3. The new parity data associated with the sixth partition W06* or the new parity data associated with the seventh partition W07* can be moved to any non-temporary SRAM region (e.g., SRAM regions 310a-310f) if the previous parity data for the sixth partition or the seventh partition or the sixth partition does not already exist.

[0075] In Figure 3D The controller 302 receives a fifth write command to write data to the first partition. Since the first partition was previously switched to the closed or resource-conserving lower performance internal state, the controller 302 switches the least recently used partition that is currently in the open and active state (i.e., the third partition) to the closed or resource-conserving lower performance internal state after a predetermined amount of time has passed since the last time the state of a partition was switched. The controller 302 then switches the first partition from the closed or resource-conserving lower performance internal state to the open and active state. The XOR engine 304 generates new parity data associated with the first partition W01* for the fifth write command and writes the new parity data to the third SRAM region 310n-2 or to a first temporary buffer location that is available. At the same time, the previous parity data associated with the first partition W01' is copied from the DRAM 312 to the third SRAM region 310c.

[0076] The controller 302 receives a sixth write command to write data to the second partition. Since the second partition was previously switched to the closed or resource-conserving lower performance internal state, the controller 302 switches the least recently used partition that is currently in the open and active state (i.e., the fourth partition) to the closed or resource-conserving lower performance internal state after a predetermined amount of time has passed since the last time the state of a partition was switched. The controller 302 then switches the second partition from the closed or resource-conserving lower performance internal state to the open and active state.

[0077] If the predetermined amount of time has not expired since switching the third partition to the closed or resource-sparing lower performance internal state and switching the first partition to the open and active state, the controller 302 will wait until the predetermined amount of time has passed or expired before closing the fourth partition and reopening the second partition. The XOR engine 304 generates new parity data associated with the second partition W02' for the sixth command and writes the new parity data to the fourth temporary SRAM region 310n-1 or the first temporary buffer location available. At the same time, the previous parity data associated with the second partition W02' is copied from the DRAM 312 to the fourth SRAM region 310d.

[0078] Thus, when a new write command to write data to a previously closed partition is received, the controller 302 opens the partition so that the new write command can be written to the partition. However, if the maximum number of open and active partitions has been reached, the controller 302 will wait until the predetermined amount of time has passed before changing the least recently used partition to the closed or resource-sparing lower performance internal state. After changing the least recently used partition to the closed or resource-sparing lower performance internal state, the controller 302 can then change the relevant partition to the open and active state. Since it takes time to copy data to the SRAM 308 and to copy data from the SRAM to the DRAM 312, the maximum number of open and active partitions is selected to minimize any write latency.

[0079] The updated parity data associated with the sixth partition W06' is copied to an available DRAM region, such as the sixth DRAM region 314f. The updated parity data associated with the seventh partition W07' is copied to an available DRAM region, such as the DRAM region 314n-4. Thus, as shown, the first partition, the second partition, the fifth partition, the sixth partition, and the seventh partition are currently in the open and active state. Since the first partition, the second partition, the fifth partition, the sixth partition, and the seventh partition are currently in the open and active state, the host can send the host desired number of commands to write data to the first partition, the second partition, the fifth partition, the sixth partition, and the seventh partition at the host desired speed and order. Figure 4

[0080] Figure 4 A diagram 400 illustrating updating in-flight data, such as parity data, in a storage device over time is shown, in accordance with one embodiment. Figure 1 The storage device can be Figure 1 ​to the storage device 106. As in the above example, parity data will be used as an example of in-flight data. The times used below are representative and can occur within seconds or minutes. The write commands for the first partition are shown as horizontal striped blocks, the write commands for the second partition are shown as vertical striped blocks, the write commands for the third partition are shown as upward diagonal striped blocks, and the write commands for the fourth partition are shown as downward diagonal striped blocks. For example, the first write command 434 is to write data to the first partition, the second write command 442 is to write data to the second partition, and the third write command 450 is to write data to the third partition. The fourth write command 450a is to write data to the fourth partition, and the fourth write command 450b is to write data to the first partition.

[0081] In the current implementation, the controller includes three available controller RAM or buffer regions 404a, 404b, 404c for storing host write commands and three available parity RAM or buffer regions 406a, 406b, 406c for storing parity data. The controller buffer regions 404a, 404b, 404c and the parity buffer regions 406a, 406b, 406c can be any of the SRAM regions of the 122a-122n of the storage device 106. The controller buffer regions 404a, 404b, 404c store data that has not yet been written to the NVM. The storage device also includes four available RAM regions 408a, 408b, 408c, 408d for parity data storage, with each region corresponding to a partition, such that the first RAM region 408a corresponds to the first partition, the second RAM region 408b corresponds to the second partition, the third RAM region 408c corresponds to the third partition, and the fourth RAM region 408d corresponds to the fourth partition. The number of regions listed above for each component is not intended to be limiting, but rather to provide an example of a possible implementation. ​

[0082] At time 1, the controller receives a first host write command 402 to write data to the first partition. The first host write command 402 is temporarily stored in the first controller buffer region 404a. Prior to or during writing the data for the first host write command 402 to the NVM for the first partition, the XOR engine 124 generates first parity data for the first host write command 402 in the parity buffer region 406a for the first partition.

[0083] ​At time 2, the controller receives a second host write command 410 to write data to the second partition. The second host write command 410 is temporarily stored in the second controller buffer area 404b. Prior to or during writing the data for the second host write command 410 to the NVM for the second partition, the XOR engine 124 generates second parity data for the second host write command 410 in the parity buffer area 406b.

[0084] At time 3, the controller receives a third host write command 418 to write data to the third partition. The third host write command 418 is temporarily stored in the third controller buffer area 404c. Prior to or during writing the data for the third host write command 418 to the NVM for the third partition, the XOR engine 124 generates third parity data for the third host write command 418 in the parity buffer area 406c.

[0085] At time 4a, the controller receives a fourth host write command 426a to write data to the fourth partition. The data for the fourth host write command 426a is written to the first controller buffer area 404a. From time 1 to time 3, previous write commands stored in the first controller buffer area 404a, such as the first host write command 402, have been successfully written to the NVM, and the data in the first controller buffer area 404a can be overwritten by the data of the new host write command, such as the fourth host write command 426a. The first parity data for the first host write command 402 is then written to the RAM area 408a, and the XOR engine 124 generates fourth parity data for the fourth host write command 426a in the parity buffer area 406a. If a fifth host write command to write data to the first partition is received, the first parity data will be copied back from the RAM area 408a to the parity buffer area 406a-406c.

[0086] However, if the controller receives a fourth host write command for a partition that has previously been written to, such as fourth host write command 426b to write data to the first partition, at time 4b, the data of the fourth host write command 426b is written to the first controller buffer area 404a. From time 1 to time 3, the data previously stored in the first controller buffer area 404a (e.g., first host write command 402) has successfully been written to the NVM. However, if the data of the previous write command is still being written to the NVM, the fourth host write command 426b is temporarily held in the controller buffer (e.g., temporary SRAM areas 310n-4 through area 310n) until the transmission to the NVM has completed. The XOR engine 124 then generates fourth parity data for the fourth host write command 426b in the parity buffer area 406a. Thus, the parity buffer area 406a includes both the first parity data for the first host write command 402 and the fourth parity data for the fourth host write command 426b.

[0087] During time 4b, because the parity buffer area 406a is still storing the first parity data for the first host write command 402 to the first partition, the controller is able to update the parity data for the first partition to include the parity data of the fourth host write command 426b without delay, unlike during time 4a. Furthermore, by waiting until the next host write command is received before copying the data from the parity buffer to the RAM area, the data can be copied to the parity buffer area and from the parity buffer area to the RAM area fewer times. Because it takes time to transfer data to and from the parity buffer area, waiting to copy the data from the parity buffer area to the RAM area allows the storage device to work in a faster and more efficient manner.

[0088] By setting the maximum number of open and active partitions based on the amount of time it takes to copy the relevant data to and from the DRAM area, write the parity data associated with the write command to a temporary buffer location in the SRAM, and update the previous parity data associated with the partition, the efficiency of the memory device can be improved. Because the host can send unlimited write commands to write data to the open and active partitions without delay, the maximum number of open and active partitions is selected to minimize any write delay. Because SRAM is fast but more expensive and DRAM is slower but less expensive, the use of both DRAM and SRAM is better optimized, reducing any DRAM access penalty.

[0089] Accordingly, by basing the maximum number of open partitions on one or more of the following quantities: the amount of time to generate new parity data for a write command in a temporary buffer location that is SRAM, the amount of time to copy previous parity data from DRAM to SRAM, the amount of time to update previous parity data with new parity data in SRAM, the amount of time to switch a partition from an open and active state to a closed or resource- saving lower performance internal state, and the amount of space in the temporary buffer, the storage device can operate in the fastest, smoothest, and most efficient manner. Furthermore, by limiting the host from opening new partitions only after a predetermined amount of time has passed, the storage device has sufficient time to copy data to DRAM and copy data from DRAM to SRAM, thereby further eliminating latency for write commands.

[0090] In one embodiment, a storage device includes a non-volatile storage unit, where a capacity of the non-volatile storage unit is divided into a plurality of partitions. The non-volatile storage unit includes a plurality of dies, and each die of the plurality of dies includes a plurality of erase blocks. The storage device also includes a first volatile memory unit and a controller coupled to the non-volatile storage unit and the first volatile memory unit. The controller includes a second volatile memory unit, where the controller is configured to set a maximum number of open and active partitions, and receive one or more first commands to write data to one or more open and active partitions of the plurality of partitions. The controller is further configured to receive one or more second commands to write data to a first partition, where the first partition is in a closed or resource-saving lower performance internal state, change a least recently used open and active partition to the closed or resource-saving lower performance internal state, and change the first partition to an open and active state.

[0091] The controller is further configured to determine which open and active partition is least recently used prior to changing the least recently used open and active partition to a closed or resource saving lower performance internal state. The maximum number of open and active partitions is determined based on an amount of time it takes to change the least recently used partition to a closed or resource saving lower performance internal state and to change the first partition to an open and active state. The controller is further configured to change the least recently used partition to a closed or resource saving lower performance internal state and to change the first partition to an open and active state after a predetermined amount of time has expired. The second volatile memory is an SRAM cell and the first volatile memory is a DRAM cell, and wherein the SRAM cell includes one or more temporary locations for generating new parity data for the received one or more first commands and the received one or more second commands. The maximum number of open and active partitions is determined based on a number of temporary locations in the SRAM cell. The controller is further configured to generate new first parity data for the first partition in a first temporary location in the SRAM cell; copy previous first parity data for the first open and active partition from the DRAM cell to the first location in the SRAM cell when the new first parity data is generated; update the previous first parity data with the new first parity data in the SRAM cell; and copy the updated first parity data from the SRAM cell to the DRAM cell when a controller buffer area of the SRAM cell is filled to capacity, the controller buffer area temporarily storing data to be written to the non-volatile memory cell. The maximum number of open and active partitions is further determined based on an amount of time it takes to generate the new first parity data, to copy the previous first parity data, and to update the previous first parity data.

[0092] In another embodiment, a storage device includes a non-volatile storage unit, where a capacity of the non-volatile storage unit is divided into a plurality of zones. The non-volatile storage unit includes a plurality of dies, and each of the plurality of dies includes a plurality of erase blocks. The storage device also includes a first volatile memory unit and a controller coupled to the non-volatile storage unit and the first volatile memory unit. The controller includes a second volatile memory unit, where the controller is configured to: set a maximum number of open and active zones; receive one or more commands to write data to one or more open and active zones of the plurality of zones; and generate new first parity data for a first open and active zone in a temporary location of one or more temporary locations in the second volatile memory unit. The controller is further configured to copy previous first parity data for the first open and active zone from the first volatile memory unit to a first location in the second volatile memory unit. The controller is also configured to update the previous first parity data with the new first parity data in the second volatile memory unit, where an amount of time taken to generate the new first parity data, copy the previous first parity data, and update the previous first parity data determines the maximum number of open and active zones.

[0093] The controller is further configured to: after receiving one or more second commands to write data to a second zone, determine that the first open and active zone is a least recently used zone of the open and active zones, where the second zone is in a closed or resource-saving lower-performance internal state; change the first open and active zone to the closed or resource-saving lower-performance internal state; and change the second zone to an open and active state. The maximum number of open and active zones is determined based on an amount of time taken to change the first zone to the closed or resource-saving lower-performance internal state and to change the second zone to the open and active state. The controller is further configured to change the least recently used zone to the closed or resource-saving lower-performance internal state only after a predetermined amount of time has expired. The controller includes one or more controller buffer regions, and the received one or more commands to write data to the one or more open and active zones of the plurality of zones fills a capacity of the one or more controller buffer regions. The maximum number of open and active zones is determined based on a number of temporary locations in the second volatile memory unit. The second volatile memory is an SRAM unit and the first volatile memory is a DRAM unit.

[0094] In another embodiment, a storage device includes a non-volatile storage unit, where a capacity of the non-volatile storage unit is divided into a plurality of zones. The non-volatile storage unit includes a plurality of dies, and each of the plurality of dies includes a plurality of erase blocks. The storage device also includes a first volatile memory unit and a controller coupled to the non-volatile storage unit and the first volatile memory unit. The controller includes a second volatile memory unit, where the second volatile memory includes one or more temporary locations. The controller is configured to: set a maximum number of open and active zones, where the maximum number of open and active zones is determined based on a number of temporary locations in the second volatile memory; and receive one or more first commands to write data to one or more open and active zones of the plurality of zones. The controller is further configured to: generate new first parity data for a first open and active zone in a first temporary location in the second volatile memory unit; change a second open and active zone to a closed or resource-saving lower-performance internal state upon receiving one or more second commands to write data to a closed zone; and change the closed zone to an open and active state.

[0095] The controller is further configured to, upon generating the new first parity data, copy previous first parity data for the first open and active zone from the first volatile memory unit to the first location in the second volatile memory unit. The controller is also configured to update the previous first parity data with the new first parity data in the second volatile memory unit. The maximum number of open and active zones is further determined based on an amount of time taken to generate the new first parity data, copy the previous first parity data, and update the previous first parity data, and an amount of time taken to change the second open and active zone to the closed or resource-saving lower-performance internal state and change the closed zone to the open and active state. The controller is further configured to determine that the second open and active zone is a least recently used open and active zone. The controller is further configured to change open and active zones to the closed or resource-saving lower-performance internal state after a predetermined amount of time has expired, where the predetermined amount of time is about 0.5 seconds to about 5 seconds, and where the maximum number of open and active zones is further determined based on the predetermined amount of time.

[0096] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure can be devised without departing from the basic scope thereof, and the scope of the present disclosure is determined by the appended claims.

Claims

1. A storage device, the storage device comprising: A non-volatile memory cell, wherein the capacity of the non-volatile memory cell is divided into multiple partitions, and wherein the non-volatile memory cell includes multiple dies, each of the multiple dies including multiple erase blocks; First volatile memory unit; and A controller, coupled to the non-volatile memory cell and the first volatile memory cell, the controller including a second volatile memory cell, wherein the controller is configured to: Set the maximum number of open and active partitions; Receive one or more first commands to write data to one or more open and active partitions among the plurality of partitions; Receive one or more second commands to write data to a first partition, wherein the first partition is in a closed or resource-saving low-performance internal state; Change the least recently used open and active partitions to the closed or resource-saving, lower-performance internal state; and Change the first partition to an open and active state.

2. The storage device of claim 1, wherein the controller is further configured to determine which open and active partition is least recently used before changing the least recently used open and active partitions to the closed or resource-saving lower performance internal state.

3. The storage device of claim 1, wherein the maximum number of open and active partitions is determined based on the amount of time taken to change the least recently used partition to the closed or resource-saving low-performance internal state and to change the first partition to the open and active state.

4. The storage device of claim 1, wherein the controller is further configured to, after a predetermined amount of time has elapsed, change the least recently used partition to the closed or resource-saving low-performance internal state and change the first partition to the open and active state.

5. The storage device of claim 1, wherein the second volatile memory is an SRAM cell and the first volatile memory is a DRAM cell, and wherein the SRAM cell includes one or more temporary locations for generating new parity data for one or more received first commands and one or more received second commands.

6. The storage device of claim 5, wherein the maximum number of open and active partitions is determined based on the number of temporary locations in the SRAM cells.

7. The storage device of claim 6, wherein the controller is further configured to: A new first parity check data for the first partition is generated in a first temporary location in the SRAM cell; When generating the new first parity data, the previous first parity data for the first partition is copied from the DRAM cell to a first location in the SRAM cell; The previous first parity data is updated with the new first parity data in the SRAM cell; as well as When the controller buffer area of ​​the SRAM cell is full, the updated first parity data is copied from the SRAM cell to the DRAM cell, and the controller buffer area temporarily stores the data to be written to the non-volatile memory cell.

8. The storage device of claim 7, wherein the maximum number of open and active partitions is further determined based on the amount of time spent generating the new first parity data, copying the previous first parity data, and updating the previous first parity data.

9. A storage device, the storage device comprising: A non-volatile memory cell, wherein the capacity of the non-volatile memory cell is divided into multiple partitions, and wherein the non-volatile memory cell includes multiple dies, each of the multiple dies including multiple erase blocks; First volatile memory unit; and A controller, coupled to the non-volatile memory cell and the first volatile memory cell, the controller including a second volatile memory cell, wherein the controller is configured to: Set the maximum number of open and active partitions; Receive one or more commands to write data to one or more open and active partitions among the plurality of partitions; Generate new first parity data for the first open and active partition in a temporary location in one or more temporary locations in the second volatile memory cell; The previous first parity data for the first open and active partitions is copied from the first volatile memory cell to a first location in the second volatile memory cell; as well as The new first parity data in the second volatile memory cell is used to update the previous first parity data, wherein the amount of time spent generating the new first parity data, copying the previous first parity data, and updating the previous first parity data determines the maximum number of open and active partitions.

10. The storage device of claim 9, wherein the controller is further configured to: Upon receiving one or more second commands to write data to the second partition, it is determined that the first open and active partition is the least recently used partition among the open and active partitions, and the second partition is in a closed or resource-saving low-performance internal state. Change the first open and active partition to the closed or resource-saving, lower-performance internal state; and Change the second partition to an open and active state.

11. The storage device of claim 10, wherein the maximum number of open and active partitions is determined based on the amount of time spent changing the first open and active partition to the closed or resource-saving lower performance internal state and changing the second partition to the open and active state.

12. The storage device of claim 10, wherein the controller is further configured to change the least recently used partition to the shut-down or resource-saving lower-performance internal state only after a predetermined amount of time has expired.

13. The storage device of claim 10, wherein the controller includes one or more controller buffer regions, and wherein one or more commands received for writing data to the one or more open and active partitions of the plurality of partitions fill the capacity of the one or more controller buffer regions.

14. The storage device of claim 9, wherein the maximum number of open and active partitions is determined based on the number of temporary locations in the second volatile memory cell.

15. The storage device of claim 9, wherein the second volatile memory is an SRAM cell and the first volatile memory is a DRAM cell.

16. A storage device, the storage device comprising: A non-volatile memory cell, wherein the capacity of the non-volatile memory cell is divided into multiple partitions, and wherein the non-volatile memory cell includes multiple dies, each of the multiple dies including multiple erase blocks; First volatile memory unit; and A controller coupled to the non-volatile memory cell and the first volatile memory cell, the controller including a second volatile memory cell, the second volatile memory including one or more temporary locations, wherein the controller is configured to: Set a maximum number of open and active partitions, wherein the maximum number of open and active partitions is determined based on the number of temporary locations in the second volatile memory; Receive one or more first commands to write data to one or more open and active partitions among the plurality of partitions; A new first parity check data for the first open and active partition is generated in a first temporary location in the second volatile memory cell; Upon receiving one or more second commands to write data to the closed partition, the second open and active partitions are changed to a closed or resource-saving, lower-performance internal state. as well as Change the closed partition to an open and active state.

17. The storage device of claim 16, wherein the controller is further configured to: When generating the new first parity data, the previous first parity data for the first open and active partitions is copied from the first volatile memory cell to a first location in the second volatile memory cell; and The previous first parity data is updated using the new first parity data in the second volatile memory cell.

18. The storage device of claim 17, wherein the maximum number of open and active partitions is further determined based on the amount of time spent generating the new first parity data, copying the previous first parity data, and updating the previous first parity data, and the amount of time spent changing the second open and active partitions to the closed or resource-saving lower performance internal state and changing the closed partitions to the open and active state.

19. The storage device of claim 16, wherein the controller is further configured to determine that the second open and active partition is the least recently used open and active partition.

20. The storage device of claim 16, wherein the controller is further configured to change open and active partitions to the closed or resource-saving lower performance internal state after a predetermined amount of time has expired, wherein the predetermined amount of time is 0.5 seconds to 5 seconds, and wherein the maximum number of open and active partitions is further determined based on the predetermined amount of time.

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