Display substrate and display device

Abstract

Provided are a display substrate and a display device. The display substrate includes a plurality of repeating units, and at least one of the plurality of repeating units includes a plurality of sub-pixels. Each sub-pixel includes: a pixel circuit having a driving transistor, a light-emitting element having an anode, and an anode connection portion, wherein the anode includes a main portion and an auxiliary portion that are electrically connected to each other. The plurality of sub-pixels include a first sub-pixel and a second sub-pixel. In the first sub-pixel, the orthographic projection of the anode connection portion (YZ1) on the substrate does not overlap with the orthographic projection of the driving active layer on the substrate, and the orthographic projection of the main portion (Y11) of the anode on the substrate does not overlap with the orthographic projection of the anode connection portion (YZ1) on the substrate; in the second sub-pixel, the orthographic projection of the anode connection portion (YZ2) on the substrate overlaps with the orthographic projection of the driving active layer on the substrate, and the orthographic projection of the main portion (Y21) of the anode on the substrate overlaps with the orthographic projection of the anode connection portion (YZ2) on the substrate.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of display technologies, and particularly to a display substrate and a display device. Background Art

[0002] With the continuous development of display technologies, organic light-emitting diode (OLED) display substrates have been increasingly applied to various electronic devices due to their advantages such as self-luminescence, wide viewing angle, high contrast ratio, low power consumption, and high response speed. With the increasing requirements for OLED display substrates, in order to achieve a high-resolution design in the display substrate, the OLED display substrate usually adopts an SPR pixel arrangement, that is, a pixel borrowing method. Summary of the Invention

[0003] The display substrate provided by the embodiments of the present disclosure includes:

[0004] A plurality of sub-pixels, at least one of the plurality of sub-pixels includes: a pixel circuit and a light-emitting element located on a substrate, the pixel circuit includes a driving transistor for driving the light-emitting element to emit light;

[0005] The display substrate includes an active semiconductor layer; the driving active layer of the driving transistor is located in the active semiconductor layer;

[0006] The driving gate in the driving transistor is electrically connected to the active semiconductor layer through a driving via;

[0007] A first conductive layer, located on a side of the active semiconductor layer away from the substrate, and the first conductive layer includes an anode transfer portion and a signal line arranged at intervals;

[0008] In the sub-pixel, at least a part of the projection of the driving via on the substrate does not overlap with the projections of the anode transfer portion and the signal line on the substrate.

[0009] In some examples, the display substrate further includes:

[0010] A first insulating layer, located on a side of the first conductive layer away from the substrate, and the first insulating layer includes a first via exposing at least a part of the anode transfer portion;

[0011] The light-emitting element includes an anode, the anode is located on a side of the first insulating layer away from the substrate, and the anode includes a main body portion and an auxiliary portion that are electrically connected to each other; wherein, the auxiliary portion is electrically connected to the anode transfer portion through the first via;

[0012] Wherein, the plurality of sub-pixels include a first sub-pixel and a second sub-pixel;

[0013] In the first sub-pixel, the orthographic projection of the anode transition portion on the base substrate does not overlap with the orthographic projection of the driving active layer on the base substrate, and the orthographic projection of the main body portion on the base substrate does not overlap with the orthographic projection of the anode transition portion on the base substrate;

[0014] In the second sub-pixel, the orthographic projection of the anode transition portion on the base substrate overlaps with the orthographic projection of the driving active layer on the base substrate, and the orthographic projection of the main body on the base substrate overlaps with the orthographic projection of the anode transition portion on the base substrate.

[0015] In some examples, the anode transition portion in the second sub-pixel includes: a first sub-anode transition portion and a second sub-anode transition portion electrically connected to each other; wherein the first sub-anode transition portion has a hollow structure, and the second sub-anode transition portion has a solid structure; the auxiliary portion is electrically connected to the second sub-anode transition portion through the first via hole;

[0016] In the second sub-pixel, an orthographic projection of the first sub-anode transition portion on the base substrate overlaps with an orthographic projection of the driving active layer on the base substrate.

[0017] In some examples, the display substrate further includes: a gate conductive layer located between the active semiconductor layer and the first conductive layer, the gate conductive layer including: a scan line;

[0018] In the direction parallel to the base substrate, in the same second sub-pixel, the orthographic projection of the scanning line on the base substrate is located on the side where the orthographic projection of the driving active layer on the base substrate is away from the orthographic projection of the second sub-anode transition portion on the base substrate;

[0019] In the second sub-pixel, an orthographic projection of the first sub-anode transfer portion on the base substrate overlaps with an orthographic projection of the scan line on the base substrate.

[0020] In some examples, in the second sub-pixel, an orthographic projection of a hollow region in the hollow structure in the first sub-anode transition portion on the base substrate overlaps with an orthographic projection of the driving via on the base substrate.

[0021] In some examples, the first sub-anode transition portion has a first sub-transition portion and a second sub-transition portion that are disposed opposite to each other;

[0022] In the second sub-pixel, the orthographic projection of the main body portion on the substrate overlaps with the orthographic projections of the two signal lines on the substrate; and in the first direction, the orthographic projection of the first sub-transfer portion on the substrate is located between the orthographic projection of the second sub-transfer portion and the orthographic projections of the two signal lines on the substrate.

[0023] In some examples, at least one of the plurality of repeating units includes: a first color sub-pixel, a second color sub-pixel, a third color sub-pixel, and a fourth color sub-pixel; wherein, the plurality of repeating units are arranged in a first direction to form a repeating unit group, the repeating unit group is arranged in a second direction, and the first direction is different from the second direction;

[0024] The first sub-pixel includes the first color sub-pixel;

[0025] The second sub-pixel includes at least one of a second color sub-pixel, a third color sub-pixel, and the fourth color sub-pixel.

[0026] In some examples, the second sub-pixel includes the second color sub-pixel;

[0027] In the second color sub-pixel, the orthographic projection of the main body portion on the substrate overlaps with the orthographic projection of the first sub-anode transfer portion on the substrate.

[0028] In some examples, in the second color sub-pixel, the orthographic projection of the main body portion on the substrate overlaps with the orthographic projections of both the first sub-transfer portion and the second sub-transfer portion on the substrate.

[0029] In some examples, the main body portion in the second color sub-pixel has a second main symmetry axis along the second direction;

[0030] In the second color sub-pixel, the center line along the second direction of the overlapping portion of the two signal lines with the orthographic projection of the main body portion on the substrate and the center lines of the first sub-transfer portion and the second sub-transfer portion along the first direction are respectively located on opposite sides of the second main symmetry axis.

[0031] In some examples, the second sub-pixel includes the fourth color sub-pixel;

[0032] In the fourth color sub-pixel, the orthographic projection of the main body portion on the substrate overlaps with the orthographic projection of the second sub-anode transfer portion on the substrate, and the orthographic projection of the main body portion on the substrate overlaps with the orthographic projections of the two signal lines on the substrate.

[0033] In some examples, in the second direction, in the fourth color sub-pixel, at least a part of the main body portion is orthogonally projected onto the substrate and is located on a side of the orthographic projection of the second sub-anode transfer portion onto the substrate away from the orthographic projection of the first sub-anode transfer portion onto the substrate.

[0034] In some examples, the main body portion in the fourth color sub-pixel has a fourth main body symmetry axis along the second direction;

[0035] In the fourth color sub-pixel, the center lines along the second direction of the overlapping portions of the two signal lines and the main body portion on the substrate are respectively located on opposite sides of the fourth main body symmetry axis from the center line of the second sub-anode transfer portion along the second direction.

[0036] In some examples, each of the signal lines further includes a signal protrusion portion; the multiple signal lines include a first signal line and a second signal line; wherein, one column of sub-pixels corresponds to one first signal line and one second signal line; the signal protrusion portions of the first signal line are respectively electrically connected to odd-row sub-pixels, and the signal protrusion portions of the second signal line are respectively electrically connected to even-row sub-pixels;

[0037] The second color sub-pixel and the fourth color sub-pixel in adjacent repeating units along the second direction are adjacent along the second direction;

[0038] Along the second direction, the orthographic projection of the main body portion in the fourth color sub-pixel onto the substrate overlaps with the orthographic projection of the signal protrusion portion in the adjacent second color sub-pixel onto the substrate.

[0039] In some examples, each of the signal lines further includes a signal protrusion portion; the multiple signal lines include a first signal line and a second signal line; wherein, one column of sub-pixels corresponds to one first signal line and one second signal line; the signal protrusion portions of the first signal line are respectively electrically connected to odd-row sub-pixels, and the signal protrusion portions of the second signal line are respectively electrically connected to even-row sub-pixels;

[0040] Among the two first signal lines and the two second signal lines corresponding to two adjacent columns of sub-pixels, two of the first signal lines are adjacent to form a first signal line group, or two of the second signal lines are adjacent to form a second signal line group.

[0041] In some examples, the area of the orthographic projection of the second sub-anode transfer portion in one fourth color sub-pixel onto the substrate is larger than the area of the orthographic projection of the second sub-anode transfer portion in one second color sub-pixel onto the substrate.

[0042] In some examples, the second sub-anode transfer portion in the second color sub-pixel has a second width along the second direction in the orthographic projection on the substrate, and the second sub-anode transfer portion in the fourth color sub-pixel has a fourth width along the second direction in the orthographic projection on the substrate; the fourth width is greater than the second width.

[0043] In some examples, the second sub-pixel includes the third color sub-pixel;

[0044] In the third color sub-pixel, the orthographic projection of the main body portion on the substrate overlaps with the orthographic projection of the first sub-anode transfer portion on the substrate, and the orthographic projection of the main body portion on the substrate overlaps with the orthographic projections of the two signal lines on the substrate.

[0045] In some examples, in the third color sub-pixel, the orthographic projection of the main body portion on the substrate overlaps with the orthographic projections of the first sub-transfer portion and the second sub-transfer portion on the substrate.

[0046] In some examples, the main body portion in the third color sub-pixel has a third main body symmetry axis along the second direction;

[0047] In the third color sub-pixel, the center lines along the second direction of the overlapping portions of the two signal lines and the main body portion on the substrate are respectively located on opposite sides of the third main body symmetry axis from the center lines along the second direction of the first sub-transfer portion and the second sub-transfer portion.

[0048] In some examples, in the third color sub-pixel, the orthographic projection of the main body portion on the substrate covers the orthographic projection of the signal protrusion portion on the substrate.

[0049] In some examples, in the third color sub-pixel, the signal protrusion portion is located on a side of the first sub-anode transfer portion away from the second sub-anode transfer portion.

[0050] In some examples, in the first color sub-pixel, the orthographic projection of the main body portion on the substrate overlaps with the orthographic projections of the two signal lines on the substrate, and the orthographic projection of the main body portion on the substrate does not overlap with the orthographic projections of the anode transfer portion and the signal protrusion portion on the substrate.

[0051] In some examples, the main body portion in the first color sub-pixel has a first main body symmetry axis along the second direction;

[0052] In the first color sub-pixel, in the second direction, the two signal lines overlapping with the orthographic projection of the main body portion on the base substrate are respectively located on opposite sides of the first main body symmetry axis.

[0053] In some examples, a ratio of a distance between a first sub-transition portion and a second sub-transition portion in the same first sub-anode transition portion in the first direction to a distance between the two signal lines in the first direction is 0.8 to 1.2.

[0054] In some examples, the signal line is configured as a data line for transmitting a data signal.

[0055] The display device provided by the embodiment of the present disclosure includes the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figure 1 A schematic diagram of the structure of a display substrate provided in an embodiment of the present disclosure;

[0057] Figure 2a A schematic diagram of the structure of some pixel circuits provided in the embodiments of the present disclosure;

[0058] Figure 2b A signal timing diagram provided for an embodiment of the present disclosure;

[0059] Figure 2c A schematic diagram of the structure of some pixel circuits provided in the embodiments of the present disclosure;

[0060] Figure 3 Schematic diagram of the layout structure of some display substrates provided in the embodiments of the present disclosure;

[0061] Figure 4a A schematic diagram of the layout structure of the active semiconductor layer provided in an embodiment of the present disclosure;

[0062] Figure 4b A schematic diagram of the layout structure of the gate conductive layer provided in an embodiment of the present disclosure;

[0063] Figure 4c A schematic diagram of the layout structure of a reference conductive layer provided in an embodiment of the present disclosure;

[0064] Figure 4d A schematic diagram of the layout structure of the source and drain metal layers provided in an embodiment of the present disclosure;

[0065] Figure 4e A schematic diagram of the layout structure of the first conductive layer provided in an embodiment of the present disclosure;

[0066] Figure 4f A schematic diagram of the layout structure of the anode layer provided in an embodiment of the present disclosure;

[0067] Figure 5 Another schematic diagram of the layout structure of the display substrate provided by the embodiments of the present disclosure;

[0068] Figure 6a is Figure 5 A cross-sectional structure schematic diagram along the AA' direction in the shown layout structure schematic diagram;

[0069] Figure 6b is Figure 5 A cross-sectional structure schematic diagram along the BB' direction in the shown layout structure schematic diagram;

[0070] Figure 6c is Figure 5 A cross-sectional structure schematic diagram along the CC' direction in the shown layout structure schematic diagram;

[0071] Figure 6d is Figure 5 A cross-sectional structure schematic diagram along the DD' direction in the shown layout structure schematic diagram. Detailed implementation manners

[0072] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. And, without conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0073] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the ordinary meanings as understood by those of ordinary skill in the art belonging to the field of the present disclosure. The "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. The terms such as "including" or "comprising" mean that the elements or items appearing before this word cover the elements or items listed after this word and their equivalents, without excluding other elements or items. The terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0074] It should be noted that the sizes and shapes of the various figures in the drawings do not reflect the actual proportions, and the purpose is only to schematically illustrate the content of the present disclosure. And, the same or similar reference numerals represent the same or similar elements or elements having the same or similar functions throughout.

[0075] Such as Figure 1As shown, the display substrate provided by the embodiments of the present disclosure may include: a substrate substrate 10. A plurality of repeating units PX located on the substrate substrate 10, at least one repeating unit PX (e.g., each repeating unit) among the plurality of repeating units PX may include a plurality of sub-pixels spx. For example, the plurality of sub-pixels may include a first color sub-pixel spx1, a second color sub-pixel spx2, a third color sub-pixel spx3, and a fourth color sub-pixel spx4. That is, the repeating unit may be made to include the first color sub-pixel spx1, the second color sub-pixel spx2, the third color sub-pixel spx3, and the fourth color sub-pixel spx4. In this way, the display substrate can mix light using the first color sub-pixel spx1, the second color sub-pixel spx2, the third color sub-pixel spx3, and the fourth color sub-pixel spx4 to achieve color display. In some examples, the first color, the second color, the third color, and the fourth color may be selected from red, green, and blue. For example, the first color is red, the second color is green, the third color is blue, and the fourth color is green. Of course, the embodiments of the present disclosure include but are not limited to this. Hereinafter, an example will be described in which the repeating unit includes the first color sub-pixel spx1, the second color sub-pixel spx2, the third color sub-pixel spx3, and the fourth color sub-pixel spx4, and the second color and the fourth color are green, the first color is red, and the third color is blue.

[0076] Exemplarily, in combination with Figure 1 As shown, the plurality of repeating units are arranged in a first direction F1 to form a repeating unit group PXZ, and the repeating unit group PXZ is arranged in a second direction F2. Among them, the first direction F1 is different from the second direction F2. Exemplarily, the first direction F1 is perpendicular to the second direction F2. For example, the first direction F1 is the row direction, and the second direction F2 is the column direction. Or, the first direction F1 is the column direction, and the second direction F2 is the row direction.

[0077] Exemplarily, in combination with Figure 1 and Figure 2a As shown, at least one sub-pixel spx (e.g., each sub-pixel) among the plurality of sub-pixels spx may include: a pixel circuit 0121 and a light-emitting element 0120. Among them, the pixel circuit 0121 has transistors and capacitors, and generates an electrical signal through the interaction of the transistors and capacitors, and the generated electrical signal is input into the anode of the light-emitting element 0120. And by applying a corresponding voltage to the cathode of the light-emitting element 0120, the light-emitting element 0120 can be driven to emit light.

[0078] In combination with Figure 2aAs shown, the pixel circuit 0121 may include: a driving control circuit 0122, a first light-emitting control circuit 0123, a second light-emitting control circuit 0124, a data writing circuit 0126, a storage circuit 0127, a threshold compensation circuit 0128, and a reset circuit 0129.

[0079] The driving control circuit 0122 may include a control terminal, a first terminal, and a second terminal. And the driving control circuit 0122 is configured to provide a driving current for driving the light-emitting element 0120 to emit light to the light-emitting element 0120. For example, the first light-emitting control circuit 0123 is connected to the first terminal of the driving control circuit 0122 and the first voltage terminal VDD. And the first light-emitting control circuit 0123 is configured to connect and conduct or disconnect the connection between the driving control circuit 0122 and the first voltage terminal VDD.

[0080] The second light-emitting control circuit 0124 is electrically connected to the second terminal of the driving control circuit 0122 and the anode of the light-emitting element 0120. And the second light-emitting control circuit 0124 is configured to connect and conduct or disconnect the connection between the driving control circuit 0122 and the light-emitting element 0120.

[0081] The data writing circuit 0126 is electrically connected to the first terminal of the driving control circuit 0122. And the data writing circuit 0126 is configured to write the signal on the data line VD into the storage circuit 0127.

[0082] The storage circuit 0127 is electrically connected to the control terminal of the driving control circuit 0122 and the first voltage terminal VDD. And the storage circuit 0127 is configured to store data signals and information of the driving control circuit 0122.

[0083] The threshold compensation circuit 0128 is electrically connected to the control terminal and the second terminal of the driving control circuit 0122 respectively. And the threshold compensation circuit 0128 is configured to perform threshold compensation on the driving control circuit 0122.

[0084] The reset circuit 0129 is also electrically connected to the control terminal of the driving control circuit 0122 and the anode of the light-emitting element 0120 respectively. And the reset circuit 0129 is configured to reset the anode of the light-emitting element 0120 and reset the control terminal of the driving control circuit 0122.

[0085] Among them, the light-emitting element 0120 can be set as an electroluminescent diode, such as at least one of OLED, QLED, micro LED, and mini OLED. Among them, the light-emitting element 0120 can include an anode, a light-emitting layer, and a cathode arranged in layers. Further, the light-emitting layer can also include film layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. Of course, in practical applications, the light-emitting element 0120 can be designed and determined according to the requirements of the actual application environment, and is not limited herein.

[0086] Exemplarily, in combination with Figure 2a As shown, the drive control circuit 0122 includes: a drive transistor T1. The control end of the drive control circuit 0122 includes the drive gate of the drive transistor T1. The first end of the drive control circuit 0122 includes the first pole of the drive transistor T1. The second end of the drive control circuit 0122 includes the second pole of the drive transistor T1.

[0087] Exemplarily, in combination with Figure 2a As shown, the data writing circuit 0126 includes a data writing transistor T2. The storage circuit 0127 includes a storage capacitor CST. The threshold compensation circuit 0128 includes a threshold compensation transistor T3. The first light emission control circuit 0123 includes a first light emission control transistor T4. The second light emission control circuit 0124 includes a second light emission control transistor T5. The reset circuit 0129 includes an initialization transistor T6 and a reset transistor T7.

[0088] Specifically, the first pole of the data writing transistor T2 is electrically connected to the first pole of the drive transistor T1. The second pole of the data writing transistor T2 is configured to be electrically connected to the data line VD to receive a data signal. The gate of the data writing transistor T2 is configured to be electrically connected to the scan line GA to receive a signal.

[0089] The first pole of the storage capacitor CST is electrically connected to the first power supply terminal VDD. The second pole of the storage capacitor CST is electrically connected to the drive gate of the drive transistor T1.

[0090] The first pole of the threshold compensation transistor T3 is electrically connected to the second pole of the drive transistor T1. The second pole of the threshold compensation transistor T3 is electrically connected to the drive gate of the drive transistor T1. The gate of the threshold compensation transistor T3 is configured to be electrically connected to the scan line GA to receive a signal.

[0091] The first pole of the initialization transistor T6 is configured to be electrically connected to the initialization line VINIT to receive a reset signal. The second pole of the initialization transistor T6 is electrically connected to the drive gate of the drive transistor T1. The gate of the initialization transistor T6 is configured to be electrically connected to the reset line RST to receive a signal.

[0092] The first pole of the reset transistor T7 is configured to be electrically connected to the initialization line VINIT to receive a reset signal. The second pole of the reset transistor T7 is electrically connected to the anode of the light-emitting element 0120. The gate of the reset transistor T7 is configured to be electrically connected to the reset line RST to receive a signal.

[0093] Alternatively, as Figure 2c shown, the first pole of the initialization transistor T6 is configured to be electrically connected to the initialization line VINIT1 to receive a first reset signal. The second pole of the initialization transistor T6 is electrically connected to the driving gate of the driving transistor T1. The gate of the initialization transistor T6 is configured to be electrically connected to the reset line RST to receive a signal. The first pole of the reset transistor T7 is configured to be electrically connected to the initialization line VINIT2 to receive a second reset signal. The second pole of the reset transistor T7 is electrically connected to the anode of the light-emitting element 0120. The gate of the reset transistor T7 is configured to be electrically connected to the reset line RST to receive a signal. In this way, the initialization transistor T6 and the reset transistor T7 can receive different reset signals respectively.

[0094] The first pole of the first light-emitting control transistor T4 is electrically connected to the first power supply terminal VDD. The second pole of the first light-emitting control transistor T4 is electrically connected to the first pole of the driving transistor T1. The gate of the first light-emitting control transistor T4 is configured to be electrically connected to the light-emitting control line EM to receive a light-emitting control signal.

[0095] The first pole of the second light-emitting control transistor T5 is electrically connected to the second pole of the driving transistor T1. The second pole of the second light-emitting control transistor T5 is electrically connected to the anode of the light-emitting element 0120. The gate of the second light-emitting control transistor T5 is configured to be electrically connected to the light-emitting control line EM to receive a light-emitting control signal.

[0096] The cathode of the light-emitting element 0120 is electrically connected to the second power supply terminal VSS. Among them, the first pole and the second pole of the above-mentioned transistor can be determined as the source or the drain according to the actual application, and are not limited here.

[0097] Exemplarily, one of the first power supply terminal VDD and the second power supply terminal VSS is a high-voltage terminal, and the other is a low-voltage terminal. For example, as Figure 2a shown in the embodiment, the first power supply terminal VDD is a voltage source to output a constant first voltage. For example, the first voltage is a positive voltage; and the second power supply terminal VSS can be a voltage source to output a constant second voltage. For example, the second voltage is 0 or a negative voltage, etc. For example, in some examples, the second power supply terminal VSS can be grounded.

[0098] Figure 2a The signal timing diagram corresponding to the pixel circuit shown, as Figure 2bAs shown. During one frame display time, the operation process of the pixel circuit has three stages: T10 stage, T20 stage, and T30 stage. Among them, rst represents the signal transmitted on the reset line RST, ga represents the signal transmitted on the scan line GA, and em represents the signal transmitted on the emission control line EM.

[0099] In the T10 stage, the signal rst controls the initialization transistor T6 to conduct, so that the signal transmitted on the initialization line VINIT can be provided to the driving gate of the driving transistor T1 to reset the driving gate of the driving transistor T1. The signal rst controls the reset transistor T7 to conduct to provide the signal transmitted on the initialization line VINIT to the anode of the light-emitting element 0120 to reset the anode of the light-emitting element 0120. And in this stage, the signal ga controls both the data writing transistor T2 and the threshold compensation transistor T3 to be cut off. The signal em controls both the first light-emitting control transistor T4 and the second light-emitting control transistor T5 to be cut off.

[0100] In the T20 stage, the signal ga controls the data writing transistor T2 and the threshold compensation transistor T3 to conduct. The conducting data writing transistor T2 charges the driving gate of the driving transistor T1 with the data signal transmitted on the data line VD, so that the voltage of the driving gate of the driving transistor T1 becomes: Vdata + Vth. Wherein, Vth represents the threshold voltage of the driving transistor T1, and Vdata represents the voltage of the data signal. And in this stage, the signal rst controls both the initialization transistor T6 and the reset transistor T7 to be cut off. The signal em controls both the first light-emitting control transistor T4 and the second light-emitting control transistor T5 to be cut off.

[0101] In the T30 stage, the signal em controls both the first light-emitting control transistor T4 and the second light-emitting control transistor T5 to conduct. The conducting first light-emitting control transistor T4 provides the voltage Vdd of the first power supply terminal VDD to the first pole of the driving transistor T1, so that the voltage of the first pole of the driving transistor T1 is Vdd. The driving transistor T1 generates a driving current according to its gate voltage Vdata + |Vth| and the voltage Vdd of the first pole. This driving current is provided to the light-emitting element 0120 through the conducting second light-emitting control transistor T5 to drive the light-emitting element 0120 to emit light. And in this stage, the signal rst controls the initialization transistor T6 and the reset transistor T7 to be cut off. The signal ga controls the data writing transistor T2 and the threshold compensation transistor T3 to be cut off.

[0102] It should be noted that in the embodiments of the present disclosure, the first pole of the above transistor can be its source electrode, and the second pole can be its drain electrode; or the first pole can be its drain electrode and the second pole can be its source electrode, which can be designed and determined according to the actual application requirements. And the pixel circuit in the sub-pixel can be Figure 2a andFigure 2b In addition to the structures shown, structures including other numbers of transistors are also possible, and the embodiments of the present disclosure do not limit this. Below, taking Figure 2a the structure shown as an example for illustration.

[0103] Exemplarily, the display substrate includes a substrate 10, a transistor array layer disposed on the substrate 10, a first conductive layer on the side of the transistor array layer away from the substrate 10, a first insulating layer on the side of the first conductive layer away from the substrate 10, an anode on the side of the first insulating layer away from the substrate 10, a light-emitting layer on the side of the anode away from the substrate 10, and a cathode on the side of the light-emitting layer away from the substrate 10. Among them, the transistor array layer can be used to form transistors and capacitors in the pixel circuit, as well as to form scan lines, reset lines, light-emitting control lines EM, initialization lines VINIT, and first power signal lines VDD of the first power supply terminal VDD. Exemplarily, the transistor array layer may include an active semiconductor layer 0310, a gate conductive layer 0320, a reference conductive layer 0330, and a source-drain metal layer 0340.

[0104] Exemplarily, as Figure 3 shown in Figure 4a FIG. shows the active semiconductor layer0310 of the pixel circuit 0121. The active semiconductor layer 0310 can be formed by patterning a semiconductor material. The active semiconductor layer 0310 can be used to fabricate the driving active layer T1-A of the driving transistor T1, the active layer T2-A of the data writing transistor T2, the active layer T3-A of the threshold compensation transistor T3, the active layer T4-A of the first light-emitting control transistor T4, the active layer T5-A of the second light-emitting control transistor T5, the active layer T6-A of the initialization transistor T6, and the active layer T7-A of the reset transistor T7. Each active layer may include a source region, a drain region, and a channel region between the source region and the drain region. For example, the active layers of the respective transistors are integrally provided.

[0105] Exemplarily, the active semiconductor layer 0310 can be made of amorphous silicon, polysilicon, oxide semiconductor materials, etc. It should be noted that the above-mentioned source region and drain region can be regions doped with n-type impurities or p-type impurities.

[0106] Exemplarily, a gate insulating layer is formed on the above-mentioned active semiconductor layer 0310 to protect the above-mentioned active semiconductor layer 0310. As Figure 3 shown in Figure 4bAs shown, the gate conductive layer 0320 of the pixel circuit 0121 is shown. The gate conductive layer 0320 is disposed on the gate insulating layer and thus insulated from the active semiconductor layer 0310. The gate conductive layer 0320 may include the second pole cc2 of the storage capacitor CST, the scan line GA, the reset line RST, the emission control line EM, and the gates of the driving transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the first emission control transistor T4, the second emission control transistor T5, the initialization transistor T6, and the reset transistor T7.

[0107] For example, as Figure 4b shown, the gate of the data writing transistor T2 may be the overlapping portion of the scan line GA and the active semiconductor layer 0310. The gate of the first emission control transistor T4 may be the first overlapping portion of the emission control line EM and the active semiconductor layer 0310. The gate of the second emission control transistor T5 may be the second overlapping portion of the emission control line EM and the active semiconductor layer 0310. The gate of the initialization transistor T6 is the first overlapping portion of the reset line RST and the active semiconductor layer 0310. The gate of the reset transistor T7 is the second overlapping portion of the reset line RST and the active semiconductor layer 0310. The threshold compensation transistor T3 may be a thin film transistor with a double gate structure. The first gate of the threshold compensation transistor T3 may be the overlapping portion of the scan line GA and the active semiconductor layer 0310. The second gate of the threshold compensation transistor T3 may be the overlapping portion of the protruding portion protruding from the scan line GA and the active semiconductor layer 0310. As Figure 3 With Figure 4b shown, the driving gate of the driving transistor T1 may be the second pole cc2 of the storage capacitor CST.

[0108] It should be noted that Figure 4a each dotted line in

[0109] exemplarily shows the overlapping portions of the gate conductive layer 0320 and the active semiconductor layer 0310. Figure 3 With Figure 4b shown, the scan line GA, the reset line RST, and the emission control line EM are arranged along the second direction F2. And the scan line GA, the reset line RST, and the emission control line EM extend substantially along the first direction F1. Exemplarily, the scan line GA is located between the reset line RST and the emission control line EM. Exemplarily, Figure 3 only the second direction F2 is taken as the column direction and the first direction F1 is taken as the row direction for illustration.

[0110] Exemplarily, in the second direction F2, the second pole cc2 of the storage capacitor CST is located between the scan line GA and the emission control line EM. And the protruding portion protruding from the scan line GA is located on the side of the scan line GA away from the emission control line EM.

[0111] Exemplarily, an interlayer dielectric layer is formed on the above-mentioned gate conductive layer 0320 to protect the above-mentioned gate conductive layer 0320. As Figure 3 shown in Figure 4c the reference conductive layer 0330 of the pixel circuit 120a is shown, and the reference conductive layer 0330 includes a first pole cc1 of the storage capacitor CST, an initialization line VINIT, and a light-shielding layer ZG. Among them, the first pole cc1 of the storage capacitor CST and the second pole cc2 of the storage capacitor CST overlap at least partially to form the storage capacitor CST. Exemplarily, the first pole cc1 of the storage capacitor CST has a hollow area LQ, and the hollow area LQ can expose a part of the second pole cc2 of the storage capacitor CST.

[0112] Exemplarily, as Figure 3 shown in Figure 4c the positive projection of the light-shielding layer ZG on the substrate 10 overlaps with the source region of the reset transistor T7 in the active semiconductor layer 0310 (for example, the source region of the reset transistor T7 and the source region of the initialization transistor T6 are an integrated structure) in the positive projection on the substrate 10. This can reduce the influence of light on the reset transistor T7 and improve the reset accuracy. For example, the threshold compensation transistor T3 is a double-gate transistor. For example, the light-shielding layer ZG shields the active layer part between the two gates of the threshold compensation transistor T3. Since the threshold compensation transistor T3 is directly connected to the driving transistor T1, it can play a role in stabilizing the working state of the driving transistor T1. For example, in the first direction, the projection of the light-shielding layer ZG on the substrate is located in the pixel circuit region where it is located, and between the projections of a signal line (such as a data line) and a first power supply signal line VDD on the substrate, playing a role in shielding signal interference. For example, in the first direction, the projection of the light-shielding layer ZG on the substrate is located between the projections of the signal line such as the data line and the first power supply signal line VDD on the substrate, which is connected to the pixel circuit in the pixel circuit region where it is located.

[0113] Exemplarily, as Figure 3 shown in Figure 4c the positive projection of the light-shielding layer ZG on the substrate 10 overlaps with the drain region of the initialization transistor T6 in the active semiconductor layer 0310 in the positive projection on the substrate 10. This can reduce the influence of light on the initialization transistor T6 and improve the reset accuracy.

[0114] Exemplarily, as Figure 3 shown in Figure 4c the positive projection of the light-shielding layer ZG on the substrate 10 overlaps with the conductive region between the active layer T3-A of the threshold compensation transistor T3 in the active semiconductor layer 0310 in the positive projection on the substrate 10. This can reduce the influence of light on the threshold compensation transistor T3 and improve the accuracy of threshold compensation.

[0115] Exemplarily, a first interlayer insulating layer is formed on the above-mentioned reference conductive layer 0330 to protect the above-mentioned reference conductive layer 0330. As Figure 3 shown in Figure 4d FIG. 6, the source-drain metal layer 0340 of the pixel circuit 0121 is shown. The source-drain metal layer 0340 may include a first power supply signal line VDD, and connection portions LB1, LB2, LB3, and LB4. Exemplarily, the first color sub-pixel spx1, the second color sub-pixel spx2, the third color sub-pixel spx3, and the fourth color sub-pixel spx4 respectively include the connection portions LB1, LB2, LB3, and LB4.

[0116] Exemplarily, a second interlayer insulating layer is formed on the above-mentioned source-drain metal layer 0340 to protect the above-mentioned source-drain metal layer 0340. As Figure 3 shown in Figure 4e FIG. 7, the first conductive layer 0350 of the pixel circuit 0121 is shown. The first conductive layer 0350 includes signal lines and anode transfer portions YZ1, YZ2, YZ3, and YZ4 that are spaced apart from each other. Exemplarily, the first color sub-pixel spx1 may include the anode transfer portion YZ1, the second color sub-pixel spx2 may include the anode transfer portion YZ2, the third color sub-pixel spx3 may include the anode transfer portion YZ3, and the fourth color sub-pixel spx4 may include the anode transfer portion YZ4.

[0117] Exemplarily, the plurality of signal lines include a first signal line and a second signal line; wherein, one column of sub-pixels corresponds to one first signal line and one second signal line. For example, the pixel circuits on the left and right sides of one column of sub-pixels are respectively adjacent to one first signal line and one second signal line. For example, adjacent means that, for example, in the first direction, between the pixel circuit and the adjacent first signal line and second signal line, there are no other first signal lines or second signal lines. The signal protrusions of the first signal line are respectively electrically connected to the odd-row sub-pixels, and the signal protrusions of the second signal line are respectively electrically connected to the even-row sub-pixels. For example, the signal lines may be configured as data lines VD for transmitting data signals. In some embodiments, the data line VD has signal protrusions TQ. The data line Vd extends along the second direction F2 and is arranged along the first direction F1. In some embodiments, one column of sub-pixels corresponds to two data lines. For example, the pixel circuits on the left and right sides of one column of sub-pixels are respectively adjacent to one first signal line and one second signal line; the signal protrusions of one of the two data lines are respectively electrically connected to the pixel circuits of the odd-row sub-pixels, and the signal protrusions of the other data line are respectively electrically connected to the pixel circuits of the even-row sub-pixels.

[0118] It should be noted that one column of sub-pixels corresponding to one first signal line and one second signal line may refer to: the signal lines (such as data lines) directly adjacent to the pixel circuits of this column of sub-pixels. Here, directly adjacent means that there are no other signal lines between the signal line and the pixel circuit. For example, directly adjacent means that there are no other data lines between the data line and the pixel circuit.

[0119] Exemplarily, among the two first signal lines and two second signal lines corresponding to two adjacent columns of sub-pixels, two of the first signal lines may be adjacent to form a first signal line group. For example, two adjacent first signal lines electrically connecting odd-row sub-pixels may form a first signal line group. It should be noted that there are no other corresponding signal lines between these two first signal lines in the first signal line group. For example, there are no other data lines arranged between these two adjacent data lines.

[0120] Exemplarily, among the two first signal lines and two second signal lines corresponding to two adjacent columns of sub-pixels, two of the second signal lines may be adjacent to form a second signal line group. For example, two adjacent second signal lines electrically connecting even-row sub-pixels may form a second signal line group. It should be noted that there are no other corresponding signal lines between these two second signal lines in the second signal line group. For example, there are no other data lines arranged between these two adjacent data lines.

[0121] For example, as Figure 5As shown, the repeating units adjacent along the second direction F2 are arranged with a dislocation, so that the second color sub-pixel spx2 in one repeating unit and the fourth color sub-pixel spx4 in another repeating unit adjacent along the second direction F2 are adjacent along the second direction F2. For example, the second color sub-pixel spx2 and the fourth color sub-pixel spx4 in the repeating units adjacent along the second direction F2 are located in the same column along the second direction F2, forming a sub-pixel pair, for example, aligned vertically in the column direction. For example, the first color sub-pixel spx1, a sub-pixel pair formed by a second color sub-pixel spx2 and a fourth color sub-pixel spx4, and a third color sub-pixel spx3 are arranged in sequence in the first direction F1. For example, the second color sub-pixel spx2 and the fourth color sub-pixel spx4 in the repeating units adjacent along the second direction F2 are used to display the same color, and their light-emitting layers are integrally formed. For example, the light-emitting area sizes of the second color sub-pixel spx2 and the fourth color sub-pixel spx4 in the repeating units adjacent along the second direction F2 are the same. For example, the light-emitting areas of the second color sub-pixel spx2 and the fourth color sub-pixel spx4 in the repeating units adjacent along the second direction F2 are approximately two rounded polygon areas or circular areas that are vertically symmetric, for example, a rounded pentagon area. For example, the light-emitting area of the first color sub-pixel spx1 is approximately a rounded polygon area or an oval area, for example, a rounded hexagon area. For example, the light-emitting area of the third color sub-pixel spx3 is approximately a rounded polygon area or an oval area, for example, a rounded hexagon area. For example, the size of the light-emitting area of the first color sub-pixel spx1 in the second direction F2 is larger than the sizes of the second color sub-pixel spx2, the third color sub-pixel spx3, and the fourth color sub-pixel spx4 in the second direction F2 respectively. For example, the size of the light-emitting area of the third color sub-pixel spx3 in the second direction F2 is larger than the sizes of the second color sub-pixel spx2 and the fourth color sub-pixel spx4 in the second direction F2 respectively. For example, the size of the light-emitting area of the third color sub-pixel spx3 in the first direction F1 is larger than the sizes of the second color sub-pixel spx2, the fourth color sub-pixel spx4, and the first color sub-pixel spx1 in the first direction F1 respectively. For example, the size of the light-emitting area of the first color sub-pixel spx1 in the first direction F1 is smaller than the sizes of the second color sub-pixel spx2 and the fourth color sub-pixel spx4 in the first direction F1 respectively.

[0122] Exemplarily, a first insulating layer is formed on the above-mentioned first conductive layer 0350 to protect the above-mentioned first conductive layer 0350. As Figure 3 With Figure 4fAs shown, an anode layer 0360 is shown on a side of the first conductive layer 0350 away from the substrate 10. The anode layer 0360 includes anodes Y1, Y2, Y3, and Y4. Exemplarily, the first color sub-pixel spx1 may include anode Y1, the second color sub-pixel spx2 may include anode Y2, the third color sub-pixel spx3 may include anode Y3, and the fourth color sub-pixel spx4 may include anode Y4.

[0123] As Figures 3 to 4f shown, the first power supply signal line VDD is electrically connected to a source region of a corresponding first light-emitting control transistor T4 in the active semiconductor layer 0310 through at least one via penetrating the gate insulating layer, the interlayer dielectric layer, and the first interlayer insulating layer. The first power supply signal line VDD is electrically connected to a first pole cc1 of a storage capacitor CST in the reference conductive layer 0330 through at least one via penetrating the first interlayer insulating layer. The first power supply signal line VDD is also electrically connected to the light-shielding layer ZG through at least one via penetrating the first interlayer insulating layer. Also, the first power supply signal line VDD is electrically connected to the light-shielding layer ZG in the reference conductive layer 0330 through at least one via penetrating the first interlayer insulating layer.

[0124] As Figures 3 to 4f shown, one end of the connection part LB1 is electrically connected to a drain region of a corresponding threshold compensation transistor T3 in the active semiconductor layer 0310 through at least one via penetrating the gate insulating layer, the interlayer dielectric layer, and the first interlayer insulating layer. The other end of the connection part LB1 is electrically connected to the initialization line VINIT through at least one via penetrating the first interlayer insulating layer.

[0125] As Figures 3 to 4f shown, one end of the connection part LB2 is electrically connected to a signal protrusion TQ of the data line through a via penetrating the second interlayer insulating layer, and the other end of the connection part LB2 is electrically connected to a source region of a data writing transistor T2 in the active semiconductor layer 0310 through at least one via penetrating the gate insulating layer, the interlayer dielectric layer, and the first interlayer insulating layer.

[0126] As Figures 3 to 4fAs shown, one end of the connection portion LB3 is electrically connected to the second electrode cc2 of the storage capacitor CST (i.e., the driving gate of the driving transistor T1) through at least one driving via GK0 penetrating the interlayer dielectric layer and the first interlayer insulating layer. The other end of the connection portion LB3 is electrically connected to the drain region of the initialization transistor T6 in the active semiconductor layer 0310 through at least one via penetrating the gate insulating layer, the interlayer dielectric layer, and the first interlayer insulating layer. In other words, the driving gate in the driving transistor is electrically connected to the active semiconductor layer through the driving via, which may mean that the driving gate of the driving transistor T1 is electrically connected to one end of the connection portion LB3 through the driving via GK0, and the other end of the connection portion LB3 is electrically connected to the drain region of the initialization transistor T6 in the active semiconductor layer 0310 through at least one via penetrating the gate insulating layer, the interlayer dielectric layer, and the first interlayer insulating layer. And, as Figures 3 to 4f As shown, in the sub-pixel, the orthographic projection of at least part of the driving via GK0 on the base substrate does not overlap with the orthographic projections of the anode transfer portion and the signal line on the base substrate.

[0127] like Figures 3 to 4f As shown, the connection portion LB4 is electrically connected to the drain region of the second light emission control transistor T5 in the active semiconductor layer 0310 through at least one via hole penetrating the gate insulating layer, the interlayer dielectric layer and the first interlayer insulating layer.

[0128] In some examples, such as Figures 3 to 4fAs shown, the first insulating layer includes a first via hole that exposes a part of the anode connection portion, and the anode includes a main portion and an auxiliary portion that are electrically connected to each other; wherein, the auxiliary portion is electrically connected to the anode connection portion through the first via hole. For example, in the first color sub-pixel spx1, the anode Y1 includes a main portion Y11 and an auxiliary portion Y12 that are electrically connected to each other, and the auxiliary portion Y12 is electrically connected to the anode connection portion YZ1 through the first via hole K11. The anode connection portion YZ1 is electrically connected to the connection portion LB4 through a via hole penetrating the second interlayer insulating layer. In the second color sub-pixel spx2, the anode Y2 includes a main portion Y21 and an auxiliary portion Y22 that are electrically connected to each other, and the auxiliary portion Y22 is electrically connected to the anode connection portion YZ2 through the first via hole K12. The anode connection portion YZ2 is electrically connected to the connection portion LB4 through a via hole penetrating the second interlayer insulating layer. In the third color sub-pixel spx3, the anode Y3 includes a main portion Y31 and an auxiliary portion Y32 that are electrically connected to each other, and the auxiliary portion Y32 is electrically connected to the anode connection portion YZ3 through the first via hole K13. The anode connection portion YZ3 is electrically connected to the connection portion LB4 through a via hole penetrating the second interlayer insulating layer. In the fourth color sub-pixel spx4, the anode Y4 includes a main portion Y41 and an auxiliary portion Y42 that are electrically connected to each other, and the auxiliary portion Y42 is electrically connected to the anode connection portion YZ4 through the first via hole K14. The anode connection portion YZ4 is electrically connected to the connection portion LB4 through a via hole penetrating the second interlayer insulating layer.

[0129] It should be noted that the main portion and the auxiliary portion of the anode that are electrically connected to each other are an integral structure, that is, the main portion and the auxiliary portion are formed continuously.

[0130] In some examples, as Figures 3 to 5 shown, the multiple sub-pixels include a first sub-pixel 01 and a second sub-pixel 02; wherein, in the first sub-pixel 01, the orthographic projection of the anode connection portion on the substrate 10 does not overlap with the orthographic projection of the driving active layer on the substrate 10, and the orthographic projection of the main portion on the substrate 10 does not overlap with the orthographic projection of the anode connection portion on the substrate 10. Also, in the second sub-pixel 02, the orthographic projection of the anode connection portion on the substrate 10 overlaps with the orthographic projection of the driving active layer on the substrate 10, and the orthographic projection of the main portion on the substrate 10 overlaps with the orthographic projection of the anode connection portion on the substrate 10. In this way, by overlapping the main portion of the anode with the anode connection portion in some sub-pixels, the flatness of the main portion of the anode can be adjusted through the anode connection portion, thereby avoiding the unevenness of the anode caused by the first conductive layer, and further improving the color shift phenomenon of the display substrate.

[0131] In some examples, a pixel defining layer is further provided on the side of the anode layer away from the substrate, a light-emitting layer is further provided on the side of the pixel defining layer away from the substrate, and a cathode layer is further provided on the side of the light-emitting layer away from the substrate. In this way, the anode, the light-emitting layer, and the cathode can form a light-emitting element. Exemplarily, in combination with Figures 4f to 6c , the pixel defining layer may include a plurality of opening regions (such as: KK1, KK2, KK3, KK4). Among them, one anode corresponds to one opening region, and the orthographic projection of the opening region on the substrate 10 is located within the orthographic projection of the main body portion of the corresponding anode on the substrate 10. For example, in the first color sub-pixel, the opening region KK1 corresponds to the main body portion Y11 of the anode Y1. In the second color sub-pixel, the opening region KK2 corresponds to the main body portion Y21 of the anode Y2. In the third color sub-pixel, the opening region KK3 corresponds to the main body portion Y31 of the anode Y3. In the fourth color sub-pixel, the opening region KK4 corresponds to the main body portion Y41 of the anode Y4. In some examples, in the second sub-pixel, the orthographic projection of the opening region corresponding to the anode on the substrate overlaps with the orthographic projection of the anode transfer portion on the substrate. In the first sub-pixel, the orthographic projection of the opening region corresponding to the anode on the substrate does not overlap with the orthographic projection of the anode transfer portion on the substrate. For example, the light-emitting regions of the respective sub-pixels correspond to the respective opening regions. For example, the light-emitting region of the first color sub-pixel is the opening region corresponding to its anode, the light-emitting region of the second color sub-pixel is the opening region corresponding to its anode, the light-emitting region of the third color sub-pixel is the opening region corresponding to its anode, and the light-emitting region of the fourth color sub-pixel is the opening region corresponding to its anode.

[0132] In some examples, such as Figures 3 to 5 and Figure 6d shown, the first sub-pixel 01 includes the first color sub-pixel spx1. That is to say, in the first color sub-pixel spx1, the orthographic projection of the anode transfer portion YZ1 on the substrate 10 does not overlap with the orthographic projection of the driving active layer T1-A on the substrate 10, and the orthographic projection of the main body portion Y11 on the substrate 10 does not overlap with the orthographic projection of the anode transfer portion YZ1 on the substrate 10. Further, the orthographic projection of the anode transfer portion YZ1 on the substrate 10 does not overlap with the orthographic projection of the opening region KK1 on the substrate 10.

[0133] Further, in the first color sub-pixel spx1, the orthographic projection of the anode transfer portion YZ1 on the substrate 10 overlaps with the edge of the orthographic projection of the first pole cc1 of the storage capacitor CST on the substrate 10, and the orthographic projection of the anode transfer portion YZ1 on the substrate 10 does not overlap with the orthographic projection of the second pole cc2 of the storage capacitor CST on the substrate 10.

[0134] In some examples, such as Figures 3 to 5As shown, in the first color sub-pixel spx1, the positive projection of the main body portion Y11 on the substrate 10 overlaps with the positive projection of two signal lines (for example, the following first signal line group (such as two data lines Vd) or the second signal line group (such as two data lines Vd)) on the substrate 10, and the positive projection of the main body portion Y11 on the substrate 10 does not overlap with the positive projection of the anode connection portion YZ1 and the signal bump portion on the substrate 10. In some embodiments, in the first color sub-pixel spx1, the two signal lines (for example, the following first signal line group (such as two data lines Vd) or the second signal line group (such as two data lines Vd)) that overlap with the positive projection of the main body portion Y11 on the substrate 10 are respectively located on both sides of the center of the main body portion Y11. Exemplarily, the main body portion Y11 in the first color sub-pixel spx1 has a first main symmetry axis along the second direction F2. In the first color sub-pixel spx1, in the second direction F2, the two signal lines (for example, the following first signal line group (such as two data lines Vd) or the second signal line group (such as two data lines Vd)) that overlap with the positive projection of the main body portion Y11 on the substrate 10 are respectively located on opposite sides of the first main symmetry axis. Further, in the first color sub-pixel spx1, in the first direction F1, the ratio of the distances between the two signal lines (for example, the following first signal line group (such as two data lines Vd) or the second signal line group (such as two data lines Vd)) that overlap with the positive projection of the main body portion Y11 on the substrate 10 and the first main symmetry axis is 0.8 to 1.2. For example, in the first direction F1, the ratio of the distances between the two signal lines (for example, the following first signal line group (such as two data lines Vd) or the second signal line group (such as two data lines Vd)) that overlap with the positive projection of the main body portion Y11 on the substrate 10 and the first main symmetry axis is 0.8, 1.0, 1.1, or 1.2. Further, in the first color sub-pixel spx1, the main body portion Y11 does not overlap with the signal bump portion TQ connected to the same pixel circuit.

[0135] In some examples, such as Figures 3 to 5 As shown, the second sub-pixel 02 may include at least one of a second color sub-pixel spx2, a third color sub-pixel spx3, and a fourth color sub-pixel spx4. For example, when the second sub-pixel 02 includes the second color sub-pixel spx2, that is, in the second color sub-pixel spx2, the positive projection of the anode connection portion YZ2 on the substrate 10 overlaps with the positive projection of the driving active layer T1-A on the substrate 10, and the positive projection of the main body portion Y21 on the substrate 10 overlaps with the positive projection of the anode connection portion YZ2 on the substrate 10. Further, the positive projection of the opening region KK2 on the substrate 10 overlaps with the positive projection of the anode connection portion YZ2 on the substrate 10. Further, in the second color sub-pixel spx2, the main body portion Y21 does not overlap with the signal bump portion TQ connected to the same pixel circuit.

[0136] Further, in the second color sub-pixel spx2, the positive projection of the anode transfer portion YZ2 on the substrate 10 overlaps with the positive projection of the first electrode cc1 of the storage capacitor CST on the substrate 10, and the positive projection of the anode transfer portion YZ2 on the substrate 10 also overlaps with the positive projection of the second electrode cc2 of the storage capacitor CST on the substrate 10. Further, in the second direction, the positive projection of the anode transfer portion YZ2 on the substrate 10 passes through the positive projection of the first electrode cc1 of the storage capacitor CST on the substrate 10, and in the second direction, the positive projection of the anode transfer portion YZ2 on the substrate 10 also passes through the positive projection of the second electrode cc2 of the storage capacitor CST on the substrate 10.

[0137] For example, when the second sub-pixel 02 includes the third color sub-pixel spx3, that is to say, in the third color sub-pixel spx3, the positive projection of the anode transfer portion YZ3 on the substrate 10 overlaps with the positive projection of the driving active layer T1-A on the substrate 10, and the positive projection of the main body portion Y31 on the substrate 10 overlaps with the positive projection of the anode transfer portion YZ3 on the substrate 10. Further, the positive projection of the opening region KK3 on the substrate 10 overlaps with the positive projection of the anode transfer portion YZ3 on the substrate 10. Further, in the third color sub-pixel spx3, the main body portion Y31 overlaps with the signal bump portion TQ connected to the same pixel circuit.

[0138] Further, in the third color sub-pixel spx3, the positive projection of the anode transfer portion YZ3 on the substrate 10 overlaps with the positive projection of the first electrode cc1 of the storage capacitor CST on the substrate 10, and the positive projection of the anode transfer portion YZ3 on the substrate 10 also overlaps with the positive projection of the second electrode cc2 of the storage capacitor CST on the substrate 10. Further, in the second direction, the positive projection of the anode transfer portion YZ3 on the substrate 10 passes through the positive projection of the first electrode cc1 of the storage capacitor CST on the substrate 10, and in the second direction, the positive projection of the anode transfer portion YZ3 on the substrate 10 also passes through the positive projection of the second electrode cc2 of the storage capacitor CST on the substrate 10.

[0139] For example, when the second sub-pixel 02 includes the fourth color sub-pixel spx4, that is to say, in the fourth color sub-pixel spx4, the positive projection of the anode connection portion YZ4 on the substrate 10 overlaps with the positive projection of the driving active layer T1-A on the substrate 10, and the positive projection of the main body portion Y41 on the substrate 10 overlaps with the positive projection of the anode connection portion YZ4 on the substrate 10. Further, the positive projection of the opening region KK4 on the substrate 10 overlaps with the positive projection of the anode connection portion YZ4 on the substrate 10. Further, in the fourth color sub-pixel spx4, the main body portion Y41 does not overlap with the signal bump portion TQ connected to the same pixel circuit. And the main body portion Y41 in the fourth color sub-pixel spx4 overlaps with the signal bump portion TQ in the pixel circuit connected to the adjacent second color sub-pixel spx2.

[0140] Further, in the fourth color sub-pixel spx4, the positive projection of the anode connection portion YZ4 on the substrate 10 overlaps with the positive projection of the first pole cc1 of the storage capacitor CST on the substrate 10, and the positive projection of the anode connection portion YZ4 on the substrate 10 also overlaps with the positive projection of the second pole cc2 of the storage capacitor CST on the substrate 10. Further, in the second direction, the positive projection of the anode connection portion YZ4 on the substrate 10 passes through the positive projection of the first pole cc1 of the storage capacitor CST on the substrate 10, and in the second direction, the positive projection of the anode connection portion YZ4 on the substrate 10 also passes through the positive projection of the second pole cc2 of the storage capacitor CST on the substrate 10.

[0141] In some examples, such as Figures 3 to 5 shown, the anode connection portion in the second sub-pixel 02 (i.e., the anode connection portion whose positive projection on the substrate 10 overlaps with the main body portion) may include: a first sub-anode connection portion and a second sub-anode connection portion that are electrically connected to each other; wherein, the first sub-anode connection portion has a hollow structure, and the second sub-anode connection portion has a solid structure; the auxiliary portion is electrically connected to the second sub-anode connection portion through a first via. And, in the second sub-pixel 02, the positive projection of the first sub-anode connection portion on the substrate 10 overlaps with the positive projection of the driving active layer on the substrate 10. It should be noted that the solid structure may mean that the positive projection of the second sub-anode connection portion on the substrate is a whole surface and there is no hollow inside.

[0142] Exemplarily, such as Figures 3 to 5As shown, in the second color sub-pixel spx2, the anode transition part YZ2 may include: a first sub-anode transition part YZ21 and a second sub-anode transition part YZ22 electrically connected to each other; wherein the first sub-anode transition part YZ21 has a hollow structure, and the second sub-anode transition part YZ22 has a solid structure; the auxiliary part Y22 is electrically connected to the second sub-anode transition part YZ22 through the first via K12. In addition, the orthographic projection of the first sub-anode transition part YZ21 on the base substrate 10 overlaps with the orthographic projection of the driving active layer T1-A on the base substrate 10.

[0143] For example, Figures 3 to 5 As shown, in the third color sub-pixel spx3, the anode transition part YZ3 may include: a first sub-anode transition part YZ31 and a second sub-anode transition part YZ32 electrically connected to each other; wherein the first sub-anode transition part YZ31 has a hollow structure, and the second sub-anode transition part YZ32 has a solid structure; the auxiliary part Y32 is electrically connected to the second sub-anode transition part YZ32 through the first via K13. In addition, the orthographic projection of the first sub-anode transition part YZ31 on the base substrate 10 overlaps with the orthographic projection of the driving active layer T1-A on the base substrate 10.

[0144] For example, Figures 3 to 5 As shown, in the fourth color sub-pixel spx4, the anode transition part YZ4 may include: a first sub-anode transition part YZ41 and a second sub-anode transition part YZ42 electrically connected to each other; wherein the first sub-anode transition part YZ41 has a hollow structure, and the second sub-anode transition part YZ42 has a solid structure; the auxiliary part Y42 is electrically connected to the second sub-anode transition part YZ42 through the first via K14. In addition, the orthographic projection of the first sub-anode transition part YZ41 on the base substrate 10 overlaps with the orthographic projection of the driving active layer T1-A on the base substrate 10.

[0145] For example, Figures 3 to 5 As shown, in the second direction F2, in the same sub-pixel, the orthographic projection of the scanning line on the substrate 10 is located on the side of the orthographic projection of the driving active layer on the substrate 10 away from the orthographic projection of the second sub-anode transition portion on the substrate 10. Moreover, in the second sub-pixel 02, the orthographic projection of the first sub-anode transition portion on the substrate 10 overlaps with the orthographic projection of the scanning line on the substrate 10. For example, as Figures 3 to 5 As shown, in the second color sub-pixel spx2 , the orthographic projection of the first sub-anode transition portion YZ21 on the base substrate 10 overlaps with the orthographic projection of the scanning line GA on the base substrate 10 .

[0146] For example, Figures 3 to 5As shown, in the third color sub-pixel spx3, the positive projection of the first sub-anode transfer portion YZ31 on the substrate 10 overlaps with the positive projection of the scan line GA on the substrate 10. Exemplarily, the positive projection of the first sub-anode transfer portion YZ31 on the substrate 10 is at least partially covered by the positive projection of the anode Y3 on the substrate 10. Further, the positive projection of the first sub-anode transfer portion YZ31 on the substrate 10 is entirely covered by the positive projection of the anode Y3 on the substrate 10.

[0147] Exemplarily, as Figures 3 to 5 shown, in the fourth color sub-pixel spx4, the positive projection of the first sub-anode transfer portion YZ41 on the substrate 10 overlaps with the positive projection of the scan line GA on the substrate 10.

[0148] Exemplarily, the positive projection of the anode Y4 in the fourth color sub-pixel spx4 covers a part of the positive projection of the anode transfer portion YZ4 on the substrate 10. The positive projection of the anode Y2 in the second color sub-pixel spx2 covers a part of the positive projection of the anode transfer portion YZ2 on the substrate 10. And, in the same repeating unit, the area of the part of the anode transfer portion YZ2 in the second color sub-pixel spx2 covered by the anode Y2 is larger than the area of the part of the anode transfer portion YZ4 in the fourth color sub-pixel spx4 covered by the anode Y4.

[0149] In some examples, as Figures 3 to 5 shown, in the second sub-pixel 02, the hollow region LQ in the hollow structure of the first sub-anode transfer portion overlaps with the positive projection of the via GK0 connecting the driving gate on the substrate 10. For example, the positive projection of the hollow structure in the first sub-anode transfer portion overlaps with the first pole cc1 of the storage capacitor CST with a hollow region LQ. This hollow region LQ serves as a via for connecting the driving gate (i.e., the second pole cc2 of the storage capacitor CST) and other transistors. For example, one pole (source or drain) of the threshold compensation transistor is connected to the driving gate (i.e., the second pole cc2 of the storage capacitor CST) through the connection line LB3 located in the source-drain metal layer. Exemplarily, as Figures 3 to 5As shown, in the second color sub-pixel spx2, the positive projection of the hollow structure in the first sub-anode transfer portion YZ21 on the substrate 10 overlaps with the positive projection of the central region of the driving gate on the substrate 10. Moreover, the positive projection of the hollow structure in the first sub-anode transfer portion YZ21 on the substrate 10 has a hollow region overlap with the first pole cc1 of the storage capacitor CST. In the third color sub-pixel spx3, the positive projection of the hollow structure in the first sub-anode transfer portion YZ31 on the substrate 10 overlaps with the positive projection of the central region of the driving gate on the substrate 10. Moreover, the positive projection of the hollow structure in the first sub-anode transfer portion YZ21 on the substrate 10 has a hollow region overlap with the first pole cc1 of the storage capacitor CST. In the fourth color sub-pixel spx4, the positive projection of the hollow structure in the first sub-anode transfer portion YZ41 on the substrate 10 overlaps with the positive projection of the central region of the driving gate on the substrate 10. Moreover, the positive projection of the hollow structure in the first sub-anode transfer portion YZ21 on the substrate 10 has a hollow region overlap with the first pole cc1 of the storage capacitor CST.

[0150] In some examples, as Figures 3 to 5 shown, in the second sub-pixel 02, the positive projection of the main body portion Y21 on the substrate 10 overlaps with the positive projection of two signal lines (for example, the first signal line group (such as two data lines Vd) or the second signal line group (such as two data lines Vd)) on the substrate 10. Exemplarily, as Figures 3 to 5 shown, in the second color sub-pixel spx2, the positive projection of the main body portion Y21 on the substrate 10 overlaps with the positive projection of two signal lines (such as two data lines Vd) on the substrate 10. In the third color sub-pixel spx3, the positive projection of the main body portion Y31 on the substrate 10 overlaps with the positive projection of two signal lines (such as two data lines Vd) on the substrate 10. In the fourth color sub-pixel spx4, the positive projection of the main body portion Y41 on the substrate 10 overlaps with the positive projection of two signal lines (such as two data lines Vd) on the substrate 10.

[0151] In some examples, as Figures 3 to 5 shown, the first sub-anode transfer portion has a first sub-transfer portion and a second sub-transfer portion arranged oppositely; wherein, in the first direction, the positive projection of the first sub-transfer portion on the substrate 10 is located between the second sub-transfer portion and the positive projection of two signal lines on the substrate 10. Exemplarily, the first sub-transfer portion can be made to extend substantially along the second direction F2, or the second sub-transfer portion can be made to extend substantially along the second direction F2.

[0152] Exemplarily, as Figures 3 to 5As shown, in the second color sub-pixel spx2, the first sub-anode transfer portion YZ21 has a first sub-transfer portion YZ211 and a second sub-transfer portion YZ212 that are oppositely arranged; among them, the orthographic projection of the first sub-transfer portion YZ211 on the substrate 10 is located between the second sub-transfer portion YZ212 and the orthographic projection of two signal lines (such as two data lines Vd) that overlap with the main body portion Y21 of the second color sub-pixel spx2 on the substrate 10. Exemplarily, the first sub-transfer portion YZ211 is closer to the center of the main body portion Y21 than the second sub-transfer portion YZ212. For example, the orthographic projection of the second sub-transfer portion YZ212 on the substrate 10 overlaps with the edge of the orthographic projection of the main body portion Y21 on the substrate 10. For example, in the first direction F1, the portions of the first sub-transfer portion YZ211 and the second sub-transfer portion YZ212 that overlap with the projection of the main body portion Y21 are both located on the same side of the projection center of the main body portion Y21. Exemplarily, in the first direction F1, the portions of the first sub-transfer portion YZ211 and the second sub-transfer portion YZ212 that overlap with the projection of the main body portion Y21 are both located on the first side of the projection center of the main body portion Y21, and the projections of the two signal lines (such as two data lines Vd) that overlap with the main body portion Y21 of the second color sub-pixel spx2 are respectively located on the second side of the projection center of the main body portion Y21, and the first side and the second side are opposite sides. In this way, the first sub-transfer portion YZ211, the second sub-transfer portion YZ212, and the two signal lines that overlap with the main body portion Y21 of the second color sub-pixel spx2 can play a better flattening role. Further, as Figures 3 to 5 shown, in the second color sub-pixel spx2, the main body portion Y21 partially overlaps with the second sub-anode transfer portion YZ22. Further, in the second color sub-pixel spx2, in the second direction, the projection of the anode transfer portion YZ2 located on the second side of the projection center of the main body portion Y21 completely penetrates the projection of the main body portion Y21, and the projection of the signal line located on the first side of the projection center of the main body portion Y21 completely penetrates the projection of the main body portion Y21 to achieve a better flattening effect.

[0153] Exemplarily, as Figures 3 to 5As shown, in the third color sub-pixel spx3, the first sub-anode transfer portion YZ31 has a first sub-transfer portion YZ311 and a second sub-transfer portion YZ312 which are oppositely arranged; wherein, the orthographic projection of the first sub-transfer portion YZ311 on the substrate 10 is located between the orthographic projection of the second sub-transfer portion YZ312 and the orthographic projection of two signal lines (such as two data lines Vd) overlapping with the main body portion Y31 of the third color sub-pixel spx3 on the substrate 10. Exemplarily, the first sub-transfer portion YZ311 is closer to the center of the main body portion Y31 than the second sub-transfer portion YZ312. For example, the orthographic projection of the second sub-transfer portion YZ312 on the substrate 10 overlaps with the edge of the orthographic projection of the main body portion Y31 on the substrate 10. For example, in the first direction F1, the overlapping portions of the first sub-transfer portion YZ311 and the second sub-transfer portion YZ312 with the projection of the main body portion Y31 are both on the same side of the projection center of the main body portion Y31.

[0154] Exemplarily, in the first direction F1, the overlapping portions of the first sub-transfer portion YZ311 and the second sub-transfer portion YZ312 with the projection of the main body portion Y31 are both on the first side of the projection center of the main body portion Y31, and the projections of two signal lines (such as the first signal line group (such as two data lines Vd) or the second signal line group (such as two data lines Vd) described below) overlapping with the main body portion Y31 of the third color sub-pixel spx3 are respectively on the second side of the projection center of the main body portion Y31, and the first side and the second side are opposite sides. In this way, the first sub-transfer portion YZ311, the second sub-transfer portion YZ312, and the two signal lines overlapping with the main body portion Y31 of the third color sub-pixel spx3 can play a better flattening role. Further, in the third color sub-pixel spx3, in the second direction, the projection of the signal line located on the first side of the projection center of the main body portion Y31 completely penetrates the projection of the main body portion Y31 to achieve a better flattening effect.

[0155] Exemplarily, as Figures 3 to 5As shown, in the third color sub-pixel spx3, the signal protrusion TQ and the anode connection part YZ3 overlap in the first direction. Alternatively, a straight line parallel to the second direction can pass through the signal protrusion TQ and the anode connection part YZ3. Further, in the second direction, the signal protrusion TQ and the anode connection part YZ3 do not overlap, and the anode connection part YZ3 is at least partially located on the side of the center of the main body part Y31 away from the signal protrusion TQ. This can make the anode connection part YZ3 and the signal protrusion TQ located on both sides of the center of the main body part Y31, so that the anode Y3 can be made flatter further. Further, in the third color sub-pixel spx3, the center of the signal protrusion TQ and the center lines of the two data lines overlapping with the main body part Y31 of the third color sub-pixel spx3 can also be located on both sides of the center of the main body part Y31. In this way, the anode Y3 can be made flatter further.

[0156] Exemplarily, as Figures 3 to 5As shown, in the fourth color sub-pixel spx4, the first sub-anode transfer portion YZ41 has a first sub-transfer portion YZ411 and a second sub-transfer portion YZ412 that are oppositely arranged; wherein, the orthographic projection of the first sub-transfer portion YZ411 on the substrate 10 is located between the second sub-transfer portion YZ412 and the orthographic projection of two signal lines (such as the first signal line group (such as two data lines Vd) or the second signal line group (such as two data lines Vd)) that overlap with the main body portion Y41 of the fourth color sub-pixel spx4 on the substrate 10. Exemplarily, the first sub-transfer portion YZ411 is closer to the center of the main body portion Y41 than the second sub-transfer portion YZ412. For example, in the first direction F1, the overlapping portions of the first sub-transfer portion YZ311 and the second sub-transfer portion YZ312 with the projection of the main body portion Y31 are both on the same side of the projection center of the main body portion Y31. Exemplarily, in the first direction F1, the overlapping portions of the first sub-transfer portion YZ311 and the second sub-transfer portion YZ312 with the projection of the main body portion Y31 are both on the first side of the projection center of the main body portion Y31, and the projections of the two signal lines (such as two data lines Vd) that overlap with the main body portion Y41 of the fourth color sub-pixel spx4 are respectively on the second side of the projection center of the main body portion Y41, and the first side and the second side are opposite sides. In this way, the first sub-transfer portion YZ411, the second sub-transfer portion YZ412, and the two signal lines that overlap with the main body portion Y41 of the fourth color sub-pixel spx4 can play a better flattening role. Further, in the fourth color sub-pixel spx4, the main body portion Y41 completely covers the second sub-anode transfer portion YZ42. Further, in the fourth color sub-pixel spx4, the signal protrusion portion TQ that overlaps with the main body portion Y41 is located on the side of the anode transfer portion YZ4 away from the overlapping main body portion Y41. Further, in the fourth color sub-pixel spx4, in the second direction, the projection of the signal line located on the first side of the projection center of the main body portion Y41 completely penetrates the projection of the main body portion Y41 to achieve a better flattening effect.

[0157] Exemplarily, such as Figures 3 to 5As shown, the two signal lines overlapping the main body portion Y21 in the second color sub-pixel spx2 are located on the side of the second color sub-pixel spx2 close to the first color sub-pixel spx1 in the same repeating unit, and the anode transfer portion YZ2 in the second color sub-pixel spx2 is located on the side of the second color sub-pixel spx2 close to the third color sub-pixel spx3 in the same repeating unit. The two signal lines overlapping the main body portion Y41 in the fourth color sub-pixel spx4 are located on the side of the fourth color sub-pixel spx4 close to the third color sub-pixel spx3 in the same repeating unit, and the anode transfer portion YZ4 in the fourth color sub-pixel spx4 is located on the side of the fourth color sub-pixel spx4 away from the third color sub-pixel spx3 in the same repeating unit. In this way, the two signal lines overlapping the main body portion Y21 in the second color sub-pixel spx2 and the two signal lines overlapping the main body portion Y41 in the fourth color sub-pixel spx4 can be both located on the same side.

[0158] In some examples, as Figures 3 to 6a shown, when the second sub-pixel 02 includes the second color sub-pixel spx2, in the second color sub-pixel spx2, the orthographic projection of the main body portion Y21 on the substrate 10 overlaps with the orthographic projection of the first sub-anode transfer portion YZ21 on the substrate 10. Exemplarily, in the second color sub-pixel spx2, the orthographic projection of the main body portion Y21 on the substrate 10 overlaps with the orthographic projections of the first sub-transfer portion YZ211 and the second sub-transfer portion YZ212 on the substrate 10. Exemplarily, the main body portion Y21 in the second color sub-pixel spx2 has a second main symmetry axis along the second direction F2; and, in the second color sub-pixel spx2, the center lines along the second direction F2 of the portions of the two signal lines (such as two data lines Vd) overlapping the orthographic projection of the main body portion Y21 on the substrate 10 are respectively located on the opposite sides of the second main symmetry axis from the center lines of the first sub-transfer portion YZ211 and the second sub-transfer portion YZ212 along the second direction F2. Exemplarily, the ratio of the distance between the center lines along the second direction F2 of the two signal lines (such as two data lines Vd) overlapping the orthographic projection of the main body portion Y21 on the substrate 10 to the distance between the center lines of the first sub-transfer portion YZ211 and the second sub-transfer portion YZ212 along the second direction F2 and the second main symmetry axis is 0.8 to 1.2, and can be, for example, one of 0.8, 0.9, 1.0, 1.1, and 1.2. In this way, by supporting the main body portion Y21 through the data line Vd and the first sub-transfer portion YZ211 and the second sub-transfer portion YZ212, the main body portion Y21 can be made as flat as possible, thereby reducing the asymmetry of the main body portion Y21. Furthermore, the luminous asymmetry of the effective light-emitting region EQ can be improved, or even eliminated, thereby improving, or even eliminating, the color shift phenomenon of the display substrate.

[0159] In some examples, such as Figures 3 to 5 and Figure 6b shown, when the second sub-pixel 02 includes the fourth color sub-pixel spx4, in the fourth color sub-pixel spx4, the orthographic projection of the main body portion Y41 on the substrate 10 overlaps with the orthographic projection of the second sub-anode transfer portion YZ42 on the substrate 10, and the orthographic projection of the main body portion Y41 on the substrate 10 overlaps with the orthographic projections of two signal lines (for example, two data lines Vd) on the substrate 10. Exemplarily, in the second direction F2, in the fourth color sub-pixel spx4, at least a part of the orthographic projection of the main body portion Y41 on the substrate 10 is located on the side of the orthographic projection of the second sub-anode transfer portion YZ42 on the substrate 10 away from the orthographic projection of the first sub-anode transfer portion YZ41 on the substrate 10. Exemplarily, the main body portion in the fourth color sub-pixel spx4 has a fourth main symmetry axis along the second direction F2; in the fourth color sub-pixel spx4, the parts of the two signal lines (for example, two data lines Vd) overlapping with the orthographic projection of the main body portion Y41 on the substrate 10, along the center line in the second direction F2, and the center line of the second sub-anode transfer portion YZ42 along the second direction F2 are respectively located on both sides of the fourth main symmetry axis. Exemplarily, the ratio of the distance between the center line of the two signal lines (for example, two data lines Vd) overlapping with the orthographic projection of the main body portion Y41 on the substrate 10 along the second direction F2 and the center line of the second sub-anode transfer portion YZ42 along the second direction F2 to the distance between the fourth main symmetry axis is 0.8 to 1.2, and can be, for example, one of 0.8, 1.0, and 1.2. Further, along the second direction, for example, in the same column, the orthographic projection of the main body portion Y41 in the fourth color sub-pixel spx4 on the substrate 10 overlaps with the orthographic projection of the signal protrusion in the adjacent second color sub-pixel spx2 on the substrate 10. Thus, by supporting the main body portion Y41 through the data line Vd, the second sub-anode transfer portion YZ42, and the signal protrusion, the main body portion Y41 can be made as flat as possible, thereby reducing the asymmetry of the main body portion Y41. Furthermore, the luminous asymmetry of the effective light-emitting region EQ can be improved, and even the luminous asymmetry of the effective light-emitting region EQ can be eliminated, thereby improving, and even eliminating the color shift phenomenon of the display substrate.

[0160] In some examples, such as Figures 3 to 5As shown, the area of the orthographic projection of the second sub-anode connection part YZ42 in a fourth color sub-pixel spx4 on the substrate 10 is larger than the area of the orthographic projection of the second sub-anode connection part YZ22 in a second color sub-pixel spx2 on the substrate 10. For example, the orthographic projection of the second sub-anode connection part YZ22 in the second color sub-pixel spx2 on the substrate 10 has a second width W2 along the second direction F2, and the orthographic projection of the second sub-anode connection part YZ42 in the fourth color sub-pixel spx4 on the substrate 10 has a fourth width W4 along the second direction F2; the fourth width W4 is larger than the second width W2.

[0161] Exemplarily, as Figure 4e shown, the orthographic projection of the second sub-anode connection part YZ22 in the second color sub-pixel spx2 on the substrate 10 has a first width W1 along the first direction F1, and W2:W1 can be set to 1.5:1. In practical applications, different sizes of the second color sub-pixels spx2 have different requirements for the values of the first width W1 and the second width W2. Therefore, in combination with the condition that W2:W1 is set to 1.5:1, the values of the first width W1 and the second width W2 are set according to actual application requirements, which are not limited here. For example, the second width W2 can be 5 to 18 micrometers. For example, the second width W2 can be 10 to 15 micrometers. For example, the second width W2 can be 5 micrometers, the second width W2 can also be 10 micrometers, the second width W2 can also be 12 micrometers, the second width W2 can also be 15 micrometers, the second width W2 can also be 18 micrometers. For example, the first width W1 can be 4 to 15 micrometers. For example, the first width W1 is 8 to 12 micrometers. For example, the first width W1 can be 4 micrometers, the first width W1 can also be 8 micrometers, the first width W1 can also be 10 micrometers, the first width W1 can also be 12 micrometers, the first width W1 can also be 15 micrometers. For example, the size of the second sub-anode connection part YZ22 should be at least larger than the size of the via hole. For example, the size of a via hole is about 5*5 micrometers. For example, the size of a via hole is about 4*4 micrometers. For example, the size of a via hole is about 3*4 micrometers. For example, the size of a via hole is about 3*3 micrometers. For example, the size of a via hole is a circular hole with a diameter of 2 to 5 micrometers.

[0162] Exemplarily, as Figure 4eAs shown, the second sub-anode transfer portion YZ32 in the third color sub-pixel spx3 has a fifth width W5 along the first direction F1 in the orthographic projection on the substrate 10, and the second sub-anode transfer portion YZ32 in the third color sub-pixel spx3 has a sixth width W6 along the second direction F2 in the orthographic projection on the substrate 10. The ratio of W6:W5 can be set to 1.5:1. In practical applications, different third color sub-pixels spx3 have different requirements for the values of the fifth width W5 and the sixth width W6. Therefore, in combination with the condition that W6:W5 is set to 1.5:1, the values of the fifth width W5 and the sixth width W6 are set according to the actual application requirements, which are not limited herein. For example, the sixth width W6 can be 5 to 18 micrometers. For example, the sixth width W6 can be 10 to 15 micrometers. For example, the sixth width W6 can be 5 micrometers, the sixth width W6 can also be 10 micrometers, the sixth width W6 can also be 12 micrometers, the sixth width W6 can also be 15 micrometers, and the sixth width W6 can also be 18 micrometers. For example, the fifth width W5 can be 4 to 18 micrometers. For example, the fifth width W5 is 8 to 15 micrometers. For example, the fifth width W5 can be 4 micrometers, the fifth width W5 can also be 8 micrometers, the fifth width W5 can also be 10 micrometers, the fifth width W5 can also be 15 micrometers, and the fifth width W5 can also be 18 micrometers. For example, the size of the second sub-anode transfer portion YZ32 should be at least larger than the size of the via. For example, the size of a via is approximately 5*5 micrometers. For example, the size of a via is approximately 4*4 micrometers. For example, the size of a via is approximately 3*4 micrometers. For example, the size of a via is approximately 3*3 micrometers. For example, the size of a via is a circular hole with a diameter of 2 to 5 micrometers.

[0163] Exemplarily, as Figure 4e With Figure 5As shown, the second sub-anode transfer portion YZ42 in the fourth color sub-pixel spx4 has a third width W3 in the first direction F1 and a fourth width W4 in the second direction F2 in the orthographic projection on the substrate 10, and W4:W3 can be set to 2:1. For example, the center of the opening area of the fourth color sub-pixel spx4 is farther from the anode transfer portion or farther from the midpoint of the dimension of the anode transfer portion in the second direction than the centers of the opening areas of other sub-pixels (e.g., at least one of spx1, spx2, and spx3). Therefore, the dimension of the second sub-anode transfer portion YZ42 of the fourth color sub-pixel spx4 in the second direction is larger than that of other sub-pixels. For example, the dimensions of the second sub-anode transfer portions of each sub-pixel in the first direction are approximately equal. In practical applications, different third color sub-pixels spx3 have different requirements for the values of the third width W3 and the fourth width W4. Therefore, combined with the condition that W4:W3 is set to 2:1, the values of the third width W3 and the fourth width W4 are set according to actual application requirements, which are not limited herein. For example, the fourth width W4 can be 10 to 30 microns. For example, the fourth width W4 can be 14 to 25 microns. For example, the fourth width W4 can be 16 to 24 microns. For example, the fourth width W4 can be 10 microns, the fourth width W4 can also be 14 microns, the fourth width W4 can also be 16 microns, the fourth width W4 can also be 20 microns, the fourth width W4 can also be 24 microns, the fourth width W4 can also be 25 microns, and the fourth width W4 can also be 30 microns. For example, the third width W3 is 8 to 15 microns. For example, the third width W3 is 10 to 13 microns. For example, the third width W3 can be 8 microns, the third width W3 can also be 10 microns, the third width W3 can also be 12 microns, the third width W3 can also be 13 microns, and the third width W3 can also be 15 microns. Further, the dimension of the second sub-anode transfer portion YZ42 should be at least larger than the dimension of the via hole. For example, the dimension of a via hole is, for example, approximately 5*5 microns. For example, the dimension of a via hole is, for example, approximately 4*4 microns. For example, the dimension of a via hole is, for example, approximately 3*4 microns. For example, the dimension of a via hole is, for example, approximately 3*3 microns. For example, the via hole is a circular hole with a diameter of 2 to 5 microns.

[0164] Exemplarily, as Figure 4eAs shown, the anode transfer portion YZ1 in the first color sub-pixel spx1 has a seventh width W7 in the positive projection along the first direction F1 on the substrate 10, and the anode transfer portion YZ1 in the first color sub-pixel spx1 has an eighth width W8 in the positive projection along the second direction F2 on the substrate 10. The ratio of W8:W7 can be set to 1.5:1. In practical applications, the requirements for the values of the seventh width W7 and the eighth width W8 are different for different sizes of the first color sub-pixels spx1. Therefore, combined with the condition that W8:W7 is set to 1.5:1, the values of the seventh width W7 and the eighth width W8 are set according to the actual application requirements, which are not limited here. For example, the eighth width W8 can be 5 to 18 micrometers. For example, the eighth width W8 can be 10 to 15 micrometers. For example, the eighth width W8 can be 5 micrometers, the eighth width W8 can also be 10 micrometers, the eighth width W8 can also be 13 micrometers, the eighth width W8 can also be 15 micrometers, and the eighth width W8 can also be 18 micrometers. For example, the seventh width W7 can be 4 to 15 micrometers. For example, the seventh width W7 is 8 to 12 micrometers. For example, the seventh width W7 can be 4 micrometers, the seventh width W7 can also be 8 micrometers, the seventh width W7 can also be 10 micrometers, the seventh width W7 can also be 12 micrometers, and the seventh width W7 can also be 15 micrometers. For example, the size of the second sub-anode transfer portion YZ12 should be at least larger than the size of the via hole. For example, the size of a via hole is about 5*5 micrometers. For example, the size of a via hole is about 4*4 micrometers. For example, the size of a via hole is about 3*4 micrometers. For example, the size of a via hole is about 3*3 micrometers. For example, the size of a via hole is a circular hole with a diameter of 2 - 5 micrometers.

[0165] In some examples, such as Figures 3 to 5 and Figure 6cAs shown, when the second sub-pixel 02 includes the third color sub-pixel spx3, in the third color sub-pixel spx3, the orthographic projection of the main body portion Y31 on the substrate 10 overlaps with the orthographic projection of the first sub-anode transfer portion YZ31 on the substrate 10, and the orthographic projection of the main body portion Y31 on the substrate 10 overlaps with the orthographic projection of two signal lines (such as two data lines Vd) on the substrate 10. Exemplarily, in the third color sub-pixel spx3, the orthographic projection of the main body portion Y31 on the substrate 10 overlaps with the orthographic projections of the first sub-transfer portion YZ311 and the second sub-transfer portion YZ312 on the substrate 10. Exemplarily, the main body portion Y31 in the third color sub-pixel spx3 has a third main symmetry axis along the second direction F2; and, in the third color sub-pixel spx3, the center lines along the second direction F2 of the portions where the two signal lines (such as two data lines Vd) overlap with the orthographic projection of the main body portion Y31 on the substrate 10 are respectively located on the opposite sides of the third main symmetry axis from the center lines along the second direction F2 of the first sub-transfer portion YZ311 and the second sub-transfer portion YZ312. Exemplarily, the ratio of the center lines along the second direction F2 of the two signal lines (such as two data lines Vd) that overlap with the orthographic projection of the main body portion Y31 on the substrate 10 to the distances between the center lines along the second direction F2 of the first sub-transfer portion YZ311 and the second sub-transfer portion YZ312 and the third main symmetry axis is 0.8 to 1.2, and can be, for example, one of 0.8, 0.9, 1.0, 1.1, and 1.2. Further, in the third color sub-pixel spx3, the orthographic projection of the main body portion Y31 on the substrate 10 covers the orthographic projection of the signal bump portion on the substrate 10. Exemplarily, in the third color sub-pixel spx3, the signal bump portion is located on the side of the first sub-anode transfer portion YZ31 away from the second sub-anode transfer portion YZ32.

[0166] In some examples, such as Figure 3 and Figure 4eAs shown, the signal protrusion TQ includes a protrusion main body tq1 and a connection portion tq2 connecting the protrusion main body tq1 and the data line Vd. For example, the signal protrusion TQ is used for the electrical connection between the signal line and other film layers, generally through vias. For example, vias for connecting the data line Vd integrally connected thereto and other film layers are provided on the protrusion main body tq1. Therefore, its dimensions in the first direction F1 and the second direction F2 cannot be too small, at least larger than the size of the via. For example, the size of a via is, for example, 4*4 microns. For example, the size of a via is, for example, 3*3 microns. For example, the size of a via is a circular hole with a diameter of 2 to 4 microns. For example, the data signal for each sub-pixel display is transmitted on the protrusion main body tq1. In order to reduce interference with other signals, its dimensions in the first direction F1 and the second direction F2 cannot be too large. For example, in the first direction F1, there is a gap between the protrusion main body tq1 and another adjacent signal line, such as a data line, and the gap is, for example, 3 to 18 microns. For example, the gaps between the first protrusion for connecting one of the odd rows and the even rows and the second protrusion for connecting the other of the odd rows and the even rows on the same data line Vd and an adjacent other data line are different. For example, taking the signal protrusion main body tq1 for connecting the odd rows as the first protrusion T1 and the signal protrusion main body tq1 for connecting the even rows as the second protrusion T2, the spacing between the first protrusion T1 and its adjacent data line is different from the spacing between the second protrusion and its adjacent data line. For example, the first protrusion T1 and the second protrusion T2 are alternately arranged along the second direction F2 in the same column. For example, the spacing from the first protrusion T1 to an adjacent other data line is 3 to 8 microns. For example, the spacing from the second protrusion T2 to an adjacent other data line is 6 to 18 microns. For example, the sizes of the first protrusion T1 and the second protrusion T2 are substantially equal. For example, the sizes and shapes of the first protrusion T1 and the second protrusion T2 are substantially a rectangular block. For example, the dimension of the connection portion tq2 connecting the first protrusion T1 and the data line in the first direction F1 is substantially 6 to 20 microns. For example, the dimension of the connection portion tq2 connecting the second protrusion T2 and the data line in the first direction F1 is substantially 3 to 8 microns. For example, there are two adjacent data lines between two adjacent pixel circuit regions, and the protrusions corresponding to the two data lines are substantially flush, that is, they are substantially at the same height in the second direction F2, and one has the first protrusion T1 and the other has the second protrusion T2.

[0167] In some examples, such as Figures 3 to 5As shown, the ratio between the distance in the first direction F1 between the first sub-transfer part and the second sub-transfer part in the same first sub-anode transfer part and the distance in the first direction F1 between two signal lines can be 0.8 to 1.2. For example, the ratio between the distance in the first direction F1 between the first sub-transfer part and the second sub-transfer part in the same first sub-anode transfer part and the distance in the first direction F1 between two signal lines can be 0.8, 1.0, 1.1, or 1.2.

[0168] In some examples, as Figures 3 to 5 shown, the distance in the first direction F1 between the first sub-transfer part and the second sub-transfer part in the same first sub-anode transfer part is substantially the same as the distance in the first direction F1 between two signal lines. Exemplarily, in the second color sub-pixel spx2, the distance H1 in the first direction F1 between the first sub-transfer part YZ211 and the second sub-transfer part YZ212 in the same first sub-anode transfer part YZ21 is substantially the same as the distance H2 in the first direction F1 between two signal lines (such as two data lines Vd). In the third color sub-pixel spx3, the distance H1 in the first direction F1 between the first sub-transfer part YZ311 and the second sub-transfer part YZ312 in the same first sub-anode transfer part YZ31 is substantially the same as the distance H2 in the first direction F1 between two signal lines (such as two data lines Vd). In the fourth color sub-pixel spx4, the distance H1 in the first direction F1 between the first sub-transfer part YZ411 and the second sub-transfer part YZ412 in the same first sub-anode transfer part YZ41 is substantially the same as the distance H2 in the first direction F1 between two signal lines (such as two data lines Vd).

[0169] Exemplarily, the distance H2 can be set to 5 to 7 μm. For example, the distance H2 can be set to 5 μm, or the distance H2 can be set to 6 μm, or the distance H2 can be set to 7 μm. Of course, in actual applications, the specific value of the distance H2 can be determined according to the requirements of actual applications, which is not limited herein.

[0170] Exemplarily, the distance H1 can be set to 5 to 6 μm. For example, the distance H1 can be set to 5 μm, or the distance H1 can be set to 5.5 μm, or the distance H1 can be set to 6 μm. Of course, in actual applications, the specific value of the distance H1 can be determined according to the requirements of actual applications, which is not limited herein.

[0171] Based on the same inventive concept, embodiments of the present disclosure further provide a display device, including the above-mentioned electroluminescent display substrate provided by the embodiments of the present disclosure. The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television set, a monitor, a laptop computer, a digital photo frame, a navigator, etc. Other essential components of the display device are understood by those of ordinary skill in the art and will not be elaborated here, nor should they be regarded as a limitation to the present disclosure. The implementation of the display device may refer to the embodiments of the above-mentioned electroluminescent display substrate, and the repeated parts will not be elaborated.

[0172] Although the preferred embodiments of the present disclosure have been described, those skilled in the art can make additional changes and modifications to these embodiments once they know the basic creative concept. Therefore, the appended claims are intended to be construed to include the preferred embodiments as well as all changes and modifications falling within the scope of the present disclosure.

[0173] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure also intends to include these changes and modifications.

Claims

1. A display substrate, wherein, Including: A plurality of sub-pixels, at least one of the plurality of sub-pixels including: a pixel circuit and a light-emitting element located on a substrate, the pixel circuit including a driving transistor for driving the light-emitting element to emit light; The display substrate includes an active semiconductor layer; the driving active layer of the driving transistor is located in the active semiconductor layer; The driving gate in the driving transistor is electrically connected to the active semiconductor layer through a driving via; A first conductive layer, located on a side of the active semiconductor layer away from the substrate, and the first conductive layer includes an anode transfer portion and a signal line arranged at intervals; In the sub-pixel, at least a part of the driving via in the orthographic projection on the substrate does not overlap with the orthographic projections of the anode transfer portion and the signal line on the substrate; The display substrate further includes: A first insulating layer, located on a side of the first conductive layer away from the substrate, and the first insulating layer includes a first via, and at least a part of the anode transfer portion is exposed by the first via; The light-emitting element includes an anode, the anode is located on a side of the first insulating layer away from the substrate, and the anode includes a main body portion and an auxiliary portion that are electrically connected to each other; wherein, the auxiliary portion is electrically connected to the anode transfer portion through the first via; Wherein, the plurality of sub-pixels include a first sub-pixel and a second sub-pixel; In the first sub-pixel, the orthographic projection of the anode transfer portion on the substrate does not overlap with the orthographic projection of the driving active layer on the substrate, and the orthographic projection of the main body portion on the substrate does not overlap with the orthographic projection of the anode transfer portion on the substrate; In the second sub-pixel, the orthographic projection of the anode transfer portion on the substrate overlaps with the orthographic projection of the driving active layer on the substrate, and the orthographic projection of the main body portion on the substrate overlaps with the orthographic projection of the anode transfer portion on the substrate.

2. The display substrate according to claim 1, wherein, The anode transfer portion in the second sub-pixel includes: a first sub-anode transfer portion and a second sub-anode transfer portion that are electrically connected to each other; wherein, the first sub-anode transfer portion has a hollow structure, and the second sub-anode transfer portion has a solid structure; the auxiliary portion is electrically connected to the second sub-anode transfer portion through the first via; In the second sub-pixel, the orthographic projection of the first sub-anode transfer portion on the substrate overlaps with the orthographic projection of the driving active layer on the substrate.

3. The display substrate according to claim 2, wherein The display substrate further includes: a gate conductive layer located between the active semiconductor layer and the first conductive layer, the gate conductive layer including: a scan line; In a direction parallel to the substrate, in the same second sub-pixel, the orthographic projection of the scan line on the substrate is located on a side of the orthographic projection of the driving active layer on the substrate away from the orthographic projection of the second sub-anode transfer portion on the substrate; In the second sub-pixel, the orthographic projection of the first sub-anode transfer portion on the substrate overlaps with the orthographic projection of the scan line on the substrate.

4. The display substrate according to claim 3, wherein, In the second sub-pixel, the orthographic projection of the hollow area in the hollow structure in the first sub-anode transfer portion on the base substrate overlaps with the orthographic projection of the driving via on the base substrate.

5. The display substrate according to claim 4, wherein, The first sub-anode transition portion comprises a first sub-transition portion and a second sub-transition portion which are arranged opposite to each other; In the second sub-pixel, the orthographic projection of the main body portion on the base substrate overlaps with the orthographic projections of two signal lines on the base substrate; Furthermore, in the first direction, the orthographic projection of the first sub-transfer portion on the base substrate is located between the orthographic projections of the second sub-transfer portion and the two signal lines on the base substrate.

6. The display substrate according to claim 5, wherein, At least one of the plurality of repeating units includes: a first color sub-pixel, a second color sub-pixel, a third color sub-pixel, and a fourth color sub-pixel; wherein the plurality of repeating units are arranged along a first direction to form a repeating unit group, and the repeating unit group is arranged along a second direction, and the first direction is different from the second direction; The first sub-pixel includes the first color sub-pixel; The second sub-pixel includes at least one of a second color sub-pixel, a third color sub-pixel, and the fourth color sub-pixel.

7. The display substrate according to claim 6, wherein, The second sub-pixel includes the second color sub-pixel; In the second color sub-pixel, an orthographic projection of the main body portion on the base substrate overlaps with an orthographic projection of the first sub-anode transfer portion on the base substrate.

8. The display substrate according to claim 7, wherein In the second color sub-pixel, an orthographic projection of the main body portion on the base substrate overlaps with both orthographic projections of the first sub-transfer portion and the second sub-transfer portion on the base substrate.

9. The display substrate according to claim 8, wherein, The main body portion of the second color sub-pixel has a second main body symmetry axis along the second direction; In the second color sub-pixel, the center lines of the two signal lines at the parts overlapping with the orthographic projection of the main body on the base substrate along the second direction and the center lines of the first sub-transfer portion and the second sub-transfer portion along the first direction are respectively located on opposite sides of the second main body symmetry axis.

10. The display substrate according to claim 9, wherein, The second sub-pixel includes the fourth color sub-pixel; In the fourth color sub-pixel, the orthographic projection of the main part on the base substrate overlaps with the orthographic projection of the second sub-anode transfer portion on the base substrate, and the orthographic projection of the main part on the base substrate overlaps with the orthographic projections of the two signal lines on the base substrate.

11. The display substrate according to claim 10, wherein, In the second direction, in the fourth color sub-pixel, at least part of the main portion has an orthographic projection on the base substrate located on a side of the orthographic projection of the second sub-anode transition portion on the base substrate away from the orthographic projection of the first sub-anode transition portion on the base substrate.

12. The display substrate according to claim 11, wherein, The main body portion of the fourth color sub-pixel has a fourth main body symmetry axis along the second direction; In the fourth color sub-pixel, the part where the two signal lines overlap with the main part on the orthographic projection of the base substrate, and the center line along the second direction and the center line of the second sub-anode transition part along the second direction are respectively located on two opposite sides of the fourth main body symmetry axis.

13. The display substrate according to claim 12, wherein, Each of the signal lines further includes a signal protrusion; the two signal lines include a first signal line and a second signal line; wherein, one column of sub-pixels corresponds to one first signal line and one second signal line; the signal protrusions of the first signal line are electrically connected to the sub-pixels in odd rows respectively, and the signal protrusions of the second signal line are electrically connected to the sub-pixels in even rows respectively; The second color sub-pixel and the fourth color sub-pixel in the repeating units adjacent along the second direction are adjacent along the second direction; Along the second direction, the orthographic projection of the main body part of the fourth color sub-pixel on the substrate overlaps with the orthographic projection of the signal protrusion of the adjacent second color sub-pixel on the substrate.

14. The display substrate according to claim 13, wherein, Each of the signal lines further includes a signal protrusion; the two signal lines include a first signal line and a second signal line; wherein, one column of sub-pixels corresponds to one first signal line and one second signal line; the signal protrusions of the first signal line are electrically connected to the sub-pixels in odd rows respectively, and the signal protrusions of the second signal line are electrically connected to the sub-pixels in even rows respectively; Among the two first signal lines and the two second signal lines corresponding to two adjacent columns of sub-pixels, two of the first signal lines are adjacent to form a first signal line group, or two of the second signal lines are adjacent to form a second signal line group.

15. The display substrate according to claim 14, wherein, The area of the orthographic projection of the second sub-anode transfer part of one fourth color sub-pixel on the substrate is larger than the area of the orthographic projection of the second sub-anode transfer part of one second color sub-pixel on the substrate.

16. The display substrate according to claim 15, wherein, The orthographic projection of the second sub-anode transfer part of the second color sub-pixel on the substrate has a second width along the second direction, and the orthographic projection of the second sub-anode transfer part of the fourth color sub-pixel on the substrate has a fourth width along the second direction; The fourth width is greater than the second width.

17. The display substrate according to claim 16, wherein, The second sub-pixel includes the third color sub-pixel; In the third color sub-pixel, the orthographic projection of the main body part on the substrate overlaps with the orthographic projection of the first sub-anode transfer part on the substrate, and the orthographic projection of the main body part on the substrate overlaps with the orthographic projections of the two signal lines on the substrate.

18. The display substrate according to claim 17, wherein, In the third color sub-pixel, the orthographic projection of the main body part on the substrate overlaps with the orthographic projections of both the first sub-transfer part and the second sub-transfer part on the substrate.

19. The display substrate according to claim 18, wherein, The main body part of the third color sub-pixel has a third main symmetry axis along the second direction; In the third color sub-pixel, the center lines along the second direction of the overlapping parts of the two signal lines and the main body part on the substrate are respectively located on the opposite sides of the third main symmetry axis from the center lines along the second direction of the first sub-transfer part and the second sub-transfer part.

20. The display substrate according to claim 19, wherein, In the third color sub-pixel, the orthographic projection of the main body part on the substrate covers the orthographic projection of the signal protrusion on the substrate.

21. The display substrate according to claim 20, wherein, In the third color sub-pixel, the signal protrusion is located on the side of the first sub-anode transfer part away from the second sub-anode transfer part.

22. The display substrate according to claim 21, wherein, In the first color sub-pixel, the orthographic projection of the main body portion on the substrate overlaps the orthographic projections of the two signal lines on the substrate, and the orthographic projection of the main body portion on the substrate does not overlap the orthographic projections of the anode connection portion and the signal protrusion portion on the substrate.

23. The display substrate according to claim 22, wherein, The main body portion in the first color sub-pixel has a first main body symmetry axis along the second direction; In the first color sub-pixel, in the second direction, the two signal lines overlapping the orthographic projection of the main body portion on the substrate are respectively located on opposite sides of the first main body symmetry axis.

24. The display substrate according to claim 23, wherein, The ratio of the distance between the first sub-connection portion and the second sub-connection portion in the first direction in the same first sub-anode connection portion to the distance between the two signal lines in the first direction is 0.8 to 1.

2.

25. The display substrate according to claim 1, wherein, The signal line is configured as a data line for transmitting data signals.

26. A display device, wherein, It includes the display substrate according to any one of claims 1-25.

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