System and method for verifying multi-level caches

Abstract

This application provides a system and method for verifying multi-level caches, relating to the field of computer technology. The system includes: a cache reference model; multiple bus functional models, each including an interface connecting the design under test (DUT) and the cache reference model, which send test cases in the form of bus transactions to both the DUT and the cache reference model, wherein the DUT is a cache system including a multi-level cache; and a verification module that compares and verifies the data in the memory of both the cache system and the cache reference model after running the test cases, determining whether they meet the requirements. The system provided in this application treats the entire cache system including the multi-level cache as the DUT for testing and verification, achieving a high degree of decoupling between the verification system and the cache design, effectively improving the versatility of the verification system.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more specifically, to a system, method, and computer-readable storage medium for verifying multi-level caches. Background Technology

[0002] In the design of central processing units (CPUs) and system-on-chips (SoCs), caches are typically introduced to improve bandwidth and latency. As multi-level caches become increasingly complex, their verification faces significant challenges, such as how to decouple the verification system from the cache design to improve the versatility of the verification system. Summary of the Invention

[0003] This application provides a system, method, and computer-readable storage medium for verifying multi-level caches, aiming to solve at least one technical problem in the prior art.

[0004] According to a first aspect of the embodiments of this application, a system for verifying a multi-level cache is provided, the system comprising:

[0005] The design under test is a cache system that includes multi-level caches;

[0006] Cache reference model;

[0007] Multiple bus function models, including interfaces connecting the cache system and the cache reference model, send test cases in the form of bus transactions to the cache system and the cache reference model respectively;

[0008] The verification module compares and verifies the data in the memory of the cache system and the cache reference model after running test cases to determine whether they meet the requirements.

[0009] In one possible implementation, the bus function model is used to initiate read or write requests to any level of cache, send the read or write requests to the cache reference model in the form of a bus transaction, and convert the bus transaction into the interface timing of the cache level and send it to the cache level in the cache system.

[0010] In another possible implementation, the bus function model is used to receive read data returned by the cache reference model and the cache system respectively according to the read request, and compare whether the two are consistent.

[0011] In another possible implementation, the cache system is configured to receive read or write requests from the bus function model, send read or write requests to the memory configured therewith, receive read data returned by the memory, and update the data of the memory configured therewith according to the address and write data in the write request.

[0012] In another possible implementation, the bus function model is also used to store information from the cache system and the cache reference model into a trace log;

[0013] The information includes read data, the address of the read data, and response information for the read request; or, the information includes write data, the address of the write data, and response information for the write request.

[0014] In another possible implementation, the cache system includes: a level 1 instruction cache, a level 1 data cache, and a level 2 cache.

[0015] According to a second aspect of the embodiments of this application, a method for verifying a multi-level cache is provided, the method comprising:

[0016] Multiple bus function models will send test cases in the form of bus transactions to the design under test and the cache reference model respectively, wherein the design under test is a cache system including a multi-level cache;

[0017] The verification module compares and verifies the data in the memory of the cache system and the cache reference model after running test cases to determine whether they meet the requirements.

[0018] In one possible implementation, the multiple bus function models will send test cases in the form of bus transactions to the cache system of the design under test and the cache reference model, including:

[0019] The bus function model initiates a read or write request to any level of cache, sends the read or write request to the cache reference model in the form of a bus transaction, and converts the bus transaction into the interface timing of that level of cache and sends it to that level of cache in the cache system.

[0020] In yet another possible implementation, the method further includes:

[0021] The bus function model receives read data returned by the cache reference model and the cache system respectively according to the read request, and compares whether the two are consistent.

[0022] In another possible implementation, the method further includes:

[0023] The cache system receives read or write requests from the bus function model, sends read or write requests to the memory configured with the cache system, receives read data returned by the memory, and updates the data in the memory configured with the cache system according to the address and write data in the write request.

[0024] In another possible implementation, the bus function model stores information from the cache system and the cache reference model in a trace log;

[0025] The information may include read data, the address of the read data, and a response to the read request; or the information may include write data, the address of the write data, and a response to the write request.

[0026] According to a third aspect of the embodiments of this application, a computer device is provided, including: a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the verification method for the multi-level cache shown in the second aspect above.

[0027] According to a fourth aspect of the embodiments of this application, a computer-readable storage medium is provided, wherein when the computer program is executed by a processor, it implements the steps of the verification method for the multi-level cache shown in the second aspect above.

[0028] The beneficial effects of the technical solutions provided in this application are:

[0029] Because the verification system treats the entire cache system, including multiple levels of caches, as the design under test for testing and verification, rather than isolating the first-level or second-level caches in the multi-level cache system and treating them as separate designs under test for testing and verification, it achieves a high degree of decoupling between the verification system and the cache design. This verification system is applicable to the testing of different cache systems, and has wider universality and stronger versatility. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments of this application will be briefly introduced below.

[0031] Figure 1 A schematic diagram of a system for verifying a multi-level cache is provided in this application embodiment;

[0032] Figure 2 A schematic diagram of a system for verifying a multi-level cache is provided as another embodiment of this application;

[0033] Figure 3 An exemplary structural diagram of a system for verifying multi-level caches is provided in an embodiment of this application;

[0034] Figure 4 A flowchart illustrating a verification method for a multi-level cache provided in this application embodiment;

[0035] Figure 5 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0036] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions of the embodiments of this application.

[0037] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0038] A cache is a small but high-speed buffer located between the CPU and main memory (DRAM, or Dynamic Random Access Memory). It is typically composed of SRAM (Static Random Access Memory). The function of the cache is to improve the CPU's data input / output speed. The CPU's general-purpose registers are much faster than main memory. When the CPU directly accesses data from main memory, it has to wait for a certain period. The cache, however, can store data that the CPU has just used or that is used repeatedly. If the CPU needs to use this data again, it can retrieve it directly from the cache. This avoids repeated data access, reduces CPU waiting time, and thus improves system efficiency.

[0039] Multi-level caches include L1 cache (Level 1 cache), L2 cache (Level 2 cache), and L3 cache (Level 3 cache). L1 cache is primarily integrated within the CPU, while L2 cache is integrated on the motherboard or CPU. L1 cache includes L1I-cache (Level 1 instruction cache) and L1D-cache (Level 1 data cache). L1I-cache stores instructions, while L1D-cache stores data. The difference is that data in L1D-cache can be written back, while data in L1I-cache is read-only.

[0040] In CPU and SoC design, caches are typically introduced to improve bandwidth and latency. As multi-level caches become increasingly complex, their verification faces significant challenges, such as: how to decouple the verification system from the cache design to improve the versatility of the verification system; how to implement automatic error comparison; and how to improve localization efficiency. Current technologies often treat the L1 and L2 caches in a multi-level cache as independent designs under test, resulting in deep coupling between the verification system and the cache design, thus affecting the versatility of the verification system.

[0041] To address the aforementioned issues, this application proposes a system for verifying multi-level caches. This verification system is highly decoupled from the cache design, has high versatility, can automatically compare and report errors, and can also improve the location efficiency by leveraging trace logs.

[0042] The technical solutions of this application and their effects are described below through several exemplary embodiments. It should be noted that the following embodiments can be referenced, borrowed from, or combined with each other. Identical terms, similar features, and similar implementation steps in different embodiments will not be repeated.

[0043] The "verification" referred to in this paper involves applying test cases to the DUT (design-under-test) and comparing the results with expected results to determine whether the DUT works correctly. In this application, the DUT is a two-level cache subsystem, including L1 I-cache, L1 D-cache, and L2 cache. The entire cache system is treated as the DUT during verification, rather than isolating the L1 cache or L2 cache for verification. This achieves a high degree of decoupling between the verification system and the cache design.

[0044] BFM (Bus Functional Model): Functional verification of the logical design of a standardized bus interface typically involves using BFM software tools. BFM emulates the bus protocol to apply test cases from the simulation to the Device Under Test (DUT). BFM allows verification engineers to write test cases as bus transactions. Bus transactions can be represented using Bus Functional Language (BFL) statements. BFM describes the behavior of the device at the interface level; that is, it does not model the internal operations of the device. This application includes several BFM types: IFU BFM (Instruction fetch unit BFM) and LSU BFM (Load store unit BFM). IFU BFM is used to access the Level 1 instruction cache to retrieve and verify the contents of instructions; LSU BFM is used to access the Level 1 data cache and Level 2 cache to retrieve and verify data.

[0045] Cache RM (reference model): Used in conjunction with IFU BFM and LSU BFM to verify the correctness of data retrieved or stored based on memory access instructions.

[0046] Memory BFM (Memory-bus functional model): Used to return or store data based on memory access instructions from the cache system.

[0047] This application provides a system for verifying multi-level caches, comprising: a cache reference model, various bus function models, and a verification module.

[0048] Multiple bus function models are provided, including interfaces connecting the design under test (DUT) and the cache reference model. Test cases are sent to the DUT and the cache reference model respectively in the form of bus transactions. The DUT is a cache system including multi-level caches.

[0049] The verification module compares and verifies the data in the memory of the cache system and the cache reference model after running test cases to determine whether they meet the requirements.

[0050] In one possible embodiment, when multiple bus function models initiate a read request or write request to any level of cache, they are used to send the read request or write request to the cache reference model in the form of a bus transaction, and convert the bus transaction into the interface timing of that level of cache and send it to that level of cache in the cache system.

[0051] In another possible embodiment, multiple bus function models are also used to receive read data returned by the cache reference model and the cache system respectively according to the read request, and compare whether the two are consistent.

[0052] In some embodiments, a cache system is configured to receive read or write requests from a bus function model, send read or write requests to memory configured with the cache system, receive read data returned by the memory, and update data in the memory configured with the cache system according to the address and write data in the write request.

[0053] In other embodiments, to provide location efficiency, the bus function model is also used to store information from the cache system and the cache reference model into a trace log. This information includes read data, the address of the read data, and response information for read requests; or, the information includes write data, the address of the write data, and response information for write requests.

[0054] In embodiments of this application, the cache system may include: a level 1 instruction cache, a level 1 data cache, and a level 2 cache.

[0055] The following is combined Figures 1 to 3 This application provides a detailed description of a system for verifying multi-level caches.

[0056] Figure 1 This is a schematic diagram of a system for verifying a multi-level cache, provided as an embodiment of this application. Figure 1 The system 10 shown includes: IFU BUF module 101, LSUBFM module 102, and Cache RM module 103. The design under test (DUT) 20 is a cache system including multiple levels of caches.

[0057] IFU BFM module 101 is used to send read requests for the target cache in DUT 20 to DUT 20 and Cache RM module 103 respectively, and to compare and verify the read data from DUT 20 and Cache RM module 103.

[0058] LSU BFM module 102 is used to send read requests for the target cache to DUT 20 and Cache RM module 103 respectively, and to compare and verify the read data from DUT 20 and Cache RM module 103.

[0059] The Cache RM module 103 is used to receive read requests from the IFU BFM module 101 or the LSU BFM module 102 and return the read data.

[0060] In this embodiment, the entire cache system, including multi-level caches, is considered as the Design Under Test (DUT). The IFUBFM module 101 can send read requests for the target cache in the DUT to both the DUT 20 and the Cache RM module 103, and compare the read data from the DUT and the Cache RM module 103. If the read data from the DUT 20 and the Cache RM module 103 are different, an error is reported. Similarly, the LSUBFM module 102 can send read requests for the target cache in the DUT 20 to both the DUT and the Cache RM module 103, and compare the read data from the DUT and the Cache RM module 103. If the read data from the DUT 20 and the Cache RM module 103 are different, an error is reported.

[0061] The verification system provided in this application verifies the entire cache system, including multi-level caches, as a DUT for testing and verification, rather than isolating a first-level or second-level cache in the multi-level cache and verifying them separately as DUTs. Therefore, it achieves a high degree of decoupling between the verification system and the cache design. This verification system is applicable to the testing of different cache systems, has wider universality and stronger versatility, and can also achieve automatic comparison and error reporting.

[0062] Specifically, in this embodiment, the IFU BFM module 101 or the LSU BFM module 102 can also send the read request to the Cache RM module 103 in the form of a bus transaction, and then send the bus transaction to the DUT 20 after converting it into the interface timing of the target cache. The transaction information may include the address of the data to be read.

[0063] It should be noted that, in this embodiment, the specific process by which the IFUBFM module or LSUBFM module converts bus transactions into the interface timing of the target cache can be implemented using existing related technologies, and will not be elaborated here for the sake of brevity.

[0064] Since the IFU BFM module or LSU BFM module can convert bus transactions into the interface timing of the target cache and then send them to the multi-level cache, the functionality of the multi-level cache is transparent to the IFU BFM module or LSU BFM module. In this way, the Cache RM module can be highly abstracted into a memory model, which greatly simplifies the development cost of the reference model.

[0065] Figure 2This is a schematic diagram of a verification system for verifying multi-level caches, provided as another embodiment of this application. The diagram is related to... Figure 1 Modules with the same or similar functions are represented by the same labels, and will not be described again. For example... Figure 2 The verification system 10 shown includes: IFU BFM module 101, LSU BFM module 102, Cache RM module 103 and memory BFM module 104 configured with DUT 20, wherein the memory BFM module 104 is used to receive read requests from DUT 20 and return read data.

[0066] In this embodiment, when the DUT 20 receives a read request for the target cache from the IFU BFM module 101 or the LSU BFM module 102, it can send the received read request to the memory BFM module 104. The memory BFM module 104 reads the data according to the received read request and returns it to the DUT 20. The DUT 20 can then return the read data to the IFU BFM module 101 or the LSU BFM module 102.

[0067] This application provides one possible implementation method, such as... Figure 2 The verification system 10 shown also includes: a verification module 105, wherein,

[0068] The LSUBFM module 101 is also used to send write requests for the target cache to the DUT 20 and the Cache RM module 103, respectively.

[0069] The Cache RM module 103 is also used to update the contents of the memory 1031 of the Cache RM module 103 based on the received write requests.

[0070] The memory BFM module 104 is also used to receive write requests from the DUT 20 and update the contents of memory 1041 of the memory BFM module 104 based on the write requests.

[0071] Verification module 105 is used to compare and verify the contents in memory 1031 of Cache RM module 103 with the contents in memory 1041 of memory BFM module 104.

[0072] Specifically, in this embodiment, the LSUBFM module 102 can send write requests to the Cache RM module 103 in the form of a bus transaction, and then convert the bus transaction into the interface timing of the target cache before sending it to the DUT 20. The transaction information may include the write data and the address of the write data.

[0073] It should be noted that, in this embodiment, the specific process by which the LSUBFM module converts bus transactions into the interface timing of the target cache can be implemented using existing related technologies, and will not be elaborated here for the sake of brevity.

[0074] This application provides a possible implementation method in which the IFUBFM module 101 or the LSUBFM module 102 is further used to store information from the DUT 20 and the Cache RM module 103 into a trace log.

[0075] The information includes read data, the address of the read data, and response information for the read request; or, the information includes write data, the address of the write data, and response information for the write request.

[0076] Specifically, in this embodiment, the IFUBFM module 101 can store read data, read data addresses, and response information for read requests from the DUT 20 and Cache RM module 103 into the trace log; the LSUBFM module 102 can store read data, read data addresses, and response information for read requests from the DUT 20 and Cache RM module 103 into the trace log; or, the LSUBFM module 102 can store write data, write data addresses, and response information for write requests from the DUT 20 and Cache RM module 103 into the trace log. By writing key information related to read / write requests into the trace log, keyword searches can be performed, which helps in locating and facilitating the viewing of historical information.

[0077] In the above embodiments, if the IFUBFM module sends a read request, the target cache is the Level 1 instruction cache (L1 I-cache) in a multi-level cache. If the LSUBFM module sends a read request or a write request, the target cache includes the Level 1 data cache (L1 D-cache) and the Level 2 cache (L2 cache) in a multi-level cache.

[0078] Specifically, in the above embodiment, the IFU BFM module 101 is specifically used to send read requests to the Cache RM module in the form of bus transactions, and to convert the bus transactions into the interface timing of the first-level instruction cache and send them to the multi-level cache.

[0079] The LSUBFM module 102 is specifically used to send read or write requests to the Cache RM module in the form of bus transactions, and to convert the bus transactions into the interface timing of the first-level data cache and send them to the multi-level cache.

[0080] Alternatively, LSUBFM module 102 is specifically used to send read or write requests to the Cache RM module in the form of bus transactions, and to convert the bus transactions into interface timings for the secondary cache and send them to the multi-level cache.

[0081] Figure 3 This is an exemplary structural diagram of a system for verifying a multi-level cache, provided as an embodiment of this application. The following is in conjunction with… Figure 3 Taking a secondary cache as an example of a DUT, the system 30 provided in this application embodiment will be described in detail.

[0082] DUT is a two-level cache20, which includes L1 I-cache, L1 D-cache and L2cache.

[0083] The IFU BFM module 301 initiates a read request to the L1 I-cache. This read request is sent to the Cache RM (reference model) module 303 in the form of a transaction. At the same time, the IFU BFM module 301 converts the transaction into the L1 I-cache interface timing and sends it to the DUT 20. In addition, the IFU BFM module 301 obtains the read data from the DUT 20 and the Cache RM module 303 and compares the two. If they are different, the IFU BFM module 301 will report an error.

[0084] LSU BFM module 302 initiates a read / write request to L1 D-cache. This read / write request is sent to Cache RM module 303 in the form of a transaction. At the same time, IFU BFM module converts the transaction into L1 D-cache interface timing and sends it to DUT 20. In addition, LSU BFM module 302 obtains read data from DUT 20 and Cache RM module 303 and compares the two. If they are different, LSU BFM module 302 will report an error.

[0085] The Cache RM module 303 receives read / write requests from the IFU BFM module 301 or the LSU BFM module 302. For read requests, the Cache RM module 303 returns the read data to the IFU BFM module 301 and the LSU BFM module 302; for write requests, the Cache RM module 303 updates the content of memory 3031 according to the address and write data of the write request. For example, an array can be used to update the content of the memory.

[0086] The memory BFM module 304 receives read / write requests from the DUT 20. For a read request, the memory BFM module 304 returns the read data to the DUT 20; for a write request, the memory BFM module 304 updates the content of memory 3041 according to the address of the write request and the write data. For example, an array can be used to update the content of the memory.

[0087] After the test is completed, the verification module (Checker) 305 will use a backdoor to compare the contents of memory 3031 in the Cache RM module 303 with the contents of memory 3041 in the memory BFM module 304. If the two are different, Checker 305 will report an error.

[0088] To improve location efficiency, the IFU BFM module and LSU BFM module can write received information from the DUT and Cache RM modules to a trace log. This information can include addresses, read data, and write data. The advantage of using a trace log is that it allows for keyword searching, making it easy to view historical information.

[0089] This verification system tests the entire cache system as a DUT, rather than isolating L1 cache or L2 cache as separate DUTs. The advantages of this approach are: the verification system is highly decoupled from the cache design and implementation; the verification system is applicable to testing different cache systems, improving its versatility; and by treating the cache as a performance-enhancing component whose functionality is transparent to IFU / LSU, the cache RM module can be highly abstracted into a memory model, greatly simplifying reference model development.

[0090] Figure 4 This is a flowchart illustrating a verification method for a multi-level cache provided in an embodiment of this application. Figure 4 The method shown can be applied to the system for verifying multi-level caches shown in the above embodiments, and the method includes:

[0091] S401. Multiple bus function models will send test cases in the form of bus transactions to the design under test and the cache reference model respectively. The design under test is a cache system including a multi-level cache.

[0092] S402. The verification module compares and verifies the data in the memory of the cache system and the cache reference model after running test cases to determine whether they meet the requirements.

[0093] In the above embodiments, since the verification system tests and verifies the entire cache system, including multi-level caches, as a DUT, rather than isolating the L1 cache or L2 cache in the multi-level cache as separate DUTs, the verification system is highly decoupled from the cache design. This verification system is applicable to the testing of different cache systems, and has wider applicability and stronger versatility.

[0094] In some embodiments, S401 may specifically include: the bus function model initiating a read request or write request to any level of cache, sending the read request or write request to the cache reference model in the form of a bus transaction, and converting the bus transaction into the interface timing of the cache level and sending it to the cache level in the cache system.

[0095] Specifically, in this embodiment, the bus function module can be an LSUBFM module. The LSUBFM module can send write requests for the target cache to both the DUT and the Cache RM module. Based on the received write requests, the Cache RM module updates the data in its memory. The memory BFM module updates the data in its memory based on the write requests from the DUT. Then, the verification module compares the data in the memory of the Cache RM module with the data in the memory of the memory BFM module. If the data in the two memories are different, the verification module reports an error.

[0096] One alternative approach is that, after the test is completed, the verification module can compare the data in the memory of the Cache RM module with the data in the memory of the memory BFM module via a backdoor. If the two are different, an error will be reported.

[0097] Specifically, in this embodiment, the LSUBFM module sends the write request to the Cache RM module in the form of a bus transaction, and then converts the bus transaction into the interface timing of the target cache before sending it to the DUT. The transaction information may include the write data and the address of the write data.

[0098] Alternatively, the IFUBFM or LSUBFM module may send read requests to the Cache RM module as a bus transaction, which is then converted into the target cache's interface timing before being sent to the DUT. The transaction information may include the address of the data to be read.

[0099] It should be noted that, in this embodiment, the specific process by which the IFUBFM module or LSUBFM module converts bus transactions into the interface timing of the target cache can be implemented using existing related technologies, and will not be elaborated here for the sake of brevity.

[0100] In another embodiment, the above method may further include:

[0101] The bus function model receives read data returned by the cache reference model and the cache system respectively based on the read request, and compares whether the two are consistent.

[0102] Specifically, in this embodiment, the bus function module can be an IFUBFM module. The IFUBFM module can send read requests for the target cache in the DUT to the DUT and the Cache RM module respectively, and compare the read data from the DUT and the Cache RM module. If they are different, an error will be reported.

[0103] Alternatively, the bus function module can be an LSUBFM module. In this case, the LSUBFM module can send read requests for the target cache in the DUT to both the DUT and the Cache RM module, and compare the read data from the DUT and the Cache RM module. If they are different, an error will be reported.

[0104] The verification method provided in this application embodiment tests and verifies the entire cache system, including multi-level caches, as a DUT, rather than isolating a first-level or second-level cache in the multi-level cache and verifying them separately as DUTs. Therefore, it achieves a high degree of decoupling between the verification system and the cache design. This verification system is applicable to the testing of different cache systems, has wider universality and stronger versatility, and can also achieve automatic comparison and error reporting.

[0105] In another possible implementation, the method also includes:

[0106] The cache system receives read or write requests from the bus function model, sends read or write requests to the memory configured with the cache system, receives read data returned by the memory, and updates the data in the memory configured with the cache system according to the address and write data in the write request.

[0107] Specifically, in this embodiment, after receiving a read request, the cache system can transmit the read request to the memory BFM module configured with it, and return the read data returned by the memory BFM module to the IFUBFM module or the LSUBFM module.

[0108] In other words, if the cache system receives a read request for the target cache from the IFUBFM module of the verification system, it can retrieve the read data based on the received read request and return it to the IFUBFM module. The IFUBFM module then compares the read data from the DUT and Cache RM modules; if they are different, an error is reported. Similarly, if the cache system receives a read request for the target cache from the LSUBFM module of the verification system, it can retrieve the read data based on the received read request and return it to the LSUBFM module. The LSUBFM module then compares the read data from the DUT and Cache RM modules; if they are different, an error is reported.

[0109] If the cache system receives a write request for the target cache from the LSUBFM module of the verification system, it can transmit the write request to the memory BFM module of the verification system so that the memory BFM module can update the data in its memory based on the write request.

[0110] This application provides a possible implementation method, which further includes:

[0111] The bus function model stores information from the cache system and the Cache RM module in the trace log.

[0112] The information includes read data, the address of the read data, and the response to the read request; or, the information includes write data, the address of the write data, and the response to the write request.

[0113] Specifically, in this embodiment, if the bus function model is an IFUBFM module, the IFUBFM module can store read data from the DUT and Cache RM modules, the address of the read data, and the response to the read request in the trace log. If the bus function model is an LSUBFM module, if a read request is initiated to the target cache, the read data from the DUT and Cache RM modules, the address of the read data, and the response to the read request can be stored in the trace log; if a write request is initiated to the target cache, the write data from the DUT and Cache RM modules, the address of the write data, and the response to the write request can be stored in the trace log. By writing key information related to read / write requests into the trace log, keyword searching can be performed, which helps in locating and facilitating the viewing of historical information.

[0114] It should be understood that, in this embodiment, the read data from the DUT is returned by the memory BFM module.

[0115] It should also be understood that information from the DUT and Cache RM modules can be in the form of bus transactions.

[0116] In the above embodiments, if the IFUBFM module sends a read request, the target cache is the first-level instruction cache in a multi-level cache.

[0117] If the LSUBFM module sends a read request or a write request, the target cache includes the first-level data cache and the second-level cache in a multi-level cache.

[0118] Specifically, in this embodiment, the IFUBFM module can initiate a read request to the Level 1 Instruction Cache (L1 I-cache) in the multi-level cache and transmit the read request to the multi-level cache and the Cache RM module respectively.

[0119] The IFUBFM module can initiate read / write requests to the Level 1 Data Cache (L1 D-cache) or Level 2 Cache (L2 cache) in a multi-level cache, and transmit the read / write requests to the multi-level cache and the Cache RM module respectively.

[0120] In summary, the verification method for multi-level caches provided in this application verifies the entire cache system, including the multi-level cache, as a DUT for testing and verification, rather than isolating the L1 cache or L2 cache in the multi-level cache and verifying them separately as DUTs. Therefore, it achieves a high degree of decoupling between the verification system and the cache design. This verification system is applicable to the testing of different cache systems, has wider universality and stronger versatility, and can also achieve automatic comparison and error reporting.

[0121] It should be noted that the division of units in the embodiments of this application is illustrative and only represents one logical functional division. In actual implementation, other division methods may be used. Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated units described above can be implemented in hardware or as software functional units.

[0122] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a processor-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0123] This application provides a computer device including memory, a processor, and a computer program stored in the memory. The processor executes the computer program to implement the steps of the calibration method provided in this application. Compared with the prior art, it can achieve the following: Since the verification system tests and verifies the entire cache system including multi-level caches as a DUT, instead of isolating the L1 cache or L2 cache in the multi-level cache as separate DUTs, the design of the verification system and the cache is highly decoupled. This verification system is suitable for testing different cache systems, has wider applicability and stronger versatility, and can also achieve automatic comparison and error reporting.

[0124] In one alternative embodiment, a computer device is provided, such as Figure 5 As shown, Figure 5 The computer device 50 shown includes a processor 501 and a memory 503. The processor 501 and the memory 503 are connected, for example, via a bus 502.

[0125] Processor 501 may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. Processor 501 may also be a combination that implements computational functions, such as including one or more microprocessor combinations, a combination of a DSP and a microprocessor, etc.

[0126] Bus 502 may include a pathway for transmitting information between the aforementioned components. Bus 502 may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. Bus 502 can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 5 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0127] Memory 503 may be ROM (Read Only Memory) or other types of static storage devices capable of storing static information and instructions, RAM (Random Access Memory) or other types of dynamic storage devices capable of storing information and instructions, or EEPROM (Electrically Erasable Programmable Read Only Memory), CD-ROM (Compact Disc Read Only Memory) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), disk storage media, other magnetic storage devices, or any other medium capable of carrying or storing computer programs and capable of being read by a computer, without limitation herein.

[0128] Memory 503 is used to store computer programs that execute embodiments of this application, and its execution is controlled by processor 501. Processor 501 is used to execute the computer programs stored in memory 503 to implement the steps shown in the foregoing method embodiments.

[0129] This application provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it can implement the steps and corresponding content of the aforementioned method embodiments.

[0130] The processor-readable storage medium can be any available medium or data storage device that the processor can access, including but not limited to magnetic memory (e.g., floppy disk, hard disk, magnetic tape, magneto-optical disk (MO)), optical memory (e.g., CD, DVD, BD, HVD), and semiconductor memory (e.g., ROM, EPROM, EEPROM, non-volatile memory (NAND FLASH), solid-state drive (SSD)).

[0131] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk memory and optical memory) containing computer-usable program code.

[0132] It should be understood that although arrows indicate various operation steps in the flowcharts of this application's embodiments, the order in which these steps are implemented is not limited to the order indicated by the arrows. Unless explicitly stated herein, in some implementation scenarios of this application's embodiments, the implementation steps in each flowchart can be executed in other orders as required. Furthermore, some or all steps in each flowchart, based on the actual implementation scenario, may include multiple sub-steps or multiple stages. Some or all of these sub-steps or stages can be executed at the same time, and each sub-step or stage can also be executed at different times. In scenarios where execution times differ, the execution order of these sub-steps or stages can be flexibly configured according to requirements, and this application's embodiments do not limit this.

[0133] The above description is only an optional implementation method for some implementation scenarios of this application. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this application without departing from the technical concept of this application also fall within the protection scope of the embodiments of this application.

Claims

1. A system for verifying multi-level caches, characterized in that, The system includes: Cache reference model; Multiple bus function models, including interfaces connecting the design under test (DUT) and the cache reference model, send test cases in the form of bus transactions to the DUT and the cache reference model respectively, wherein the DUT is a cache system including multi-level caches; The verification module compares and verifies the data in the memory of the cache system and the cache reference model after running test cases to determine whether they meet the requirements. The bus function model is used to initiate read or write requests to any level of cache, send the read or write requests to the cache reference model in the form of bus transactions, and convert the bus transactions into the interface timing of the cache level and send them to the cache level in the cache system. The bus function model is also used to store information from the cache system and the cache reference model into a trace log; The cache system includes: a level 1 instruction cache, a level 1 data cache, and a level 2 cache; The various bus function models include: Instruction Fetch Unit-Bus Function Model (IFU BFM) and Load Memory Unit-Bus Function Model (LSU BFM). The IFU BFM is used to access the Level 1 instruction cache to retrieve and verify the contents of the instruction, and the LSU BFM is used to access the Level 1 data cache and the Level 2 cache to retrieve and verify the data. The IFU BFM or the LSU BFM sends a read request for the target cache in the cache system to the cache system and the cache reference model. The read request is sent to the cache reference model in the form of a bus transaction, and the bus transaction is converted into the interface timing of the cache at that level and sent to the cache system.

2. The system according to claim 1, characterized in that, The bus function model is also used to receive read data returned by the cache reference model and the cache system respectively according to the read request, and compare whether the two are consistent.

3. The system according to claim 1, characterized in that, The cache system is configured to receive read or write requests from the bus function model, send read or write requests to the memory configured with the cache system, receive read data returned by the memory, and update the data of the memory configured with the cache system according to the address and write data in the write request.

4. The system according to claim 1, characterized in that, The information includes read data, the address of the read data, and response information for the read request; or, the information includes write data, the address of the write data, and response information for the write request.

5. A verification method for a multi-level cache, characterized in that, The method includes: Multiple bus function models will send test cases in the form of bus transactions to the design under test and the cache reference model respectively, wherein the design under test is a cache system including a multi-level cache; The verification module compares and verifies the data in the memory of the cache system and the cache reference model after running test cases to determine whether they meet the requirements. The various bus function models will send test cases in the form of bus transactions to the cache system of the design under test and the cache reference model, including: The bus function model initiates a read or write request to any level of cache, sends the read or write request to the cache reference model in the form of a bus transaction, and converts the bus transaction into the interface timing of that level of cache and sends it to that level of cache in the cache system. The method further includes: The bus function model stores information from the cache system and the cache reference model in the trace log; The cache system includes: a level 1 instruction cache, a level 1 data cache, and a level 2 cache; The various bus function models include: Instruction Fetch Unit-Bus Function Model (IFU BFM) and Load Memory Unit-Bus Function Model (LSU BFM). The IFU BFM is used to access the Level 1 instruction cache to retrieve and verify the contents of the instruction, and the LSU BFM is used to access the Level 1 data cache and the Level 2 cache to retrieve and verify the data. The various bus function models will send test cases in the form of bus transactions to the design under test and the cache reference model, respectively, including: The IFU BFM or the LSU BFM sends a read request for the target cache in the cache system to the cache system and the cache reference model. The read request is sent to the cache reference model in the form of a bus transaction, and the bus transaction is converted into the interface timing of the cache at that level and sent to the cache system.

6. The method according to claim 5, characterized in that, The method further includes: The bus function model receives read data returned by the cache reference model and the cache system respectively according to the read request, and compares whether the two are consistent.

7. The method according to claim 5, characterized in that, The information includes read data, the address of the read data, and a response to the read request; or, the information includes write data, the address of the write data, and a response to the write request.

8. A computer device, comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the verification method for the multi-level cache as described in any one of claims 5-7.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the verification method for the multi-level cache as described in any one of claims 5-7.

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