Display panel and display device

Abstract

The present disclosure provides a display panel and a display device. In a second pixel region of the display panel, there is a second gap between a third conductive connection portion and a fourth conductive connection portion in a second conductive connection layer; a third conductive connection layer is respectively coupled to fifth signal line patterns included in respective sub-pixels in a corresponding sub-pixel group, the fifth signal line patterns being configured to transmit a fifth signal having a fixed potential, and a positive projection of the third conductive connection layer on a substrate of the display panel covers at least a part of a positive projection of the second gap on the substrate.

Description

[0001] This application is a divisional application of a Chinese patent application with an application date of May 15, 2020 and an application number of 202080000747.0. Technical Field

[0002] The present disclosure relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0003] With the increasing requirements of consumers for screen integrity, the technology of setting a camera under the display screen has become increasingly popular. This under-screen camera technology mainly sets the camera within the display area of the display screen and under the pixel units, and by reducing the pixel density in the area where the camera is located, it is compatible with the display function of the display panel and the imaging function of the camera. Summary of the Invention

[0004] The purpose of the present disclosure is to provide a display panel and a display device.

[0005] A first aspect of the present disclosure provides a display panel, including a first pixel area and a second pixel area, wherein the pixel density of the second pixel area is lower than that of the first pixel area; the second pixel area includes a plurality of pixel units distributed in an array, the plurality of pixel units form multiple rows of pixel unit rows, and each row of pixel unit rows includes a plurality of pixel units arranged along a first direction; each pixel unit includes a plurality of sub-pixels arranged along the first direction, and in the same row of pixel unit rows, the two closest sub-pixels in two adjacent pixel units form a sub-pixel group; the sub-pixel includes: a sub-pixel driving circuit, and a first signal line pattern to a fifth signal line pattern respectively coupled to the sub-pixel driving circuit;

[0006] The display panel further includes: a plurality of conductive connection structures corresponding to the sub-pixel groups one by one, the conductive connection structures are located between the two sub-pixels included in the corresponding sub-pixel group, and the conductive connection structures include: a first conductive connection layer, a second conductive connection layer, and a third conductive connection layer arranged in different layers;

[0007] The first conductive connection layer includes a first conductive connection portion and a second conductive connection portion, and there is a first gap between the first conductive connection portion and the second conductive connection portion; the first conductive connection portion is respectively coupled to the first signal line patterns included in the respective sub-pixels in the corresponding sub-pixel group, and the second conductive connection portion is respectively coupled to the second signal line patterns included in the respective sub-pixels in the corresponding sub-pixel group;

[0008] The second conductive connection layer includes a third conductive connection portion and at least one fourth conductive connection portion, and there is a second gap between adjacent third conductive connection portions and fourth conductive connection portions; the third conductive connection portions are respectively coupled to third signal line patterns included in each sub-pixel in the corresponding sub-pixel group, and the at least one fourth conductive connection portion corresponds one-to-one to fourth signal line patterns included in each sub-pixel in the corresponding sub-pixel group, and the fourth conductive connection portions are respectively coupled to the corresponding fourth signal line patterns;

[0009] The third conductive connection layer is respectively coupled to fifth signal line patterns included in each sub-pixel in the corresponding sub-pixel group, the fifth signal line patterns are used to transmit a fifth signal with a fixed potential, and a positive projection of the third conductive connection layer on the substrate of the display panel covers at least part of a positive projection of the first gap on the substrate and at least part of a positive projection of the second gap on the substrate.

[0010] Optionally, the first signal line pattern includes a first reset signal line pattern, and at least part of the first reset signal line pattern extends along the first direction; the second signal line pattern includes a light emission control signal line pattern, and at least part of the light emission control signal line pattern extends along the first direction.

[0011] Optionally, the third signal line pattern includes gate line patterns and a second reset signal line pattern arranged along a second direction, at least part of the gate line patterns and at least part of the second reset signal line pattern extend along the first direction, and the gate line patterns and the second reset signal line pattern are used to transmit the same third signal;

[0012] The third conductive connection portion includes a first portion, a second portion, and a third portion, the first portion and the second portion extend along the second direction, the third portion extends along the first direction, and the second direction intersects the first direction; the first portion is respectively coupled to the gate line pattern and the second reset signal line pattern included in one sub-pixel in the sub-pixel group, the second portion is respectively coupled to the gate line pattern and the second reset signal line pattern included in another sub-pixel in the sub-pixel group, and the third portion is respectively coupled to the first portion and the second portion.

[0013] Optionally, the fourth signal line pattern includes two initialization signal line patterns arranged along the second direction, the second direction intersects the first direction, the second conductive connection layer includes two fourth conductive connection portions, the two fourth conductive connection portions correspond one-to-one to the initialization signal line patterns included in each sub-pixel in the corresponding sub-pixel group, and each fourth conductive connection portion is respectively coupled to the corresponding fourth signal line pattern;

[0014] At least a part of the positive projection of the third conductive connection portion on the substrate is located between the positive projections of the two fourth conductive connection portions on the substrate.

[0015] Optionally, the sub-pixel driving circuit includes a storage capacitor, the storage capacitor includes a first electrode plate and a second electrode plate which are oppositely arranged, and the first electrode plate is located between the substrate and the second electrode plate;

[0016] The fifth signal line pattern includes a power supply signal line pattern, at least a part of the power supply signal line pattern extends along the second direction, and in the same sub-pixel, the second electrode plate is coupled to the power supply signal line pattern;

[0017] The third conductive connection layer is respectively coupled to the second electrode plates included in the respective sub-pixels in the corresponding sub-pixel group.

[0018] Optionally, the positive projection of the first conductive connection portion on the substrate overlaps with the positive projection of the third conductive connection portion on the substrate and the positive projection of one of the two fourth conductive connection portions on the substrate respectively; and / or,

[0019] The positive projection of the second conductive connection portion on the substrate overlaps with the positive projection of the third conductive connection portion on the substrate and the positive projection of the other of the two fourth conductive connection portions on the substrate respectively.

[0020] Optionally, the first conductive connection portion, the second conductive connection portion, and the fourth conductive connection portion all include a first side portion and a second side portion, and an intermediate portion located between the first side portion and the second side portion; the intermediate portion extends along the first direction, the first side portion includes a part extending along the first direction and a part extending along the second direction, and the second side portion includes a part extending along the first direction and a part extending along the second direction;

[0021] The positive projection on the substrate of the intermediate portion included in one of the two fourth conductive connection portions, the positive projection on the substrate of the intermediate portion included in the first conductive connection portion, the positive projection on the substrate of the third part of the third conductive connection portion, the positive projection on the substrate of the intermediate portion included in the second conductive connection portion, and the positive projection on the substrate of the intermediate portion included in the other of the two fourth conductive connection portions are arranged in sequence along the second direction.

[0022] Optionally, wherein the sub-pixel driving circuit includes a storage capacitor, the storage capacitor includes a first electrode plate and a second electrode plate which are oppositely arranged in a direction perpendicular to the substrate, and the first electrode plate is located between the substrate and the second electrode plate;

[0023] The fourth signal line pattern includes a power supply signal line pattern, at least a part of the power supply signal line pattern extends along a second direction, and the second electrode plate is coupled to the power supply signal line pattern;

[0024] The second conductive connection layer includes a fourth conductive connection portion, and the fourth conductive connection portion is respectively coupled to the second electrode plates included in the respective sub-pixels in the corresponding sub-pixel group.

[0025] Optionally, the fifth signal line pattern includes two initialization signal line patterns arranged along the second direction, and the third conductive connection layer is respectively coupled to the initialization signal line patterns included in the respective sub-pixels in the corresponding sub-pixel group.

[0026] Optionally, the orthographic projection of the fourth conductive connection portion on the substrate is located between the orthographic projection of the first conductive connection portion on the substrate and the orthographic projection of the second conductive connection portion on the substrate; the orthographic projection of the third conductive connection portion on the substrate overlaps with the orthographic projection of the second conductive connection portion on the substrate.

[0027] Optionally, the orthographic projection of the fourth conductive connection portion on the substrate overlaps with the orthographic projection of the first conductive connection portion on the substrate and the orthographic projection of the second conductive connection portion on the substrate respectively.

[0028] Optionally, the orthographic projection of the fourth conductive connection portion on the substrate overlaps with the orthographic projection of the first conductive connection portion on the substrate; the orthographic projection of the third conductive connection portion on the substrate overlaps with the orthographic projection of the second conductive connection portion on the substrate.

[0029] Optionally, the first conductive connection portion, the second conductive connection portion, and the fourth conductive connection portion all include a first side portion and a second side portion, and an intermediate portion located between the first side portion and the second side portion; the intermediate portion extends along a first direction, the first side portion includes a part extending along the first direction and a part extending along the second direction, and the second side portion includes a part extending along the first direction and a part extending along the second direction;

[0030] There is a first gap between the intermediate portion of the first conductive connection portion and the intermediate portion of the second conductive connection portion, the first gap has a first width in a direction perpendicular to the first direction, and the first width is the minimum width that satisfies the insulation condition between the intermediate portion of the first conductive connection portion and the intermediate portion of the second conductive connection portion;

[0031] There is the second gap between the middle part of the third conductive connection part and the middle part of the fourth conductive connection part. The second gap has a second width in the direction perpendicular to the first direction, and the second width is the minimum width that satisfies the insulation condition between the middle part of the third conductive connection part and the middle part of the fourth conductive connection part.

[0032] Optionally, the orthographic projection of the third conductive connection layer on the substrate overlaps with the orthographic projection of the first conductive connection part on the substrate, the orthographic projection of the second conductive connection part on the substrate, the orthographic projection of the third conductive connection part on the substrate, and the orthographic projection of the fourth conductive connection part on the substrate.

[0033] Optionally, the first conductive connection part, the second conductive connection part, and the fourth conductive connection part each include a first side part and a second side part, and a middle part located between the first side part and the second side part; the middle part extends in the first direction, the first side part includes a part extending in the first direction and a part extending in the second direction, and the second side part includes a part extending in the first direction and a part extending in the second direction;

[0034] The orthographic projection of the middle part included in the fourth conductive connection part on the substrate, the orthographic projection of the middle part included in the first conductive connection part on the substrate, the orthographic projection of the third part of the third conductive connection part on the substrate, and the orthographic projection of the middle part included in the second conductive connection part on the substrate are all located inside the orthographic projection of the third conductive connection layer on the substrate.

[0035] Optionally, the sub-pixel further includes a data line pattern that extends in the second direction; the sub-pixel driving circuit includes: a transistor structure and a storage capacitor, and the storage capacitor includes a first electrode plate and a second electrode plate that are oppositely arranged;

[0036] The first conductive connection layer is provided with the same layer and the same material as the gate of the transistor structure;

[0037] The second conductive connection layer is provided with the same layer and the same material as the data line pattern;

[0038] The third conductive connection layer is provided with the same layer and the same material as the second electrode plate.

[0039] Optionally, the sub-pixel further includes a data line pattern that extends in the second direction; the sub-pixel driving circuit includes: a transistor structure and a storage capacitor, and the storage capacitor includes a first electrode plate and a second electrode plate that are oppositely arranged;

[0040] The first conductive connection layer is provided with the same layer and the same material as the second electrode plate;

[0041] The second conductive connection layer is provided with the same layer and the same material as the data line pattern;

[0042] The third conductive connection layer is provided with the same layer and the same material as the gate of the transistor structure.

[0043] Optionally, the first signal line pattern includes a first reset signal line pattern, the second signal line pattern includes a light emission control signal line pattern, and the third signal line pattern includes a gate line pattern and a second reset signal line pattern; the sub-pixel further includes a power supply signal line pattern, a data line pattern, a first initialization signal line pattern, and a second initialization signal line pattern;

[0044] The sub-pixel driving circuit all includes: a storage capacitor, a driving transistor, a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor;

[0045] The gate of the driving transistor is coupled to the second pole of the first transistor, the first pole of the driving transistor is coupled to the second pole of the fifth transistor, and the second pole of the driving transistor is coupled to the first pole of the first transistor;

[0046] The gate of the first transistor is coupled to the gate line pattern;

[0047] The gate of the second transistor is coupled to the first reset signal line pattern, the first pole of the second transistor is coupled to the first initialization signal line pattern, and the second pole of the second transistor is coupled to the gate of the driving transistor;

[0048] The gate of the fourth transistor is coupled to the gate line pattern, the first pole of the fourth transistor is coupled to the data line pattern, and the second pole of the fourth transistor is coupled to the first pole of the driving transistor;

[0049] The gate of the fifth transistor is coupled to the light emission control signal line pattern, and the first pole of the fifth transistor is coupled to the power supply signal line pattern;

[0050] The gate of the sixth transistor is coupled to the light emission control signal line pattern, the first pole of the sixth transistor is coupled to the second pole of the driving transistor, and the second pole of the sixth transistor is coupled to the corresponding light emitting element in the display panel;

[0051] The second pole of the seventh transistor is coupled to the corresponding light emitting element, the gate of the seventh transistor is coupled to the second reset signal line pattern, and the first pole of the seventh transistor is coupled to the second initialization signal line pattern.

[0052] Based on the technical solution of the above display panel, a second aspect of the present disclosure provides a display device, and the display device includes the above display panel.

[0053] Based on the technical solution of the above display panel, a third aspect of the present disclosure provides a method for manufacturing a display panel. The display panel includes a first pixel region and a second pixel region, and the pixel density of the second pixel region is lower than that of the first pixel region. The manufacturing method includes:

[0054] Manufacturing a plurality of pixel units and a plurality of conductive connection structures distributed in an array in the second pixel region;

[0055] The plurality of pixel units form a plurality of rows of pixel unit rows, and each row of pixel unit rows includes a plurality of pixel units arranged along a first direction; each pixel unit includes a plurality of sub-pixels arranged along the first direction. In the same row of pixel unit rows, the two closest sub-pixels in two adjacent pixel units form a sub-pixel group; the sub-pixel includes: a sub-pixel driving circuit, and a first signal line pattern to a fifth signal line pattern respectively coupled to the sub-pixel driving circuit;

[0056] The plurality of conductive connection structures correspond to the sub-pixel groups one by one. The conductive connection structure is located between the two sub-pixels included in the corresponding sub-pixel group. The conductive connection structure includes: a first conductive connection layer, a second conductive connection layer, and a third conductive connection layer arranged in different layers;

[0057] The first conductive connection layer includes a first conductive connection portion and a second conductive connection portion, and there is a first gap between the first conductive connection portion and the second conductive connection portion; the first conductive connection portion is respectively coupled to the first signal line patterns included in the respective sub-pixels in the corresponding sub-pixel group, and the second conductive connection portion is respectively coupled to the second signal line patterns included in the respective sub-pixels in the corresponding sub-pixel group;

[0058] The second conductive connection layer includes a third conductive connection portion and at least one fourth conductive connection portion, and there is a second gap between the adjacent third conductive connection portion and the fourth conductive connection portion; the third conductive connection portion is respectively coupled to the third signal line patterns included in the respective sub-pixels in the corresponding sub-pixel group, the at least one fourth conductive connection portion corresponds to the fourth signal line patterns included in each sub-pixel in the corresponding sub-pixel group one by one, and the fourth conductive connection portions are respectively coupled to the corresponding fourth signal line patterns;

[0059] The third conductive connection layer is respectively coupled to fifth signal line patterns included in each sub-pixel of the corresponding sub-pixel group. The fifth signal line patterns are used to transmit a fifth signal having a fixed potential. A positive projection of the third conductive connection layer on a substrate of the display panel covers at least a part of a positive projection of the first gap on the substrate and at least a part of a positive projection of the second gap on the substrate. Description of the Drawings

[0060] The drawings described herein are used to provide a further understanding of the present disclosure, and constitute a part of the present disclosure. The illustrative embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation to the present disclosure. In the drawings:

[0061] Figure 1 It is a first layout schematic diagram of a sub-pixel group provided by an embodiment of the present disclosure;

[0062] Figure 2 It is a circuit diagram of a sub-pixel driving circuit provided by an embodiment of the present disclosure;

[0063] Figure 3 It is a timing diagram of a sub-pixel driving circuit provided by an embodiment of the present disclosure;

[0064] Figure 4 It is a second layout schematic diagram of a sub-pixel group provided by an embodiment of the present disclosure;

[0065] Figure 5 is Figure 4 a layout schematic diagram of an active layer therein;

[0066] Figure 6 is Figure 4 a layout schematic diagram of a first gate metal layer therein;

[0067] Figure 7 is Figure 4 a layout schematic diagram of a second gate metal layer therein;

[0068] Figure 8 is Figure 4 a first schematic diagram of a first source-drain metal layer therein;

[0069] Figure 9 is Figure 4 a second schematic diagram of a first source-drain metal layer therein;

[0070] Figure 10 It is a third layout schematic diagram of a sub-pixel group provided by an embodiment of the present disclosure;

[0071] Figure 11 is Figure 10 a layout schematic diagram of a second gate metal layer therein;

[0072] Figure 12 isFigure 10 Schematic layout diagram of the first source-drain metal layer. Detailed implementation manners

[0073] To further illustrate the display panel and the display device provided by the embodiments of the present disclosure, a detailed description will be given below with reference to the accompanying drawings of the specification.

[0074] As Figure 1 shown, the present disclosure provides a display panel, the display panel includes a first pixel region and a second pixel region, and the pixel density of the second pixel region is lower than that of the first pixel region; the second pixel region includes a plurality of pixel units arranged in an array, the plurality of pixel units form a plurality of rows of pixel unit rows, and each row of pixel unit rows includes a plurality of pixel units arranged along a first direction; each pixel unit includes a plurality of sub-pixels arranged along the first direction, and in the same row of pixel unit rows, the two closest sub-pixels in two adjacent pixel units form a sub-pixel group; the sub-pixel includes: a sub-pixel driving circuit, and a signal line pattern respectively coupled to the sub-pixel driving circuit, and the signal line pattern may specifically include: a power supply signal line pattern 901, a data signal line pattern 908, a gate line pattern 902, a light emission control signal line pattern 903, a first reset signal line pattern 905, a first initialization signal line pattern 904, a second reset signal line pattern 905', and a second initialization signal line pattern 904'. It should be noted that the pixel density represents the number of pixels per inch.

[0075] The first pixel region is also provided with a plurality of pixel units arranged in an array, and the specific structure of the sub-pixels included in each pixel unit is the same as that of the second pixel region. Since an under-screen camera is provided in the second pixel region, the pixel density in the second pixel region is relatively low. When arranging the pixel units in the first pixel region and the pixel units in the second pixel region, the pixel units in the first pixel region are tightly arranged, while the pixel units in the second pixel region are loosely arranged. In the second pixel region, in the same row of pixel unit rows, the distance between two adjacent pixel units is relatively large, and a conductive connection structure needs to be provided between the sub-pixel groups to couple the same signal line patterns included in the sub-pixels in the sub-pixel group together.

[0076] Please continue to refer to Figure 1, in the sub-pixel group, the conductive connection structure between two sub-pixels includes seven conductive connection parts, which are used to couple the first initialization signal line patterns 904 included in each sub-pixel in the sub-pixel group, to couple the first reset signal line patterns 905 included in each sub-pixel in the sub-pixel group, to couple the gate line patterns 902 included in each sub-pixel in the sub-pixel group, to couple the light emission control signal line patterns 903 included in each sub-pixel in the sub-pixel group, to couple the second initialization signal line patterns 904' included in each sub-pixel in the sub-pixel group, to couple the second reset signal line patterns 905' included in each sub-pixel in the sub-pixel group, and to couple the power supply signal line patterns 901 included in each sub-pixel in the sub-pixel group.

[0077] Although the display panel provided in the above embodiment is compatible with the display function of the display panel and the imaging function of the camera by reducing the pixel density of the second pixel region where the camera is located, there are gaps between adjacent conductive connection parts, and the light transmitted through the gaps will form diffraction and glare, thus affecting the imaging quality of the camera when taking pictures. In addition, since the number of formed conductive connection parts is large and the occupied layout space area is large, the transmittance of the screen in the second pixel region is low, thus affecting the imaging quality of the camera when taking pictures.

[0078] Please refer to Figure 4 and Figure 10 , the embodiment of the present disclosure provides a display panel, including a first pixel region and a second pixel region, the pixel density of the second pixel region is lower than that of the first pixel region; the second pixel region includes a plurality of pixel units arranged in an array, the plurality of pixel units form a plurality of rows of pixel unit rows, and each row of pixel unit rows includes a plurality of pixel units arranged along a first direction; each pixel unit includes a plurality of sub-pixels arranged along the first direction, and in the same row of pixel unit rows, the two closest sub-pixels in adjacent two pixel units form a sub-pixel group; the sub-pixel includes: a sub-pixel driving circuit, and a first signal line pattern 81 to a fifth signal line pattern 85 respectively coupled to the sub-pixel driving circuit;

[0079] The display panel further includes: a plurality of conductive connection structures corresponding to the sub-pixel groups one by one, the conductive connection structures are located between two sub-pixels included in the corresponding sub-pixel group, and the conductive connection structures include: a first conductive connection layer, a second conductive connection layer and a third conductive connection layer 75 arranged in different layers;

[0080] The first conductive connection layer includes a first conductive connection portion 71 and a second conductive connection portion 72, and there is a first gap between the first conductive connection portion 71 and the second conductive connection portion 72; the first conductive connection portion 71 is respectively coupled to the first signal line patterns 81 included in each sub-pixel in the corresponding sub-pixel group, and the second conductive connection portion 72 is respectively coupled to the second signal line patterns 82 included in each sub-pixel in the corresponding sub-pixel group;

[0081] The second conductive connection layer includes a third conductive connection portion 73 and at least one fourth conductive connection portion 74, and there is a second gap between the adjacent third conductive connection portion 73 and the fourth conductive connection portion 74; the third conductive connection portion 73 is respectively coupled to the third signal line patterns 83 included in each sub-pixel in the corresponding sub-pixel group, the at least one fourth conductive connection portion 74 corresponds one by one to the fourth signal line patterns 84 included in each sub-pixel in the corresponding sub-pixel group, and the fourth conductive connection portion 74 is respectively coupled to the corresponding fourth signal line patterns 84;

[0082] The third conductive connection layer 75 is respectively coupled to the fifth signal line patterns 85 included in each sub-pixel in the corresponding sub-pixel group, the fifth signal line patterns 85 are used to transmit a fifth signal with a fixed potential, and the orthographic projection of the third conductive connection layer 75 on the substrate of the display panel covers at least part of the orthographic projection of the first gap on the substrate and at least part of the orthographic projection of the second gap on the substrate.

[0083] Specifically, the display panel includes a first pixel region and a second pixel region, and both the first pixel region and the second pixel region can realize a display function. The pixel density of the second pixel region is lower than that of the first pixel region, and in the second pixel region, a camera is provided between the substrate and the sub-pixel driving circuit.

[0084] The specific layout manners of the pixel units in the first pixel region and the second pixel region are various. Exemplarily, the pixel units in the first pixel region and the pixel units in the second pixel region are both arranged in an array. Exemplarily, along the first direction, among the pixel units in the same row of the display panel, the signal line patterns located in the first pixel region are electrically connected to the signal line patterns for transmitting the same signal located in the second pixel region.

[0085] In the second pixel region, a plurality of pixel units arranged in an array can form a plurality of rows of pixel unit rows arranged in sequence along the second direction, and each row of pixel unit rows includes a plurality of pixel units arranged in sequence along the first direction. The first direction intersects with the second direction. Exemplarily, the first direction includes the X direction, and the second direction includes the Y direction.

[0086] In the second pixel region, each pixel unit includes a plurality of sub-pixels arranged in a first direction. Exemplarily, each pixel unit includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel arranged in the first direction. The plurality of sub-pixels included in each pixel unit are arranged compactly, and in one pixel unit, the signal line patterns for transmitting the same signal included in each sub-pixel are directly coupled. Exemplarily, in one pixel unit, the signal line patterns for transmitting the same signal included in each sub-pixel can be formed into an integral structure.

[0087] In the same row of pixel units, the two closest sub-pixels in two adjacent pixel units form a sub-pixel group; Exemplarily, each pixel unit includes a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged in sequence in the first direction. Among the sub-pixels included in the two adjacent pixel units, the third sub-pixel of the previous pixel unit and the first sub-pixel of the subsequent pixel unit are included.

[0088] Exemplarily, the specific structures of the sub-pixels included in the pixel units in the first pixel region and the second pixel region are the same. Each sub-pixel includes a sub-pixel driving circuit and a plurality of signal line patterns respectively coupled to the sub-pixel driving circuit. Exemplarily, the plurality of signal line patterns include a first signal line pattern 81, a second signal line pattern 82, a third signal line pattern 83, a fourth signal line pattern 84, and a fifth signal line pattern 85; each signal line pattern is used to transmit a corresponding signal.

[0089] In the first pixel region, along the first direction, the pixel units located in the same row are arranged compactly. In the second pixel region, along the first direction, there is a certain distance between adjacent pixel units located in the same row, and this distance is located between the two sub-pixels in the sub-pixel group, and is used to transmit light so that the camera located in the second pixel region can achieve the imaging function.

[0090] It should be noted that on the premise of meeting the pixel density necessary for screen display, the pixel density or pixel size of the second pixel region should be minimized as much as possible (subject to the existing manufacturing process), and the area of the conductive connection part between sub-pixels should be reduced, so as to better improve the light transmittance of the second pixel region.

[0091] The display panel further includes: a plurality of conductive connection structures corresponding to the sub-pixel groups one by one. Each conductive connection structure is located between the two sub-pixels included in the corresponding sub-pixel group. The specific structure of the conductive connection structure is diverse. Exemplarily, the conductive connection structure includes: a first conductive connection layer, a second conductive connection layer, and a third conductive connection layer 75; among the first conductive connection layer, the second conductive connection layer, and the third conductive connection layer 75, any two layers are arranged in different layers.

[0092] The specific structures and connection relationships of the first conductive connection layer, the second conductive connection layer, and the third conductive connection layer 75 are diverse, and exemplary descriptions will be given below.

[0093] The first conductive connection layer includes a first conductive connection portion 71 and a second conductive connection portion 72. At least a part of the first conductive connection portion 71 extends in a first direction, and at least a part of the second conductive connection portion 72 extends in the first direction. There is a first gap between the first conductive connection portion 71 and the second conductive connection portion 72. The first conductive connection portion 71 is respectively coupled to the first signal line patterns 81 included in each sub-pixel in the corresponding sub-pixel group. Exemplarily, the first conductive connection portion 71 and the first signal line pattern 81 to which it is coupled form an integral structure. The second conductive connection portion 72 is respectively coupled to the second signal line patterns 82 included in each sub-pixel in the corresponding sub-pixel group. Exemplarily, the second conductive connection portion 72 and the second signal line pattern 82 to which it is coupled form an integral structure.

[0094] The second conductive connection layer includes a third conductive connection portion 73 and at least one fourth conductive connection portion 74. At least a part of the third conductive connection portion 73 extends in a first direction, and at least a part of the fourth conductive connection portion 74 extends in the first direction. There is a second gap between the adjacent third conductive connection portion 73 and the fourth conductive connection portion 74. The third conductive connection portion 73 is respectively coupled to the third signal line patterns 83 included in each sub-pixel in the corresponding sub-pixel group. Exemplarily, the orthographic projection of the third conductive connection portion 73 on the substrate and the orthographic projection of the third signal line pattern 83 to which it is coupled on the substrate form an overlapping area. In this overlapping area, the third conductive connection portion 73 is coupled to the third signal line pattern 83 through a via hole. It should be noted that the first gap and the second gap are generally small-sized gaps, and the first gap and the second gap can be set as the minimum gaps that satisfy the insulation condition between the two conductive connection portions.

[0095] The at least one fourth conductive connection portion 74 corresponds one-to-one to each fourth signal line pattern 84 included in each sub-pixel in the corresponding sub-pixel group, and the fourth conductive connection portion 74 is respectively coupled to the corresponding fourth signal line pattern 84; Exemplarily, as Figure 4 shown, the orthographic projection of the fourth conductive connection portion 74 on the substrate and the orthographic projection of the fourth signal line pattern 84 to which it is coupled on the substrate form an overlapping area. In this overlapping area, the fourth conductive connection portion 74 is coupled to the fourth signal line pattern 84 through a via hole.

[0096] The third conductive connection layer 75 is respectively coupled to the fifth signal line patterns 85 included in each sub-pixel in the corresponding sub-pixel group. The fifth signal line patterns 85 are used to transmit a fifth signal with a fixed potential. Exemplarily, the third conductive connection layer 75 and the fifth signal line patterns 85 coupled thereto are formed as an integral structure. Exemplarily, the fifth signal line patterns 85 are coupled to a target pattern in the display panel. The orthographic projection of the third conductive connection layer 75 on the substrate overlaps with the orthographic projection of the target pattern on the substrate. In this overlapping region, the third conductive connection layer 75 is coupled to the target pattern through a via hole, so as to realize the coupling of the third conductive connection layer 75 to the fifth signal line patterns 85 through the target pattern.

[0097] At least a part of the third conductive connection layer 75 extends along the first direction. Exemplarily, the orthographic projection of the third conductive connection layer 75 on the substrate of the display panel covers at least a part of the orthographic projection of the first gap on the substrate and at least a part of the orthographic projection of the second gap on the substrate. Exemplarily, the orthographic projection of the third conductive connection layer 75 on the substrate of the display panel completely covers at least a part of the orthographic projection of the first gap on the substrate and at least a part of the orthographic projection of the second gap on the substrate.

[0098] According to the specific structure of the above display panel, in the display panel provided by the embodiments of the present disclosure, a conductive connection structure is provided between two sub-pixels included in a sub-pixel group. The conductive connection structure includes: a first conductive connection layer, a second conductive connection layer, and a third conductive connection layer 75 disposed in different layers; the first conductive connection layer and the second conductive connection layer are used to couple the signal line patterns for transmitting the same signal included in each sub-pixel in the sub-pixel group together; the third conductive connection layer 75 is used to couple the fifth signal line patterns 85 for transmitting a fifth signal with a fixed potential included in each sub-pixel in the sub-pixel group together; therefore, the display panel provided by the embodiments of the present disclosure realizes the corresponding coupling of the signal line patterns for transmitting the same signal included in each sub-pixel in the sub-pixel group by providing the conductive connection structure.

[0099] In addition, in the display panel provided by the embodiments of the present disclosure, by setting the orthographic projection of the third conductive connection layer 75 on the substrate of the display panel to cover at least a part of the orthographic projection of the first gap on the substrate and at least a part of the orthographic projection of the second gap on the substrate, the third conductive connection layer 75 can cover the gap between adjacent conductive connection portions between two sub-pixels in the sub-pixel group, reducing the light leakage phenomenon generated at the gap, thereby avoiding problems such as disturbing diffraction and glare generated when light passes through the gap, and better ensuring the imaging quality of the camera in the display panel when taking pictures.

[0100] In addition, in the display panel provided by the embodiments of the present disclosure, the third conductive connection layer 75 is coupled to a fifth signal line pattern 85 for transmitting a fifth signal with a fixed potential, so that the third conductive connection layer 75 has a stable potential and will not have too much impact on the RC (resistance-capacitance) loading of the fifth signal line pattern 85.

[0101] As Figure 4 and Figure 6 shown, in some embodiments, the first signal line pattern 81 includes a first reset signal line pattern 905, and at least a part of the first reset signal line pattern 905 extends along the first direction; the second signal line pattern 82 includes a light emission control signal line pattern 903, and at least a part of the light emission control signal line pattern 903 extends along the first direction.

[0102] Specifically, the first conductive connection portion 71 is respectively coupled to the first reset signal line patterns 905 included in the respective sub-pixels in the corresponding sub-pixel group. Exemplarily, the first conductive connection portion 71 and the respective first reset signal line patterns 905 coupled thereto form an integral structure.

[0103] The second conductive connection portion 72 is respectively coupled to the light emission control signal line patterns 903 included in the respective sub-pixels in the corresponding sub-pixel group. Exemplarily, the second conductive connection portion 72 and the respective light emission control signal line patterns 903 coupled thereto form an integral structure.

[0104] Exemplarily, in the same sub-pixel, the first reset signal line pattern 905 and the light emission control signal line pattern 903 are arranged along a second direction, and the second direction intersects the first direction.

[0105] In the display panel provided in the above embodiment, by setting the first signal line pattern 81 to include a first reset signal line pattern 905, the first conductive connection portion 71 and each of the first reset signal line patterns 905 coupled thereto are formed into an integral structure, so that the first conductive connection portion 71 and the first reset signal line pattern 905 can be formed simultaneously in the same patterning process, and the formed first conductive connection portion 71 and the first reset signal line pattern 905 can be directly coupled. Similarly, by setting the second signal line pattern 82 to include a light emission control signal line pattern 903, the second conductive connection portion 72 and each of the light emission control signal line patterns 903 coupled thereto are formed into an integral structure, so that the second conductive connection portion 72 and the light emission control signal line pattern 903 can be formed simultaneously in the same patterning process, and the formed second conductive connection portion 72 and the light emission control signal line pattern 903 can be directly coupled. Therefore, the display panel provided in the above embodiment effectively simplifies the manufacturing process flow and saves the manufacturing cost.

[0106] As Figure 4 , Figure 8 , Figure 10 and Figure 12 shown, in some embodiments, the third signal line pattern 83 includes a gate line pattern 902 and a second reset signal line pattern 905' arranged along the second direction, at least a part of the gate line pattern 902 and at least a part of the second reset signal line pattern 905' both extend along the first direction, and the gate line pattern 902 and the second reset signal line pattern 905' are used to transmit the same third signal;

[0107] The third conductive connection portion 73 includes a first portion 731, a second portion 732, and a third portion 733. The first portion 731 and the second portion 732 extend along the second direction, the third portion 733 extends along the first direction, and the second direction intersects the first direction; the first portion 731 is respectively coupled to the gate line pattern 902 and the second reset signal line pattern 905' included in one sub-pixel of the sub-pixel group, the second portion 732 is respectively coupled to the gate line pattern 902 and the second reset signal line pattern 905' included in another sub-pixel of the sub-pixel group, and the third portion 733 is respectively coupled to the first portion 731 and the second portion 732.

[0108] Specifically, in each sub-pixel, the third signal line pattern 83 includes a gate line pattern 902 and a second reset signal line pattern 905' arranged along the second direction, and the gate line pattern 902 and the second reset signal line pattern 905' are used to transmit the same third signal.

[0109] The specific structure of the third conductive connection portion 73 is diverse. Exemplarily, the third conductive connection portion 73 includes the first portion 731, the second portion 732, and the third portion 733. The first portion 731 and the second portion 732 extend along the second direction, and the third portion 733 extends along the first direction. Exemplarily, the first portion 731, the second portion 732, and the third portion 733 are formed as an integral structure.

[0110] The first portion 731 is used to couple the gate line pattern 902 and the second reset signal line pattern 905' included in the first sub-pixel in the sub-pixel group respectively. Exemplarily, the orthographic projection of the first portion 731 on the substrate forms an overlapping region with the orthographic projection of the gate line pattern 902 on the substrate and the orthographic projection of the second reset signal line pattern 905' on the substrate respectively. The first portion 731 can be coupled to the gate line pattern 902 and the second reset signal line pattern 905' respectively through vias formed in the overlapping region.

[0111] The second portion 732 is used to couple the gate line pattern 902 and the second reset signal line pattern 905' included in the second sub-pixel in the sub-pixel group respectively. Exemplarily, the orthographic projection of the second portion 732 on the substrate forms an overlapping region with the orthographic projection of the gate line pattern 902 on the substrate and the orthographic projection of the second reset signal line pattern 905' on the substrate respectively. The second portion 732 can be coupled to the gate line pattern 902 and the second reset signal line pattern 905' respectively through vias formed in the overlapping region.

[0112] In the display panel provided by the above embodiment, by providing the third conductive connection portion 73, the gate line pattern 902 and the second reset signal line pattern 905' for transmitting the same third signal included in each sub-pixel in the corresponding sub-pixel group are coupled together, effectively reducing the layout space occupied by the conductive connection structure, and thus better improving the light transmittance of the second pixel region.

[0113] In addition, in the display panel provided by the above embodiment, by providing the first portion 731, the second portion 732, and the third portion 733 to be formed as an integral structure, the third conductive connection portion 73 can be formed in a single patterning process, thus effectively simplifying the manufacturing process of the display panel and saving the manufacturing cost.

[0114] Such as Figure 4 、 Figure 7 and Figure 9As shown, in some embodiments, the fourth signal line pattern 84 includes two initialization signal line patterns arranged along a second direction, the second direction intersects the first direction, the second conductive connection layer includes two fourth conductive connection portions 74, and the two fourth conductive connection portions 74 respectively correspond to each sub-pixel included in the corresponding sub-pixel group. Each fourth conductive connection portion 74 is respectively coupled to the corresponding fourth signal line pattern 84;

[0115] At least a part of the positive projection of the third conductive connection portion 73 on the substrate is located between the positive projections of the two fourth conductive connection portions 74 on the substrate.

[0116] Specifically, the fourth signal line pattern 84 includes a first initialization signal line pattern 904 and a second initialization signal line pattern 904' arranged along the second direction. At least a part of the first initialization signal line pattern 904 and at least a part of the second initialization signal line pattern 904' both extend along the first direction.

[0117] The second conductive connection layer includes two fourth conductive connection portions 74. One of the fourth conductive connection portions 74 is respectively coupled to the first initialization signal line patterns 904 included in each sub-pixel of the corresponding sub-pixel group; the other fourth conductive connection portion 74 is respectively coupled to the second initialization signal line patterns 904' included in each sub-pixel of the corresponding sub-pixel group.

[0118] When the second conductive connection layer is provided to include two fourth conductive connection portions 74, the layout manner between the third conductive connection portion 73 and the two fourth conductive connection portions 74 is various. Exemplarily, at least a part of the positive projection of the third conductive connection portion 73 on the substrate is located between the positive projections of the two fourth conductive connection portions 74 on the substrate. Exemplarily, the positive projection of the third part 733 of the third conductive connection portion 73 on the substrate is located between the positive projections of the two fourth conductive connection portions 74 on the substrate.

[0119] In the display panel, since the first initialization signal line patterns 904, gate line patterns 902, second initialization signal line patterns 904', and second reset signal line patterns 905' included in each sub-pixel are arranged in sequence along the second direction, the above setting that the positive projection of the third conductive connection portion 73 on the substrate is located between the positive projections of the two fourth conductive connection portions 74 on the substrate is beneficial to reducing the layout difficulty of the third conductive connection portion 73 and the two fourth conductive connection portions 74 while ensuring insulation between the third conductive connection portion 73 and the fourth conductive connection portion 74.

[0120] Such as Figure 4, Figure 7 and Figure 8 As shown in Figure 8 and Figure 7 , in some embodiments, the sub-pixel driving circuit includes a storage capacitor, the storage capacitor includes a first electrode plate and a second electrode plate which are oppositely arranged, and the first electrode plate is located between the substrate and the second electrode plate; the fifth signal line pattern 85 includes a power supply signal line pattern 901, at least a part of the power supply signal line pattern 901 extends along the second direction, and in the same sub-pixel, the second electrode plate is coupled to the power supply signal line pattern 901; the third conductive connection layer 75 is respectively coupled to the second electrode plates included in the respective sub-pixels in the corresponding sub-pixel group.

[0121] Specifically, the sub-pixel driving circuit includes a driving transistor and a storage capacitor, the storage capacitor includes a first electrode plate and a second electrode plate which are oppositely arranged, and the first electrode plate is located between the substrate and the second electrode plate. Exemplarily, the first electrode plate is multiplexed as the gate of the driving transistor. Exemplarily, the first electrode plate is made of the first gate metal layer in the display panel, and the second electrode plate is made of the second gate metal layer in the display panel.

[0122] The fifth signal line pattern 85 includes a power supply signal line pattern 901, at least a part of the power supply signal line pattern 901 extends along the second direction. In the same sub-pixel, the orthographic projection of the second electrode plate on the substrate and the orthographic projection of the power supply signal line pattern 901 on the substrate form an overlapping area, and in this overlapping area, the power supply signal line pattern 901 is coupled to the second electrode plate through a via hole. Exemplarily, the power supply signal line pattern 901 can be made of the first source-drain metal layer in the display panel. Exemplarily, the respective power supply signal line patterns 901 located in the same column of sub-pixels along the second direction are sequentially coupled and can form an integral structure.

[0123] Exemplarily, the third conductive connection layer 75 can be made of the second gate metal layer in the display panel, that is, the third conductive connection layer 75 and the second electrode plate are arranged in the same layer and made of the same material. In this way, the third conductive connection layer 75 can be formed in the same lithography process as the second electrode plate and can achieve direct coupling, thereby greatly simplifying the manufacturing process flow of the display panel and reducing the manufacturing cost.

[0124] In the display panel provided in the above embodiments, by coupling the power signal line pattern 901 to the second electrode plate, and coupling the third conductive connection layer 75 to the second electrode plates included in the respective sub-pixels in the corresponding sub-pixel group, the third conductive connection layer 75 is coupled to the power signal line patterns 901 included in the respective sub-pixels in the corresponding sub-pixel group, so that the third conductive connection layer 75 has the same stable potential as the power signal line pattern 901. In this way, when using the large-area third conductive connection layer 75 to block the gap between adjacent conductive connection portions, the stability of the display panel during operation can be better ensured.

[0125] In some embodiments, the orthographic projection of the first conductive connection portion 71 on the substrate overlaps with the orthographic projection of the third conductive connection portion 73 on the substrate and the orthographic projection of one of the two fourth conductive connection portions 74 on the substrate; and / or, the orthographic projection of the second conductive connection portion 72 on the substrate overlaps with the orthographic projection of the third conductive connection portion 73 on the substrate and the orthographic projection of the other of the two fourth conductive connection portions 74 on the substrate.

[0126] Specifically, since the first conductive connection portion 71 and the second conductive connection portion 72 are both disposed in a different layer from the third conductive connection portion 73 and the fourth conductive connection portion 74, even if the first conductive connection portion 71 overlaps with the third conductive connection portion 73 and the fourth conductive connection portion 74 in the direction perpendicular to the substrate, the first conductive connection portion 71 will not be short-circuited with the third conductive connection portion 73 and the fourth conductive connection portion 74. Similarly, even if the second conductive connection portion 72 overlaps with the third conductive connection portion 73 and the fourth conductive connection portion 74 in the direction perpendicular to the substrate, the second conductive connection portion 72 will not be short-circuited with the third conductive connection portion 73 and the fourth conductive connection portion 74.

[0127] The orthographic projection of the first conductive connection portion 71 on the substrate, respectively, overlaps with the orthographic projection of the third conductive connection portion 73 on the substrate and the orthographic projection of one of the two fourth conductive connection portions 74 on the substrate, which can effectively reduce the layout space occupied by the first conductive connection portion 71, the third conductive connection portion 73, and the fourth conductive connection portion 74 as a whole. Similarly, setting the orthographic projection of the second conductive connection portion 72 on the substrate to overlap with the orthographic projection of the third conductive connection portion 73 on the substrate and the orthographic projection of the other of the two fourth conductive connection portions 74 on the substrate can effectively reduce the layout space occupied by the second conductive connection portion 72, the third conductive connection portion 73, and the fourth conductive connection portion 74 as a whole. Therefore, the above setting method can minimize the layout space occupied by the conductive connection structure to the greatest extent and effectively improve the light transmittance of the display panel in the second pixel region.

[0128] As Figure 4 shown, in some embodiments, the first conductive connection portion 71, the second conductive connection portion 72, and the fourth conductive connection portion 74 each include a first side portion and a second side portion, and an intermediate portion located between the first side portion and the second side portion; the intermediate portion extends in a first direction, the first side portion includes a portion extending in the first direction and a portion extending in a second direction, and the second side portion includes a portion extending in the first direction and a portion extending in the second direction;

[0129] As Figure 6 and Figure 9 shown, the orthographic projection of the intermediate portion 743 included in one of the two fourth conductive connection portions 74 on the substrate, the orthographic projection of the intermediate portion included in the first conductive connection portion 71 on the substrate, the orthographic projection of the third portion 733 of the third conductive connection portion 73 on the substrate, the orthographic projection of the intermediate portion included in the second conductive connection portion 72 on the substrate, and the orthographic projection of the intermediate portion included in the other of the two fourth conductive connection portions 74 on the substrate are arranged in sequence along the second direction.

[0130] Specifically, the specific structures of the first conductive connection portion 71, the second conductive connection portion 72, and the fourth conductive connection portion 74 are diverse. Exemplarily, the first conductive connection portion 71, the second conductive connection portion 72, and the fourth conductive connection portion 74 each include a first side portion and a second side portion, and an intermediate portion located between the first side portion and the second side portion.

[0131] Exemplarily, the middle portions 713 of the first conductive connection portion 71, the middle portions 723 of the second conductive connection portion 72, and the middle portions 743 of the fourth conductive connection portion 74 can all extend along the first direction; the first side portion 711 and the second side portion 712 of the first conductive connection portion 71 each include a portion extending along the first direction and a portion extending along the second direction; the first side portion 721 and the second side portion 722 of the second conductive connection portion 72 each include a portion extending along the first direction and a portion extending along the second direction; one of the two fourth conductive connection portions 74 (such as Figure 9 the mark 741 therein) includes a first side portion 744 and a second side portion 745 each including a portion extending along the first direction and a portion extending along the second direction; the other of the two fourth conductive connection portions 74 (such as Figure 9 the mark 742 therein) includes a first side portion 744 and a second side portion 745 each including a portion extending along the second direction.

[0132] Exemplarily, the orthographic projection of the middle portion included in one of the two fourth conductive connection portions 74 on the substrate, the orthographic projection of the middle portion included in the first conductive connection portion 71 on the substrate, the orthographic projection of the third part 733 of the third conductive connection portion 73 on the substrate, the orthographic projection of the middle portion included in the second conductive connection portion 72 on the substrate, and the orthographic projection of the middle portion included in the other of the two fourth conductive connection portions 74 on the substrate are closely adjacent to each other to reduce the layout space occupied by the conductive connection structure.

[0133] Exemplarily, in the first conductive connection portion 71, the second conductive connection portion 72, and the fourth conductive connection portion 74, the first side portion and the second side portion included both extend away from the middle portion.

[0134] With the above arrangement, the orthographic projection of the middle portion included in one of the two fourth conductive connection portions 74 on the substrate, the orthographic projection of the middle portion included in the first conductive connection portion 71 on the substrate, the orthographic projection of the third part 733 of the third conductive connection portion 73 on the substrate, the orthographic projection of the middle portion included in the second conductive connection portion 72 on the substrate, and the orthographic projection of the middle portion included in the other of the two fourth conductive connection portions 74 on the substrate are closely adjacent to each other and are arranged in sequence along the second direction, which can effectively reduce the layout space occupied by the conductive connection structure while meeting the connection requirements.

[0135] Such as Figure 10 , Figure 11 and Figure 12As shown, in some embodiments, the sub-pixel driving circuit includes a storage capacitor. The storage capacitor includes a first electrode plate and a second electrode plate oppositely arranged along a direction perpendicular to the substrate. The first electrode plate is located between the substrate and the second electrode plate;

[0136] The fourth signal line pattern 84 includes a power supply signal line pattern 901. At least a part of the power supply signal line pattern 901 extends along a second direction. The second electrode plate is coupled to the power supply signal line pattern 901;

[0137] The second conductive connection layer includes a fourth conductive connection portion 74. The fourth conductive connection portion 74 is respectively coupled to the second electrode plates included in each sub-pixel in the corresponding sub-pixel group.

[0138] Specifically, the sub-pixel driving circuit includes a driving transistor and a storage capacitor. The storage capacitor includes a first electrode plate and a second electrode plate oppositely arranged. The first electrode plate is located between the substrate and the second electrode plate. Exemplarily, the first electrode plate is reused as the gate of the driving transistor. Exemplarily, the first electrode plate is made of a first gate metal layer in the display panel, and the second electrode plate is made of a second gate metal layer in the display panel.

[0139] The fourth signal line pattern 84 includes a power supply signal line pattern 901. At least a part of the power supply signal line pattern 901 extends along a second direction. In the same sub-pixel, the orthographic projection of the second electrode plate on the substrate and the orthographic projection of the power supply signal line pattern 901 on the substrate form an overlapping area. In this overlapping area, the power supply signal line pattern 901 is coupled to the second electrode plate through a via hole. Exemplarily, the power supply signal line pattern 901 can be made of a first source-drain metal layer in the display panel. Exemplarily, the power supply signal line patterns 901 in each column of sub-pixels located along the second direction are sequentially coupled and can form an integral structure.

[0140] The second conductive connection layer may include a fourth conductive connection portion 74. Exemplarily, the fourth conductive connection portion 74 is made of a first source-drain metal layer in the display panel. The orthographic projection of the fourth conductive connection portion 74 on the substrate and the orthographic projection of the corresponding second electrode plate on the substrate have an overlapping area. The fourth conductive connection portion 74 is coupled to the corresponding second electrode plate through a via hole provided in this overlapping area.

[0141] In the display panel provided by the above embodiments, by coupling the second electrode plate to the power signal line pattern 901, and coupling the fourth conductive connection portion 74 to the second electrode plates included in the respective sub-pixels of the corresponding sub-pixel group, the fourth conductive connection portion 74 is coupled to the power signal line patterns 901 included in the respective sub-pixels of the corresponding sub-pixel group.

[0142] As Figure 10 and Figure 11 shown, in some embodiments, the fifth signal line pattern 85 includes two initialization signal line patterns arranged along the second direction, and the third conductive connection layer 75 is respectively coupled to the initialization signal line patterns included in the respective sub-pixels of the corresponding sub-pixel group.

[0143] Specifically, at least a part of the initialization signal line pattern extends along the first direction, and the initialization signal line pattern is used to transmit an initialization signal, and the initialization signal is a DC signal with a stable potential.

[0144] Exemplarily, the third conductive connection layer 75 and the initialization signal line pattern are formed as an integral structure. This setting method enables the third conductive connection layer 75 and the initialization signal line pattern to be formed simultaneously in the sequential patterning process and enables direct coupling.

[0145] By setting the third conductive connection layer 75 to be respectively coupled to the initialization signal line patterns included in the respective sub-pixels of the corresponding sub-pixel group, the third conductive connection layer 75 can be coupled to four initialization signal line patterns included in the corresponding sub-pixel group at the same time. This setting method enables the third conductive connection layer 75 to have the same stable potential as the initialization signal line pattern. When using the large-area third conductive connection layer 75 to block the gap between adjacent conductive connection portions, the stability of the display panel during operation can be better ensured.

[0146] As Figure 10 shown, in some embodiments, it can be set that the orthographic projection of the fourth conductive connection portion 74 on the substrate is located between the orthographic projection of the first conductive connection portion 71 on the substrate and the orthographic projection of the second conductive connection portion 72 on the substrate; the orthographic projection of the third conductive connection portion 73 on the substrate overlaps with the orthographic projection of the second conductive connection portion 72 on the substrate.

[0147] Specifically, in the sub-pixel, the orthographic projection of the second electrode plate on the substrate is located between the orthographic projection of the first reset signal line pattern 905 on the substrate and the orthographic projection of the light emission control signal line pattern 903 on the substrate. The above setting makes the orthographic projection of the fourth conductive connection portion 74 on the substrate located between the orthographic projection of the first conductive connection portion 71 on the substrate and the orthographic projection of the second conductive connection portion 72 on the substrate, which is more conducive to reducing the layout difficulty of the first conductive connection portion 71, the second conductive connection portion 72, and the fourth conductive connection portion 74.

[0148] The above setting makes the orthographic projection of the third conductive connection portion 73 on the substrate overlap with the orthographic projection of the second conductive connection portion 72 on the substrate, so that the layout space jointly occupied by the second conductive connection portion 72 and the third conductive portion is reduced, thereby better improving the light transmittance of the display panel in the second pixel region.

[0149] In some embodiments, the orthographic projection of the fourth conductive connection portion 74 on the substrate may be set to overlap with the orthographic projection of the first conductive connection portion 71 on the substrate and the orthographic projection of the second conductive connection portion 72 on the substrate respectively.

[0150] The above setting makes the orthographic projection of the fourth conductive connection portion 74 on the substrate overlap with the orthographic projection of the first conductive connection portion 71 on the substrate and the orthographic projection of the second conductive connection portion 72 on the substrate respectively, so that the layout space jointly occupied by the first conductive connection portion 71, the second conductive connection portion 72, and the fourth conductive portion is reduced, thereby better improving the light transmittance of the display panel in the second pixel region.

[0151] In some embodiments, the orthographic projection of the fourth conductive connection portion 74 on the substrate overlaps with the orthographic projection of the first conductive connection portion 71 on the substrate; the orthographic projection of the third conductive connection portion 73 on the substrate overlaps with the orthographic projection of the second conductive connection portion 72 on the substrate.

[0152] The above setting makes the orthographic projection of the fourth conductive connection portion 74 on the substrate overlap with the orthographic projection of the first conductive connection portion 71 on the substrate, and the orthographic projection of the third conductive connection portion 73 on the substrate overlap with the orthographic projection of the second conductive connection portion 72 on the substrate, so that the layout space jointly occupied by the first conductive connection portion 71, the second conductive connection portion 72, the third conductive connection portion 73, and the fourth conductive portion is reduced, thereby better improving the light transmittance of the display panel in the second pixel region.

[0153] Such as Figure 6 AndFigure 9 As shown, in some embodiments, the first conductive connection portion 71, the second conductive connection portion 72, and the fourth conductive connection portion 74 each include a first side portion and a second side portion, and an intermediate portion located between the first side portion and the second side portion; the intermediate portion extends in a first direction, the first side portion includes a portion extending in the first direction and a portion extending in a second direction, and the second side portion includes a portion extending in the first direction and a portion extending in the second direction;

[0154] There is the first gap between the intermediate portion 713 of the first conductive connection portion 71 and the intermediate portion 723 of the second conductive connection portion 72. The first gap has a first width in a direction perpendicular to the first direction, and the first width is the minimum width that satisfies the insulation condition between the intermediate portion 713 of the first conductive connection portion 71 and the intermediate portion 723 of the second conductive connection portion 72;

[0155] There is the second gap between the intermediate portion of the third conductive connection portion 73 and the intermediate portion 743 of the fourth conductive connection portion 74. The second gap has a second width in a direction perpendicular to the first direction, and the second width is the minimum width that satisfies the insulation condition between the intermediate portion of the third conductive connection portion 73 and the intermediate portion 743 of the fourth conductive connection portion 74.

[0156] Specifically, since the first conductive connection portion 71 and the second conductive connection portion 72 are arranged in the same layer and correspondingly connect signal line patterns for transmitting different signals, therefore, the first conductive connection portion 71 and the second conductive connection portion 72 need to be spaced apart to avoid short - circuit between the first conductive connection portion 71 and the second conductive connection portion 72.

[0157] Similarly, since the third conductive connection portion 73 and the fourth conductive connection portion 74 are arranged in the same layer and correspondingly connect signal line patterns for transmitting different signals, therefore, the third conductive connection portion 73 and the fourth conductive connection portion 74 need to be spaced apart to avoid short - circuit between the third conductive connection portion 73 and the fourth conductive connection portion 74.

[0158] The above - mentioned setting that there is the first gap between the intermediate portion 713 of the first conductive connection portion 71 and the intermediate portion 723 of the second conductive connection portion 72, and there is the second gap between the intermediate portion of the third conductive connection portion 73 and the intermediate portion 743 of the fourth conductive connection portion 74 enables the first conductive connection portion 71, the second conductive connection portion 72, the third conductive connection portion 73, and the fourth conductive connection portion 74 to be compactly arranged, thereby better improving the light transmittance of the display panel in the second pixel region.

[0159] In some embodiments, the positive projection of the third conductive connection layer 75 on the substrate may overlap with the positive projections of the first conductive connection portion 71, the second conductive connection portion 72, the third conductive connection portion 73, and the fourth conductive connection portion 74 on the substrate.

[0160] With the above arrangement, the first conductive connection portion 71, the second conductive connection portion 72, the third conductive connection portion 73, the fourth conductive connection portion 74, and the third conductive connection layer 75 can be compactly arranged, thereby better improving the light transmittance of the display panel in the second pixel region.

[0161] As Figure 4 shown, in some embodiments, the first conductive connection portion 71, the second conductive connection portion 72, and the fourth conductive connection portion 74 each include a first side portion, a second side portion, and an intermediate portion located between the first side portion and the second side portion; the intermediate portion extends in a first direction, the first side portion includes a portion extending in the first direction and a portion extending in a second direction, and the second side portion includes a portion extending in the first direction and a portion extending in the second direction;

[0162] The positive projection of the intermediate portion included in the fourth conductive connection portion 74 on the substrate, the positive projection of the intermediate portion included in the first conductive connection portion 71 on the substrate, the positive projection of the third part 733 of the third conductive connection portion 73 on the substrate, and the positive projection of the intermediate portion included in the second conductive connection portion 72 on the substrate are all located inside the positive projection of the third conductive connection layer 75 on the substrate.

[0163] With the above arrangement, the first conductive connection portion 71, the second conductive connection portion 72, the third conductive connection portion 73, the fourth conductive connection portion 74, and the third conductive connection layer 75 can be compactly arranged, thereby better improving the light transmittance of the display panel in the second pixel region.

[0164] It should be noted that in addition to reducing the layout space of the conductive connection structure by setting the gap width and the overlapping relationship between different conductive connection portions, the line widths of the first conductive connection portion 71, the second conductive connection portion 72, the third conductive connection portion 73, the fourth conductive connection portion 74, and the area of the third conductive connection layer 75 can also be minimized as much as possible under the condition of meeting the functional requirements, thereby better improving the light transmittance of the display panel in the second pixel region.

[0165] In some embodiments, it may be provided that the sub-pixel further includes a data line pattern 908, and the data line pattern 908 extends in the second direction; the sub-pixel driving circuit includes: a transistor structure and a storage capacitor, and the storage capacitor includes a first electrode plate and a second electrode plate which are oppositely arranged; the first conductive connection layer is provided on the same layer and made of the same material as the gate of the transistor structure; the second conductive connection layer is provided on the same layer and made of the same material as the data line pattern 908; the third conductive connection layer 75 is provided on the same layer and made of the same material as the second electrode plate.

[0166] The above setting of the first conductive connection layer on the same layer and made of the same material as the gate of the transistor structure enables the first conductive connection layer and the gate of the transistor structure to be formed in the same lithography process; the setting of the second conductive connection layer on the same layer and made of the same material as the data line pattern 908 enables the second conductive connection layer and the data line pattern 908 to be formed in the same lithography process; the setting of the third conductive connection layer 75 on the same layer and made of the same material as the second electrode plate enables the third conductive connection layer 75 and the second electrode plate to be formed in the same lithography process; thereby better simplifying the manufacturing process flow of the display panel and saving the manufacturing cost.

[0167] In some embodiments, it may be provided that the sub-pixel further includes a data line pattern 908, and the data line pattern 908 extends in the second direction; the sub-pixel driving circuit includes: a transistor structure and a storage capacitor, and the storage capacitor includes a first electrode plate and a second electrode plate which are oppositely arranged; the first conductive connection layer is provided on the same layer and made of the same material as the second electrode plate; the second conductive connection layer is provided on the same layer and made of the same material as the data line pattern 908; the third conductive connection layer 75 is provided on the same layer and made of the same material as the gate of the transistor structure.

[0168] The above setting of the first conductive connection layer on the same layer and made of the same material as the second electrode plate enables the first conductive connection layer and the second electrode plate to be formed in the same lithography process; the setting of the second conductive connection layer on the same layer and made of the same material as the data line pattern 908 enables the second conductive connection layer and the data line pattern 908 to be formed in the same lithography process; the setting of the third conductive connection layer 75 on the same layer and made of the same material as the gate of the transistor structure enables the third conductive connection layer 75 and the gate of the transistor structure to be formed in the same lithography process; thereby better simplifying the manufacturing process flow of the display panel and saving the manufacturing cost.

[0169] In some embodiments, the first signal line pattern includes a first reset signal line pattern, the second signal line pattern includes a light emission control signal line pattern, and the third signal line pattern includes a gate line pattern and a second reset signal line pattern; the sub-pixel further includes a power supply signal line pattern, a data line pattern, a first initialization signal line pattern, and a second initialization signal line pattern;

[0170] The sub-pixel driving circuit includes: a storage capacitor, a driving transistor, a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor;

[0171] The gate of the driving transistor is coupled to the second pole of the first transistor, the first pole of the driving transistor is coupled to the second pole of the fifth transistor, and the second pole of the driving transistor is coupled to the first pole of the first transistor;

[0172] The gate of the first transistor is coupled to the gate line pattern;

[0173] The gate of the second transistor is coupled to the first reset signal line pattern, the first pole of the second transistor is coupled to the first initialization signal line pattern, and the second pole of the second transistor is coupled to the gate of the driving transistor;

[0174] The gate of the fourth transistor is coupled to the gate line pattern, the first pole of the fourth transistor is coupled to the data line pattern, and the second pole of the fourth transistor is coupled to the first pole of the driving transistor;

[0175] The gate of the fifth transistor is coupled to the light emission control signal line pattern, and the first pole of the fifth transistor is coupled to the power supply signal line pattern;

[0176] The gate of the sixth transistor is coupled to the light emission control signal line pattern, the first pole of the sixth transistor is coupled to the second pole of the driving transistor, and the second pole of the sixth transistor is coupled to the corresponding light emitting element in the display panel;

[0177] The second pole of the seventh transistor is coupled to the corresponding light emitting element, the gate of the seventh transistor is coupled to the second reset signal line pattern, and the first pole of the seventh transistor is coupled to the second initialization signal line pattern.

[0178] Specifically, such as Figure 1 、 Figure 4 and Figure 10As shown, the multiple sub-pixel driving circuits included in the display panel can be divided into multiple rows of sub-pixel driving circuits arranged in sequence along the second direction and multiple columns of sub-pixel driving circuits arranged in sequence along the first direction. The first initialization signal line patterns 904 corresponding to the sub-pixel driving circuits belonging to the same pixel unit are electrically connected in sequence to form an integrated structure; the second initialization signal line patterns 904' corresponding to the sub-pixel driving circuits belonging to the same pixel unit are electrically connected in sequence to form an integrated structure; the gate line patterns 902 corresponding to the sub-pixel driving circuits belonging to the same pixel unit are electrically connected in sequence to form an integrated structure; the light emission control signal line patterns 903 corresponding to the sub-pixel driving circuits belonging to the same pixel unit are electrically connected in sequence to form an integrated structure; the first reset signal line patterns 905 corresponding to the sub-pixel driving circuits belonging to the same pixel unit are electrically connected in sequence to form an integrated structure; the second reset signal line patterns 905' corresponding to the sub-pixel driving circuits belonging to the same pixel unit are electrically connected in sequence to form an integrated structure; the data line patterns 908 corresponding to the sub-pixel driving circuits located in the same column are electrically connected in sequence to form an integrated structure; the power supply signal line patterns 901 corresponding to the sub-pixel driving circuits located in the same column are electrically connected in sequence to form an integrated structure.

[0179] As Figure 1 , Figure 4 and Figure 10 shown, taking a sub-pixel driving circuit as an example, this sub-pixel driving circuit includes 7 thin film transistors and 1 capacitor. Each transistor included in this sub-pixel driving circuit is a P-type transistor. Among them, the first transistor T1 has a double-gate structure. The gate 201g of the first transistor T1 is coupled to the gate line pattern 902. The source S1 of the first transistor T1 is coupled to the drain D3 of the third transistor T3 (i.e., the driving transistor). The drain D1 of the first transistor T1 is coupled to the gate 203g of the third transistor T3.

[0180] The second transistor T2 has a double-gate structure. The gate 202g of the second transistor T2 is coupled to the first reset signal line pattern 905. The source S2 of the second transistor T2 is coupled to the first initialization signal line pattern 904. The drain D2 of the second transistor T2 is coupled to the gate 203g of the third transistor T3.

[0181] The gate 204g of the fourth transistor T4 is coupled to the gate line pattern 902. The source S4 of the fourth transistor T4 is coupled to the data line pattern 908. The drain D4 of the fourth transistor T4 is coupled to the source S3 of the third transistor T3.

[0182] The gate 205g of the fifth transistor T5 is coupled to the light emission control signal line pattern 903, the source S5 of the fifth transistor T5 is coupled to the power supply signal line pattern 901, and the drain D5 of the fifth transistor T5 is coupled to the source S3 of the third transistor T3.

[0183] The gate 206g of the sixth transistor T6 is coupled to the light emission control signal line pattern 903, the source S6 of the sixth transistor T6 is coupled to the drain D3 of the third transistor T3, and the drain D6 of the sixth transistor T6 is coupled to the corresponding light emitting element in the display panel.

[0184] The gate 207g of the seventh transistor T7 is coupled to the second reset signal line pattern 905', the drain D7 of the seventh transistor T7 is coupled to the light emitting element, and the source S7 of the seventh transistor T7 is coupled to the second initialization signal line pattern 904'.

[0185] The first electrode plate Cst1 of the storage capacitor Cst is multiplexed as the gate 203g of the third transistor T3, and the second electrode plate Cst2 of the storage capacitor Cst is coupled to the power supply signal line pattern 901.

[0186] As Figure 2 and Figure 3 shown, when the display sub-pixel driving circuit of the above structure is working, each working cycle includes a reset period P1, a write compensation period P2, and a light emission period P3. Figure 3 Among them, E1 represents the light emission control signal transmitted on the light emission control signal line pattern 903 in the current sub-pixel, R1 represents the reset signal transmitted on the first reset signal line pattern 905 in the current sub-pixel, D1 represents the data signal transmitted on the data line pattern 908 in the current sub-pixel, G1 represents the gate scan signal transmitted on the gate line pattern 902 in the current sub-pixel, and R1' represents the reset signal transmitted on the second reset signal line pattern 905' in the current sub-pixel. When the display panel functions, it scans line by line in the direction from bottom to top.

[0187] In the first reset period P1, the reset signal input by the first reset signal line pattern 905 is at an effective level, the second transistor T2 is turned on, and the initialization signal input by the first initialization signal line pattern 904’ is input to the gate 203g of the third transistor T3, so that the gate-source voltage Vgs held on the third transistor T3 in the previous frame is cleared, realizing the reset of the gate 203g of the third transistor T3.

[0188] During the write compensation period P2, the reset signal input to the first reset signal line pattern 905 is at an invalid level, the second transistor T2 is turned off, the gate scan signal input to the gate line pattern 902 is at a valid level, controlling the first transistor T1 and the fourth transistor T4 to conduct, writing a data signal to the data line pattern 908, and transmitting it to the source S3 of the third transistor T3 through the fourth transistor T4. At the same time, when the first transistor T1 and the fourth transistor T4 conduct, the third transistor T3 is formed into a diode structure. Therefore, through the cooperation of the first transistor T1, the third transistor T3, and the fourth transistor T4, the threshold voltage compensation of the third transistor T3 is achieved. When the compensation time is long enough, the potential of the gate 203g of the third transistor T3 can be controlled to finally reach Vdata + Vth, where Vdata represents the data signal voltage value and Vth represents the threshold voltage of the third transistor T3.

[0189] During the write compensation period P2, the reset signal input to the second reset signal line pattern 905' is at a valid level, controlling the seventh transistor T7 to conduct, and the initialization signal transmitted by the second initialization signal line pattern 904' is input to the anode of the light-emitting element EL, controlling the light-emitting element EL not to emit light.

[0190] During the light-emitting period P3, the light-emitting control signal written to the light-emitting control signal line pattern 903 is at a valid level, controlling the fifth transistor T5 and the sixth transistor T6 to conduct, so that the power supply signal transmitted by the power supply signal line pattern 901 is input to the source S3 of the third transistor T3. At the same time, since the gate 203g of the third transistor T3 is maintained at Vdata + Vth, the third transistor T3 conducts, and the gate-source voltage corresponding to the third transistor T3 is Vdata + Vth - VDD, where VDD is the voltage value corresponding to the power supply signal. The leakage current generated based on this gate-source voltage flows to the anode of the corresponding light-emitting element EL, driving the corresponding light-emitting element EL to emit light.

[0191] As Figures 4 to 7 shown, when manufacturing the above display sub-pixel driving circuit, the layout of each film layer corresponding to the display sub-pixel driving circuit is as follows:

[0192] An active film layer, a gate insulating layer, a first gate metal layer, a first interlayer insulating layer, a second gate metal layer, a second interlayer insulating layer, a first source-drain metal layer, and a third interlayer insulating layer are sequentially stacked in a direction away from the substrate.

[0193] As Figure 5As shown, the active film layer is used to form the channel regions (such as 101pg - 107pg) of the transistors in the display sub-pixel driving circuit, the source formation regions and the drain formation regions. Due to the doping effect, the conductivity of the active film layer corresponding to the source formation region and the drain formation region is better than that of the active film layer corresponding to the channel region. The active film layer can be made of amorphous silicon, polysilicon, oxide semiconductor materials, etc. It should be noted that the above-mentioned source region and drain region can be regions doped with n-type impurities or p-type impurities.

[0194] In addition, it is worth noting that the active film layer corresponding to the source formation region and the drain formation region can be directly used as the corresponding source (such as S1 - S7) and drain (such as D1 - D7), or alternatively, a source in contact with the source formation region can be made of a metal material, and a drain in contact with the drain formation region can be made of a metal material.

[0195] As Figure 6 shown, the first gate metal layer is used to form the gates of the transistors in the sub-pixel driving circuit (such as 201g - 207g), as well as structures such as the gate line pattern 902, the light emission control signal line pattern 903, and the reset signal line pattern 905 included in the display panel. The gate 203g of the third transistor T3 in each sub-pixel driving circuit is multiplexed as the first electrode plate Cst1 of the second storage capacitor Cst in this sub-pixel driving circuit.

[0196] As Figure 7 shown, the second gate metal layer is used to form the second electrode plate Cst2 of the second storage capacitor Cst, as well as the first initialization signal line pattern 904 and the second initialization signal line pattern 904' included in the display substrate.

[0197] As Figure 8 shown, the first source-drain metal layer is used to form the data line pattern 908, the power supply signal line pattern 901, and some conductive connection parts included in the display panel.

[0198] More specifically, please continue to refer to Figures 4 to 5 , the gate 201g of the first transistor T1 covers the first channel region 101pg, the gate 202g of the second transistor T2 covers the second channel region 102pg, the gate 203g of the third transistor T3 covers the third channel region 103pg, the gate 204g of the fourth transistor T4 covers the fourth channel region 104pg, the gate 205g of the fifth transistor T5 covers the fifth channel region 105pg, the gate 206g of the sixth transistor T6 covers the sixth channel region 106pg, and the gate 207g of the seventh transistor T7 covers the seventh channel region 107pg. The gate 203g of the third transistor T3 is multiplexed as the first electrode plate Cst1 of the storage capacitor Cst, and the second electrode plate Cst2 of the storage capacitor Cst is coupled to the power supply signal line pattern 901.

[0199] In addition, as Figure 4 shown, in the second direction (such as the Y direction) of the display panel provided by the present disclosure, the gate 204g of the fourth transistor T4, the gate 201g of the first transistor T1, and the gate 202g of the second transistor T2 are all located on the first side of the gate of the driving transistor (i.e., the gate 203g of the third transistor T3), and the gate of the seventh transistor T7, the gate 206g of the sixth transistor T6, and the gate of the fifth transistor T5 are all located on the second side of the gate of the driving transistor. Exemplarily, the first side and the second side of the gate of the driving transistor are two sides opposite to each other along the second direction. Further, the first side of the gate of the driving transistor may be the lower side of the gate of the driving transistor, and the second side of the gate of the driving transistor may be the upper side of the gate of the driving transistor. The lower side, for example, the side of the display panel for binding the IC is the lower side of the display panel, and the lower side of the gate of the driving transistor is the side of the gate of the driving transistor closer to the IC. The upper side is the opposite side of the lower side, for example, the side of the gate of the driving transistor farther from the IC.

[0200] In the first direction (such as the X direction), the gate 204g of the fourth transistor T4 and the gate 205g of the fifth transistor T5 are both located on the third side of the gate of the driving transistor, and the gate 201g of the first transistor T1 and the gate 206g of the sixth transistor T6 are both located on the fourth side of the gate of the driving transistor. Exemplarily, the third side and the fourth side of the gate of the driving transistor are two sides opposite to each other along the first direction; further, the third side of the gate of the driving transistor may be the right side of the gate of the driving transistor, and the fourth side of the gate of the driving transistor may be the left side of the gate of the driving transistor. The left side and the right side, for example, in the same sub-pixel, the data line pattern 908 is located on the right side of the power supply signal line pattern 901, and the power supply signal line pattern 901 is located on the left side of the data line pattern 908.

[0201] The embodiment of the present disclosure also provides a display device, and the display device includes the display panel provided in the above embodiment.

[0202] In the display panel provided in the above embodiments, a conductive connection structure is provided between two sub-pixels included in the sub-pixel group. The conductive connection structure includes: a first conductive connection layer, a second conductive connection layer, and a third conductive connection layer 75 that are arranged in different layers; the first conductive connection layer and the second conductive connection layer are used to couple together signal line patterns for transmitting the same signal included in each sub-pixel in the sub-pixel group; the third conductive connection layer 75 is used to couple together fifth signal line patterns 85 for transmitting a fifth signal with a fixed potential included in each sub-pixel in the sub-pixel group; therefore, by providing the conductive connection structure, the display panel provided in the above embodiments realizes the corresponding coupling together of the signal line patterns for transmitting the same signal included in each sub-pixel in the sub-pixel group.

[0203] In addition, in the display panel provided in the above embodiments, by setting the orthographic projection of the third conductive connection layer 75 on the substrate of the display panel to cover the orthographic projection of the first gap on the substrate and the orthographic projection of the second gap on the substrate, the third conductive connection layer 75 can cover the gap between adjacent conductive connection parts between two sub-pixels in the sub-pixel group, reducing the light leakage phenomenon generated at the gap, thereby avoiding problems such as disturbing diffraction and glare generated when light passes through the gap, and better ensuring the imaging quality of the camera in the display panel during photographing.

[0204] Furthermore, in the display panel provided in the above embodiments, the third conductive connection layer 75 is coupled to the fifth signal line pattern 85 for transmitting a fifth signal with a fixed potential, so that the third conductive connection layer 75 has a stable potential and will not have too much impact on the RC (resistance-capacitance) loading of the fifth signal line pattern 85.

[0205] Therefore, when the display device provided in the embodiments of the present disclosure includes the above display panel, it also has the above beneficial effects, which will not be elaborated here.

[0206] It should be noted that the display device may be: a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, or any product or component with a display function, etc.

[0207] The embodiments of the present disclosure also provide a manufacturing method for a display panel for manufacturing the display panel provided in the above embodiments. The display panel includes a first pixel area and a second pixel area, and the pixel density of the second pixel area is lower than that of the first pixel area; the manufacturing method includes:

[0208] Manufacturing a plurality of pixel units and a plurality of conductive connection structures distributed in an array in the second pixel area;

[0209] The multiple pixel units form multiple rows of pixel unit rows, and each row of pixel unit rows includes multiple pixel units arranged in a first direction; each pixel unit includes multiple sub-pixels arranged in the first direction, and in the same row of pixel unit rows, the two closest sub-pixels in two adjacent pixel units form a sub-pixel group; the sub-pixel includes: a sub-pixel driving circuit, and a first signal line pattern to a fifth signal line pattern respectively coupled to the sub-pixel driving circuit;

[0210] The multiple conductive connection structures correspond to the sub-pixel groups one by one, the conductive connection structures are located between the two sub-pixels included in the corresponding sub-pixel group, and the conductive connection structures include: a first conductive connection layer, a second conductive connection layer and a third conductive connection layer arranged in different layers;

[0211] The first conductive connection layer includes a first conductive connection portion and a second conductive connection portion, and there is a first gap between the first conductive connection portion and the second conductive connection portion; the first conductive connection portion is respectively coupled to the first signal line patterns included in the respective sub-pixels in the corresponding sub-pixel group, and the second conductive connection portion is respectively coupled to the second signal line patterns included in the respective sub-pixels in the corresponding sub-pixel group;

[0212] The second conductive connection layer includes a third conductive connection portion and at least one fourth conductive connection portion, and there is a second gap between the adjacent third conductive connection portion and the fourth conductive connection portion; the third conductive connection portion is respectively coupled to the third signal line patterns included in the respective sub-pixels in the corresponding sub-pixel group, the at least one fourth conductive connection portion corresponds to the fourth signal line patterns included in each sub-pixel in the corresponding sub-pixel group one by one, and the fourth conductive connection portions are respectively coupled to the corresponding fourth signal line patterns;

[0213] The third conductive connection layer is respectively coupled to the fifth signal line patterns included in the respective sub-pixels in the corresponding sub-pixel group, the fifth signal line pattern is used to transmit a fifth signal with a fixed potential, and the orthographic projection of the third conductive connection layer on the substrate of the display panel covers at least part of the orthographic projection of the first gap on the substrate and at least part of the orthographic projection of the second gap on the substrate.

[0214] In the display panel manufactured by using the manufacturing method provided by the embodiments of the present disclosure, a conductive connection structure is disposed between two sub-pixels included in a sub-pixel group. The conductive connection structure includes: a first conductive connection layer, a second conductive connection layer, and a third conductive connection layer 75 which are arranged in different layers; the first conductive connection layer and the second conductive connection layer are used to couple together signal line patterns for transmitting the same signal included in each sub-pixel in the sub-pixel group; the third conductive connection layer 75 is used to couple together fifth signal line patterns 85 for transmitting a fifth signal with a fixed potential included in each sub-pixel in the sub-pixel group; therefore, in the display panel manufactured by using the manufacturing method provided by the embodiments of the present disclosure, by disposing the conductive connection structure, the signal line patterns for transmitting the same signal included in each sub-pixel in the sub-pixel group are correspondingly coupled together.

[0215] In addition, in the display panel manufactured by using the manufacturing method provided by the embodiments of the present disclosure, by disposing the positive projection of the third conductive connection layer 75 on the substrate of the display panel to cover at least part of the positive projection of the first gap on the substrate and at least part of the positive projection of the second gap on the substrate, the third conductive connection layer 75 can cover the gap between adjacent conductive connection parts between two sub-pixels in the sub-pixel group, reducing the light leakage phenomenon generated at the gap, thereby avoiding problems such as interference diffraction and glare generated when light passes through the gap, and better ensuring the imaging quality of the camera in the display panel when taking pictures.

[0216] In addition, in the display panel manufactured by using the manufacturing method provided by the embodiments of the present disclosure, the third conductive connection layer 75 is coupled to the fifth signal line pattern 85 for transmitting a fifth signal with a fixed potential, so that the third conductive connection layer 75 has a stable potential and will not have too much influence on the RC (resistance-capacitance) loading of the fifth signal line pattern 85.

[0217] It should be noted that the embodiments in this specification are all described in a progressive manner. The same or similar parts between the embodiments can be referred to each other, and the key points of each embodiment are the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the product embodiments, they are described relatively simply, and the relevant parts can be referred to the partial description of the product embodiments.

[0218] Unless otherwise defined, technical terms or scientific terms used in this disclosure shall have the ordinary meanings as understood by those of ordinary skill in the field to which this disclosure pertains. The "first", "second" and similar terms used in this disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Words such as "comprising" or "including" mean that the elements or items appearing before this word cover the elements or items listed after this word and their equivalents, without excluding other elements or items. Words such as "connected", "coupled" or "linked" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper", "lower", "left", "right", etc. are only used to indicate relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0219] It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, the element can be "directly" on or under the other element, or intervening elements may be present.

[0220] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in any one or more embodiments or examples in a suitable manner.

[0221] As described above, the above are only specific embodiments of this disclosure, but the protection scope of this disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by this disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of this disclosure. Therefore, the protection scope of this disclosure shall be subject to the protection scope of the claims.

Claims

1. A display panel includes a first pixel region and a second pixel region, and the pixel density of the second pixel region is lower than that of the first pixel region; the second pixel region includes a plurality of pixel units distributed in an array, each pixel unit includes a plurality of sub-pixels, and the two closest sub-pixels in two adjacent pixel units form a sub-pixel group; the sub-pixels include: A sub-pixel driving circuit, and a first signal line pattern, a third signal line pattern, a fourth signal line pattern, and a fifth signal line pattern respectively coupled to the sub-pixel driving circuit; The display panel further includes: a plurality of conductive connection structures corresponding to the sub-pixel groups one by one, the conductive connection structures being located between two sub-pixels included in the corresponding sub-pixel groups, and the conductive connection structures including: a first conductive connection layer, a second conductive connection layer, and a third conductive connection layer arranged in different layers; The first conductive connection layer includes a first conductive connection portion and a second conductive connection portion, and there is a first gap between the first conductive connection portion and the second conductive connection portion; the first conductive connection portion is respectively coupled to the first signal line patterns included in each sub-pixel in the corresponding sub-pixel group; The second conductive connection layer includes a third conductive connection portion and at least one fourth conductive connection portion, and there is a second gap between the adjacent third conductive connection portion and the fourth conductive connection portion; the third conductive connection portion is respectively coupled to the third signal line patterns included in each sub-pixel in the corresponding sub-pixel group, and the at least one fourth conductive connection portion corresponds to the fourth signal line patterns included in each sub-pixel in the corresponding sub-pixel group one by one, and the fourth conductive connection portions are respectively coupled to the corresponding fourth signal line patterns; The third conductive connection layer is respectively coupled to the fifth signal line patterns included in each sub-pixel in the corresponding sub-pixel group, the fifth signal line patterns are used to transmit a fifth signal with a fixed potential, and the positive projection of the third conductive connection layer on the substrate of the display panel covers at least part of the positive projection of the first gap on the substrate and at least part of the positive projection of the second gap on the substrate; along a first direction, in the same row of pixel units of the display panel, the signal line patterns in the first pixel region are electrically connected to the signal line patterns for transmitting the same signal in the second pixel region.

2. The display panel according to claim 1, wherein, The two sub-pixels in the sub-pixel group are arranged along the first direction.

3. The display panel according to claim 2, wherein, The fourth signal line pattern includes an initialization signal line pattern.

4. The display panel according to claim 3, wherein, The sub-pixel driving circuit includes a storage capacitor, and the storage capacitor includes a first electrode plate and a second electrode plate arranged oppositely, and the first electrode plate is located between the substrate and the second electrode plate; At least part of the fifth signal line pattern extends along a second direction, and the second direction intersects with the first direction.

5. The display panel according to claim 1, wherein, The positive projection of the first conductive connection portion on the substrate overlaps with the positive projection of the fourth conductive connection portion on the substrate.

6. The display panel according to claim 1, wherein, The sub-pixel driving circuit includes a storage capacitor, and the storage capacitor includes a first electrode plate and a second electrode plate arranged oppositely along a direction perpendicular to the substrate, and the first electrode plate is located between the substrate and the second electrode plate; The fourth signal line pattern includes a power supply signal line pattern, at least part of the power supply signal line pattern extends along the second direction, and the second electrode plate is coupled to the power supply signal line pattern; The second conductive connection layer includes one fourth conductive connection portion, and the fourth conductive connection portion is respectively coupled to the second electrode plates included in each sub-pixel in the corresponding sub-pixel group.

7. The display panel according to claim 6, wherein, The fifth signal line pattern includes an initialization signal line pattern, and the third conductive connection layer is respectively coupled to the initialization signal line patterns included in each sub-pixel in the corresponding sub-pixel group.

8. The display panel according to claim 1, wherein, The sub-pixel driving circuit includes: a transistor structure and a storage capacitor, and the storage capacitor includes a first electrode plate and a second electrode plate which are oppositely arranged; The first conductive connection layer is arranged on the same layer and made of the same material as the gate of the transistor structure.

9. The display panel according to claim 1, wherein, The sub-pixel includes a first reset signal line pattern, a light emission control signal line pattern, a gate line pattern, a second reset signal line pattern, a power supply signal line pattern, a data line pattern, a first initialization signal line pattern, and a second initialization signal line pattern; Each sub-pixel driving circuit includes: a storage capacitor, a driving transistor, a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; The gate of the driving transistor is coupled to the second pole of the first transistor, the first pole of the driving transistor is coupled to the second pole of the fifth transistor, and the second pole of the driving transistor is coupled to the first pole of the first transistor; The gate of the first transistor is coupled to the gate line pattern; The gate of the second transistor is coupled to the first reset signal line pattern, the first pole of the second transistor is coupled to the first initialization signal line pattern, and the second pole of the second transistor is coupled to the gate of the driving transistor; The gate of the fifth transistor is coupled to the light emission control signal line pattern, and the first pole of the fifth transistor is coupled to the power supply signal line pattern; The gate of the sixth transistor is coupled to the light emission control signal line pattern, the first pole of the sixth transistor is coupled to the second pole of the driving transistor, and the second pole of the sixth transistor is coupled to the corresponding light-emitting element in the display panel; The second pole of the seventh transistor is coupled to the corresponding light-emitting element, the gate of the seventh transistor is coupled to the second reset signal line pattern, and the first pole of the seventh transistor is coupled to the second initialization signal line pattern.

10. A display device, the display device includes the display panel according to any one of claims 1 to 9.

Images