Interference detectable time controller

Abstract

A timing controller that can detect interference includes timing control circuitry. The timing control circuitry is configured to provide an input signal to control a source driver. When at least one of the timing controller and the source driver detects that an interference event occurs in the input signal, the timing control circuitry is configured to adjust a frequency of at least one of a data signal or a clock signal from a normal operating frequency to at least one anti-interference frequency. The timing control circuitry is further configured to provide at least one of the data signal and the clock signal to the source driver.

Description

[0001] This invention is a divisional application of the invention patent application filed on January 30, 2019, with application number 201910092048.2 and title "Drive Circuit, Timing Controller and Anti-interference Method Thereof". Technical Field

[0002] The present invention relates to a display device, and more particularly to a timing controller for driving a display panel that can detect interference. Background Technology

[0003] When a mobile phone (or other radio frequency device) is near a display device, radio frequency noise (RF noise) may cause abnormalities in the display image. One reason for this is that the RF noise from the mobile phone may interfere with the transmission of data signals between the timing controller and the source drive circuit.

[0004] Figure 1 This is a schematic diagram illustrating a scenario where a mobile phone 110 is close to a display device 120. The timing controller 121 transmits data signals to the source drive circuit 122 via a transmission line, and the source drive circuit 122 drives the display panel to display an image according to the data signals. When the mobile phone 110 is close to the display device 120, the radio frequency noise 111 of the mobile phone 110 may interfere with the transmission of data signals between the timing controller 121 and the source drive circuit 122. When the energy of the radio frequency noise in the data signal is sufficiently high, the source drive circuit 122 may fail to properly latch the data signal.

[0005] Figure 2 This is an explanation Figure 1 The diagram shows a scenario where the signal received by the source drive circuit 122 is subject to radio frequency noise interference. Figure 2 The horizontal axis represents time. Figure 2 As shown, Rx represents the data signal received by the source driver circuit 122, while CDR_CLK represents the clock signal of the clock data recovery (CDR) circuit inside the source driver circuit 122. (Similar to...) Figure 2As shown in the left half, when the radio frequency noise 111 has not yet occurred, the CDR circuit inside the source drive circuit 122 can correctly lock the data signal Rx, meaning the phase of the data signal Rx can match the phase of the clock signal CDR_CLK. When the radio frequency noise 111 occurs, it interferes with the data signal Rx, causing the phase of the data signal Rx to not match the phase of the clock signal CDR_CLK. In other words, the CDR circuit inside the source drive circuit 122 may lose lock on the data signal. When the source drive circuit 122 cannot correctly lock the data signal Rx, the display panel of the display device 120 will naturally not display the correct image.

[0006] It should be noted that the content of the "Background Art" paragraph is used to help understand the present invention. Some (or all) of the content disclosed in the "Background Art" paragraph may not be publicly known to those skilled in the art. The content disclosed in the "Background Art" paragraph does not imply that such content was known to those skilled in the art prior to this application. Summary of the Invention

[0007] The present invention provides a timing controller device that can automatically determine whether an interference event occurs in the input signal, and then decide whether to dynamically adjust the operating frequency of the source drive circuit and / or the timing control circuit based on the determination result.

[0008] An embodiment of the present invention provides a timing controller. The timing controller includes a timing control circuit. The timing control circuit is configured to provide an input signal to control a source driver. When at least one of the timing control circuit and the source driver detects an interference event occurring at the input signal, the timing control circuit is configured to adjust the frequency of a data signal or a clock signal from a normal operating frequency to at least one anti-interference frequency. The timing control circuit is further configured to provide at least one of a data signal and a clock signal to the source driver.

[0009] Based on the above, and based on the timing controller and its anti-interference method described in the embodiments of the present invention, at least one of the timing controller and the source driver can determine whether an interference event has occurred in the input signal. When an interference event occurs, the operating frequency of the source driver and / or the timing controller can be dynamically adjusted.

[0010] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0011] Figure 1 This is a schematic diagram illustrating a scenario where a mobile phone is brought close to a display device.

[0012] Figure 2 This is an explanation Figure 1 The diagram shows a scenario where the signal received by the source drive circuit is subject to radio frequency noise interference.

[0013] Figure 3 This is a schematic diagram of a circuit block of a display device according to an embodiment of the present invention.

[0014] Figure 4 This is a flowchart illustrating an anti-interference method for a driving circuit according to an embodiment of the present invention.

[0015] Figure 5 This is a signal timing diagram illustrating an interference event according to an embodiment of the present invention.

[0016] Figure 6 This is a circuit block diagram illustrating a timing controller according to an embodiment of the present invention.

[0017] Figure 7 This is a circuit block diagram illustrating a timing controller according to another embodiment of the present invention.

[0018] Figure 8 This is a circuit block diagram illustrating a timing controller according to another embodiment of the present invention.

[0019] Figure 9 This is a flowchart illustrating an anti-interference method for a driving circuit according to another embodiment of the present invention.

[0020] Figure 10 This is a circuit block diagram of a source drive circuit according to an embodiment of the present invention.

[0021] Figure 11 This is a flowchart illustrating an anti-interference method for a driving circuit according to another embodiment of the present invention.

[0022] Figure 12 This is a circuit block diagram of a source drive circuit according to another embodiment of the present invention.

[0023] Figure 13 This is a flowchart illustrating an anti-interference method for a driving circuit according to a further embodiment of the present invention.

[0024] Figure 14 This is described according to an embodiment of the present invention. Figure 12 The signal timing diagram of the receiving circuit shown illustrates the bandwidth.

[0025] Figure 15 This is described according to an embodiment of the present invention. Figure 12The signal timing diagram of the receiving circuit shown illustrates the bandwidth.

[0026] Figure 16 This is a circuit block diagram illustrating a phase-locked loop (PLL) circuit in a receiving circuit according to an embodiment of the present invention.

[0027] Symbol Explanation

[0028] 110: Mobile Phone

[0029] 111: Radio Frequency Noise

[0030] 120: Display device

[0031] 121: Timing Controller

[0032] 122: Source drive circuit

[0033] 300: Display device

[0034] 310: Timing Controller

[0035] 311: Timing control circuit

[0036] 312: Interference Detection Circuit

[0037] 313: PLL circuit

[0038] 320: Drive circuit

[0039] 321, 322, 323, 324: Source drivers

[0040] 330: Display panel

[0041] 700: Source drive circuit

[0042] 710: Filter circuit

[0043] 720: Receiver circuit

[0044] 801: Source drive circuit

[0045] 802: Interference Detection Circuit

[0046] 900: Source drive circuit

[0047] 1700: PLL circuit

[0048] 1710: Phase Detector

[0049] 1720: Loop Filter

[0050] 1730: Voltage-controlled oscillator

[0051] B1, B2, B3, B4, BN: Frequency bands

[0052] BW: Bandwidth

[0053] C: Capacitor

[0054] CDR_CLK: Clock signal

[0055] CLK: System Clock

[0056] CT: Clock training data string

[0057] ECC: Number of Bit Errors

[0058] FB: Feedback Signal

[0059] Freq1, Freq2: Frequency values

[0060] R1, R2: Resistors

[0061] Rx: Data signal

[0062] S410, S420, S430, S440, S450, S620, S650, S820, S850, S1020, S1050: Steps

[0063] SCK: Clock signal

[0064] SD: Detection signal

[0065] Sdata: Data signal

[0066] VCM: Common-mode potential

[0067] Vth: High threshold

[0068] VTL: Low barrier to entry Detailed Implementation

[0069] The term "coupled (or connected)" as used throughout this specification (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or some means of connection. The terms "first," "second," etc., used throughout this specification (including the claims) are used to name elements or distinguish different embodiments or scopes, and are not intended to limit the upper or lower limit of the number of elements, nor to limit the order of elements. Furthermore, wherever possible, elements / components / steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Elements / components / steps using the same reference numerals or the same terms in different embodiments may be referred to mutually in the relevant descriptions.

[0070] Figure 3 This is a circuit block diagram illustrating a display device 300 according to an embodiment of the present invention. The display device 300 includes a driving circuit and a display panel 330. This embodiment does not limit the implementation of the display panel 330. Depending on design requirements, for example, the display panel 330 may be a known display panel or other display panels. The display device 300 may include one or more integrated circuits, such as... Figure 3 The timing controller 310 and the drive circuit 320 shown are at least one of them. In some embodiments, the timing controller 310 may be packaged within the drive circuit 320 based on design requirements. The drive circuit 320 may include one or more source drivers. Figure 3 Four source drivers 321, 322, 323, and 324 are illustrated; however, the number of source drivers is determined according to design requirements. Source drivers 321-324 are configured to be controlled by a timing controller 310. The timing controller 310 is configured to transmit data signals to source drivers 321-324 via transmission lines (e.g., wires on a printed circuit board). Source drivers 321-324 include their respective source drive circuits, which drive the display panel 330 to display images according to the data signals.

[0071] When interference events (e.g.) Figure 1 and Figure 2When the interference scenario shown does not occur, the operating frequencies of the timing controller 310 and the source drivers 321-324 can be maintained at their normal operating frequencies. The operating frequency of the source drive circuit in each source driver 321-324 can be indicated by an indication signal received by the source drive circuit from the timing control circuit of the timing controller 310. Specifically, the indication signal may include a clock signal or a data signal. The source drivers can use the clock signal or the data signal to generate a clock signal used to control the operating frequency of the source drive circuit in each source driver 321-324. More specifically, in some interfaces such as mini-LVDS interfaces, the timing controller 310 can be configured to send a clock signal to the source drivers 321-324, and then the source drivers 321-324 use this clock signal to control the operating frequency of the source drive circuit in the source drivers 321-324. In other words, the frequency of the clock signal can be the operating frequency of the source driver. In some other embodiments, such as a point-to-point (P2P) interface, the timing controller is configured to send a data signal, for example, in the format 11111110000000, which is then received and used by the source driver to generate a clock signal capable of controlling the operating frequency of the source drive circuitry in source drivers 321-324. In other words, the frequency of the data signal can be the operating frequency of the source driver.

[0072] The normal operating frequency can be determined according to design requirements. When interference events (e.g.) occur... Figure 1 and Figure 2 When the interference scenario shown occurs, radio frequency noise may interfere with the transmission of data signals between timing controller 310 and source drivers 321-324. At least one of timing controller 310 or source drivers 321-324 can be configured to detect whether an interference event has occurred. In some embodiments, when any of timing controller 310 or source drivers 321-324 detects an interference event, source drivers 321-324 can adjust their operating frequency from their normal operating frequency to at least one anti-interference frequency. Further, timing controller 310 can adjust the frequency of an indication signal (i.e., a data signal or a clock signal), and then source drivers 321-324 can adjust the operating frequency of their source drive circuits to at least one anti-interference frequency based on the received input signal. In summary, when the interference event disappears, the operating frequency of source drivers 321-324 can be adjusted from the at least one anti-interference frequency back to the normal operating frequency.

[0073] For example, in some embodiments, the timing controller 310 can detect whether an interference event has occurred. When the timing controller 310 detects an interference event, it can send an indication signal to the source drivers 321-324. This indication signal can indicate whether the timing controller 310 has detected an interference event. Alternatively, the indication signal can indicate one of at least one anti-interference frequency. The indication signal can be a data signal or a clock signal. The source drivers 321-324 can receive the indication signal from the timing controller 310 and adjust the operating frequency of the source drive circuitry based on the indication signal, which ranges from the normal operating frequency to one of the at least one anti-interference frequencies.

[0074] In other embodiments, source drivers 321-324 may receive input signals (e.g., data signals) from timing controller 310. Source drivers 321-324 may detect whether an interference event has occurred with this input signal. When a source driver (e.g., one of source drivers 321-324) detects an interference event, it may notify timing controller 310. Timing controller 310, notified of the interference event by the source driver, may send an indication signal to source drivers 321-324. The indication signal may indicate whether timing controller 310 has detected an interference event. Alternatively, the indication signal may indicate one of at least one anti-interference frequency. The indication signal may be a data signal or a clock signal. Source drivers 321-324 may receive the indication signal from timing controller 310 and adjust the operating frequency of the source drive circuitry based on the indication signal, ranging from the normal operating frequency to one of at least one anti-interference frequency.

[0075] In some embodiments, source drivers 321-324 can detect whether an interference event has occurred. When source drivers 321-324 detect an interference event, they generate a feedback signal to timing controller 310. This feedback signal is provided to timing controller 310, which can then provide an indication signal to the source drivers to adjust the operating frequency of source drivers 321-324. Depending on design requirements, the feedback signal can be a hardware pin signal or other types of signals. For example (but not limited to), when the feedback signal is a logic high signal, it can indicate that an interference event has occurred; and when the feedback signal is a logic low signal, it can indicate that no interference event has occurred. Alternatively, the feedback signal can be a differential signal. When the feedback signal is in a first logic state, it can indicate that an interference event has occurred; and when the feedback signal is in a second logic state, it can indicate that no interference event has occurred. Alternatively, the feedback signal can be a differential signal having a first terminal signal and a second terminal signal. When the first terminal signal and the second terminal signal are mutually inverted, that is, when the first terminal signal and the second terminal signal are out of phase, the feedback signal can indicate that "no interference event has occurred"; and when the first terminal signal and the second terminal signal are in phase, the feedback signal can indicate that "an interference event has occurred".

[0076] In other embodiments, source drivers 321-324 may receive input signals (e.g., data signals) from timing controller 310. Timing controller 310 may detect whether an interference event has occurred with this input signal. When timing controller 310 detects an interference event, it may provide an indication signal to the source drivers to adjust the operating frequency of source drivers 321-324.

[0077] Figure 4 This is a flowchart illustrating an anti-interference method for a driving circuit according to an embodiment of the present invention. Please refer to... Figure 3 and Figure 4After the timing controller 310 and source drivers 321-324 are powered on, they enter clock training mode (step S410). In clock training mode, the timing control circuit of the timing controller 310 transmits the clock training data string as a data signal to the source drivers 321-324. This embodiment does not limit the operational details in clock training mode. For example, the operational details of clock training mode can be known clock training operations or other operations. At this time, the clock data recovery (CDR) circuit (not shown) inside the source drivers 321-324 can perform frequency locking and / or phase locking operations on the clock training data string provided by the timing controller 310.

[0078] After the clock training mode ends, the CDR circuits of the source drivers 321-324 can correctly lock the clock training data string provided by the timing control circuit of the timing controller 310. Therefore, the timing controller 310 and the source drivers 321-324 enter the normal mode (step S420). In the normal mode, the operating frequency of the source drivers 321-324 is set to the normal operating frequency. The normal operating frequency can be determined according to design requirements.

[0079] The CDR circuit inside the source drivers 321-324 may lose lock on the data signal. When the CDR circuit loses lock on the data signal (step S430 determines "yes"), the normal mode ends and the system returns to the clock training mode (step S410). When the CDR circuit does not lose lock on the data signal (step S430 determines "no"), the timing controller 310 and the source drivers 321-324 remain in the normal mode, and at least one of the timing controller 310 and the source drivers 321-324 can detect whether an interference event has occurred (step S440). When no interference event has occurred (step S440 determines "no"), steps S420 and S430 are performed again. That is, the timing control circuit of the timing controller 310 transmits the data signal to the source drive circuit of the source drivers 321-324 at the normal operating frequency.

[0080] Figure 5 This is a signal timing diagram illustrating an interference event according to an embodiment of the present invention. Please refer to... Figure 3 and Figure 5The timing controller 310 transmits the data signal Sdata to the source drivers 321-324 at the normal operating frequency. During the active period, the timing controller 310 transmits RGB data (sub-pixel data, as the data signal Sdata) along with control commands to the source drivers 321-324. During the vertical blanking period, the timing controller 310 transmits the clock training data string CT as the data signal Sdata to the source drivers 321-324 for clock training.

[0081] When interference events (e.g.) Figure 1 and Figure 2 When the interference scenario shown occurs, radio frequency noise may interfere with the transmission of the data signal Sdata between the timing controller 310 and the source drivers 321-324, causing a change in the common-mode voltage VCM of the data signal Sdata, i.e., generating a ripple in the common-mode voltage. At least one of the timing controller 310 and the source drivers 321-324 can detect the common-mode voltage VCM of the data signal Sdata. In this embodiment, the high threshold Vth and the low threshold Vtl can be set according to design requirements. When the common-mode voltage VCM is greater than the high threshold Vth and / or less than the low threshold Vtl, the timing controller 310 (or the source drivers 321-324) can determine that "an interference event has occurred" (step S440 determines "yes"). Conversely, when the common-mode potential VCM is not greater than the high threshold Vth and not less than the low threshold Vtl, the timing controller 310 (or source driver 321-324) can determine that "no interference event has occurred" (step S440 determines "no").

[0082] For example, source drivers 321-324 can detect the common-mode potential VCM of the data signal Sdata (input signal) sent from timing controller 310 to source drivers 321-324. Based on this common-mode potential, source drivers 321-324 can determine whether an interference event has occurred and feed back a feedback signal related to the interference event to timing controller 310.

[0083] In any case, the determination method of step S440 should not be limited to the above-described embodiments. For example, in some other embodiments, source drivers 321-324 can process the data signal Sdata (input signal) sent from timing controller 310 to source drivers 321-324 according to at least one operating parameter to generate output data. Source drivers 321-324 can detect the number of bit errors in the output data. Source drivers 321-324 can determine whether an interference event has occurred based on the number of bit errors. For example, when the number of bit errors is greater than a certain threshold (determined according to design requirements), source drivers 321-324 can determine that an interference event has occurred. Source drivers 321-324 can feed back the feedback signal related to the interference event to timing controller 310.

[0084] Please refer to Figure 4 When an interference event occurs (step S440 determines "Yes"), the operating frequency of the source driver circuits 321-324 can be adjusted from the normal operating frequency to at least one anti-interference frequency (step S450). For example, if the noise frequency of the interference event is greater than the frequency of the data signal Sdata, the operating frequency of the source drivers 321-324 can be reduced to decrease the impact of noise on the data signal Sdata. If the noise frequency of the interference event is less than the frequency of the data signal Sdata, the operating frequency of the source drivers 321-324 can be increased to reduce the impact of noise on the data signal Sdata.

[0085] In an embodiment where source drivers 321-324 can provide feedback signals related to interference events to timing controller 310, when this feedback signal indicates that the interference event occurs during the first vertical blanking period, timing controller 310 can provide an indication signal (data signal or clock signal) to source drivers 321-324 in step S450 to adjust the operating frequency of source drivers 321-324 from the normal operating frequency to the first anti-interference frequency, thereby reducing the impact of noise on the data signal Sdata. After step S450 is completed, this process returns to step S440. When this feedback signal indicates that the interference event occurs during the second vertical blanking period after the first vertical blanking period (step S440 is again determined to be "yes"), timing controller 310 can provide an indication signal (data signal or clock signal) to source drivers 321-324 to adjust the operating frequency of source drivers 321-324 from the first anti-interference frequency to the second anti-interference frequency, thereby reducing the impact of noise on the data signal Sdata.

[0086] After step S450 is completed, the process returns to step S440. When the feedback signal indicates that no interference event has occurred during the second vertical blanking period after the first vertical blanking period (step S440 determines "no"), the timing controller 310 can provide an indication signal (data signal or clock signal) to the source drivers 321-324 to adjust the operating frequency of the source drivers 321-324 from the first anti-interference frequency to the normal operating frequency (step S420).

[0087] For example, in some other embodiments, the timing controller 310 can detect the common-mode potential VCM of the data signal Sdata (input signal) sent from the timing controller 310 to the source drivers 321-324 in step S440. Based on this common-mode potential, the timing controller 310 can determine whether an interference event has occurred. When the common-mode potential VCM is greater than the high threshold Vth or less than the low threshold Vtl, the timing control circuit determines that an interference event has occurred. When an interference event occurs in the data signal Sdata (input signal), if the noise frequency of the interference event is greater than the frequency of the data signal Sdata, the timing controller 310 can reduce the frequency of the data signal Sdata. When an interference event occurs in the data signal Sdata (input signal), if the noise frequency of the interference event is less than the frequency of the data signal Sdata, the timing controller 310 can increase the frequency of the data signal Sdata. The timing controller 310 can provide the data signal Sdata as an indication signal to the source drivers 321-324, and then the source drivers 321-324 can generate a clock signal with the frequency of the data signal Sdata based on the data signal Sdata. Therefore, the source drivers 321-324 can operate at a first anti-interference frequency adjusted from the normal operating frequency.

[0088] After step S450 is completed, the process returns to step S440. When the timing controller 310 determines that no interference event has occurred (step S440 determines "No"), the timing controller 310 can provide the data signal Sdata as an indication signal to the source drivers 321-324. Then, the source drivers 321-324 can generate a clock signal with the frequency of the data signal Sdata based on the data signal Sdata. Therefore, the source drivers 321-324 can operate at a normal operating frequency adjusted from the first anti-interference frequency (step S420).

[0089] Figure 6 This is a circuit block diagram illustrating a timing controller 310 according to an embodiment of the present invention. Figure 3 The timing controller 310 shown can be referenced. Figure 6 The following is a description of the timing controller 310 shown. Figure 6The timing controller 310 shown includes a timing control circuit 311 and an interference detection circuit 312. In some interfaces, such as point-to-point (P2P) interfaces, the timing control circuit 311 can be coupled to source drivers 321-324 to provide a data signal Sdata. In other interfaces, such as mini-LVDS, the timing control circuit 311 can also provide a clock signal SCK. The interference detection circuit 312 is configured to detect whether an interference event has occurred and generate a detection signal SD indicating whether an interference event has occurred. The timing control circuit 311 may include (or be coupled to) a phase-locked loop (PLL) circuit. The PLL circuit can be coupled to the interference detection circuit 312 to receive the detection signal SD. The PLL circuit can adjust the frequency of the data signal (or clock signal) according to the detection signal SD. The timing control circuit 311 can also be configured to control a transmit (TX) circuit. The TX circuit can be configured to provide a data signal (or clock signal) to the source drivers 321-324, wherein the data signal (or clock signal) can serve as an indication signal for adjusting the operating frequency of the source drivers 321-324.

[0090] Furthermore, the interference detection circuit 312 is configured to detect input signals (e.g., data signals Sdata) sent from the timing control circuit 311 to the source drive circuits of the source drivers 321-324. The interference detection circuit 312 can be configured to determine whether an interference event has occurred based on the input signal (e.g., data signals Sdata). In one embodiment, the interference detection circuit 312 is configured to detect the common-mode potential of the input signal (e.g., data signals Sdata) and determine whether an interference event has occurred based on the common-mode potential.

[0091] It should be noted that although the interference detection circuit 312 is shown as coupled to the PLL circuit to provide a detection signal SD to the PLL circuit, this disclosure is not limited thereto. For example, the interference detection circuit 312 may be configured to provide the detection signal SD to the timing control circuit 311, and then the timing control circuit 311 controls the PLL circuit to generate a data signal Sdata or a clock signal SCK based on the detection result indicated by the detection signal SD. Furthermore, in the same or alternative embodiments, the timing control circuit 311, the PLL circuit, and the interference detection circuit 312 may be (partially or entirely) separated or integrated.

[0092] Figure 7 This is a circuit block diagram illustrating the timing controller 310 and the source driver according to another embodiment of the present invention. Figure 3 The timing controller 310 shown can be referenced. Figure 7 The following is a description of the timing controller 310 shown. Figure 7 The timing controller 310 shown includes a timing control circuit 311, which may include (or be coupled to) a PLL circuit 313. For example, the output of the timing control circuit 311 is coupled to the PLL circuit 313. The input of the timing control circuit 311 may be coupled to source drivers 321-324 to receive feedback signal FB. Figure 7 In the illustrated embodiment, each of source drivers 321-324 includes a source drive circuit 801 and an interference detection circuit 802. The source drive circuit 801 is configured to receive an input signal (e.g., a data signal Sdata) from the timing controller 310. The interference detection circuit 802 is configured to detect whether an interference event has occurred with the input signal and generate a detection signal indicating whether an interference event has occurred. The source driver can then provide the detection signal as a feedback signal FB to the timing controller 310.

[0093] The timing control circuit 311 can be coupled to the interference detection circuit 802 to receive a feedback signal FB when an interference event occurs. The timing control circuit 311 adjusts the operating frequency of the data signal or clock signal based on the feedback signal FB. For example, when the feedback signal FB indicates "no noise detected," the timing control circuit 311 provides a frequency value "M1" to the PLL circuit 313. When the feedback signal FB indicates "noise detected," the timing control circuit 311 provides one of the frequency values ​​"M2," "M3," "M4," and / or other values ​​to the PLL circuit 313.

[0094] PLL circuit 313 is configured to receive frequency values ​​and generate a data signal Sdata or a clock signal SCK based on the frequency values. The data signal Sdata or clock signal SCK can then be provided to the source drive circuits of source drivers 321-324. Assuming the system clock CLK frequency is F, and the frequency value provided by timing control circuit 311 is M1, the frequency of the clock signal SCK output by PLL circuit 313 (normal operating frequency) is F*M1 / N, where N is the frequency division value of PLL circuit 313. Assuming the frequency value provided by timing control circuit 311 is M2, the frequency of the clock signal SCK output by PLL circuit 313 (anti-interference frequency) is F*M2 / N. It should be noted that in different embodiments, part or all of timing control circuit 311 can be integrated with interference detection circuit 802. For example, the source driver can provide feedback signals indicating frequency values ​​such as M1 and M2 to timing controller 310, so that timing controller 310 does not need to determine the frequency value.

[0095] Figure 8 This is a circuit block diagram illustrating a timing controller 310 according to an embodiment of the present invention. Figure 3The timing controller 310 shown can be referenced. Figure 8 The following is a description of the timing controller 310. Each of the source drivers 321 to 324 can detect the error rate (ECC) of the output data of the source drive circuit. The source drivers 321 to 324 provide the error rate (ECC) to the timing controller 310. Figure 8 The timing controller 310 shown includes a timing control circuit 311 and a PLL circuit 313. The PLL circuit 313 can be separate from or integrated with the timing control circuit 311. For example, the output of the timing control circuit 311 can be coupled to the PLL circuit 313, as shown. The timing controller 310 may also include an interference detection circuit 312, which can be separate from or integrated with the timing control circuit 311. The input of the interference detection circuit 312 can be coupled to source drivers 321-324 to receive the number of bit errors (ECC). The interference detection circuit 312 can determine whether an interference event has occurred based on the number of bit errors (ECC). For example, when the number of bit errors (ECC) is greater than a certain threshold (which can be determined based on design requirements), the interference detection circuit 312 can determine that an interference event has occurred and generate a detection signal SD to provide to the timing control circuit 311. For example, when the interference detection circuit 312 determines "no noise detected" based on the number of bit errors (ECC), the interference detection circuit 313 provides a detection signal SD indicating the detection result to the timing control circuit 311, and then the timing control circuit 311 provides a frequency value "M1" to the PLL circuit 313. Conversely, when the interference detection circuit 313 determines "noise detected" based on the number of bit errors (ECC), the interference detection circuit 313 provides a detection signal SD indicating the detection result to the timing control circuit 311. Then, the timing control circuit 311 provides one of the frequency values ​​"M2", "M3", "M4", and / or other values ​​to the PLL circuit 313.

[0096] Figure 9 This is a flowchart illustrating an anti-interference method for a driving circuit according to another embodiment of the present invention. Figure 9 Steps S410, S430, and S440 shown can be referred to Figure 4 The relevant explanations can be deduced by analogy, so they will not be repeated here. Please refer to... Figure 3 and Figure 9 After the clock training mode ends, the CDR circuits (not shown) of the source drivers 321-324 can correctly lock the clock training data string CT provided by the timing controller 310, so the timing controller 310 and the source drivers 321-324 enter the normal mode (step S620).

[0097] Furthermore (or), when at least one of the timing control circuit and the source drive circuit detects an interference event, any of the source drivers 321-324 can adjust the receiving bandwidth of the source drive circuit. In other words, in some embodiments, when an interference event occurs, any source driver can adjust the operating frequency of its source drive circuit without adjusting the receiving bandwidth of the source drive circuit. In some other embodiments, when an interference event occurs, any source driver can adjust the receiving bandwidth of its source drive circuit without adjusting the operating frequency of the source drive circuit. In still other embodiments, when an interference event occurs, any source driver can adjust both the receiving bandwidth and the operating frequency of the source drive circuit.

[0098] Various implementations are possible to achieve the adjustment of the received bandwidth. In some embodiments, each source driver may also include a filter circuit (not shown). In normal mode (step S620), the operating frequency of source drivers 321-324 is set to the normal operating frequency, and source drivers 321-324 do not use the filter circuit (not shown) to filter the data signal Sdata. The normal operating frequency can be determined according to design requirements. Figure 9 Step S620 shown can be referred to Figure 4 The relevant description of step S420 shown is analogous, so other details will not be repeated. In another embodiment, source drivers 321-324 can use a filter circuit (not shown) to filter the data signal Sdata in normal mode (step S620), but the operating parameters of the filter circuit are set to "all pass".

[0099] When an interference event occurs (step S440 determines "yes"), the operating frequency of the source drivers 321-324 (and / or the operating frequency of the timing controller 310) can be adjusted from the normal operating frequency to at least one anti-interference frequency (step S650). Figure 9 Step S650 shown can be referred to Figure 4 The description of step S450 is analogous to this, so further details will not be repeated. In addition, source drivers 321-324 can also use a filter circuit (not shown) to filter the data signal Sdata in step S650. In other words, one of source drivers 321-324 can enable filtering to avoid the frequency band of interference events. Besides enabling filtering, one of source drivers 321-324 can also adjust the bandwidth of the filter circuit to avoid the frequency band of interference events. It should be noted that in alternative embodiments, the operating frequency in steps S620 and S650 can both be set to the normal operating frequency. The difference between steps S620 and S650 is whether the filter circuit is enabled.

[0100] Figure 10 This is a circuit block diagram of a source drive circuit 700 according to an embodiment of the present invention. Figure 3 Any of the source drive circuits of the source drivers 321-324 shown can be referenced. Figure 10 The description of the source drive circuit 700 shown can be extrapolated. The source drive circuit 700 includes an input configured to be coupled to the timing control circuit 311. The receiving circuit 720 includes a PLL circuit (not shown) coupled to the input of the source drive circuit 700. For example, Figure 10 The source drive circuit 700 shown includes a filter circuit 710 and a receiver circuit 720. The input of the filter circuit 710 can be coupled to the timing control circuit 311 of the timing controller 310 to receive an input signal (e.g., a data signal Sdata) from the timing control circuit 311. The input of the receiver circuit 720 is coupled to the output of the filter circuit 710.

[0101] When no interference event occurs, the output of filter circuit 710 provides the data signal Sdata (input signal) to the input of receiving circuit 720. Based on at least one of whether an interference event occurs and the noise frequency of the interference event, the operation of filter circuit 710 can be adjusted, for example, to have different bandwidths. In some embodiments, when an interference event occurs on the data signal Sdata (input signal), filter circuit 710 performs a corresponding filtering operation to filter out the noise of the interference event and generate a filtered signal. Filter circuit 710 is configured not to perform filtering on the input signal received by the source drive circuit when no interference event occurs. The bandwidth of filter circuit 710 is also configured to be adjusted based on the noise frequency of the interference event when it occurs. The output of filter circuit 710 provides the filtered signal to the input of receiving circuit 720.

[0102] Depending on the design requirements, the filter circuit 710 may include multiple filters configured to filter the input signal received (or coupled) from the timing control circuit 311. Figure 10The detailed structure of the filter circuit 710 is also illustrated with reference to an exemplary embodiment. In the exemplary embodiment, the filter circuit 710 includes one or more filters configured to perform different filtering operations, which, as shown in the figure, may include low-pass filtering, high-pass filtering, and / or band-pass filtering. Different corresponding filtering operations can be performed when different interference detection conditions occur. Further, when an interference event occurs in the data signal Sdata (input signal), if the noise frequency of the interference event is greater than the frequency of the data signal Sdata, the filter circuit 710 can use a low-pass filter (or any corresponding filter) to perform a low-pass filtering operation (or any corresponding filtering operation) on the data signal Sdata, and then provide the filtered signal to the input of the receiving circuit 720. When an interference event occurs in the data signal Sdata (input signal), if the noise frequency of the interference event is less than the frequency of the data signal Sdata, the filter circuit 710 can use a high-pass filter (or any corresponding filter) to perform a high-pass filtering operation (or any corresponding filtering operation) on the data signal Sdata, and then provide the filtered signal to the input of the receiving circuit 720. In certain applications, when an interference event occurs on the data signal Sdata (input signal), the filter circuit 710 can use a bandpass filter (or any corresponding filter) to perform a bandpass filtering operation on the data signal Sdata (or any corresponding filtering operation), and then provide the filtered signal to the input terminal of the receiving circuit 720.

[0103] In the above embodiments (but this disclosure is not limited thereto), the receiving bandwidth of the source drive circuit 700 is adjusted before the receiving circuit. In other embodiments, the receiving bandwidth of the source drive circuit 700 can be adjusted within the receiving circuit. In an example of adjusting the receiving bandwidth of the source drive circuit 700 within the receiving circuit, the receiving circuit 720 can process the signal (data signal Sdata or filtered signal) at the output of the filter circuit 710 based on at least one operating parameter to generate output data. For example, the at least one operating parameter may include bandwidth. In some embodiments, the bandwidth is independent of whether an interference event occurs. In other embodiments, the bandwidth can be dynamically adjusted based on whether an interference event occurs. For example, when no interference event occurs, the bandwidth of the receiving circuit 720 is set to a first bandwidth. When an interference event occurs at the data signal Sdata (input signal), the bandwidth of the receiving circuit 720 is reduced from the first bandwidth to a corresponding bandwidth. More details regarding adjusting the bandwidth of the receiving circuit can be found in [reference needed]. Figures 14 to 16 .

[0104] In summary, the receiving bandwidth of the source driver's source drive circuit can be adjusted by adjusting the bandwidth of the filter set before the receiving circuit of the source drive circuit and / or the bandwidth of the receiving circuit.

[0105] Figure 11 This is a flowchart illustrating an anti-interference method for a driving circuit according to another embodiment of the present invention. Figure 11 Steps S410, S430, and S440 shown can be referred to Figure 4 The relevant explanations can be deduced by analogy, so they will not be repeated here. Please refer to... Figure 10 and Figure 11 In normal mode (step S820), the operating frequency of the source drive circuit 700 is set to the normal operating frequency, and the output of the filter circuit 710 provides the data signal Sdata (input signal) to the input of the receiving circuit 720 (without using a filter). The normal operating frequency can be determined according to design requirements. Figure 11 Step S820 can be referred to Figure 4 The relevant descriptions of step S420 shown are analogous, so other details will not be repeated. In addition, when no interference event occurs, the bandwidth of the receiving circuit 720 is set to the first bandwidth.

[0106] When an interference event occurs (step S440 determines "yes"), the operating frequency of the source drive circuit 700 (and / or the operating frequency of the timing controller 310) can be adjusted from the normal operating frequency to at least one anti-interference frequency (step S850). Figure 11 Step S850 shown can be referred to Figure 4 The relevant descriptions of step S450 are analogous, so other details will not be repeated. In step S850, the source drive circuit 700 can also use the filter circuit 710 to filter the data signal Sdata to obtain a filtered signal. In addition, when an interference event occurs in the data signal Sdata, in step S850, the bandwidth of the receiving circuit 720 is reduced from the first bandwidth to a corresponding bandwidth to avoid the frequency band of the interference event.

[0107] Figure 12 This is a circuit block diagram of a source drive circuit 900 according to another embodiment of the present invention. Figure 3 Any of the source drivers 321 to 324 shown can be referenced. Figure 12 The description of the source drive circuit 900 shown can be used as a reference. The source drive circuit (source drive circuit 900) includes an input terminal that is configured to be coupled to the timing control circuit 311. Figure 12The source drive circuit 900 shown includes a receiving circuit 720. The receiving circuit 720 includes a PLL circuit (not shown) coupled to the input of the source drive circuit 900. For example, by adjusting the configuration of the PLL circuit, the receiving bandwidth of the source drive circuit (source drive circuit 900) can be adjusted within the receiving circuit 720. The input of the receiving circuit 720 can receive an input signal (e.g., a data signal Sdata) from the timing controller 310. The receiving circuit 720 can process the data signal Sdata based on its bandwidth to generate output data. When no interference event occurs, the bandwidth of the receiving circuit 720 is set to a first bandwidth. When an interference event occurs with the data signal Sdata (input signal), the bandwidth of the receiving circuit 720 is reduced from the first bandwidth to a corresponding bandwidth.

[0108] Figure 13 This is a flowchart illustrating an anti-interference method for a driving circuit according to another embodiment of the present invention. Figure 13 Steps S410, S430, and S440 shown can be referred to Figure 4 The relevant explanations can be deduced by analogy, so they will not be repeated here. Please refer to... Figure 12 and Figure 13 In the normal mode (step S1020), the operating frequency of the source drive circuit 900 is set to the normal operating frequency. The normal operating frequency can be determined according to design requirements. Figure 13 Step S1020 shown can be referred to Figure 4 The relevant descriptions of step S420 shown are analogous, so other details will not be repeated. In addition, when no interference event occurs, the bandwidth of the receiving circuit 720 is set to the first bandwidth.

[0109] When an interference event occurs (step S440 determines "yes"), the operating frequency of the source drive circuit 900 (and / or the operating frequency of the timing controller 310) can be adjusted from the normal operating frequency to at least one anti-interference frequency (step S1050). Figure 13 Step S1050 shown can be referred to Figure 4 The relevant explanations for step S450 shown are analogous, so other details will not be repeated. In addition, when an interference event occurs in the data signal Sdata, in step S1050, the bandwidth of the receiving circuit 720 is reduced from the first bandwidth to a corresponding bandwidth to avoid the frequency band of the interference event.

[0110] Figure 14 This is described according to an embodiment of the present invention. Figure 12 The signal timing diagram for the bandwidth BW of the receiving circuit 720 shown is illustrated. Please refer to... Figure 12 and Figure 14The receiving circuit 720 also adjusts the bandwidth BW to avoid the frequency band BN of interference events. For example, when no interference event occurs, the receiving circuit 720 adjusts the bandwidth BW to "B1". When an interference event occurs, the receiving circuit 720 adjusts the bandwidth BW to one of "B2", "B3", "B4" and / or other bandwidths.

[0111] Figure 15 This is described according to an embodiment of the present invention. Figure 12 The signal timing diagram for the bandwidth BW of the receiving circuit 720 shown is illustrated. Please refer to... Figure 12 and Figure 15 The receiving circuit 720 adjusts its operating frequency and bandwidth BW to avoid the frequency band BN of interference events. For example, when no interference event occurs, the receiving circuit 720 adjusts the bandwidth BW to "B1" and sets the operating frequency of the receiving circuit 720 to the frequency value "Freq1". When an interference event occurs, the receiving circuit 720 adjusts the bandwidth BW to "B2" and sets the operating frequency of the receiving circuit 720 to the frequency value "Freq2".

[0112] Figure 16 This is a circuit block diagram illustrating a phase-locked loop (PLL) circuit 1700 in a receiving circuit 720 according to an embodiment of the present invention. The PLL circuit 1700 includes a phase detector 1710, a loop filter 1720, and a voltage-controlled oscillator (VCO) 1730. The PLL circuit 1700 generates an output clock signal for the source drive circuit 900. The receiving bandwidth of the source drive circuit 900 can be adjusted by modifying the configuration of the loop filter 1720. Figure 16 In this embodiment, the loop filter 1720 includes resistors R1 and R2 and capacitor C. The bandwidth of the receiving circuit 720 is 1 / 4C(R1+R2). The bandwidth of the receiving circuit 720 is changed by changing the resistance value of resistor R2.

[0113] In summary, at least one of the timing controller and the source driver can be configured to determine whether an interference event has occurred with the input signal. When an interference event occurs, at least one of the operating parameters of the source driver circuit (e.g., operating frequency and / or receiving bandwidth) can be dynamically adjusted to avoid the frequency band of the interference event. Different combinations of the above adjustment operations can be performed to mitigate the impact of the interference event. More specifically, one or more of the following adjustment operations can be performed: adjusting the operating frequency of the source driver circuit and adjusting the receiving bandwidth of the source driver circuit. The adjustment of the receiving bandwidth of the source driver circuit can be performed by at least one of the following operations: adjusting the bandwidth of the receiving circuit of the source driver circuit, enabling the filtering circuit of the source driver circuit, and adjusting the bandwidth of the filtering circuit of the source driver circuit. The filter circuit can be configured before the receiving circuit of the source driver circuit.

[0114] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A timing controller capable of detecting interference, characterized in that, The timing controller includes: Timing control circuitry is configured to provide input signals to control the source driver; and When at least one of the timing control circuit and the source driver detects an interference event occurring in the input signal provided by the timing control circuit to the source driver, the timing control circuit is configured to adjust the operating frequency of the data signal from the normal operating frequency to at least one anti-interference frequency. The timing control circuit is further configured to provide the source driver with the data signal having the at least one anti-interference frequency, and the at least one anti-interference frequency is used to reduce interference from external radio frequency devices to the input signal. When the interference event occurs in the input signal provided by the timing control circuit to the source driver, if the noise frequency of the interference event is less than the operating frequency of the data signal, the timing control circuit is configured to increase the operating frequency of the data signal. When the interference event occurs in the input signal provided by the timing control circuit to the source driver, and the noise frequency of the interference event is greater than the operating frequency of the data signal, the timing control circuit is configured to reduce the operating frequency of the data signal.

2. The timing controller according to claim 1, characterized in that, The timing controller further includes: An interference detection circuit is configured to detect whether the interference event has occurred and generate an indication signal indicating whether the interference event has occurred.

3. The timing controller according to claim 2, characterized in that, The indication signal includes the data signal indicating or having a frequency, and the operating frequency is adjusted according to the frequency.

4. The timing controller according to claim 2, characterized in that, The timing control circuit is configured to receive the indication signal from the interference detection circuit and adjust the operating frequency of the data signal according to the indication signal.

5. The timing controller according to claim 2, characterized in that, The timing controller further includes: The phase-locked loop circuit is configured to receive the indication signal from the interference detection circuit and generate the data signal based on the indication signal.

6. The timing controller according to claim 1, characterized in that, When the source driver detects the occurrence of the interference event, the timing control circuit is configured to receive a feedback signal from the source driver and adjust the operating frequency of the data signal according to the feedback signal.

7. The timing controller according to claim 6, characterized in that, The timing controller further includes: A phase-locked loop circuit is configured to receive the feedback signal from the source driver and generate the data signal based on the feedback signal.

8. The timing controller according to claim 1, characterized in that, When the interference event occurs during the first vertical blanking period, the timing control circuit adjusts the operating frequency of the data signal from the normal operating frequency to the first anti-interference frequency.

9. The timing controller according to claim 8, characterized in that, When the interference event occurs during the second vertical blanking period after the first vertical blanking period, the timing control circuit is configured to adjust the operating frequency of the data signal from the first anti-interference frequency to the second anti-interference frequency.

10. The timing controller according to claim 8, characterized in that, When no interference event occurs during the second vertical blanking period following the first vertical blanking period, the timing control circuit is configured to adjust the operating frequency of the data signal from the first anti-interference frequency to the normal operating frequency.

11. The timing controller according to claim 2, characterized in that, The interference detection circuit is configured to detect the common-mode potential of the input signal and determine whether the interference event has occurred based on the common-mode potential of the input signal.

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