Video encoding method, decoding method and corresponding electronic device

Abstract

Methods for multiple transform selection (MTS) are provided. A video decoder receives data from a bitstream to decode a pixel block into a current block in a current picture of a video. The decoder sets a zeroing indication based on one or more non-zero coefficient indications of sub-blocks of the current block. When the zeroing indication indicates that there are no non-zero coefficients in a zeroing region, the decoder parses the bitstream for an MTS index. When the zeroing indication indicates that there is at least one non-zero coefficient in the zeroing region, the decoder does not parse the MTS index from the bitstream and sets the MTS index to a preset value. The decoder selects a transform mode for the current block according to the MTS index. The decoder reconstructs the current block by using the selected transform mode.

Description

[0001] Cross-reference

[0002] This disclosure is part of a non - provisional application that claims priority to U.S. Provisional Patent Application No. 62 / 940,955, filed on November 27, 2019. The content of the above - mentioned application is incorporated herein by reference. [[ID=\\5]] [[ID=\\6]]Technical Field[[ID=\\7]] [[ID=\\8]]

[0003] [[ID=\\9]]This disclosure generally relates to video coding and decoding. In particular, this disclosure relates to methods for selecting multiple transform operations to encode or decode a pixel block. [[ID=\\10]] [[ID=\\11]]Background Art[[ID=\\12]] [[ID=\\13]]

[0004] [[ID=\\14]]Unless otherwise indicated herein, the methods described in this section are not prior art with respect to the claims listed below and are not to be considered admitted to be prior art by virtue of their inclusion in this section. [[ID=\\15]] [[ID=\\16]]

[0005] [[ID=\\17]]High Efficiency Video Coding (HEVC) is an international video coding and decoding standard developed by the Joint Collaborative Team on Video Coding (JCT - VC). HEVC is a codec architecture based on a hybrid block - based motion - compensated DCT - like transform. The basic unit of compensation (referred to as a coding unit, CU) is a 2Nx2N square block, and each CU can be recursively divided into four smaller CUs until a predetermined minimum size is reached. Each CU includes one or more prediction units (PUs). [[ID=\\18]] [[ID=\\19]]

[0006] [[ID=\\20]]To achieve the best coding and decoding efficiency of the hybrid coding and decoding architecture in HEVC, intra - prediction and inter - prediction can be used for each PU. For the intra - prediction mode, spatially adjacent reconstructed pixels can be used to generate directional predictions. There are up to 35 directions in HEVC. For the inter - prediction mode, temporally reconstructed reference frames can be used to generate motion - compensated predictions. There are three different types of inter - prediction modes, including Skip, Merge, and Advanced Motion Vector Prediction (AMVP) mode. [[ID=\\21]] [[ID=\\22]]

[0007] After prediction, the residual for CU prediction is partitioned into transform units (TUs) and coded / decoded using transforms and quantization. HEVC uses Discrete Cosine Transform type II (DCT-II) as its core (primary) transform because of its strong energy compaction property. For intra modes, Discrete Sine Transform (DST) is also introduced and is used in some cases to replace DCT. For inter-prediction residuals, DCT-II is the only transform currently used in HEVC. Discrete Sine Transform type VII (DST-VII) and Discrete Cosine Transform type VIII (DCT-VIII) are also used in some cases. SUMMARY OF THE INVENTION

[0008] The following summary is illustrative only and is not intended to be limiting in any way. That is, the following summary is provided to introduce concepts, highlights, benefits, and advantages of the novel and non-obvious techniques described herein. Selective rather than all embodiments are further described in the detailed description below. Accordingly, the following summary is not used to determine the essential features of the claimed subject matter nor to determine the scope of the claimed subject matter.

[0009] Some embodiments provide a method for multiple transform selection (MTS). A video decoder receives data from a bitstream to decode a pixel block as a current block in a current picture of a video. The decoder sets a zeroing indication based on one or more non-zero coefficient indications of sub-blocks of the current block. When the zeroing indication indicates that there are no non-zero coefficients in a zeroing region, the decoder parses the bitstream for an MTS index. Alternatively, when the zeroing indication indicates that there is at least one non-zero coefficient in the zeroing region, the decoder does not parse the MTS index from the bitstream and sets the MTS index to a preset value. The decoder selects a transform mode from a plurality of transform kernels based on the MTS index for the current block. The decoder reconstructs the current block by using the selected transform mode.

[0010] The transform mode indicates the horizontal and vertical transforms of the associated luminance transform block in the current block. When the current block references a coded block that includes one or more transform blocks, the zero-out region of the current block is the region of the current block defined as follows. In one example, the zero-out region is the region outside the 16x16 range from the upper left corner of the current block. In another example, the zero-out region is defined by one or more sub-block positions that exceed a vertical threshold position or a horizontal threshold position. The horizontal threshold position and the vertical threshold position are the positions (xS, yS) of the coding group in the current transform block (or the sub-block at position (xS, yS) in the current transform block). For example, the sub-block includes 16 transform coefficients. In other words, the sub-block includes 4x4 transform coefficients.

[0011] In some embodiments, one or more non-zero coefficient indications of the sub-blocks are used to indicate whether the sub-blocks of the current block located in the zero-out region of the current block have one or more non-zero coefficients. The zero-out region of the current block is the region of the current block defined by sub-block positions that exceed a vertical threshold position or a horizontal threshold position. The zero indication is defined based on one or more non-zero coefficient indications of the sub-blocks to indicate whether the sub-blocks of the current block located in the zero-out region of the current block have one or more non-zero coefficients.

[0012] In some embodiments, the default value for the transform mode for MTS is Discrete Cosine Transform Type II (DCT-II) for both horizontal and vertical transforms. In some embodiments, when MTS is enabled, the low-frequency non-separable transform (LFNST) is disabled for the current block. In some embodiments, when LFNST is enabled, MTS is disabled. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The following drawings are used to provide a further understanding of the present invention and are incorporated into and constitute a part of the present invention. These drawings illustrate embodiments of the present invention and, together with the specification, are used to explain the principles of the present invention. To clearly illustrate the concepts of the present invention, some elements may not be shown to scale compared to their actual implementation sizes, and these drawings do not need to be drawn to scale.

[0014] Figure 1 Illustrates the procedure of the low-frequency non-separable transform (LFNST).

[0015] Figure 2 Illustrates a 32x32 transform block with zero and non-zero coefficients.

[0016] Figure 3Illustrates using non-zero coefficient indications of sub-blocks to determine whether to profile a Multiple Transform Selection (MTS) index.

[0017] Figure 4 Illustrates an example video encoder.

[0018] Figure 5 Illustrates some parts of an encoder that implements MTS by selectively enabling transform operations.

[0019] Figure 6 Conceptually illustrates a procedure to encode a pixel block using multiple transform selections.

[0020] Figure 7 Illustrates an example video decoder.

[0021] Figure 8 Illustrates some parts of a decoder that implements MTS by selectively enabling transform operations.

[0022] Figure 9 Conceptually illustrates a procedure to decode a pixel block using multiple transform selections.

[0023] Figure 10 Conceptually illustrates an electronic system in which some embodiments of the present disclosure may be implemented. Detailed Description

[0024] In the following detailed description, for the purpose of thorough understanding of the relevant teachings, numerous specific details are set forth by way of example. Any changes, derivations, and / or extensions based on the teachings described herein are within the scope of the present invention. To avoid unnecessarily obscuring aspects of the teachings of the present invention, methods, procedures, elements, and / or circuits known in one or more of the exemplary embodiments disclosed herein are sometimes described at a relatively high level without detailed elaboration.

[0025] Multiple Transform Selection (MTS)

[0026] To improve pixel data compression via transformation, in some embodiments of the present disclosure, a Multiple Transform Selection (MTS) architecture is used for residual encoding and decoding of intra- and / or inter-coded blocks. The MTS architecture uses multiple transforms selected from the DCT / DST family, including the newly introduced DCT-8 transform. In particular, in some embodiments, in addition to DCT-II, the MTS architecture is used for residual encoding and decoding of intra- and / or inter-coded blocks, such as by using DCT-8 and / or DST-7. Table I below shows the basic functions of the selected DST / DCT.

[0027] Table 1: Basic functions of DCT-II / VIII and DST VII for N-point input

[0028]

[0029] To maintain the orthogonality of the transform matrix, the transform matrix is quantized more accurately than the transform matrix in HEVC. In some embodiments, to keep the intermediate values of the transformed coefficients within the 16-bit range (after horizontal and vertical transforms), all coefficients have 10 bits.

[0030] To control the MTS architecture, separate enabling flags are specified at the SPS level for intra and inter frames respectively. In some embodiments, when MTS is enabled at the SPS, CU-level flags are signaled to indicate whether MTS is applied. Here, MTS is only applied to luma. This MTS CU-level flag (mts_idx) can be signaled when both the width and height are less than or equal to 32 and / or the CBF flag for the current block (CU level) is equal to one. When the MTS CU flag is equal to 0, DCT-2 is applied in both directions (horizontal transform and vertical transform). However, if the MTS CU flag is equal to 1, two other flags are additionally signaled to indicate the transform types in the horizontal and vertical directions respectively. The transform and signaling mapping table based on the MTS CU flag is shown in Table 2.

[0031] Table 2: Mapping for transforms in the MTS architecture

[0032]

[0033] In this table, different combinations of MTS_CU_flag, MTS_Hor_flag, and MTS_Ver_flag are mapped to different values of an MTS index, which can be used to select a combination of horizontal and vertical transforms. For example, an MTS index equal to 0 indicates that DCT2 is used in both directions. As another example, an MTS index equal to 1 indicates that DCT7 is used in both directions. As another example, an MTS index equal to 2 indicates that DCT8 is used for the horizontal transform and DCT7 is used for the vertical transform. As another example, an MTS index equal to 3 indicates that DCT7 is used for the horizontal transform and DCT8 is used for the vertical transform. As another example, an MTS index equal to 4 indicates that DCT8 is used in both directions.

[0034] In some embodiments, to convert matrix precision, an 8-bit primary transform core is used, and all HEVC transform cores are used, including 4-point DCT-2 and DST-7, 8-point, 16-point, and 32-point DCT-2. In addition, other transform cores, such as 64-point DCT-2, 4-point DCT-8, 8-point / 16-point / 32-point DST-7, and DCT-8 use the 8-bit primary transform core. In some embodiments, to reduce the complexity of large-size DST-7 and DCT-8, in DST-7 and DCT-8 blocks with a size (width or height, or both width and height) equal to 32, high-frequency transform coefficients are set to zero. Only the coefficients in the 16x16 low-frequency region are used.

[0035] A. Low-Frequency Non-Separable Transform (LFNST)

[0036] In some embodiments, the well-known low-frequency non-separable transform (LFNST) as a simplified secondary transform is applied between the forward primary transform and quantization (at the encoder) and between de-quantization and the inverse primary transform (at the decoder). Figure 1 Illustrates the procedure of the low-frequency non-separable transform (LFNST). In LFNST, a 4x4 non-separable transform or an 8x8 non-separable transform is applied according to the block size. For example, a 4x4 LFNST is applied to small blocks (i.e., min(width, height) < 8) and an 8x8 LFNST is applied to larger blocks (i.e., min(width, height) > 4). Using the input as an example, the application of the non-separable transform (which is used in LFNST) can be described as follows. Apply a 4x4 LFNST to the 4x4 input block X.

[0037]

[0038] First, it is represented as a vector as:

[0039]

[0040] This non-separable transform is calculated as where indicates the transform coefficient vector, and T is a 16x16 transform matrix. Using the scan order (horizontal, vertical, or diagonal) for the block, the 16x1 coefficient vector is then reorganized into a 4x4 block. Coefficients with smaller indices are placed at positions with smaller scan indices in the 4x4 coefficient block.

[0041] The LFNST applies non-separable transforms in a direct matrix multiplication manner such that it is performed on a single pass without multiple iterations. The non-separable transform matrix dimension is reduced to reduce the computational complexity and memory space to store the transform coefficients. Thus, the reduced non-separable transform (or RST) method is used in the LFNST. In some embodiments, the reduced non-separable transform maps an N-dimensional vector (for an 8x8 NSST, N is typically equal to 64) to an R-dimensional vector in a different space, where N / R (R < N) is the reduction factor. Thus, the RST matrix becomes an R×N matrix (instead of an NxN matrix) as follows:

[0042]

[0043] Wherein, the R columns of the transform are the R bases of the N-dimensional space. The inverse transform matrix for the RT is the transpose of its forward transform. For the 8x8 LFNST, a reduction factor of 4 is applied, and a 64x64 direct matrix (which is the size of the conventional 8x8 non-separable transform matrix) is reduced to a 16x48 direct matrix. Thus, a 48×16 inverse RST matrix is used on the decoder side to generate the core (primary) transform coefficients in the 8×8 upper left region. When a 16x48 matrix with the same transform group configuration is applied (instead of 16x64), it takes 48 input data from each of the three 4x4 blocks of the upper left 8×8 block (excluding the lower right 4x4 block). With the assistance of the reduced dimension, the memory usage for storing all LFNST matrices is reduced from 10KB to 8KB with a reasonable performance degradation.

[0044] In some embodiments, to reduce the computational complexity, the LFNST is applied only when all coefficients outside the first coding group are non-significant, e.g., zero. In other words, when the LFNST is applied, all primary-only transform coefficients are zero. This allows the LFNST index signaling to depend on the last valid position and thus avoids additional coefficient scanning in the LFNST design (otherwise it would only need to check for valid coefficients at specific positions).

[0045] The worst-case handling of LFNST (in terms of per-pixel multiplication) limits the non-separable transforms for 4x4 and 8x8 blocks to 8x16 and 8x48 transforms, respectively. For these cases, in some embodiments, when LFNST is applied, the last valid scan position is constrained to be less than 8 for 4x4 and less than 16 for other sizes. For blocks with 4xN and Nx4 (where N>8) shapes, the proposed limit implies that LFNST is applied only once and only to the top-left 4x4 region. Since all primary-only coefficients are zero when LFNST is applied, the number of operations required for the primary transform is reduced in these cases. From the encoder's perspective, coefficient quantization is simplified when the LFNST transform is tested. Rate-distortion optimized quantization is done at the maximum for the first 16 coefficients (in scan order), and the remaining coefficients are forced to zero.

[0046] In some embodiments, 4 transform groups and 2 non-separable transform matrices (cores) / per transform group are used for LFNST. The mapping from intra prediction modes to transform groups is predefined as shown in Table 3:

[0047] Table 3: LFNST Transform Selection Table

[0048]

[0049]

[0050] If one of the three CCLM modes (INTRA_LT_CCLM, INTRA_T_CCLM, or INTRA_L_CCLM) is used for the current block (81 <= predModeIntra <= 83), transform group 0 is selected for the current chroma block. For each transform group, the selected non-separable secondary transform candidate is further specified by the explicitly signaled LFNST index. For intra CUs, this index is signaled in the bitstream after the transform coefficients.

[0051] Since LFNST is only restricted to be applicable when all coefficients outside the first coefficient group are non-significant, in some embodiments, the LFNST index coding and decoding depends on the position of the last significant coefficient. In addition, the LFNST index is context coded but does not depend on the intra prediction mode, and only the first bit bin is context coded. Furthermore, LFNST is applied to intra CUs in both intra and inter slices, and for both luminance and chrominance. If the dual tree is enabled, the LFNST indices for luminance and chrominance are signaled separately. For inter slices (dual tree disabled), a single LFNST index is signaled and used for both luminance and chrominance.

[0052] Considering that due to the existing maximum transform size limit (64x64 or as configured), large CUs (e.g., larger than 64x64) are implicitly split (TU partitioning, TU tiling), for some number of decoding pipeline stages, the LFNST index search can increase the data buffering by four times. Therefore, the maximum allowable size of LFNST is 64x64 or the maximum transform size. In some embodiments, MTS is only enabled when LFNST is off.

[0053] B. Signaling the MTS Index

[0054] In some embodiments, the MTS index indicates which transform kernels are applied along the horizontal and vertical directions in the associated luminance transform block of the current pixel block (e.g., CU). According to the syntax of LFNST, the MTS index is signaled at the CU level (after signaling / parsing all transform blocks of the current block). An example of the corresponding CU syntax table is shown in Table 4.

[0055] Table 4: Coding Unit Syntax Table Including the MTS Index

[0056]

[0057]

[0058] The MTS signaling criterion is: the MTS index is signaled if all of the following conditions are met; otherwise, the MTS index is not signaled (and inferred as 0 (default value)).

[0059] The current CB is for luminance

[0060] The Cbf of the current CB is greater than 0

[0061] The CB width is <= 32 and the CB height is <= 32

[0062] The current CU is not an ISP (the ISP has its own implicit selection rules for MTS).

[0063] The current CU is not an SBT (the SBT has its own implicit selection rules for MTS).

[0064] transform_skip_flag for the transform block of the current CB = 0

[0065] MtsZeroOutSigCoeffFlag = 1 (initialized to 1 and updated for each luminance TU / TB of the current CU / CB as shown in Table 5).

[0066] Table 5: Residual Coding Syntax Table

[0067]

[0068]

[0069]

[0070] [[ID=2५]]

[0071] In some embodiments, when the decoder receives transformed coefficients for each luminance TU / TB of the current CU / CB (for each TB (transform block)), the decoder first parses the position of the last significant (non-zero) coefficient, and then parses the syntax for each coding group (CG) or sub-block (e.g., one CG = one 4x4 sub-block). Figure 2 Illustrates a 32x32 transform block 200 with zero and non-zero coefficients. In this figure, each grid position represents a 4x4 CG and the number of each grid position represents the (diagonal) scan order for each CG in the TB. These CGs are thus in diagonal scan order from grid number 0 to 63. In some embodiments, the syntax for each CG includes a coded_sub_block_flag or sb_coded_flag to indicate whether there are any non-zero coefficients in this CG, i.e., whether the coefficients of the sub-block are coded. Specifically, sb_coded_flag[xS][yS] specifies the following for the sub-block at position (xS,yS) in the current transform block, where the sub-block is an array of transform coefficient levels:

[0072] When sb_coded_flag[xS][yS] is equal to 0, all transform coefficient levels of the sub-block at position (xS,yS) are inferred to be equal to 0.

[0073] When sb_coded_flag[xS][yS] does not exist, it is inferred to be equal to 1. For the sub-block where the last significant coefficient position of the current TB is located, sb_coded_flag[xS][yS] is inferred to be 1.

[0074] In some embodiments, whether to parse the MTS index depends on the syntax element MtsZeroOutSigCoeffFlag (1 = parse the MTS index for the TB / CU and 0 = bypass the MTS index for the TB / CU), which is initialized to 1 and updated for each luminance TB of the current CU / CB. According to the syntax table shown in Table 5, if LastSignificantCoeffX > 15 or LastSignificantCoeffY > 15, the value of MtsZeroOutSigCoeffFlag is set to 0, and the MTS index is bypassed (not signaled in the bitstream or not parsed from the bitstream). Figure 2 In the example, if LastSignificantCoeffX ≤ 15 and LastSignificantCoeffY ≤ 15, the last significant coefficient position is in the hashed region 210 (diagonal scan order in the CGs at grid positions 0-9, 11-13, 17-18, and 24). On the other hand, if LastSignificantCoeffX > 15 or LastSignificantCoeffY > 15, the last significant coefficient position for this TB is in the dark black region (diagonal scan order in the CGs at grid positions > 24), MtsZeroOutSigCoeffFlag is set to 0, and the MTS index is bypassed.

[0075] However, if the video encoder / decoder relies only on LastSignificantCoeffX and / or LastSignificantCoeffY to determine whether to bypass the MTS index for the current block, there will be redundancy between the residual signaling and the MTS index. For example, for a 32x32 TB 200, since only the coefficients in the 16x16 low-frequency region (the region 210 where MTS is applied, or the CG at grating positions 0-9, 11-13, 17-18, and 24) are retained for each MTS-applied TB, if there are any non-zero coefficients outside the 16x16 region, the MTS index should be 0. However, if only MtsZeroOutSigCoeffFlag (which is derived from the last significant coefficient position) is used, redundancy will occur when the last significant coefficient position satisfies LastSignificantCoeffX <= 15 and LastSignificantCoeffY <= 15 (e.g., at the CG in grating position 24), and when there can be some non-zero coefficients in the white area with grating positions <= 24 (the CG at grating positions 10, 14-16, and 19-23). In these cases, MtsZeroOutSigCoeffFlag will be set to 1 and the MTS index will still be parsed but will always be 0 (which may be redundant).

[0076] In some embodiments of the present disclosure, the MTS index is parsed only when there are no coefficients outside the MTS-applied region (e.g., region 210). The value of MtsZeroOutSigCoeffFlag is determined based on whether there are any non-zero coefficients outside the MTS-applied region. If so, MtsZeroOutSigCoeffFlag is set to 0 such that the MTS index is not parsed and is inferred to be 0. Otherwise, MtsZeroOutSigCoeffFlag is set to 1, and if other MTS signaling conditions are satisfied, the MTS index is parsed from the bitstream and is used to select the MTS transform mode.

[0077] In some embodiments, the syntax element coded_sub_block_flag may be used to indicate whether a sub-block or CG outside the 16x16 region (the region to which MTS is applied) has any non-zero coefficients. After the value of the coded_sub_block_flag of the sub-block or CG is determined (parsed / inferred), MtsZeroOutSigCoeffFlag may be set according to the value of the coded_sub_block_flag of the sub-block. Specifically, if the coded_sub_block_flag of any sub-block outside the MTS-applied region is equal to 1, MtsZeroOutSigCoeffFlag is set to 0.

[0078] Specifically, for the sub-block at position (xS, yS) in the current transform block, coded_sub_block_flag[xS][yS] indicates the following:

[0079] If coded_sub_block_flag[xS][yS] does not exist, it is inferred to be equal to 1.

[0080] If coded_sub_block_flag[xS][yS] is equal to 0, the 16 transform coefficient levels of the sub-block at position (xS, yS) are inferred to be equal to 0.

[0081] If coded_sub_block_flag[xS][yS] is equal to 1, the following is applied:

[0082] If (xS, yS) is equal to (0, 0) and (LastSignificantCoeffX, LastSignificantCoeffY) is not equal to (0, 0), at least one of the 16 sig_coeff_flag syntax elements exists for the sub-block at position (xS, yS).

[0083] Otherwise, at least one of the 16 transform coefficient levels of the sub-block at position (xS, yS) has a non-zero value.

[0084] For example, when (xS≥4 or yS≥4) and coded_sub_block_flag[xS][yS] == true, MtsZeroOutSigCoeffFlag is set to 0. In some embodiments, rules defined based on coded_sub_block_flag rather than the last significant coefficient position can be used to determine the value of MtsZeroOutSigCoeffFlag. The corresponding syntax tables for residual coding and decoding are shown in Table 6 below.

[0085] Table 6: Residual Coding and Decoding Syntax Table with coded_sub_block_flag for Determining the Value of MtsZeroOutSigCoeffFlag

[0086]

[0087]

[0088]

[0089] According to Table 6, if any sub-block or CG at a horizontal or vertical position greater than or equal to 4 (xS≥4 or yS≥4) has non-zero coefficients (indicated by coded_sub_block_flag[xS][yS]), MtsZeroOutSigCoeffFlag is set to 0, and MTS index profiling is bypassed.

[0090] In other words, the corresponding syntax table can be as follows.

[0091]

[0092] Figure 3 Illustrates the use of the non-zero coefficient indication (coded_sub_block_flag) of the sub-block to determine whether to profile the MTS index. As shown, when the MTS index is profiled or signaled, the sub-blocks (MTS-applied region 210) at positions xS≤3 and yS≤3 in block 200 can have non-zero coefficients. However, if any sub-block or CG at a position xS≥4 or yS≥4 in region 300 has non-zero coefficients (indicated by coded_sub_block_flag[xS][yS]), MtsZeroOutSigCoeffFlag is set to 0, and MTS index profiling is bypassed. Region 300 of the current block (where xS>3 or yS>3) is therefore also referred to as the MTS zero-out region or the zero-out region of the current block.

[0093] In some embodiments, coded_sub_block_flag may be used together with the last significant coefficient position to determine whether to parse the MTS index. The corresponding syntax tables for residual coding / decoding are shown in Table 7 below.

[0094] Table 7:

[0095]

[0096]

[0097]

[0098] In some embodiments, based on LastSignificantCoeffX and LastSignificantCoeffY, MtsZeroOutSigCoeffFlag is initially set (i.e., when MtsZeroOutSigCoeffFlag is not equal to 0, it is changed to 0) and then this MtsZeroOutSigCoeffFlag is used to determine whether to check the coded_sub_block_flag of the sub-block. The corresponding syntax tables for residual coding / decoding are shown in Table 8 below.

[0099] Table 8:

[0100]

[0101]

[0102]

[0103] Another example of the corresponding syntax tables for residual coding / decoding is shown in Table 9 below.

[0104] Table 9:

[0105]

[0106]

[0107]

[0108] Any of the methods proposed above may be combined. Any of the variations above may be determined implicitly by block width or block height or block area, or explicitly by signaling a flag at the CU, CTU, slice, tile, tile group, SPS, or PPS level. "Block" in this invention may refer to TU / TB / CU / CB / PU / PB. Any of the methods proposed above may be implemented in the encoder and / or decoder. For example, any of the methods proposed may be implemented in the inter / intra / transform codec module, motion compensation module, and merge candidate derivation module of the decoder in the encoder. Any of the methods proposed may also alternatively be implemented as circuitry coupled to the inter / intra / transform codec module, and / or motion compensation module, and merge candidate derivation module of the decoder in the encoder.

[0109] Exemplary video encoder

[0110] Figure 4 FIG. shows an exemplary video encoder 400. As shown, video encoder 400 receives an input video signal from video source 405 and encodes the signal into bitstream 495. Video encoder 400 has several components or modules for encoding the signal from video source 405, including at least some components selected from transform module 410, quantization module 411, inverse quantization module 414, inverse transform module 415, intra-picture estimation module 420, intra-prediction module 425, motion compensation module 430, motion estimation module 435, loop filter 445, reconstructed picture buffer 450, MV buffer 465, MV prediction module 475, and entropy encoder 490. Motion compensation module 430 and motion estimation module 435 are part of inter-prediction module 440.

[0111] In some embodiments, modules 410-490 are modules of software instructions executed by one or more processing units (e.g., processors) of a computing device or electronic device. In some embodiments, modules 410-490 are modules of hardware circuits implemented by one or more integrated circuits (ICs) of an electronic device. Although modules 410-490 are shown as separate modules, some modules may be combined into a single module.

[0112] Video source 405 provides an original video signal that presents pixel data for each video frame without compression. Subtractor 408 calculates the difference between the original video pixel data of video source 405 and the predicted pixel data 413 from motion compensation module 430 or intra-prediction module 425. Conversion module 410 converts this difference (or residual pixel data or residual signal 409) into conversion coefficients (e.g., by performing a discrete cosine transform, or DCT). Quantization module 411 quantizes the conversion coefficients into quantized data (or quantized coefficients) 412, which are encoded by entropy encoder 490 into bitstream 495.

[0113] Inverse quantization module 414 inverse quantizes the quantized data (or quantized coefficients) 412 to obtain conversion coefficients, and inverse conversion module 415 performs an inverse conversion on the conversion coefficients to generate a reconstructed residual 419. The reconstructed residual 419 is added to the predicted pixel data 413 to generate reconstructed pixel data 417. In some embodiments, the reconstructed pixel data 417 is temporarily stored in a line buffer (not shown) for intra-picture prediction and spatial MV prediction. The reconstructed pixels are filtered by loop filter 445 and stored in reconstructed picture buffer 450. In some embodiments, the reconstructed picture buffer 450 is a memory outside video encoder 400. In some embodiments, the reconstructed picture buffer 450 is a memory within video encoder 400.

[0114] Intra-picture estimation module 420 performs intra-prediction based on the reconstructed pixel data 417 to generate intra-prediction data. The intra-prediction data is provided to entropy encoder 490 to be encoded into bitstream 495. The intra-prediction data is also used by intra-prediction module 425 to generate predicted pixel data 413.

[0115] Motion estimation module 435 performs inter-prediction by providing MVs to the reference pixel data of the previously decoded video frames stored in reconstructed picture buffer 450. These MVs are provided to motion compensation module 430 to generate predicted pixel data.

[0116] Instead of encoding the full actual MVs into the bitstream, video encoder 400 uses MV prediction to generate predicted MVs and encodes the difference between the MVs for motion compensation and the predicted MVs as residual motion data and stores it in bitstream 495.

[0117] The MV prediction module 475 generates a predicted MV based on a reference MV, which is generated during the encoding of a previous video frame, i.e., the motion compensation MV used for performing motion compensation. The MV prediction module 475 retrieves the reference MV from the previous video frame from the MV buffer 465. The video encoder 400 stores the MV generated for the current video frame in the MV buffer 465 as the reference MV for generating the predicted MV.

[0118] The MV prediction module 475 uses the reference MV to create a predicted MV. The predicted MV can be calculated by spatial MV prediction or temporal MV prediction. The difference between the predicted MV of the current video frame (residual motion data) and the motion compensation MV (MC MV) is encoded by the entropy encoder 490 into the bitstream 495.

[0119] The entropy encoder 490 encodes various parameters and data into the bitstream 495 by using entropy encoding and decoding techniques such as Context-based Adaptive Binary Arithmetic Coding (CABAC) or Huffman encoding. The entropy encoder 490 encodes various header elements, flags, and the quantized transform coefficients 412 together with the residual motion data as syntax elements into the bitstream 495. Then the bitstream 495 is stored in a storage device or transmitted to a decoder via a communication medium such as a network.

[0120] The loop filter 445 performs a filtering operation or a smoothing operation on the reconstructed pixel data 417 to reduce coding and decoding artifacts, especially at the boundaries of pixel blocks. In some embodiments, the filtering operation performed includes Sample Adaptive Offset (SAO). In some embodiments, the filtering operation includes Adaptive Loop Filter (ALF).

[0121] Figure 5 Shows some parts of the encoder 400 that perform multiple transform selection (MTS) by selectively enabling transform operations. As shown, for each pixel block, the encoder 400 determines whether to perform a specific type of secondary transform (e.g., LFNST), whether to perform a specific type of primary transform (e.g., DCT-II), whether to enable MTS, and / or which transform to use as the horizontal transform and vertical transform for MTS. The encoder also determines the signaling for MTS in the bitstream 495.

[0122] As depicted, the transform module 410 performs a primary transform and / or a secondary transform on the residual signal 409, and the inverse transform module 415 performs a corresponding inverse primary transform and / or inverse secondary transform. The encoder 400 selects the primary transform and / or the secondary transform for the transform module 410 and the inverse transform module 415. The selected primary transform can perform MTS by including a horizontal transform and a vertical transform.

[0123] The encoder 400 includes an encoding / decoding control module 500. The encoding / decoding control module 500 determines the selection of the primary transform and / or the secondary transform, and which transform will be used as the horizontal and vertical transforms if MTS is to be used. The encoding / decoding control module 500 can make this decision based on a set of current block information 510 from the transform module 410, which can indicate that the sub-blocks of the current block have non-zero coefficients (or significant coefficients greater than a threshold).

[0124] Based on the current block information 510, the encoding / decoding control module 500 generates corresponding non-zero coefficient indicators for the sub-blocks of the current block to indicate which sub-blocks have at least one non-zero coefficient (e.g., coded_sub_block_flag). The encoding / decoding control module 500 can also identify the position of the last non-zero coefficient in the current block. The encoding / decoding control module 500 can also generate an MTS index to identify the horizontal transform and the vertical transform being used for MTS. These signals are provided to the entropy encoder 490 to be incorporated into the bitstream 495.

[0125] The entropy encoder 490 then encodes the non-zero coefficient indicators of different sub-blocks into the bitstream (e.g., the coded_sub_block_flag for different sub-blocks). The entropy encoder 490 can also signal the position of the last non-zero coefficient (e.g., LastSignificantCoeffX and LastSignficantCoeffY) and the MTS index into the bitstream 495. In some embodiments, if the non-zero coefficient indicator indicates that there are non-zero coefficients in a zero region defined by sub-block positions beyond a vertical threshold position or a horizontal threshold position (e.g., defined by xS>3 or yS>3 Figure 3 zero region 300), or if the position of the last non-zero coefficient in the current block indicates that there are non-zero coefficients beyond a specific sub-block in the diagonal scan order (e.g., LastSignificantCoeffX>15 or LastSignificantCoeffY>15), the entropy encoder 490 can skip or bypass signaling the MTS index into the bitstream.

[0126] Figure 6Conceptually, program 600 is depicted to encode a pixel block using multiple transform selections. In some embodiments, one or more processing units (e.g., processors) on a computing device implementing encoder 400 implement program 600 by executing instructions stored on a computer-readable medium. In some embodiments, an electronic device implementing encoder 400 implements program 600.

[0127] The encoder receives (at block 610) data for a pixel block and encodes it as a current block in the current picture of a video into a bitstream.

[0128] Based on non-zero coefficient indications (e.g., coded_sub_block_flag) of sub-blocks in a zero-out region 300 of the current block (e.g., defined by xS > 3 or yS > 3), the encoder sets (at block 620) a zero-out indication (e.g., MtsZeroOutSigCoeffFlag). In some embodiments, the zero-out region of the current block is the region of each transform block in the current block that is beyond a vertical threshold position or a horizontal threshold position (e.g., xS > 3 or yS > 3). (The horizontal threshold position and the vertical threshold position are positions of each coding group that can include 16 transform coefficients.) In some embodiments, the encoder checks non-zero coefficient indications of sub-blocks in the zero-out region to see if any sub-blocks in the zero-out region have non-zero coefficients. If so, the encoder sets the zero-out indication to indicate that there are non-zero coefficients in the zero-out region. The program proceeds to 640. Figure 3

[0129] The encoder determines (at block 630) whether the zero-out indication indicates that there is at least one non-zero coefficient in the zero-out region of the current block. If so, the program proceeds to 640. If the zero-out indication indicates that the zero-out region has no non-zero coefficients, the encoder (at block 650) signals the MTS index into the bitstream, and then the program proceeds to 660.

[0130] At block 640, the encoder sets the MTS index to a default value without parsing the MTS index from the bitstream. The encoder selects (at block 660) a transform mode based on the MTS index for the current block. In some embodiments, the transform mode specifies the horizontal and vertical transforms of the associated luminance transform block in the current block. In some embodiments, the default value of the MTS index corresponds to a transform mode of discrete cosine transform type II (DCT-2) for both horizontal and vertical transforms. The encoder encodes (at block 670) the current block into the bitstream by using the selected transform mode.

[0131] Exemplary video encoder

[0132] Figure 7 Figure 7Illustrate an exemplary video decoder 700. As shown, the video decoder 700 is a video-decoding or video-decoding circuit that receives a bitstream 795 and decodes the content of the bitstream into pixel data of video frames for display. The video decoder 700 has several components or modules for decoding the bitstream 795, including some components selected from the inverse quantization module 714, the inverse transform module 710, the intra-prediction module 725, the motion compensation module 730, the loop filter 745, the decoded picture buffer 750, the MV buffer 765, the MV prediction module 775, and the parser 790. The motion compensation module 730 is part of the inter-prediction module 740.

[0133] In some embodiments, the modules 710-790 are modules of software instructions executed by one or more processing units (e.g., processors) of a computing device. In some embodiments, the modules 710-790 are modules of hardware circuits implemented by one or more integrated circuits of an electronic device. Although the modules 710-790 are shown as separate modules, some modules may be combined into a single module.

[0134] The parser 790 (or entropy decoder) receives the bitstream 795 and performs a preliminary parsing according to the syntax defined by a video-coding or video-coding standard. The parsed syntax elements include various header elements, flags, and quantized data (or quantized coefficients) 712. The parser 790 parses out various syntax elements by using entropy coding techniques such as context-adaptive binary arithmetic coding (CABAC) or Huffman coding.

[0135] The inverse quantization module 714 performs inverse quantization on the quantized data (or quantized coefficients) 712 to obtain transform coefficients, and the inverse transform module 710 performs an inverse transform operation on the transform coefficients 716 to generate a reconstructed residual signal 719. The reconstructed residual signal 719 is added to the predicted pixel data 713 from the intra-prediction module 725 or the motion compensation module 730 to generate decoded pixel data 717. The decoded pixel data is filtered by the loop filter 745 and stored in the decoded picture buffer 750. In some embodiments, the decoded picture buffer 750 is a memory outside the video decoder 700. In some embodiments, the decoded picture buffer 750 is a memory within the video decoder 700.

[0136] The intra-prediction module 725 receives intra-prediction data from the bitstream 795 and, based thereon, generates predicted pixel data 713 from the decoded pixel data 717 stored in the decoded picture buffer 750. In some embodiments, the decoded pixel data 717 is also stored in a line buffer (not shown) for intra-picture prediction and spatial MV prediction.

[0137] In some embodiments, the content of the decoded picture buffer 750 is used for display. The display device 755 directly retrieves the content of the decoded picture buffer 750 for display, or retrieves the content of the decoded picture buffer into a display buffer. In some embodiments, the display device receives pixel values from the decoded picture buffer 750 via pixel transfer.

[0138] The motion compensation module 730 generates predicted pixel data 713 from the decoded pixel data 717 stored in the decoded picture buffer 750 according to motion compensation MVs (MC MVs). These motion compensation MVs are decoded by adding the residual motion data received from the bitstream 795 and the predicted MVs received from the MV prediction module 775.

[0139] The MV prediction module 775 generates predicted MVs based on reference MVs, which are generated during the decoding of previous video frames, i.e., the motion compensation MVs used for performing motion compensation. The MV prediction module 775 retrieves the reference MVs of the previous video frames from the MV buffer 765. The video decoder 700 stores the motion compensation MVs generated for decoding the current video frame in the MV buffer 765 as reference MVs for generating predicted MVs.

[0140] The loop filter 745 performs a filtering operation or a smoothing operation on the decoded pixel data 717 to reduce coding artifacts, especially at the boundaries of pixel blocks. In some embodiments, the filtering operation performed includes Sample Adaptive Offset (SAO). In some embodiments, the filtering operation includes Adaptive Loop Filter (ALF).

[0141] Figure 8 Some parts of the decoder 700 that illustrate the implementation of multiple transform selection (MTS) by selectively enabling transform operations are shown. As shown, for each pixel block, the decoder 700 determines whether to perform a particular type of secondary transform, whether to perform a particular type of primary transform (e.g., DCT-II), whether to enable MTS, and / or which transform to use as the horizontal transform and the vertical transform for MTS. The decoder also determines the signaling in the bitstream 795 for MTS.

[0142] As depicted, the decoder 700 selects a primary transform and / or a secondary transform for the inverse transform module 715, and the inverse transform module 715 performs the corresponding inverse primary transform and / or inverse secondary transform. The selected primary transform can perform MTS by including a horizontal transform and a vertical transform.

[0143] The decoder 700 includes a codec control module 800. The codec control module 800 determines the selection of the primary transform and / or the secondary transform, and which transform will be used as the horizontal and vertical transforms if MTS is to be used. The codec control module 800 can map the MTS index provided by the entropy decoder 790 to the selection of the corresponding horizontal and vertical transforms.

[0144] The entropy decoder 790 parses the bitstream 795 to determine the value of the MTS index. The bitstream can include syntax elements to indicate which sub-blocks of the current block have non-zero coefficients (e.g., coded_sub_block_flag), or / and syntax elements to identify the position of the last non-zero coefficient in the current block. Based on these syntax elements, the entropy decoder can determine whether to parse the bitstream for the MTS index. Specifically, if the position of the last non-zero coefficient in the current block indicates that there are non-zero coefficients in sub-blocks beyond a specific sub-block in the diagonal scan order (e.g., LastSignificantCoeffX > 15 or LastSignificantCoeffY > 15), or if the non-zero coefficient indication indicates that there are non-zero coefficients in the zeroing region defined by sub-block positions beyond the vertical threshold position or the horizontal threshold position (e.g., the region 300 defined by xS > 3 or yS > 3) Figure 3 the entropy decoder 790 can skip or bypass parsing the bitstream for the MTS index. If the entropy decoder 790 does not parse the bitstream for the MTS index, the entropy decoder 790 sets the value of the MTS index to zero for the codec control module 800.

[0145] Figure 9 Conceptually, a procedure 900 is depicted to decode a pixel block using multiple transform selections. In some embodiments, one or more processing units (e.g., processors) on a computing device implementing the decoder 700 perform the procedure 900 by executing instructions stored on a computer-readable medium. In some embodiments, an electronic device implementing the decoder 700 performs the procedure 900.

[0146] The decoder receives (at block 910) data from the bitstream to decode the pixel block as the current block in the current picture of the video.

[0147] Based on the current block (e.g., defined by xS > 3 or yS > 3) Figure 3For non-zero coefficient indications of sub-blocks in the region 300) (such as coded_sub_block_flag), the decoder sets the zero-out indication (in block 920) to zero (such as MtsZeroOutSigCoeffFlag). In some embodiments, the zero-out region of the current block is the region of each transform block in the current block that exceeds the vertical threshold position or the horizontal threshold position (such as xS > 3 or yS > 3). The horizontal threshold position and the vertical threshold position are the positions (xS, yS) of the coding / decoding group in the current transform block (or the sub-block at the position (xS, yS) in the current transform block). For example, the sub-block includes 16 transform coefficients. In other words, the sub-block includes 4x4 transform coefficients. In some embodiments, the encoder checks the non-zero coefficient indication of the sub-block in the zero-out region to see if any sub-block in the zero-out region has non-zero coefficients. If so, the encoder sets the zero-out indication to indicate that there are non-zero coefficients in the zero-out region. The program proceeds to 940.

[0148] The decoder determines (in block 930) whether the zero-out indication indicates that there is at least one non-zero coefficient in the zero-out region of the current block. If so, the program proceeds to 940. If the zero-out indication indicates that the zero-out region of the current block does not have non-zero coefficients (if other MTS signaling conditions are also met), the decoder parses (in block 950) the bitstream for the MTS index, and the program proceeds to 960.

[0149] In block 940, the decoder sets the MTS index to a preset value without parsing the MTS index from the bitstream. The decoder selects (in block 960) a transform mode based on the MTS index for the current block. In some embodiments, the transform mode specifies the horizontal and vertical transforms of the associated luminance transform block in the current block. In some embodiments, the preset value of the MTS index corresponds to the transform mode of discrete cosine transform type II (DCT-2) for both horizontal and vertical transforms. The decoder reconstructs (in block 970) the current block by using the selected transform mode.

[0150] In some embodiments, the encoder may signal (or generate) one or more syntax elements in the bitstream so that the decoder can parse the one or more syntax elements from the bitstream.

[0151] Example electronic system

[0152] Many of the above features and applications can be implemented as software processes, which are specified as sets of instructions recorded on a computer readable storage medium (also referred to as a computer readable medium). When these instructions are executed by one or more computing units or processing units (e.g., one or more processors, processor cores, or other processing units), the instructions cause the processing unit to perform the actions represented by the instructions. Examples of computer readable media include, but are not limited to, CD-ROMs, flash drives, random access memory (RAM) chips, hard disks, erasable programmable read only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), etc. The computer readable medium does not include carrier waves and electrical signals transmitted through wireless or wired connections.

[0153] In this specification, the term "software" means including firmware in read-only memory or application programs stored in magnetic storage devices, which can be read into memory for processing by a processor. At the same time, in some embodiments, multiple software inventions can be implemented as sub-parts of a larger program while retaining different software inventions. In some embodiments, multiple software inventions can be implemented as independent programs. Finally, any combination of independent programs that together implement the software inventions described herein is within the scope of the present invention. In some embodiments, when installed to operate on one or more electronic systems, a software program defines one or more specific machine implementation manners that execute and implement the operations of the software program.

[0154] Figure 10Conceptually illustrate the electronic system 1000 in which some embodiments of the present disclosure may be implemented. The electronic system 1000 may be a computer (e.g., desktop computer, personal computer, tablet computer, etc.), a telephone, a PDA, or other types of electronic devices. This electronic system includes various types of computer-readable media and interfaces for various other types of computer-readable media. The electronic system 1000 includes a bus 1005, a processing unit 1010, a graphics-processing unit (GPU) 1015, a system memory 1020, a network 1025, a read-only memory (ROM) 1030, a permanent storage device 1035, an input device 1040, and an output device 1045.

[0155] The bus 1005 collectively represents all system buses, peripheral buses, and chipset buses of internal devices that are communicatively connected to the large number of electronic systems 1000. For example, the bus 1005 is communicatively connected to the processing unit 1010 through the graphics-processing unit 1015, the read-only memory 1030, the system memory 1020, and the permanent storage device 1035.

[0156] For these various memory units, the processing unit 1010 retrieves the instructions to be executed and the data to be processed in order to execute the processing of the present invention. In different embodiments, the processing unit may be a single processor or a multi-core processor. Certain instructions are transmitted to the graphics-processing unit 1015 and executed by it. The graphics-processing unit 1015 may offload various computations or supplement the graphics processing provided by the processing unit 1010.

[0157] The read-only memory 1030 stores static data and instructions required by the processing unit 1010 or other modules of the electronic system. On the other hand, the permanent storage device 1035 is a read-and-write memory device. This device is a non-volatile memory unit that stores instructions and data even when the electronic system 1000 is turned off. Some embodiments of the present invention use a mass storage device (e.g., magnetic disk or optical disk and their corresponding disk drives) as the permanent storage device 1035.

[0158] Other embodiments use removable storage devices (such as floppy disks, flash memory devices, etc., and their corresponding disk drives) as the permanent storage device. Like the permanent storage device 1035, the system memory 1020 is a read-write memory device. However, unlike the storage device 1035, the system memory 1020 is a volatile read-write memory, such as random access memory. The system memory 1020 stores some instructions and data that the processor needs during operation. In some embodiments, the processes according to the present invention are stored in the system memory 1020, the permanent storage device 1035, and / or the read-only memory 1030. For example, various memory units include instructions for processing multimedia clips according to some embodiments. For these various memory units, the processing unit 1010 retrieves the instructions to be executed and the data to be processed in order to execute the processes of certain embodiments.

[0159] The bus 1005 is also connected to an input device 1040 and an output device 1045. The input device 1040 enables a user to communicate information and select instructions to the electronic system. The input device 1040 includes an alphanumeric keyboard and a pointing device (also referred to as a "cursor control device"), a camera (such as a webcam), a microphone for receiving voice commands, or similar devices. The output device 1045 displays images generated by the electronic system or otherwise outputs data. The output device 1045 includes a printer and a display device, such as a cathode ray tube (CRT) or a liquid crystal display (LCD), and a speaker or similar audio output device. Some embodiments include devices such as touchscreens that serve as both input devices and output devices.

[0160] Finally, as Figure 10 shown, the bus 1005 also couples the electronic system 1000 to a network 1025 via a network adapter (not shown). In this way, the computer can be part of a computer network (e.g., a local area network (LAN), a wide area network (WAN), or an intranet) or a network of networks (e.g., the Internet). Any or all of the elements of the electronic system 1000 can be used in conjunction with the present invention.

[0161] Some embodiments include electronic components, such as, a microprocessor, a storage device, and a memory, which store computer program instructions to a machine-readable medium or a computer-readable medium (optionally referred to as a computer-readable storage medium, a machine-readable medium, or a machine-readable storage medium). Some examples of computer-readable media include RAM, ROM, read-only compact disc (CD-ROM), recordable compact disc (CD-R), rewritable compact disc (CD-RW), read-only digital versatile disc (e.g., DVD-ROM, dual-layer DVD-ROM), various recordable / rewritable DVDs (e.g., DVD RAM, DVD-RW, DVD+RW, etc.), flash memory (such as SD card, mini SD card, micro SD card, etc.), magnetic and / or solid state drives, read-only and recordable (Blu- ) discs, ultra high density optical discs, and any other optical or magnetic media, as well as floppy discs. The computer-readable medium can store a computer program executable by at least one processing unit and includes a set of instructions for performing various operations. Examples of computer programs or computer code include machine code, such as that generated by a compiler, and documents containing high-level code that is executed by a computer, an electronic component, or a microprocessor using an interpreter.

[0162] While the above discussion has mainly referred to a microprocessor or a multi-core processor that executes software, many of the above functions and applications are performed by one or more integrated circuits, such as an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA). In some embodiments, such integrated circuits execute instructions stored on the circuit itself. Additionally, some embodiments execute software stored in a programmable logic device (PLD), a ROM, or a RAM device.

[0163] As used in the specification of the present invention and in any of the claims, the terms "computer", "server", "processor", and "memory" all refer to electronic devices or other technical devices. These terms do not include a person or a group. For the purposes of this specification, the term display or display device refers to a display on an electronic device. As used in the specification of the present invention and in any of the claims, the terms "computer-readable medium", "computer-readable media", and "machine-readable medium" are entirely restricted to tangible, physical objects that store information in a computer-readable form. These terms do not include any wireless signals, wired download signals, and any other transient signals.

[0164] While the present invention has been described in connection with numerous specific details, those skilled in the art will recognize that the present invention may be embodied in other specific forms without departing from the spirit of the present invention. Additionally, a large number of figures (including Figure 6 and Figure 9 ) conceptually illustrate the processes. The specific operations of these processes may not be performed in the exact order shown and described. These specific operations may be performed not in a consecutive series of operations, and different specific operations may be performed in different embodiments. Additionally, the process is implemented by using several sub-processes, or as part of a larger macro process. Therefore, those skilled in the art will understand that the present invention is not limited by the foregoing illustrative details, but is defined by the claims.

[0165] Additional Notes

[0166] The subject matter described herein sometimes represents different elements that are included in or connected to other different elements. It will be understood that the described structure is merely an example, and in fact, many other structures may be implemented to achieve the same function. Conceptually, any arrangement of components that achieves the same function is effectively "associated" to achieve the desired function. Therefore, regardless of the structure or intermediate components, any two elements combined to achieve a specific function are considered "associated" to achieve the desired function. Similarly, any two associated elements are regarded as being "operably connected" or "operably coupled" to achieve a specific function. Any two components that can be associated are also considered to be "operably coupled" to each other to achieve a specific function. Specific examples of operable connections include, but are not limited to, physically mateable and / or physically interacting elements, and / or wirelessly interactive and / or wirelessly interacting elements, and / or logically interacting and / or logically interactive elements.

[0167] Furthermore, with regard to the use of substantially any plural and / or singular terms, those skilled in the art can convert from plural to singular and / or from singular to plural depending on the context and / or application. For clarity, different singular / plural arrangements are explicitly set forth herein.

[0168] In addition, those of ordinary skill in the art can understand that, generally, the terms used in the present invention, especially in the claims, such as the subject matter of the claims, are generally used as "open" terms. For example, "comprising" should be interpreted as "comprising but not limited to", "having" should be understood as "having at least", "including" should be interpreted as "including but not limited to", etc. Those of ordinary skill in the art can further understand that if it is planned to introduce a specific number of claim elements, it will be clearly indicated within the claims, and in the absence of such elements, it will not be shown. For example, for the purpose of helping understanding, the following claims may contain phrases such as "at least one" and "one or more" to introduce claim elements. However, the use of these phrases should not be understood as implying that the use of the indefinite article "a" or "an" to introduce claim elements limits any particular claim. Even when the same claim includes an introductory phrase "one or more" or "at least one", the indefinite article, such as "a" or "an", should be interpreted as meaning at least one or more, and the same holds for the use of an indefinite article for the express description used to introduce a claim. In addition, even when specifically referring to a specific number of introductory elements, those skilled in the art can recognize that such elements should be interpreted as meaning the number referred to. For example, "two references" without any other modification means at least two references, or two or more references. In addition, in the case of using an expression similar to "at least one of A, B, and C", generally such an expression is used so that those skilled in the art can understand the expression. For example, "The system includes at least one of A, B, and C" will include, but not be limited to, a system having only A, a system having only B, a system having only C, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B, and C, etc. Those skilled in the art can further understand that, regardless of whether in the specification, the claims, or the drawings, any separated words and / or phrases represented by two or more alternative terms should be understood as including one of these terms, one of them, or the possibility of both of these terms. For example, "A or B" should be understood as the possibility of "A", or "B", or "A and B".

[0169] From the foregoing, it can be seen that for illustrative purposes, various embodiments have been described herein, and various modifications can be made without departing from the scope and spirit of the present invention. Therefore, the various embodiments disclosed herein are not intended to be limiting, and the scope of the patent application represents the true scope and spirit.

Claims

1. A video decoding method, comprising: Receiving data from a bitstream to decode a pixel block as a current block in a current picture of a video; Determining a zeroing indication based on one or more non-zero coefficient indications of a plurality of sub-blocks of the current block, wherein the one or more non-zero coefficient indications are syntax elements coded_sub_block_flag or sb_coded_flag; When the zeroing indication indicates that there are no non-zero coefficients in the zeroing region, parsing the bitstream for a multiple transform selection index; When the zeroing indication indicates that there is at least one non-zero coefficient in the zeroing region, setting the multiple transform selection index to a preset value without parsing the multiple transform selection index from the bitstream; Selecting a transform mode for the current block according to the multiple transform selection index; and Reconstructing the current block by using the selected transform mode.

2. The video decoding method according to claim 1, wherein the one or more non-zero coefficient indications of the plurality of sub-blocks are used to indicate whether sub-blocks of the current block located in the zeroing region of the current block have one or more non-zero coefficients.

3. The video decoding method according to claim 1, wherein the transform mode specifies horizontal and vertical transforms of an associated luminance transform block in the current block.

4. The video decoding method according to claim 1, wherein the zeroing region of the current block is an area of the current block defined by sub-block positions exceeding a vertical threshold position or a horizontal threshold position.

5. The video decoding method according to claim 4, wherein the horizontal threshold position and the vertical threshold position are positions of the sub-blocks.

6. The video decoding method according to claim 1, wherein the preset value corresponds to a transform mode of discrete cosine transform type II for both horizontal and vertical transforms.

7. The video decoding method according to claim 1, wherein low-frequency non-separable transform is disabled for the current block.

8. A video encoding method, comprising: Receiving data for a pixel block, the pixel block being encoded into a bitstream as a current block in a current picture of a video; Determining a zeroing indication based on one or more non-zero coefficient indications of sub-blocks of the current block, wherein the one or more non-zero coefficient indications are syntax elements coded_sub_block_flag or sb_coded_flag; When the zeroing indication indicates that there are no non-zero coefficients in the zeroing region, signaling a multiple transform selection index in the bitstream; When the zeroing indication indicates that there is at least one non-zero coefficient in the zeroing region, not signaling the multiple transform selection index in the bitstream and setting the multiple transform selection index to a preset value; Selecting a transform mode for the current block according to the multiple transform selection index; and Encoding the current block into the bitstream by using the selected transform mode.

9. An electronic device, comprising: A video decoding circuit configured to perform the following operations: Receiving data from a bitstream to decode a pixel block as a current block in a current picture of a video; Determine a zeroing indication based on one or more non-zero coefficient indications of sub-blocks of the current block, where the one or more non-zero coefficient indications are the syntax element coded_sub_block_flag or sb_coded_flag; When the zeroing indication indicates that there are no non-zero coefficients in the zeroing region, parse the bitstream for a multiple transform selection index; When the zeroing indication indicates that there is at least one non-zero coefficient in the zeroing region, set the multiple transform selection index to a preset value without parsing the multiple transform selection index from the bitstream; Select a transform mode for the current block according to the multiple transform selection index; and Reconstruct the current block by using the selected transform mode.

Images