Circuit and method for transmitting phase values between circuits clocked by non-synchronous clock signals

Abstract

A circuit for transmitting an n-bit phase value between circuits includes a system clock input, an n-bit phase value generator coupled to the system clock input that generates a phase value output and an edge output indicating that the phase output value is valid, a latched clock delay circuit having an input coupled to the system clock input, an input coupled to the edge output, a variable phase delay circuit coupled to the phase value output, a delay adder having a first input coupled to the phase value output, a second input coupled to a delay offset signal, and an output coupled to a control input of the variable phase delay circuit, and a phase flip-flop having a data input coupled to an output of the variable phase delay circuit, a clock input coupled to a latched clock output of the variable output clock delay circuit, and a phase out output.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Provisional Patent Application Serial No. 62 / 947,195, filed December 12, 2019, the contents of which are incorporated herein by reference in their entirety, and to U.S. Non-Provisional Patent Application Serial No. 16 / 867,468, filed May 5, 2020, the contents of which are incorporated herein by reference in their entirety. Background Technology

[0003] This invention relates to data transmission between circuits. More specifically, this invention relates to a circuit for reliably transmitting data values ​​between circuits timed by asynchronous clock signals.

[0004] The output of a binary phase accumulator circuit can be configured to provide an integer portion representing the number of complete clock cycles of the input clock between overflows of the binary phase accumulator circuit, and a fractional portion stored in a register when an overflow occurs. Clock edges of a fractional-divided clock signal can be generated by delaying the input clock signal that causes the overflow to the fractional portion stored in the register when the overflow occurs.

[0005] Sometimes, one or more circuits that are out of sync with the system clock signal—that is, out of sync with the input clock signal of a fractional divider circuit—are needed to capture and use n-bit phase values ​​generated by a binary phase accumulator circuit or other circuitry that is a fractional divider circuit, for various purposes. One example is a counter for each phase or group of phases that increments or decrements at each edge of a target output clock signal generated by a frequency synthesizer employing a binary phase accumulator circuit, where the target output clock signal is out of sync with the system clock signal. At each clock edge presented to logic elements (such as flip-flops in other circuitry timed by a clock signal other than the system clock signal), the n-bit phase value to be captured and used must meet appropriate setting and holding requirements. Summary of the Invention

[0006] According to one aspect of the invention, a circuit for transmitting an N-bit phase value between circuits timed by an asynchronous clock signal includes an input to a system clock signal and a phase and marker signal generator coupled to the input to the system clock signal. The phase and marker signal generator includes a binary phase accumulator circuit configured to generate an n-bit phase value output and an edge signal configured to indicate that the n-bit phase value output is a valid n-bit phase value output. The circuit also includes: a latched clock delay circuit having a first input coupled to an input system clock signal, a second input coupled to receive edge signals from a phase and marker signal generator, and an output; an n-bit variable phase delay circuit having an input, a control input, and an output, the input of which is coupled to an n-bit phase value output of the phase and marker signal generator; a multi-bit delay adder having a first input coupled to an n-bit phase value output of the phase and marker signal generator, a second input coupled to an n-bit phase delay offset signal, and an output coupled to a control input of the n-bit variable phase delay circuit; and an n-bit phase trigger having a data input coupled to the output of the n-bit variable phase delay circuit, a clock input coupled to the output of the latched clock delay circuit, and a phase output.

[0007] According to one aspect of the invention, the latching clock delay circuit includes a gate having a first input coupled to an input system clock signal, a second input coupled to receive edge signals from a phase and marker signal generator, and an output; a variable latching clock delay circuit having an input coupled to the output of the gate, and an output; and a fixed latching clock delay circuit having an input coupled to the output of the variable latching clock delay circuit and an output coupled to the output of the latching clock delay circuit.

[0008] According to one aspect of the invention, the gate is an AND gate, and the variable latch clock delay circuit includes a control input coupled to an n-bit phase value output of a phase and marker signal generator.

[0009] According to one aspect of the invention, the binary phase accumulator circuit in the phase and marker signal generator is configured to accumulate a frequency control word (FCW) value at each system clock signal edge, and output the accumulated FCW value as an n-bit phase value output after each system clock signal edge. When the accumulated FCW value reaches an integer overflow value, the binary phase accumulator circuit is configured to modify the generated n-bit phase value output at the subsequent system clock signal edge to be equal to the integer overflow value minus the immediately preceding value of the n-bit phase value output, and output an edge signal at the subsequent system clock signal edge.

[0010] According to one aspect of the invention, the circuit further includes: a tag output of a phase and tag signal generator; a variable tag delay circuit having an input, a control input, and an output, the input being coupled to the tag output of the phase and tag signal generator, the control input of the variable tag delay circuit being coupled to the output of a multi-bit delay adder; and a tag trigger having a data input coupled to the output of the variable tag delay circuit, a clock input coupled to a latch clock delay circuit, and a latched tag output.

[0011] According to one aspect of the invention, the phase and mark signal generator is configured to generate a mark signal at the mark output every N system clock signal cycles in the same system clock signal cycle as the edge signal of the phase and mark signal generator.

[0012] According to one aspect of the invention, a method for transmitting an n-bit phase value between a circuit timing at the edge of a system clock signal and a circuit timing at the edge of a latched clock output signal, wherein the latched clock output signal is out of sync with the system clock signal, comprises: generating a new n-bit phase value by accumulating a frequency control word in response to an edge of the system clock signal, and setting a delay of the new n-bit phase value as a function of the new n-bit phase value and a fixed period. The method further comprises: generating an edge signal when the n-bit phase value is equal to or exceeds an integer overflow value; setting the transmitted n-bit phase value to a value equal to the new n-bit phase value exceeding the integer overflow value; and generating a latched clock output signal in response to the generated edge signal and by latching a clock delay from the edge delay of the system clock signal, the latched clock delay being a function of the transmitted n-bit phase value and a fixed latched clock delay.

[0013] According to one aspect of the invention, the latch clock delay is the sum of the transmission of n-bit phase values ​​and the fixed latch clock delay.

[0014] According to one aspect of the invention, the fixed latch clock delay originates from circuit characteristics.

[0015] According to one aspect of the invention, the characteristics of the edge timing circuit that is a fixed period source of the system clock signal.

[0016] According to one aspect of the invention, the fixed latch clock delay includes a delay derived from the characteristics of the edge timing circuitry originating from the system clock signal.

[0017] According to one aspect of the invention, the latch clock delay is set to be greater than the delay of the new n-bit phase value.

[0018] According to one aspect of the invention, the method further includes generating a marker signal every N system clock edges.

[0019] According to one aspect of the invention, generating a marker signal every N system clock edges includes generating the marker signal synchronously with the edge signal.

[0020] According to one aspect of the invention, the method further includes a latching marker signal.

[0021] According to one aspect of the invention, latching the marker signal includes latching the marker signal using a generated latch clock output signal. Attached Figure Description

[0022] The invention will now be explained in more detail with reference to the embodiments and accompanying drawings, in which:

[0023] Figure 1 This is a block diagram illustrating an exemplary binary phase accumulator circuit that can be used in this invention;

[0024] Figure 2 This is a schematic diagram of an exemplary circuit according to one aspect of the present invention; and

[0025] Figure 3 This is a flowchart illustrating an exemplary method for transmitting phase values ​​between circuits timed by asynchronous clock signals according to an aspect of the present invention. Detailed Implementation

[0026] Those skilled in the art will recognize that the following description is merely illustrative and not intended to be limiting in any way. Other embodiments will readily occur to those skilled in the art.

[0027] exist Figure 1In one example illustrated in block diagram form, a binary phase accumulator circuit 10, including an accumulator adder and a register, is used as a fractional divider circuit for a clock synthesizer. The principle behind using a binary phase accumulator circuit as a divider circuit to provide integer and / or fractional division of the input clock signal is to quantize the period of the input clock signal into a phase. Phase is the delay from the edge of the system clock to the edge of the resulting target or output clock. The phase of any clock signal can be represented as a multi-bit (n-bit) number representing the position (which can be represented as, for example, time) measured from the clock edge of the input clock signal (such as the edge of the system clock signal in the example shown herein), and is used to quantize the period of the input clock signal. The most common example of the principle of phase is that it is represented in degrees or radians, used to represent a position on a sine wave starting at a zero crossover representing the "clock edge" at 0° (0 radians) and extending to 360° (2π radians) at the end of a period (a single cycle). In this invention, phase is a unitless number representing the position along the input clock signal within a single cycle of the input clock signal. It is precisely by quantizing the cycle of the input clock signal into phase increments that fractional division of the input clock signal becomes possible. For the purposes of explaining the invention, an exemplary non-limiting example 1024 will be used to represent the phase of a complete cycle of the input clock signal. To illustrate this concept, if the entire cycle of the system clock signal is quantized into 1024 portions (phase increments), then the phase value of 256 quantized phase increments represents one-quarter of the input clock cycle, the phase value of 512 quantized phase increments represents one-half of the input clock cycle, and the phase value of 768 quantized phase increments represents three-quarters of the input clock cycle.

[0028] In a binary phase accumulator loop, each clock cycle of the input clock signal (e.g., a clock cycle of the system clock signal) produces a new n-bit phase value at the output of the accumulator adder. This phase value is obtained by adding the previous output obtained from a register to the frequency control word (FCW) in the adder. The FCW remains constant to generate the target output clock signal at the target output clock frequency. In some configurations, the n-bit phase value output is taken from the output of a register, which introduces a delay of one clock cycle of the input clock signal but allows the adder to operate at a higher clock rate.

[0029] In a binary phase accumulator circuit, the accumulator adder used as a fractional frequency divider is configured to overflow when the sum of the absolute values ​​of its operands exceeds its capacity (by setting the integer part of the frequency divisor and adding an appendix). Figure 1The amount referred to as the integer overflow value in the description, along with the FCW (which sets the fractional part of the frequency divisor), is selected to divide the frequency of the input clock (i.e., the system clock in the context of this invention) by a fractional number comprising both an integer and a fractional part. The amount by which the sum of the absolute values ​​of its operands exceeds the adder's integer overflow value is the fractional part of the fractional divisor used by the binary phase accumulator circuit to perform the frequency division. After the accumulator adder overflows, the fractional part is stored in a register such that the next accumulator cycle begins from that fractional part. Because the binary phase accumulator circuit is a finite state machine, the fractional part eventually returns to its initial value of zero.

[0030] As a non-limiting example, to divide the frequency of the input clock signal by 2, where the input clock cycle has been divided into 1024 phase increments, the FCW is selected as 1024 and the capacity of the phase accumulator is set to equal 2048. The circuit senses the time when the accumulator output exceeds an integer overflow value of 2048 (which provides the integer part of the divisor = 2048 / 1024 = 2), at which point the amount by which the accumulated FCW exceeds the integer overflow value (which will be 2 × 1024 minus 2048 = 0) is the fractional part of the divisor. The remainder of 0 is the fractional value 0. To divide the input clock signal by 2 - 1 / 2, the FCW is selected to equal 1280 and the capacity of the phase accumulator is set to equal 2048. The circuit senses when the accumulator output exceeds a capacity of 2048 (which provides the integer part of the divisor = 2048 / 1024 = 2). At this point, the amount by which the accumulated FCW exceeds the integer overflow value (which will be 2 × 1280 minus 2048 = 512) is the fractional part of the divisor. Since the phase value of the entire clock cycle is 1024, the remainder of 512 is half the fractional value. Typically, for any fractional divisor with an integer part I and a fractional part F = x / y, the input clock cycle is quantized into Q segments, and the FCW is selected as (Q + (x / y) / I).

[0031] Those skilled in the art will understand that the binary phase accumulator circuit 10 is shown as a circuit employing logic elements, and that the binary phase accumulator circuit 10 can be configured by software running on a processor. The binary phase accumulator 10 is configured to divide the frequency of the input clock signal by a fractional divisor comprising an integer part I and a fractional part F.

[0032] In the binary phase accumulator circuit 10, the accumulator adder 12 has a first input coupled to the current n-bit phase value output 14 and a second input coupled to the stored FCW indicated at reference numeral 16. As previously described, the value assigned to the stored FCW at reference numeral 16 is selected based on the fractional part of the divisor, which will be used to divide by the frequency of the system clock signal provided by the system clock source 20 on line 18. This system clock source may be provided as part of the binary phase accumulator circuit 10 or may be located outside the binary phase accumulator circuit 10, wherein the system clock signal is received from such an external source on line 18.

[0033] The n-bit output (denoted as SUM) of the accumulator adder 12 on line 22 is coupled to the first input (minuend) of the overflow subtractor 24. The second input (subtrahend) of the overflow subtractor 24 is coupled to the stored integer overflow value (IOV) indicated at reference numeral 26. The value of the IOV stored at reference numeral 26 is selected based on the integer portion of the divisor, which will be used to divide by the frequency of the system clock signal provided by the system clock source 20 on line 18.

[0034] The n-bit SUM output of accumulator adder 12 on line 22 is also coupled to the first input of multiplexer 28. The n-bit DIFFERENCE output of overflow subtractor 24 on line 30 is coupled to the second input of multiplexer 28. The n-bit SUM output of accumulator adder 12 is also coupled to the first input of magnitude comparator 32, and the stored IOV 26 is also coupled to the second input of magnitude comparator 32. The output of magnitude comparator 32 (denoted as CARRY) is coupled to the selection input of multiplexer 28 on line 34. The n-bit output of multiplexer 28 is coupled to the data input of flip-flop 36, which acts as an n-bit phase value register. The clock input of flip-flop 36 is coupled to the system clock signal, which is provided by system clock source 20 on line 18. The output of flip-flop 36 provides the n-bit phase value output 14 of binary phase accumulator circuit 10.

[0035] The accumulator adder 12 in the binary phase accumulator 10 adds the FCW stored at reference numeral 16 to the current n-bit phase value output on line 14, and generates the sum output (SUM) (the new n-bit phase value) of the accumulator adder 12 on line 22. The overflow subtractor 24 subtracts the IOV stored at reference numeral 26 from the SUM on line 22 and generates a DIFFERENCE output on line 30. The magnitude comparator 32 compares the SUM (i.e., the n-bit phase value output + FCW) on line 22 with the IOV, and generates a CARRY signal output on line 34 only if the SUM on line 22 is greater than or equal to the IOV stored at reference numeral 26.

[0036] Since IOV is greater than SUM on line 22, the DIFFERENCE output of the overflow subtractor 24 on line 30 is initially negative. Therefore, the CARRY signal on line 34 will initially be low, causing multiplexer 28 to pass SUM on line 22 to the data input of flip-flop 36. SUM on line 22 will be latched to the output of flip-flop 36 as an n-bit phase value output on the next clock pulse of the system clock signal from system clock source 20 on line 18.

[0037] When SUM on line 22 becomes equal to or greater than IOV stored at reference 26 in the attached diagram, the DIFFERENCE output of the overflow subtractor 24 on line 30 will equal the fractional part of the divisor, which is used to divide by the frequency of the system clock signal on line 18. At this time, the CARRY signal output on line 34 will go high, and the multiplexer 28 will pass the fractional part of the divisor to the data input of flip-flop 36, which is used to divide by the frequency of the system clock signal.

[0038] The fractional part of the divisor will be latched into the output of flip-flop 36 as an n-bit phase value output on the next clock pulse of the system clock signal on line 18 from system clock source 20, and will be used as the transmission n-bit phase value provided according to the present invention.

[0039] Optionally, a flip-flop 38 may be included as a CARRY signal register. The data input of flip-flop 38 is coupled to the output of the magnitude comparator 32, such that the CARRY signal on line 34 is coupled to flip-flop 38. The clock input of flip-flop 38 is coupled to the output of the system clock source 20 on line 18. Flip-flop 38 latches the CARRY signal on line 34 onto the next clock pulse of the system clock signal on line 18. The data output of flip-flop 38 generates an edge signal output on line 40. Those skilled in the art will understand that the edge signal output on line 40, delayed by an n-bit phase value on line 14, can be used as an edge of the synthesized output clock signal. The edge signal indicates that the output of flip-flop 36 is a valid n-bit phase value, meaning the output of flip-flop 36 represents the fractional part of the divisor used for division by the frequency of the system clock signal. The valid n-bit phase value is the delay from the edge of the system clock to the edge of the generated target or output clock.

[0040] See now Figure 2 The schematic diagram illustrates an exemplary circuit 50 according to one aspect of the present invention. Circuit 50 uses circuitry derived from a binary phase accumulator circuit (such as...) Figure 1 The variable delay represented by the n-bit phase value output of the binary phase accumulator circuit 10) is timed by the system clock signal on line 18 in the first clock domain to transmit the n-bit phase value output to the second clock domain, which is out of sync with the system clock signal on line 18 in the first clock domain, based on a known (but not variable per clock cycle) phase offset of the clock edge of the clock signal in the second clock domain relative to the clock edge of the system clock signal on line 18 in the first clock domain.

[0041] Circuit 50 includes a phase and marker signal generator 52 coupled to a system clock signal (in the first clock domain) on line 18 from system clock source 20. Phase and marker signal generator 52 includes a binary phase accumulator circuit, such as... Figure 1 The system clock signal coupled to line 18 is used to generate an n-bit phase value output on line 14 and an edge signal on line 40 in a binary phase accumulator circuit 10. As previously described, the edge signal on line 40 can be used to generate a synthesized target output frequency clock signal by dividing its delayed frequency by the fractional part F, which is stored in a flip-flop 36 on a clock pulse from the system clock signal input, which is asserted. Figure 1 The CARRY signal on line 34 occurs after this. As those skilled in the art will understand, the synthesized target output frequency clock signal generated by the fractional divider circuit will be out of sync with the system clock signal.

[0042] In some embodiments of the invention, the phase and marker signal generator 52 includes both an n-bit phase value output on line 14 and a marker signal output on line 54, the n-bit phase value output being coupled to the input of an n-bit variable phase delay circuit 56, and the marker signal output being coupled to the input of a variable marker delay circuit 64. The marker signal on line 54 is generated periodically every N cycles of the system clock signal on line 18 and asserted within the same period of the system clock signal that generates the edge signal on line 40. The marker signal on line 54 can be used for various purposes; one example is sending a signal to the system to inform the occurrence of a specific edge signal to change the divisor used in the frequency synthesizer included in the system. The marker signal on line 54 can be implemented by any of a variety of different circuits. Figure 2 In the example shown, the phase and marker signal generator 52 uses a clock divider circuit 65 and an AND gate 67 to generate marker signals. The clock divider circuit 65 is coupled to the system clock 20 to receive the system clock signal 18 and includes an output coupled to the AND gate 67. The AND gate 67 is coupled to a binary phase accumulator circuit 10 to receive edge signals on line 40. The clock divider circuit 65 is operable to divide the system clock signal 18 by N. At the AND gate 67, the edge signals on line 40 gate the output of the clock divider circuit 65.

[0043] An n-bit variable phase delay circuit 56 is used to make the n-bit phase value output delay on line 14 variable. The n-bit phase value delay at the output of the n-bit variable phase delay circuit 56 is shown as being coupled in series with an n-bit fixed phase delay circuit 58, which has an output coupled to the data input (D) of an n-bit phase value trigger 60. The n-bit fixed phase delay circuit 58 is not an actual discrete circuit element in the design, but rather represents the inherent delay of the data input to the n-bit phase trigger 60 via the n-bit phase value signal path from the phase and marker signal generator 52. The amount of delay provided by the fixed phase delay circuit 58 represents the inherent distributed delay path in the design. The data output (Q) of the n-bit phase trigger 60 forms an n-bit phase output signal on line 62.

[0044] The tag signal on line 54 is provided to a variable tag delay circuit 64, which delays the tag signal. The delayed tag signal at the output of the variable tag delay circuit 64 is shown as coupled to a fixed tag delay circuit 66, which has an output coupled to the data input (D) of the tag trigger 68. The fixed tag delay circuit 66 is not an actual discrete circuit element in the design, but rather represents the inherent delay along the tag signal path from the phase and tag signal generator 52 to the data input of the tag trigger 68. The amount of delay provided by the fixed tag delay circuit 66 represents the distributed delay path inherent in the design. The data output (Q) of the tag trigger 68 forms a tag output signal on line 70, which is therefore a latched delayed tag output.

[0045] The amount of variable delay provided by the variable marker delay circuit 64 is set to the same amount as the variable delay provided by the n-bit variable phase delay circuit 56. In some embodiments, the delay exhibited by the fixed marker delay circuit 66 is significantly different from the delay exhibited by the fixed phase delay circuit 58, and the values ​​exhibited by the corresponding variable marker delay circuit 64 and the n-bit variable phase delay circuit 56 are preferably set to different amounts for compensation. In a particular embodiment, different phase delay offset AO signals, which will be further described below, may be provided for each of the phase delay path and the marker delay path. The n-bit variable phase delay circuit 56 and the marker delay circuit 64 and the fixed phase delay circuit 58 and the marker delay circuit 66 may be configured as analog delay circuits or as shift register delay circuits known in the art.

[0046] Although the fixed-phase delay circuit 58 and the fixed-mark delay circuit 66 are in Figure 2 The circuit is shown as immediately following the n-bit variable phase delay circuit 56 and the marker delay circuit 64, but those skilled in the art will understand that the fixed delay circuits 58 and 66 represent the distributed delay inherent in their respective circuit paths, and therefore are not specifically before or after the n-bit variable phase delay circuit 56 and the marker delay circuit 64, respectively.

[0047] The amount of delay provided by the n-bit variable phase delay circuit 56 and the variable mark delay circuit 64 is determined as a function of the n-bit phase value output on line 14. The n-bit phase value output on line 14 is coupled to one set of inputs of the multi-bit delay adder 72. The other set of inputs of the multi-bit delay adder 72 is provided by the n-bit phase delay offset AO signal coupled to the multi-bit delay adder on line 74. The n-bit output of the multi-bit delay adder 72 on line 76 is a control input coupled to both the n-bit variable phase delay circuit 56 and the variable mark delay circuit 64 and is used to set the delay time of each of the n-bit variable phase delay circuit 56 and the variable mark delay circuit 64. The phase delay offset AO signal on line 74 is a fixed delay value selected to ensure the effective setting and holding time of the delayed n-bit phase value output, which is coupled to the delay mark signal at the D input of the n-bit phase trigger 60 and the D input of the mark trigger 68. In the multi-bit delay adder 72, the value of the phase delay offset AO signal on line 74 is added to the n-bit phase value output on line 14, and the resulting sum is the control signal controlling the delay of the variable phase delay circuit 56 and the marker delay circuit 64. When the n-bit phase value output on line 14 is zero, which is the minimum possible value, AO sets the minimum delay value to ensure that when the n-bit phase value output on line 14 is zero, the delay (described below) from the edge of the system clock signal on line 18 through circuit 50 to the clock phase trigger 60 and the marker trigger 68 is longer than the total combined delay of the n-bit phase value through the n-bit variable phase delay circuit 56 and the fixed phase delay circuit 58 to the n-bit phase trigger 60, and longer than the total combined delay of the marker signal through the variable marker delay circuit 64 and the fixed marker delay circuit 66 to the marker trigger 68. In circuit design, the value of the phase delay offset AO signal on line 74 is determined by considering the fixed delay in the binary phase accumulator circuit 10, the marker and n-bit phase value output paths in circuit 10, and some set / hold margins. Therefore, the value of the phase delay offset AO signal on line 74 is determined by characterizing the design using circuit 50. The value of AO is held in a register and is initially set using circuit simulation, and adjusted as needed when the actual silicon is received and characterized.

[0048] The system clock signal on line 18, provided by system clock source 20, is coupled to the first input of latch clock delay circuit 78. An edge signal on line 40 identifies system clock edges, where the n-bit phase value and a marker signal are valid, and is coupled to the second input of latch clock delay circuit 78. Latch clock delay circuit 78 delays the edge signal on line 40 to provide a latch clock signal in a second clock domain that is asynchronous with the first clock domain, for transmitting the n-bit phase value (optionally, and the marker signal). The edge signal on line 40 is coupled to one input of AND gate 80 of latch clock delay circuit 78, and the system clock signal on line 18 is coupled to the second input of AND gate 80. AND gate 80 uses the edge signal to gate the system clock signal on line 18. The output of AND gate 80 is coupled to the input of the variable latch clock delay circuit 82 of latch clock delay circuit 78, which is used to delay the output of AND gate 80, and its delay value is set as a function of the n-bit phase value output on line 14, the delay control input of which is coupled to the n-bit phase value output.

[0049] The output of the variable latch clock delay circuit 82 is shown coupled to a fixed latch clock delay circuit 84, which has an output coupled to the clock inputs of the n-bit phase value trigger 60 and the tag trigger 68. The fixed latch clock delay circuit 84 is not an actual discrete circuit element in the design, but rather represents the inherent delay of the latch clock delay signal path from the edge output of the phase and tag signal generator 52 to the clock inputs of the n-bit phase value trigger 60 and the tag trigger 68. The amount of delay provided by the fixed latch clock delay circuit 84 represents the inherent distributed delay path in the design. The variable latch clock delay circuit 82 is configured to provide a latch clock delay longer than each of the variable phase delay circuit 56 and the variable tag delay circuit 64, and has a sufficiently long delay to ensure that when the n-bit phase value is zero, both the delayed n-bit phase value signal output by the fixed phase delay circuit 58 and the delayed tag signal output by the fixed tag delay circuit 66 satisfy the settling time required by the n-bit phase trigger 60 and the tag trigger 68. The delay of the variable latch clock delay circuit 82 is selected as a function of the characteristics of the specific design. The reason for providing the variable latch clock delay circuit 82 in addition to the n-bit variable phase delay circuit 56 is to ensure that the n-bit phase value set and held for latching is the correct n-bit phase value, by providing a delay in both the clock path and the data path leading to the n-bit phase flip-flop 60 and the marker flip-flop 68. This is necessary because, depending on the period of the latch clock output signal 86, the inherent fixed circuit delay in circuit 50, indicated by reference numerals 58, 66, and 84, can be longer than the period of the latch clock output signal 86. In such cases, failure to delay the signals on both the data path and the clock path leading to the n-bit phase flip-flop 60 and the marker flip-flop 68 would result in an incorrect n-bit phase value being latched. Delaying the data path signals and clock path signals arriving at the n-bit phase flip-flop 60 and the marker flip-flop 68 ensures that the correct n-bit phase data is latched in the n-bit phase flip-flop 60, and that the marker signal has not ended before the latch clock output signal 86 reaches the clock input of the marker flip-flop 68.

[0050] The output of the fixed latch clock delay circuit 84 is the output of the latch clock delay circuit 78, forming a latch clock output signal and coupled to the clock inputs of the n-bit phase flip-flop 60 and the marker flip-flop 68. The latch clock output signal on line 86 is in the second clock domain and is generated in response to the edges of the system clock signal on line 18, which is edge-gated, and the corresponding delays provided by the variable output latch clock delay circuit 82 and the fixed output latch clock delay circuit 84. The latch clock output signal on line 86 is out of sync with the system clock signal on line 18.

[0051] See now Figure 3The flowchart illustrates an exemplary method 90 for transmitting data values ​​between circuits timed by asynchronous clock signals according to an aspect of the present invention. The method begins at reference numeral 92 in the figures.

[0052] At reference numeral 94 in the appendix, the system waits in the loop for the edge of the system clock signal. The edge of the system clock signal indicated by the decision at reference numeral 94 generates a new n-bit phase value by accumulating the frequency control word at reference numeral 96. At reference numeral 98, the delay of the new n-bit phase value (optionally, and the marker signal) is set as a function of the value of the new n-bit phase value and a fixed period, optionally derived from the characteristics of the circuit.

[0053] At reference 100 in the attached diagram, it is determined whether the new n-bit phase value is equal to or greater than the integer overflow value. If not, the method returns to reference 94 in the attached diagram, where the system waits in the loop for another system clock edge.

[0054] If at point 100 in the attached diagram, the new n-bit phase value is determined to be equal to or greater than the integer overflow value ( Figure 1 If the method proceeds to reference numeral 26, then proceeds to reference numeral 102, where an edge signal is generated. The edge signal is generated to indicate that the n-bit phase value output is a valid n-bit phase value. Then, the method proceeds to reference numeral 104, where the transmitted n-bit phase value is set to be equal to the new n-bit phase value minus the integer overflow value.

[0055] At reference numeral 106 in the attached diagram, a latched clock output signal is generated in response to an edge signal and by latching a clock delay from the edge delay of the system clock (e.g., via output clock delay circuit 78), the delay of which is equal to the transmission of n-bit phase values ​​and a fixed latched clock delay (e.g., via...). Figure 2The variable output latch clock delay circuit 82 and the fixed output latch clock delay circuit 84 are connected in series, with the fixed latch clock delay optionally derived from the characteristics of the circuit. The combination of the variable output latch clock delay circuit 82 and the fixed output latch clock delay circuit 84 is out of sync with the system clock edge. At reference numeral 108, the latch clock output signal is used to latch the transmission of n-bit phase values ​​as an n-bit phase output signal. At reference numeral 110, a marker signal can optionally be generated every N system clock cycles in sync with the edge signal. In this optional case, the system counts system clock cycles, and a marker signal is generated whenever N system clock cycles occur in sync with the edge signal generated at reference numeral 102. At optional reference numeral 112, a latch clock signal delayed by the out-of-sync clock delay is used to latch the optional marker signal if it has been generated. The method then returns to reference numeral 94 to wait for another system clock edge. Those skilled in the art will understand that, in embodiments of the present invention, the method returns to reference numeral 94 after reference numeral 108, which does not generate a marker signal as indicated by the dashed arrow.

[0056] The circuitry required by this invention is less than that required by solutions that recreate phase information, for example, by replicating the binary phase accumulator circuit 10 in the output clock domain. Such solutions would also require additional synchronization circuitry. Compared to such alternative solutions, this invention saves power and area / cost.

[0057] While embodiments and applications of the invention have been shown and described, it will be apparent to those skilled in the art that further modifications can be made without departing from the inventive concept herein. Therefore, the invention is not limited except in the spirit of the appended claims.

Claims

1. A circuit for transmitting n-bit phase values ​​between circuits timed by asynchronous clock signals, the circuit comprising: Input, the input being used for the system clock signal; A phase and marker signal generator coupled to the input for the system clock signal, the phase and marker signal generator including a binary phase accumulator circuit configured to generate an n-bit phase value output, and an edge signal configured to indicate that the n-bit phase value output is a valid n-bit phase value output; A latching clock delay circuit having a first input coupled to an input system clock signal, a second input coupled to receive the edge signals of the phase and marker signal generator, and an output; An n-bit variable phase delay circuit, the n-bit variable phase delay circuit having an input, a control input and an output, the input being coupled to the n-bit phase value output of the phase and marker signal generator; A multi-bit delay adder having a first input coupled to the n-bit phase value output of the phase and marker signal generator, a second input coupled to the n-bit phase delay offset signal, and an output coupled to the control input of the n-bit variable phase delay circuit; as well as An n-bit phase flip-flop has a data input coupled to the output of the n-bit variable phase delay circuit, a clock input coupled to the output of the latch clock delay circuit, and a phase output.

2. The circuit according to claim 1, wherein the latching clock delay circuit comprises: A gate having a first input coupled to the input system clock signal, a second input coupled to receive the edge signal of the phase and marker signal generator, and an output; as well as A variable latch clock delay circuit having an input coupled to the output of the gate, and an output.

3. The circuit according to claim 2, wherein: The gate is an AND gate; and The variable latch clock delay circuit includes a control input coupled to the n-bit phase value output of the phase and marker signal generator.

4. The circuit of claim 1, wherein the binary phase accumulator circuit in the phase and marker signal generator is configured as follows: The frequency control word (FCW) value is accumulated at the edge of each system clock signal; The accumulated FCW value is output as the n-bit phase value after each system clock signal edge; When the accumulated FCW value reaches an integer overflow value, at the edge of the subsequent system clock signal, the generated n-bit phase value output is modified to be equal to the integer overflow value minus the immediately preceding value of the n-bit phase value output; and The edge signal is output at the edge of the subsequent system clock signal.

5. The circuit according to claim 1, further comprising: The phase and the mark output of the mark signal generator; A variable mark delay circuit having an input, a control input, and an output, the input being coupled to the mark output of the phase and mark signal generator, and the control input being coupled to the output of the multi-bit delay adder; as well as A tag trigger has a data input coupled to the output of the variable tag delay circuit, a clock input coupled to the latch clock delay circuit, and a latch tag output.

6. The circuit of claim 5, wherein the phase and mark signal generator is configured to generate a mark signal at the mark output every N system clock signal cycles in the same system clock signal cycle as the edge signal of the phase and mark signal generator.

7. A method for transmitting an n-bit phase value between a circuit that is edge-timed by a system clock signal and a circuit that is edge-timed by a latched clock output signal, wherein the latched clock output signal is out of sync with the system clock signal, the method comprising: A new n-bit phase value is generated by accumulating a frequency control word at the edge in response to the system clock signal; The delay of the new n-bit phase value is set as a function of the new n-bit phase value and a fixed period; When the n-bit phase value is equal to or exceeds the integer overflow value: Generate edge signals; The transmitted n-bit phase value is set to be equal to the new n-bit phase value exceeding the integer overflow value; as well as A latched clock output signal is generated in response to the generated edge signal and from the edge delay latched clock delay of the system clock signal, the latched clock delay being a function of the transmitted n-bit phase value and the fixed latched clock delay.

8. The method of claim 7, wherein the latch clock delay is the sum of the transmitted n-bit phase value and the fixed latch clock delay.

9. The method of claim 7, wherein the fixed latch clock delay is derived from circuit characteristics.

10. The method of claim 7, wherein the fixed period is derived from the characteristics of the circuit of the edge timing of the system clock signal.

11. The method of claim 7, wherein the fixed latch clock delay includes a delay derived from the characteristics of the circuitry of the edge timing of the system clock signal.

12. The method of claim 7, wherein the latch clock delay is set to be greater than the delay of the new n-bit phase value.

13. The method of claim 7 further includes generating a marker signal every N system clock edges.

14. The method of claim 13, wherein generating the marker signal every N system clock edges includes generating the marker signal synchronously with the edge signal.

15. The method of claim 13, further comprising latching the marker signal.

16. The method of claim 15, wherein latching the marker signal comprises latching the marker signal using a generated latch clock output signal.

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