Methods of forming semiconductor devices and semiconductor structures

Abstract

Embodiments of the present application provide a method of forming a semiconductor device comprising: forming an N-well and a P-well in a substrate; depositing a first layer having silicon over the N-well and the P-well; depositing a first dielectric layer over the first layer; forming a resist pattern over the first dielectric layer, the resist pattern providing an opening located directly over the N-well; etching the first dielectric layer and the first layer through the opening, leaving a first portion of the first layer located over the N-well; removing the resist pattern; and epitaxially growing a second layer having silicon germanium (SiGe) over the first portion of the first layer. Epitaxially growing the second layer comprises the steps of (a) performing a bake process, (b) depositing a silicon seed layer, and (c) depositing a SiGe layer over the silicon seed layer, wherein steps (a), (b), and (c) are performed at about the same temperature. According to other embodiments of the present application, a semiconductor structure is also provided.

Description

Technical Field

[0001] Embodiments of this application relate to methods for forming semiconductor devices and semiconductor structures. Background Technology

[0002] The electronics industry has experienced a growing demand for smaller and faster electronic devices capable of simultaneously supporting a greater number of increasingly complex and sophisticated functions. To meet these demands, there is a persistent trend in the integrated circuit (IC) industry towards manufacturing low-cost, high-performance, and low-power ICs. To date, these goals have been largely achieved by reducing IC size (e.g., the smallest possible IC feature size), thereby increasing production efficiency and reducing associated costs. However, this scaling down also increases the complexity of IC manufacturing processes. Therefore, continued advancements in IC devices and their performance require similar progress in IC manufacturing processes and technologies.

[0003] FinFET devices have been introduced to increase gate-channel connectivity, reduce off-state current, and minimize short-channel effects (SCE) on planar transistors. However, as devices continue to shrink in scale, conventional FinFETs are approaching their performance limits. For example, the extremely compact gate size and small device volume make doping and strain engineering very challenging for FinFET devices in terms of performance. Improvements in FinFET fabrication are urgently needed. Summary of the Invention

[0004] According to one embodiment of this application, a method for forming a semiconductor device is provided, comprising: forming an N-well and a P-well in a substrate; depositing a first layer having silicon over the N-well and the P-well; depositing a first dielectric layer over the first layer; forming a resist pattern over the first dielectric layer, the resist pattern providing an opening directly above the N-well; etching the first dielectric layer and the first layer through the opening, leaving a first portion of the first layer above the N-well; removing the resist pattern; and epitaxially growing a second layer having silicon and germanium over the first portion of the first layer, wherein epitaxially growing the second layer comprises the steps of: (a) performing a baking process, (b) depositing a silicon seed layer, and (c) depositing a silicon and germanium layer over the silicon seed layer, wherein steps (a), (b), and (c) are performed at approximately the same temperature.

[0005] According to another embodiment of this application, a method for forming a semiconductor device is provided, comprising: providing a substrate; depositing a silicon layer over the substrate; etching an alignment trench into the silicon layer; depositing a first oxide layer over the silicon layer and in the alignment trench; forming an etch mask over the first oxide layer, wherein the etch mask covers the alignment trench and has an opening directly above a first portion of the silicon layer; etching the first oxide layer and the first portion of the silicon layer through the opening to form a first trench; removing the etch mask; and epitaxially growing a second layer having silicon germanium in the first trench, wherein epitaxially growing the second layer comprises the steps of: (a) performing a baking process, (b) depositing a silicon seed layer, and (c) depositing a silicon germanium layer on the silicon seed layer, wherein steps (a), (b), and (c) are performed at approximately the same temperature.

[0006] According to another embodiment of this application, a semiconductor structure is provided, comprising: a substrate; a first fin extending from the substrate, wherein the first fin includes a bottom and an upper portion above the bottom, the upper portion and the bottom comprising different materials, and the upper portion comprising silicon germanium; and an alignment mark located above the substrate and having one or more dielectric layers, wherein the top surface of the first fin is substantially coplanar with the top surface of the alignment mark.

[0007] Embodiments of this application relate to a method for forming a full strain channel. Attached Figure Description

[0008] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0009] Figure 1A , Figure 1B ,and Figure 1C A flowchart illustrating a method for forming a semiconductor device according to various aspects of the present invention is shown;

[0010] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 6A , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 14A , Figure 14B , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 ,and Figure 23 It is shown in accordance with Figures 1A-1C A cross-sectional view of a portion of a semiconductor device according to some embodiments, taken during an intermediate step in the manufacturing process of an embodiment of the method.

[0011] Figure 17A A top view of a portion of a semiconductor device according to some embodiments is shown;

[0012] Figure 21 and Figure 22 A perspective view of a portion of a semiconductor device according to some embodiments is shown. Detailed Implementation

[0013] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or structures discussed.

[0014] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to readily describe the relationship between one element or component and another (or other) element or component as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly. Moreover, when numbers or ranges of numbers are described using terms such as “approximately” or “about,” based on the specific techniques disclosed herein and the knowledge of those skilled in the art, the term covers numbers within certain variations (e.g., + / - 10% or other variations) of the described number, unless otherwise stated. For example, the term “approximately 5 nm” may cover a size range from 4.5 nm to 5.5 nm, from 4.0 nm to 5.0 nm, etc.

[0015] This application generally relates to semiconductor structures and manufacturing processes, and more specifically to CMOS (Complementary Metal-Oxide-Semiconductor) devices having p-channel FinFET transistors and n-channel FinFET transistors. The object of this invention is to provide a method for forming p-channel and n-channel fins on the same substrate, wherein the n-channel fins comprise a first semiconductor material and the p-channel fins comprise a second semiconductor material having a higher charge carrier (e.g., hole) mobility than the first semiconductor material. In embodiments of the invention, the first semiconductor material is crystalline silicon (Si), and the second semiconductor material is a silicon-germanium alloy (SiGe). In one embodiment, the p-channel fins are used to form a p-type FinFET, and the n-channel fins are used to form an n-type FinFET. Compared to methods that use the same material in the channels of both the n-type and p-type FinFETs, using p-channel fins can further improve the performance of the p-type FinFET.

[0016] Embodiments of the present invention also improve the epitaxial growth of semiconductor materials for p-channel fins through isothermal processes. For example, embodiments of the present invention grow silicon-germanium alloys by: (a) performing an H2 baking process on the workpiece; (b) depositing a silicon seed layer on the workpiece; and (c) depositing a SiGe layer on the silicon seed layer, wherein steps (a), (b), and (c) are performed at approximately the same temperature. In one example, the temperature at which steps (a), (b), and (c) are performed can vary by up to + / - 10°C. In one embodiment, steps (a), (b), and (c) are performed at temperatures in the range of approximately 650°C to 750°C. The isothermal process simplifies the overall process because there is no need to raise and lower the temperature for individual steps (a), (b), and (c), thereby reducing manufacturing time. Furthermore, the SiGe layer grown under isothermal processes has improved quality and reduced defects across the entire wafer. For example, compared to SiGe layers formed when H2 baking and SiGe layer deposition are performed at different temperatures (e.g., when H2 baking is performed at 900°C to 1000°C and SiGe layer deposition is performed at 650°C to 750°C), SiGe layers grown under isothermal processes have a substantially flat top surface and a more uniform thickness of the SiGe layer across the entire wafer. This is particularly advantageous when the wafer provides Si and SiGe fin channels for devices of different sizes (e.g., SRAM (1 or 2 fins, small channel length devices), TCD (three-fin devices), and IO (input / output, multi-fin, large channel length devices)). In other methods, the thickness of the SiGe layer varies considerably across device regions of different sizes, for example, from 10 nm to 30 nm. Using the method of this invention, the thickness variation across the entire wafer can be reduced to less than 10 nm, for example, less than 8 nm. Uniform thickness can improve the performance of subsequent processes such as chemical mechanical planarization (or polishing) (CMP). Those skilled in the art will understand that they can readily use this invention as a basis to design or modify other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein.

[0017] Figure 1A , Figure 1B ,and Figure 1C This is a flowchart of a method 10 for manufacturing a semiconductor device (or semiconductor structure) 100 according to various aspects of the present invention. Other processes are contemplated by the present invention. Other operations may be provided before, during, and after method 10, and some of the described operations may be moved, replaced, or removed for other embodiments of method 10.

[0018] The following is combined Figures 2 to 23 To describe method 10, Figures 2 to 23Various views of a semiconductor device 100 at various steps of the manufacturing process according to method 10 are shown according to some embodiments. In some embodiments, device 100 is part of an IC chip, a system-on-a-chip (SoC), or a portion thereof, which includes various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs or pFETs), n-type field-effect transistors (NFETs or nFETs), FinFETs, nanosheet FETs, nanowire FETs, other types of multi-gate FETs, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, memory devices, other suitable components, or combinations thereof. For clarity, simplified representations have been provided. Figures 2 to 23 This is to better understand the inventive concept of the present invention. Other features may be added to device 100, and some of the features described below may be replaced, modified, or removed in other embodiments of device 100.

[0019] In operation 12, method 10 ( Figure 1A A substrate 102 is provided or is provided, for example Figure 2 As shown. In the depicted embodiment, substrate 102 is a silicon substrate, such as a silicon wafer having crystalline silicon. Alternatively, substrate 102 may include another elemental semiconductor, such as germanium; compound semiconductors including silicon carbide, gallium nitride, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium phosphide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and gallium indium arsenide phosphide; or combinations thereof.

[0020] In operation 14, method 10 ( Figure 1A Alignment marks 110 are formed in substrate 102. Figure 5 This may involve multiple processes, such as... Figures 2-5 As shown. Figure 2 As shown, dielectric layer 104 is deposited over substrate 102, and dielectric layer 106 is deposited over dielectric layer 104. In one embodiment, dielectric layer 104 comprises an oxide (e.g., SiO2), while dielectric layer 106 comprises a nitride, such as silicon nitride (Si3N4). Figure 3As shown, trench 108 is etched into dielectric layers 104, 106 and substrate 102. For example, method 10 can use a photolithography process to form a resist pattern, which includes: forming a resist layer over device 100 (e.g., by spin coating), performing a pre-exposure baking process, performing an exposure process using a photomask, performing a post-exposure baking process, and developing the exposed resist layer in a developer solution. Alternatively, the exposure process can be performed or replaced by other methods such as maskless lithography, electron beam writing, ion beam writing, or combinations thereof. After development, the resist layer becomes a resist pattern that provides openings corresponding to trench 108. The dielectric layers 104, 106 and substrate 102 are then etched through the resist pattern to form trench 108. The resist pattern is then removed, for example, using resist stripping. Figure 4 As shown, for example, an etching process that selectively etches the material of dielectric layer 106 is used to remove dielectric layer 106. Figure 5 As shown, a dielectric layer fills the trench 108 and forms alignment marks 110. In one embodiment, the dielectric layer forming the alignment marks 110 comprises an oxide and may be the same as or substantially the same as the material in the dielectric layer 104.

[0021] In operation 16, method 10 ( Figure 1A N-well 116 and P-well 118 are formed in the substrate 102. Figure 6 This may involve multiple processes. For example, method 10 may form an injection mask 112 over the dielectric layer 104 and alignment marks 110, as... Figure 5 As shown. The implantation mask 112 provides an opening 114 corresponding to a region of substrate 102 where an N-well will be formed. The implantation mask 112 may be a resist pattern formed using a photolithography process as described above. In one embodiment, alignment marks 110 are used to determine the location for forming the opening 114 during the photolithography process. For example, the opening 114 is formed at a distance from the alignment marks 110. Ion implantation can then be used to form an n-type region (or N-well) 116 in substrate 102. In some embodiments, the N-well 116 is substantially aligned with the opening 114. According to some embodiments, the n-type dopant may include arsenic (As), antimony (Sb), or phosphorus (P). According to some embodiments, the concentration of the n-type dopant in the N-well 116 may be approximately 5E16 atoms / cm³. 3 Approximately 1E19 atoms / cm 3 Within a certain range. As an example and not a limitation, the N-well 116 can have a depth (e.g., in the z-direction) of about 100 nm to about 500 nm. However, the width (e.g., along the x-direction) and length (e.g., along the y-direction) can vary. Figure 5The page (of the N-well) can vary depending on the device (e.g., logic, static random access memory (SRAM), etc.). After forming the N-well 116, the injection mask 112 can be removed.

[0022] In one embodiment, a similar process involving patterning a photoresist layer into an injection mask can be used to form a p-type region (P-well) 118 in the substrate 102 adjacent to the N-well 116, such as... Figure 6 As shown. In some embodiments, the P-well 118 can be created using an ion implantation process employing a p-type dopant such as boron (B). By way of example and not limitation, the P-well 118 can have a density of approximately 5E16 atoms / cm². 3 Approximately 1E19 atoms / cm 3 Range of dopant concentrations. In some embodiments, an annealing step is performed to activate the dopants in N-well 116 and P-well 118 (e.g., to move the dopants from interstitial sites to silicon lattice sites) and repair any silicon crystal damage that occurred during the ion implantation step. According to some embodiments, dielectric layer 104 is removed after dopant activation annealing, but alignment marks 110 are left in substrate 102. For example, dielectric layer 104 can be removed by chemical mechanical planarization (CMP) and / or etching processes.

[0023] In some embodiments, the P-well 118 is formed at a distance from the alignment mark 110, for example... Figure 6 As shown. In some embodiments, the P-well 118 is configured such that the alignment mark 110 is located within the P-well 118, for example... Figure 6A As shown. In the following discussion of method 10, Figure 6 The described embodiments are used as examples. However, the same discussion can be applied to... Figure 6A The described embodiments.

[0024] In operation 18, method 10 ( Figure 1A A semiconductor layer 120 is formed over the N-well 116, the P-well 118, and the alignment mark 110, as shown below. Figure 7 As shown. For example, a silicon layer can be epitaxially grown as a semiconductor layer 120 directly above substrate 102. For example, silicon can be epitaxially grown using a precursor such as silane (SiH4), silicon tetrachloride (SiCl4), trichlorosilane (TCS), or dichlorosilane (SiH2Cl2 or DSC) using a chemical vapor deposition (CVD) process. In some embodiments, semiconductor layer 120 can have a thickness in the range of about 30 nm to about 100 nm.

[0025] In operation 20, method 10 ( Figure 1AAlignment trenches 122 are formed in semiconductor layer 120. In one embodiment, alignment trenches 122 are formed to overlap (e.g., directly above) alignment marks 110, for example... Figure 8 As shown. Alternatively, alignment trench 122 can be formed so as not to overlap with alignment mark 110. As will be discussed, another alignment mark will be formed in alignment trench 122. Alignment trench 122 and the alignment mark therein can facilitate the fabrication of a fully strained channel in semiconductor layer 120. Alignment trench 122 can be formed using the same or similar methods as those discussed above for forming alignment trench 108 (e.g., using photolithography and etching processes).

[0026] In operation 22, method 10 ( Figure 1A A dielectric layer 124 is deposited over the semiconductor layer 120 and in the alignment trench 122, for example... Figure 9 As shown. For example, dielectric layer 124 may include oxides such as silicon dioxide (SiO2). Figure 9 In the depicted embodiment, dielectric layer 124 is deposited over the sidewalls and bottom surface of alignment trench 122, but does not completely fill alignment trench 122. In an alternative embodiment, dielectric layer 124 completely fills alignment trench 122.

[0027] In operation 24, method 10 ( Figure 1A An etch mask layer 126 is formed over the dielectric layer 124. In embodiments where the dielectric layer 124 partially fills the alignment trench 122, the etch mask layer 126 fills the remaining portion of the alignment trench 122, for example... Figure 10 As shown. In embodiments where the alternative dielectric layer 124 completely fills the alignment trench 122, the etch mask layer 126 is not filled into the alignment trench 122 (not shown). In one embodiment, the etch mask layer 126 may comprise a bottom anti-reflective coating (BARC) material.

[0028] In operation 26, method 10 ( Figure 1A A resist pattern 128 is formed over the etch mask layer 126, for example... Figure 11As shown. The resist pattern 128 provides an opening 130 that exposes the area of ​​the etch mask layer 126 directly above the N-well 116. In one embodiment, the opening 130 is aligned with the N-well 116 using alignment marks 110 and alignment trenches 122 (and the dielectric layer 124 therein). The resist pattern 128 can be formed using a photolithography process that includes: spin-coating a resist layer over the device 100, baking the resist layer, exposing the resist layer using a photolithographic mask, performing post-exposure baking, and developing the exposed resist layer in a developer solution. Alternatively, the exposure process can be performed or replaced by other methods such as maskless photolithography, electron beam writing, ion beam writing, or combinations thereof. After development, the resist layer becomes the resist pattern 128.

[0029] In operation 28, method 10 ( Figure 1B Operation 28 etches the etch mask layer 126, dielectric layer 124, and semiconductor layer 120 through opening 130 to form a trench 132 in the semiconductor layer 120. Operation 28 may use one or more dry etching processes to etch the etch mask layer 126, dielectric layer 124, and semiconductor layer 120 such that the shape of the trench 132 substantially matches the opening 130. In one embodiment, after partially etching the semiconductor layer 120, a thin portion 120a of the semiconductor layer 120 is left at the bottom of the trench 132, for example... Figure 12 As shown. This can be achieved through a timed dry etching process. In an alternative embodiment, the semiconductor layer 120 is completely etched, thereby exposing the N-well 116 (not shown) in the trench 132. Figure 12 In the depicted embodiments, portion 120a may have a thickness ranging from about 0 nm to about 10 nm, for example, from about 1 nm to about 5 nm. After the etching process is completed, the resist pattern 128 is removed, for example, by using resist stripping, wet cleaning, or other suitable methods.

[0030] In operation 30, method 10 ( Figure 1B For example, cleaning, etching, or other suitable methods can be used to remove the etch mask layer 126. In embodiments where the etch mask layer 126 partially fills the trench 122, the etch mask layer 126 is also removed from the trench 122, for example... Figure 13As shown. After removing the etch mask layer 126, the dielectric layer 124 still covers the semiconductor layer 120, except for the surface of the semiconductor layer 120 exposed in the trench 132. Operation 30 can then perform a cleaning process on the surface of the semiconductor layer 120 exposed in the trench 132. For example, the cleaning process can use a mixture of nitrogen trifluoride (NF3) and ammonia (NH3) to apply plasma etching. Plasma etching can also include inert gases such as argon (Ar), helium (He), hydrogen (H2), nitrogen (N2), or combinations thereof. The cleaning process can also include an annealing process. For example, the annealing process can be performed at a temperature of about 30°C to about 200°C, for example, from about 60°C to about 200°C. The cleaning process cleans the surface of the semiconductor layer 120 and prepares it for subsequent epitaxial growth.

[0031] In operation 32, method 10 ( Figure 1B A semiconductor layer 134 is epitaxially grown in trench 132, for example... Figure 14As shown. In one embodiment, the material of semiconductor layer 134 has a higher charge carrier (e.g., hole) mobility than the material of semiconductor layer 120. For example, semiconductor layer 134 comprises silicon germanium, while semiconductor layer 120 comprises silicon. Semiconductor layer 134 provides strained channel material for a p-type FinFET. Semiconductor layer 134 is not grown on the surface of dielectric layer 124. In this embodiment, operation 32 comprises three steps (or sub-operations): a baking step, a seed layer deposition step, and a main epitaxial growth step to form an epitaxial layer on the seed layer. Furthermore, operation 32 is an isothermal operation. In other words, operation 32 performs the three sub-operations at approximately the same temperature, taking into account any temperature variations caused by heating equipment or the process chamber. For example, the temperature used for the three sub-operations (recipe temperature) may be set to the same value in the process recipe, but the actual temperature at which the three sub-operations are performed (actual temperature) may vary depending on the equipment used. In some embodiments, the actual temperature throughout the three sub-operations may vary up to + / - 10°C. In some embodiments, the actual temperature throughout the three sub-operations may vary up to + / - 5°C. In some embodiments, the actual temperature throughout the three sub-operations can vary by up to + / - 2% of the formulation temperature. All of these can be considered within the meaning of the isothermal process of the present invention. In another embodiment, operation 32 is an isobaric process. In other words, operation 32 performs the three sub-operations at approximately the same pressure, taking into account any pressure variations caused by the process chamber. For example, operation 32 may perform the three sub-operations at a nominal pressure of 10 torr or another suitable pressure. In this embodiment, operation 32 epitaxially grows a silicon-germanium layer 134 over a silicon seed layer 134a. For a further embodiment, the three sub-operations (baking, Si seed layer deposition, and SiGe epitaxial growth) are performed in a temperature range of about 650°C to about 750°C (formulation temperature).

[0032] There are many advantages to using an isothermal process in operation 32. For example, operation 32 is more efficient than some methods that use different temperatures for different steps. Because the temperature is the same throughout operation 32, there is no need to raise and lower the temperature in the process chamber, thus reducing manufacturing time. For example, if the baking step uses a higher temperature than the seed layer deposition step or the epitaxial growth step, a cooling time must be included after the baking step, which will undesirably delay manufacturing. Another advantage is that using an isothermal process can improve the quality of the semiconductor layer 134. This will be referred to with reference to an enlarged cross-sectional view of device 100. Figure 14B Further discussion is needed.

[0033] refer to Figure 14In this embodiment, semiconductor layer 134 is grown such that its top surface is higher than the top surface of semiconductor layer 120, but flush with or lower than the top surface of dielectric layer 124. Due to the isothermal process, the top surface of semiconductor layer 134 is substantially flat. In some experiments, the top surface of semiconductor layer 134 can vary by about 10 nm or less in different regions of the wafer, for example, 8 nm or less, or 5 nm or less, and in some cases, the variation across the entire wafer is only about 1 nm to about 2 nm. In other words, in some embodiments, the top surface of semiconductor layer 134 can have very high uniformity across the entire wafer. For example, in different device regions on the same wafer (e.g., device regions such as SRAM regions for smaller transistors, and device regions such as I / O regions or TCD regions for larger transistors), semiconductor layer 134 has a substantially uniform and coplanar top surface. This greatly reduces the difficulties in the subsequent chemical mechanical planarization (CMP) process, which will be discussed later. This also reduces the time required for the CMP process because less material needs to be polished compared to methods with greater inhomogeneity on the top surface of semiconductor layer 134.

[0034] In some embodiments, the edges of the dielectric layer 124 are not perfectly aligned with the trench 132 during the growth of the semiconductor layer 134. For example, this may occur during a process where a cleaning plasma (e.g., NF3 and NH3) slightly etches the dielectric layer 124 (e.g., containing silicon dioxide) to clean the trench 132. Consequently, the apex of the dielectric layer 124 may become rounded, and the edges of the dielectric layer 124 may recede from the edges of the trench 132, for example… Figure 14 As shown. In such an embodiment, semiconductor layer 134 may extend laterally over semiconductor layer 120 by a width W. This portion of semiconductor layer 134 is referred to as extension portion 134b. In some embodiments, the width W is in the range of about 5 nm to about 20 nm. The slope θ of the top surface of extension portion 134b (i.e., the angle between the top surface of extension portion 134b and the top surface of semiconductor layer 120) is in the range of 30 degrees or less, for example, in some embodiments in the range of about 5 degrees to about 20 degrees. The slope θ is smaller compared to other methods that do not use the disclosed isothermal process.

[0035] In one embodiment, the baking step of operation 32 is performed in an H2 environment at a pressure of about 10 to 600 torr for about 30 to 120 seconds. Baking in an H2 environment allows for control of the reflow of the semiconductor layer 120, reduces the surface roughness of the trench 132, and removes oxide residues from the surface of the trench 132, thereby improving the quality of the subsequently deposited seed layer and epitaxial layer. In alternative embodiments, other gases, such as argon (Ar), nitrogen (N2), helium (He), or combinations thereof, may be used additionally or alternatively. The baking step is performed in a temperature range of about 650°C to about 750°C, the same temperature as the seed layer deposition and epitaxial growth steps. This temperature is significantly lower than in other methods. For example, some methods perform the baking process in a temperature range of 900°C to 1000°C, followed by subsequent processes at lower temperatures (e.g., more than 20% lower). In this invention, the lower thermal budget of the baking step and the isothermal process result in a better profile for the trench 132 for epitaxial growth and contribute to the uniformity of the top surface of the semiconductor layer 134, the benefits of which have been discussed above.

[0036] In one embodiment, the seed layer deposition step of operation 32 can be performed at a pressure of about 5 to about 50 torr, and the seed layer 134a can be deposited on the surface of trench 132 with a thickness of about 2 nm to about 10 nm. In embodiments where the semiconductor layer 120 is partially etched during the formation of trench 132, the seed layer 134a is deposited on the surface of the semiconductor layer 120 exposed in the bottom and sidewalls of trench 132, for example... Figure 14 As shown. In an embodiment where the semiconductor layer 120 is completely etched during the formation of trench 132, a seed layer 134a is deposited on the surface of the semiconductor layer 116 at the bottom of trench 132 and on the surface of the semiconductor layer 120 exposed in the sidewalls of trench 132, for example... Figure 14AAs shown. In some embodiments, the seed layer 134a can be deposited for about 3 seconds to about 10 seconds, depending on the deposition rate of the seed layer and the desired thickness of the seed layer. The seed layer 134a can be used to control the rounding of the corners of the semiconductor layer 134. In some embodiments, the seed layer 134a can be a Si layer, a Si:C layer, a SiGe layer, or a combination thereof. For example, in some embodiments, the seed layer 134a can be Si / Si:C / SiGe, Si / SiGe, or Si:C / SiGe. Therefore, according to some embodiments, the atomic percentage (atomic %) of the carbon dopant in Si:C can be about 0.01 atomic % to about 2 atomic %. The seed layer 134a can be deposited by CVD or other suitable methods (e.g., ALD). For example, the Si seed layer 134a can be deposited using the precursor gas SiH4 and / or DCS and the carrier gas H2 or N2. For example, the SiGe seed layer 134a can be deposited using precursor gases SiH4, silane (Si2H6), germanane (GeH4), and hydrochloric acid (HCl), as well as carrier gases H2, N2, He, or Ar.

[0037] In the main epitaxial growth step of operation 32, an epitaxial layer 134 is formed on the seed layer 134a to fill the trench 132. In one embodiment, the epitaxial layer 134 comprises SiGe and can be grown using a precursor gas (e.g., SiH4, Si2H6, SiH2Cl2, GeH4, and / or HCl) and a carrier gas (e.g., H2, N2, Ar), or a combination thereof. The epitaxial growth of SiGe can be performed at a pressure of about 5 to about 50 torr. Depending on the rate of epitaxial growth and the depth of the trench 132, the epitaxial growth can be performed for about 80 seconds to about 200 seconds. In one embodiment, the growth control (e.g., timing) of the epitaxial layer 134 is such that the top surface of the epitaxial layer 134 is above the top surface of the semiconductor layer 120, but flush with or below the top surface of the dielectric layer 124. In some embodiments, the Ge concentration, in atomic percentage (atomic %), is constant over the entire thickness of the SiGe epitaxial layer 134 (e.g., along the z-direction) and may range from about 20 atomic % to about 40 atomic %. In some embodiments, the SiGe epitaxial layer 134 may include a first sublayer having a Ge concentration of up to about 5 atomic %, and a second sublayer having a constant Ge concentration ranging from about 20 atomic % to about 40 atomic % over the entire thickness of the SiGe epitaxial layer.

[0038] In operation 34, method 10 ( Figure 1B Another dielectric layer 136 is deposited over the dielectric layer 124 and the semiconductor layer 134, for example... Figure 15As shown. In one embodiment, dielectric layer 136 comprises an oxide such as silicon dioxide. In one embodiment, both dielectric layers 124 and 136 comprise an oxide such as silicon dioxide. The presence of dielectric layer 136 facilitates the removal of dielectric layer 124 by a CMP process. Otherwise, because dielectric layer 124 is relatively thin (e.g., in some embodiments, the thickness of dielectric layer 124 may be about 10 nm to about 15 nm), it is not easily removed by a CMP process without damaging semiconductor layers 120 and 134. Dielectric layer 136 can be deposited using CVD or other suitable processes. In some embodiments, dielectric layer 136 can be deposited with a thickness ranging from about 5 nm to about 20 nm. Figure 15 In the depicted embodiment, since the dielectric layer 124 does not completely fill the trench 122, the dielectric layer 136 is deposited to fill the remaining portion of the trench 122.

[0039] In operation 36, method 10 ( Figure 1B Perform CMP process to remove dielectric layers 136 and 124 from device 100, for example Figure 16 As shown. In one embodiment, the CMP process is designed to be selective for the materials of dielectric layers 136 and 124. For example, the CMP process can use a paste that is selective for the materials of dielectric layers 136 and 124 but not selective for the materials of semiconductor layers 134 and 120. In this embodiment, since the top surface of semiconductor layer 134 is substantially flat and does not protrude above dielectric layer 124, dielectric layers 136 and 124 can be completely removed from the surface of semiconductor layer 120 by the CMP process without leaving any dielectric residue on the surface of semiconductor layer 120. In some embodiments, the CMP process may leave negligible dielectric residue on the surface of semiconductor layer 120. As discussed above, in methods that do not use the isothermal process of the present invention, the top surface of semiconductor layer 134 may protrude above dielectric layer 124 and may have relatively large inhomogeneities in different device regions of the wafer. Therefore, after CMP processes have been performed to remove dielectric layers 136 and 124, a significant amount of dielectric residue (e.g., 1 nm or 2 nm thick) may remain on some areas of the top surfaces of semiconductor layers 134 and 120. Such a large amount of dielectric residue could lead to defects or defective devices in subsequent manufacturing processes. In contrast, in this invention, dielectric layers 136 and 124 can be completely removed from the top surfaces of semiconductor layers 134 and 120, and any dielectric residue on the top surfaces of semiconductor layers 134 and 120 can be ignored (e.g., if present, the dielectric residue is less than about 0.5 nm to about 0.9 nm in some cases). Figure 16As depicted, portions of dielectric layers 136 and 124 remain in trench 122 after the CMP process, thereby forming a dielectric alignment mark 138 in semiconductor layer 120. In some embodiments, when dielectric layer 124 completely fills trench 122 in operation 22, alignment mark 138 includes only dielectric layer 124 and excludes dielectric layer 136. This alignment mark 138 can be used to align fins made of semiconductor layers 134 and 120. In this embodiment, alignment marks 138 and 110 can be considered as different portions of a larger alignment mark.

[0040] In operation 38, method 10 ( Figure 1B Another CMP process is performed on semiconductor layers 134 and 120 and alignment marks 138. In one embodiment, the CMP process is designed to be non-selective on alignment marks 138 and semiconductor layers 134 and 120. In other words, the CMP process polishes semiconductor layers 134 and 120 and alignment marks 138 at approximately the same rate. Figure 17 As shown, after the CMP process is completed, the top surfaces of semiconductor layers 134 and 120 and alignment mark 138 are coplanar or substantially coplanar (depending on the capabilities of the CMP process). In this embodiment, since there is almost no dielectric residue on semiconductor layers 134 and 120, no additional etching is required to remove this dielectric residue. In some methods where an etching process is applied after the CMP process to remove dielectric residue from the top surface of semiconductor layer 120, unlike this embodiment, alignment mark 138 is recessed, and its top surface is lower than the top surfaces of semiconductor layers 120 and 134. When alignment mark 138 is too low, it may not function well as an alignment mark during subsequent photolithography processes. Because the top surfaces of semiconductor layers 134 and 120 and alignment mark 138 are coplanar or substantially coplanar, alignment mark 138 is easily identifiable by metrology tools and can function well as an alignment mark during subsequent photolithography processes. In one embodiment, the CMP process can remove approximately 5 nm to approximately 15 nm of the corresponding material along the "Z" direction. Figure 17A A portion of device 100 at this stage of manufacturing is shown in a top view. (Reference) Figure 17ADevice 100 includes various pFET regions and nFET regions arranged alternately along an "X" direction (which is the width direction of the fins to be fabricated later). Semiconductor layer 134 is disposed in each pFET region, and semiconductor layer 120 is disposed in each nFET region. Semiconductor layers 134 and 120 are longitudinally oriented along a "Y" direction, which is the longitudinal direction of the fins to be fabricated later. In this embodiment, semiconductor layer 134 comprises SiGe, and semiconductor layer 120 comprises Si. In one embodiment, semiconductor layer 120 in each nFET region may be replaced with another semiconductor material using a method similar to that used to form semiconductor layer 134.

[0041] In operation 40, method 10 ( Figure 1C A buffer semiconductor layer 150 is deposited above the flat surfaces of semiconductor layers 134, 120, and alignment marks 138, for example... Figure 18 As shown. In one embodiment, the buffer semiconductor layer 150 comprises silicon, such as amorphous silicon. In some embodiments, the thickness of the buffer semiconductor layer 150 can range from about 1 nm to about 10 nm, and it can be epitaxially grown. Operation 40 may further clean the various surfaces of the device 100. For example, operation 40 may perform SC1 (Standard Clean 1) cleaning to trim the buffer semiconductor layer 150, apply a diluted HF solution to the front and back sides of the wafer and the edges of the wafer (bevel cleaning), etc.

[0042] In operation 42, method 10 ( Figure 1C Hard mask layers 151 and 153 are formed on device 100, for example... Figure 19 As shown. In one embodiment, hard mask layer 151 comprises an oxide such as silicon oxide (SiO2), while hard mask layer 153 comprises a nitride such as silicon nitride (Si3N4). In, for example... Figure 19 In the depicted embodiment, the hard mask layer 151 has a stepped profile, wherein it is higher on the semiconductor layer 134 than on the semiconductor layer 120.

[0043] In operation 44, method 10 ( Figure 1C Semiconductor fins 144 are formed in the pFET region, and semiconductor fins 146 are formed in the nFET region, for example... Figure 20 and Figure 21 As shown. Figure 21A perspective view of device 100 at this fabrication stage is partially shown. Operation 44 can involve various processes. For example, operation 44 can form an etch mask over hard mask layer 153. The etch mask can be formed using one or more photolithography processes, including dual patterning or multiple patterning processes. Typically, dual patterning or multiple patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with smaller pitches, for example, compared to those achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a pad silicon nitride layer and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used as an etch mask to pattern fins 144 and 146. For example, operation 44 can use the etch mask as a mask element to etch semiconductor layers 134, 120 and wells 116, 118, leaving fins 144 and 146 on substrate 102.

[0044] After forming fins 144 and 146, operation 44 further forms an isolation structure 143 to electrically isolate the bottoms of fins 144 and 146. The isolation structure 143 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), fluoride-doped silicate glass (FSG), a low-k dielectric material, and / or other suitable insulating materials. In one embodiment, the isolation structure 143 includes a dielectric pad 142 (e.g., thermal oxide) on the surface of the fins and the surface of the substrate 102, and a dielectric layer 140 (e.g., silicon nitride and / or silicon oxide) on the dielectric pad 142. In one embodiment, the isolation structure 143 is formed by filling a trench between fins 144 and 146 with one or more insulating materials (e.g., using a CVD process or a spin-coating glass process); performing a chemical mechanical polishing (CMP) process to remove excess insulating material; and etching back the insulating material to form the isolation structure 143.

[0045] like Figure 20As shown, each fin 144 includes a portion of the semiconductor layer 134 above a seed layer 134a above a portion 120a of the semiconductor layer 120 located above a portion of the N-well 116; while each fin 146 includes a portion of the semiconductor layer 120 located above a portion of the P-well 118. Semiconductor layers 134, 134a, 120a, and 120 protrude above the isolation structure 143. Additionally, an alignment mark 138 is located above the isolation structure 143. The top surfaces of fins 144, 146, and alignment mark 138 are substantially coplanar. The channel layer for a p-type FinFET includes the semiconductor layer 134 of the fin 144. The channel layer for an n-type FinFET includes the semiconductor layer 120 of the fin 146. Therefore, fins 144 and 146 are also referred to as pFET fins and nFET fins, respectively.

[0046] In operation 46, method 10 ( Figure 1C Further fabrication steps are performed to form a FinFET device over the pFET fin 144 and nFET fin 146. For example, operation 46 may involve forming a dummy gate over fins 144 and 146, forming source / drain regions by etching fins 144 and 146 in the source / drain regions and epitaxially growing source / drain components over the remaining portions of fins 144 and 146 in the source / drain regions, replacing the dummy gate with a high-k metal gate, forming an interlayer dielectric layer, forming contacts to the source / drain components and the high-k metal gate, forming a multilevel interconnect structure, and performing other fabrication steps. In this regard, Figure 22 A perspective view of the device 100 after the formation of the FinET transistor in operation 46 is shown. Figure 23 It shows along Figure 22 A cross-sectional view of device 100 with the "BB" line in the diagram. (See diagram below.) Figure 22 and Figure 23 As shown, operation 46 forms an n-type FinFET above the nFET fin 146 and a p-type FinFET above the pFET fin 144, wherein a portion of fins 146 and 144 serves as a channel for the respective FinFET. Figure 22 and Figure 23 In the illustrated embodiment, a common high-k metal gate 152 is bonded to fins 146 and 144 to form a CMOS device. In an alternative embodiment, the n-type FinFET and p-type FinFET may have spaced high-k metal gates.

[0047] refer to Figure 22 and Figure 23In this embodiment, device 100 includes a high-k metal gate 152, a gate spacer 154 located on the sidewall of the high-k metal gate 152, a fin sidewall spacer 156, an n-type source / drain component 158n located above the remaining portion of the fin 146 (after the source / drain trench etching process), and a p-type source / drain component 158p located above the remaining portion of the fin 144 (after the source / drain trench etching process). Device 100 may include... Figure 22 and Figure 23 Various other components not shown. Reference Figure 23 In a p-type FinFET, a high-k metal gate 152 is disposed above the top 134 of the pFET fin 144, which provides high charge carrier mobility. The top 134 of the pFET fin 144 connects two p-type source / drain components 158p and serves as a transistor channel. Because the top 134 uses a high-mobility semiconductor material such as SiGe, the performance of the p-type FinFET is improved. In this embodiment, the top 134 of the pFET fin 144 is partially etched in the source / drain region, and the source / drain components 158p are disposed directly above the remaining portion of the top 134 in the source / drain region. In an alternative embodiment, the top 134 of the pFET fin 144 is completely etched in the source / drain region, and the source / drain components 158p are disposed directly above the bottom 120a or 116 in the source / drain region.

[0048] Source / drain components 158n and 158p can be formed by any suitable epitaxial process, such as vapor phase epitaxy, molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof. In some embodiments, source / drain component 158n comprises silicon and may be doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof (e.g., forming Si:C epitaxial source / drain components, Si:P epitaxial source / drain components, or Si:C:P epitaxial source / drain components). In some embodiments, source / drain component 158p comprises silicon-germanium or germanium and may be doped with boron, other p-type dopants, or combinations thereof (e.g., forming Si:Ge:B epitaxial source / drain components). In some embodiments, epitaxial source / drain components 158n and 158p are doped by adding impurities to the source material (i.e., in situ) during deposition. In some embodiments, epitaxial source / drain components 158n and 158p are doped by an ion implantation process following the deposition process. In some embodiments, an annealing process (e.g., rapid thermal annealing (RTA) and / or laser annealing) is performed to activate the dopants in the epitaxial source / drain components 158n and 158p. In some embodiments, the epitaxial source / drain components 158n and 158p are formed in a separate processing sequence, including, for example, masking the pFET region when forming the epitaxial source / drain component 158n in the nFET region, and masking the nFET region when forming the epitaxial source / drain component 158p in the pFET region.

[0049] In one embodiment, the high-k metal gate 152 includes a high-k gate dielectric layer 152A and a gate electrode layer 152B. The gate electrode layer 152B may include a work function layer and a body metal layer. The high-k metal gate 152 may include additional layers, such as a dielectric interface layer between the top 134 and the high-k gate dielectric layer 152A. In various embodiments, the dielectric interface layer may include a dielectric material such as silicon oxide, silicon oxynitride, or silicon germanium oxide, and may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The dielectric interface layer may include different dielectric materials for n-type FinFETs and p-type FinFETs. For example, the dielectric interface layer may include silicon oxide for n-type FinFETs and silicon germanium oxide for p-type FinFETs. The high-k gate dielectric layer 152A may include hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), strontium titanate (SrTiO3), other suitable metal oxides, or combinations thereof; and may be formed by ALD and / or other suitable methods. The function layer (a portion of the gate electrode layer 152B) may include a metal selected from, but not limited to, titanium aluminum nitride (TiAlN), titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), tungsten (W), platinum (Pt), aluminum (Al), or combinations thereof; and may be deposited by CVD, PVD, and / or other suitable processes. The bulk metal layer (a portion of the gate electrode layer 152B) may include a metal such as aluminum (Al), tungsten (W), cobalt (Co), copper (Cu), and / or other suitable materials; and may be deposited using plating, CVD, PVD, or other suitable processes.

[0050] Each of the fin sidewall spacers 156 and the gate spacers 154 may be a single-layer or multi-layer structure. In some embodiments, each of the spacers 156 and 154 includes a dielectric material, such as silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), other dielectric materials, or combinations thereof. In one example, the spacers 156 and 154 are formed by depositing a first dielectric layer (e.g., a SiO2 layer of substantially uniform thickness) as a pad layer over the device 100, depositing a second dielectric layer (e.g., a Si3N4 layer) as a primary D-shaped spacer over the first dielectric layer, and then anisotropically etching to remove portions of the dielectric layer to form the spacers 156 and 154. Alternatively, the fin sidewall spacers 156 may be partially removed during an etching process that forms recesses in the fins 146 and 144 prior to the growth of the source / drain components 158n and 158p. In some embodiments, the fin sidewall spacers 156 may be completely removed by such an etching process.

[0051] While not intended to be limiting, embodiments of the invention offer one or more of the following advantages. For example, embodiments of the invention form pFET fins and nFET fins on the same substrate, wherein the channel semiconductor material included in the pFET fin has a higher hole mobility than the channel semiconductor material in the nFET fin. This improves the performance of the p-type FinFET formed from the pFET fin. Furthermore, the growth of the channel semiconductor material for the pFET fin uses an isothermal process, which not only reduces manufacturing time but also improves the quality of the channel semiconductor material. Embodiments of the invention can be readily integrated into existing semiconductor manufacturing processes.

[0052] In one example aspect, the present invention relates to a method. The method includes: forming an N-well and a P-well in a substrate; depositing a first layer having silicon over the N-well and P-well; depositing a first dielectric layer over the first layer; forming a resist pattern over the first dielectric layer, the resist pattern providing an opening directly above the N-well; etching the first dielectric layer and the first layer through the opening, leaving a first portion of the first layer above the N-well; removing the resist pattern; and epitaxially growing a second layer having silicon germanium (SiGe) over the first portion of the first layer. Epitaxially growing the second layer includes the steps of: (a) performing a baking process, (b) depositing a silicon seed layer, and (c) depositing a SiGe layer over the silicon seed layer, wherein steps (a), (b), and (c) are performed at approximately the same temperature.

[0053] In one embodiment of the method, steps (a), (b), and (c) are performed at a temperature ranging from approximately 650°C to 750°C. In another embodiment, the baking process is performed in an H2 environment.

[0054] In one embodiment, the method further includes: depositing a second dielectric layer over the first dielectric layer and over the SiGe layer; performing a first chemical mechanical polishing (CMP) process on the second dielectric layer and the first dielectric layer; and performing a second CMP process on the SiGe layer and the first layer. In another embodiment, the method includes: patterning the first layer and a P-well to form a first fin; patterning the SiGe layer and an N-well to form a second fin; and forming an isolation member to isolate the bottoms of the first fin and the second fin. In yet another embodiment, the method includes: forming an n-type FinFET over the first fin and over the isolation member; and forming a p-type FinFET over the second fin and over the isolation member.

[0055] In one embodiment, prior to depositing the first layer, the method further includes forming a portion of an alignment mark into the substrate. In another embodiment, prior to depositing the first dielectric layer, the method further includes forming an alignment trench into the first layer.

[0056] In one embodiment of the method, the second layer is epitaxially grown such that its top surface is higher than the top surface of the first layer and lower than the top surface of the first dielectric layer. In another embodiment, the temperature change for performing steps (a), (b), and (c) is less than + / - 10°C.

[0057] In another example aspect, the invention relates to a method. The method includes: providing a substrate; depositing a silicon layer over the substrate; etching an alignment trench into the silicon layer; depositing a first oxide layer over the silicon layer and in the alignment trench; forming an etch mask over the first oxide layer, wherein the etch mask covers the alignment trench and has an opening directly above a first portion of the silicon layer; etching the first oxide layer and the first portion of the silicon layer through the opening to form the first trench; removing the etch mask; and epitaxially growing a second layer having silicon germanium (SiGe) in the first trench, wherein epitaxially growing the second layer includes the steps of: (a) performing a baking process, (b) depositing a silicon seed layer, and (c) depositing a SiGe layer on the silicon seed layer, wherein steps (a), (b), and (c) are performed at approximately the same temperature.

[0058] In one embodiment, the method further includes: depositing a second oxide layer over the first oxide layer and over the SiGe layer; performing a first chemical mechanical polishing (CMP) process on the first oxide layer and the second oxide layer; and performing a second CMP process on the SiGe layer.

[0059] In one embodiment of the method, steps (a), (b), and (c) are performed at a temperature in the range of about 650°C to 750°C. In another embodiment, the second layer is epitaxially grown such that its top surface is higher than the top surface of the silicon layer and approximately flush with or lower than the top surface of the first oxide layer.

[0060] In some embodiments, the baking process is performed in an H2 environment. In some embodiments, the baking process is performed in an environment containing N2, Ar, He, or a combination thereof. In one embodiment, a first portion of the silicon layer is etched through an opening to leave a layer of the first portion of the silicon layer located in a first trench.

[0061] In yet another example, the invention relates to a semiconductor structure comprising: a substrate; a first fin extending from the substrate; and an alignment mark located above the substrate and having one or more dielectric layers. The first fin includes a bottom portion and an upper portion located above the bottom portion, the upper and bottom portions comprising different materials, and the upper portion comprising silicon-germanium. The top surface of the first fin is substantially coplanar with the top surface of the alignment mark.

[0062] In one embodiment, the alignment mark extends partially into the substrate. In another embodiment, the alignment mark includes a first dielectric layer and a second dielectric layer located above the first dielectric layer.

[0063] According to one embodiment of this application, a method for forming a semiconductor device is provided, comprising: forming an N-well and a P-well in a substrate; depositing a first layer having silicon over the N-well and the P-well; depositing a first dielectric layer over the first layer; forming a resist pattern over the first dielectric layer, the resist pattern providing an opening directly above the N-well; etching the first dielectric layer and the first layer through the opening, leaving a first portion of the first layer above the N-well; removing the resist pattern; and epitaxially growing a second layer having silicon and germanium over the first portion of the first layer, wherein epitaxially growing the second layer comprises the steps of: (a) performing a baking process, (b) depositing a silicon seed layer, and (c) depositing a silicon and germanium layer over the silicon seed layer, wherein steps (a), (b), and (c) are performed at approximately the same temperature. In some embodiments, steps (a), (b), and (c) are performed at a temperature in the range of approximately 650°C to 750°C. In some embodiments, the baking process is performed in an H2 environment. In some embodiments, the method of forming a semiconductor device further includes: depositing a second dielectric layer over a first dielectric layer and over a silicon-germanium layer; performing a first chemical mechanical polishing process on the second dielectric layer and the first dielectric layer; and performing a second chemical mechanical polishing process on the silicon-germanium layer and the first layer. In some embodiments, the method of forming a semiconductor device further includes: patterning a first layer and a P-well to form a first fin; patterning a silicon-germanium layer and an N-well to form a second fin; and forming an isolation member to isolate the bottoms of the first fin and the second fin. In some embodiments, the method of forming a semiconductor device further includes: forming an n-type FinFET over the first fin and over the isolation member; and forming a p-type FinFET over the second fin and over the isolation member. In some embodiments, prior to depositing the first layer, the method further includes: forming a portion of an alignment mark into a substrate. In some embodiments, prior to depositing the first dielectric layer, the method further includes: forming an alignment trench into the first layer. In some embodiments, the second layer is epitaxially grown such that its top surface is higher than the top surface of the first layer and lower than the top surface of the first dielectric layer. In some embodiments, the temperature variation for performing steps (a), (b), and (c) is less than + / - 10°C.

[0064] According to another embodiment of this application, a method for forming a semiconductor device is provided, comprising: providing a substrate; depositing a silicon layer over the substrate; etching an alignment trench into the silicon layer; depositing a first oxide layer over the silicon layer and in the alignment trench; forming an etch mask over the first oxide layer, wherein the etch mask covers the alignment trench and has an opening directly above a first portion of the silicon layer; etching the first oxide layer and the first portion of the silicon layer through the opening to form a first trench; removing the etch mask; and epitaxially growing a second layer having silicon germanium in the first trench, wherein epitaxially growing the second layer comprises the steps of: (a) performing a baking process, (b) depositing a silicon seed layer, and (c) depositing a silicon germanium layer on the silicon seed layer, wherein steps (a), (b), and (c) are performed at approximately the same temperature. In some embodiments, the method for forming a semiconductor device further comprises: depositing a second oxide layer over the first oxide layer and over the silicon germanium layer; performing a first chemical mechanical polishing process on the first oxide layer and the second oxide layer; and performing a second chemical mechanical polishing process on the silicon germanium layer. In some embodiments, steps (a), (b), and (c) are performed at a temperature ranging from about 650°C to 750°C. In some embodiments, the second layer is epitaxially grown such that its top surface is above the top surface of the silicon layer and approximately flush with or below the top surface of the first oxide layer. In some embodiments, the baking process is performed in an H2 environment. In some embodiments, the baking process is performed in an environment containing N2, Ar, He, or a combination thereof. In some embodiments, a first portion of the silicon layer is etched through an opening to leave a layer of the first portion of the silicon layer located in the first trench.

[0065] According to another embodiment of this application, a semiconductor structure is provided, comprising: a substrate; a first fin extending from the substrate, wherein the first fin includes a bottom and an upper portion above the bottom, the upper portion and the bottom comprising different materials, and the upper portion comprising silicon-germanium; and an alignment mark located above the substrate and having one or more dielectric layers, wherein the top surface of the first fin is substantially coplanar with the top surface of the alignment mark. In some embodiments, the alignment mark extends partially into the substrate. In some embodiments, the alignment mark includes a first dielectric layer and a second dielectric layer located above the first dielectric layer.

[0066] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as this disclosure. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a semiconductor device, comprising: N-wells and P-wells are formed in the substrate; A first layer of silicon is deposited over the N-well and the P-well; A first dielectric layer is deposited on top of the first layer; A resist pattern is formed above the first dielectric layer, the resist pattern providing an opening directly above the N-well; The first dielectric layer and the first layer are etched through the opening, leaving a first portion of the first layer above the N-well; Remove the resist pattern; as well as A second layer having silicon and germanium is epitaxially grown over the first portion of the first layer, wherein the epitaxial growth of the second layer includes the following steps: (a) performing a baking process, (b) depositing a silicon seed layer, and (c) depositing a silicon and germanium layer over the silicon seed layer, wherein steps (a), (b), and (c) are performed at the same temperature; A second dielectric layer is deposited above the first dielectric layer and above the silicon-germanium layer; A first chemical mechanical polishing process is performed on the second dielectric layer and the first dielectric layer.

2. The method for forming a semiconductor device according to claim 1, wherein, Steps (a), (b), and (c) are performed at temperatures ranging from 650°C to 750°C.

3. The method for forming a semiconductor device according to claim 1, wherein, The baking process is carried out in an H2 environment.

4. The method for forming a semiconductor device according to claim 1, further comprising: A second chemical mechanical polishing process is performed on the silicon-germanium layer and the first layer.

5. The method for forming a semiconductor device according to claim 4, further comprising: The first layer and the P-well are patterned to form a first fin; The silicon-germanium layer and the N-well are patterned to form a second fin; as well as An isolation component is formed to isolate the bottom of the first fin and the second fin.

6. The method for forming a semiconductor device according to claim 5, further comprising: An n-type FinFET is formed above the first fin and above the isolation member; as well as A p-type FinFET is formed above the second fin and above the isolation component.

7. The method for forming a semiconductor device according to claim 1, further comprising, before depositing the first layer: A portion of the alignment mark is formed into the substrate.

8. The method for forming a semiconductor device according to claim 1, further comprising, before depositing the first dielectric layer: Alignment grooves are formed into the first layer.

9. The method for forming a semiconductor device according to claim 1, wherein, The second layer is epitaxially grown such that its top surface is higher than the top surface of the first layer and lower than the top surface of the first dielectric layer.

10. The method for forming a semiconductor device according to claim 1, wherein, The temperature change during the implementation of steps (a), (b), and (c) is less than + / - 10°C.

11. A method of forming a semiconductor device, comprising: Provide substrate; A silicon layer is deposited over the substrate; The alignment trench is etched into the silicon layer; A first oxide layer is deposited over the silicon layer and in the alignment trench; An etching mask is formed over the first oxide layer, wherein the etching mask covers the alignment trench and has an opening directly above the first portion of the silicon layer; The first trench is formed by etching the first portion of the first oxide layer and the first silicon layer through the opening; Remove the etch mask; A second layer having silicon and germanium is epitaxially grown in the first trench, wherein the epitaxial growth of the second layer includes the following steps: (a) performing a baking process, (b) depositing a silicon seed layer, and (c) depositing a silicon and germanium layer on the silicon seed layer, wherein steps (a), (b), and (c) are performed at the same temperature; A second oxide layer is deposited over the first oxide layer and over the silicon-germanium layer; and A first chemical mechanical polishing process is performed on the first oxide layer and the second oxide layer.

12. The method for forming a semiconductor device according to claim 11, further comprising: A second chemical mechanical polishing process is performed on the silicon-germanium layer.

13. The method of forming a semiconductor device according to claim 11, wherein, Steps (a), (b), and (c) are performed at temperatures ranging from 650°C to 750°C.

14. The method of forming a semiconductor device according to claim 11, wherein, The second layer is epitaxially grown such that its top surface is higher than the top surface of the silicon layer and flush with or lower than the top surface of the first oxide layer.

15. The method of forming a semiconductor device according to claim 11, wherein, The baking process is carried out in an H2 environment.

16. The method of forming a semiconductor device according to claim 11, wherein, The baking process is carried out in an environment containing N2, Ar, He, or a combination thereof.

17. The method of forming a semiconductor device according to claim 11, wherein, The first portion of the silicon layer is etched through the opening, leaving a layer of the first portion of the silicon layer located in the first trench.

18. A semiconductor structure comprising: Substrate; A first fin extends from the substrate, wherein the first fin includes a bottom and an upper portion located above the bottom, the upper portion and the bottom comprising different materials, and the upper portion comprising silicon-germanium; and Alignment marks are located above the substrate and have one or more dielectric layers, wherein the top surface of the first fin is coplanar with the top surface of the alignment marks. Wherein, the bottom of the first fin is an N-type well portion of the substrate, and the bottom surface of the N-type well portion is coplanar with the bottom surface of the alignment mark.

19. The semiconductor structure according to claim 18, wherein, The alignment mark extends partially into the substrate.

20. The semiconductor structure according to claim 18, wherein, The alignment mark includes a first dielectric layer and a second dielectric layer located above the first dielectric layer.

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