A planarization control method and a semiconductor structure
By forming an etch stop layer on the semiconductor structure and etching away the spacer structure, the problem of film thickness difference in patterned areas of semiconductor chips is solved, resulting in lower process costs and higher chip performance.
Patent Information
- Application Number
- CN202411933899.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-25
- Publication Date
- 2026-06-30
AI Technical Summary
Existing technologies are insufficient to effectively reduce the difference in film thickness between different patterned regions of semiconductor chips, resulting in a narrower process window and impacting chip performance.
An etch stop layer is formed on the structure to be planarized. The etch stop layer located in the first pattern region and the connecting region is etched away. Using the etch stop layer located in the second pattern region as a mask, the spacer structure located in the first pattern region is etched until its thickness is less than or equal to the thickness of the spacer structure in the second pattern region. The spacer structure and the filling layer are then removed to form a second spacer pillar with a thickness less than that of the protrusion structure.
It significantly reduces the difference in film thickness between different patterned regions, meets the requirements for further improvement in chip performance, reduces process costs, and reduces sacrificial layer consumption.
Smart Images
Figure CN122318831A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductors, and in particular to a planarization control method and a semiconductor structure. Background Technology
[0002] With the development of semiconductor technologies, new demands have been placed on chip performance. Considering the large number of film layers in current chips and the significant thickness differences (loading) between film layers in different patterned regions, the process window narrows, affecting subsequent processes and creating thickness differences, ultimately leading to poor chip performance.
[0003] To improve chip performance, the loading problem can be optimized. Specifically, inductively coupled plasma (ICP) combined with chemical mechanical polishing (CMP) can be used to reduce the thickness difference formed by subsequent processes. However, using ICP combined with CMP can only reduce the thickness difference formed by subsequent processes to 20nm, which cannot meet the requirement of reducing the thickness difference and further improving chip performance. Summary of the Invention
[0004] In view of this, the purpose of this application is to provide a planarization control method and a semiconductor structure that can greatly reduce the thickness difference formed by subsequent processes of film layers in different patterned regions, meet the thickness difference requirements, and meet the requirements for further improvement of chip performance.
[0005] This application provides a flattening control method, the method comprising:
[0006] A structure to be planarized is provided, the structure to be planarized including a substrate, a plurality of protrusions, spacers, and a filler layer. The spacers include a plurality of first spacers and a spacer layer, the plurality of first spacers separating the plurality of protrusions. The filler layer covers the protrusions, the spacers cover the filler layer, and the first spacers penetrate the filler layer and contact the spacers. The structure to be planarized includes a first patterned region, a second patterned region, and a connecting region. The density of the protrusions in the first patterned region and the second patterned region is different. The connecting region is located between the first patterned region and the second patterned region. The thickness of the filler layer in the first patterned region gradually decreases through the connecting region to the thickness of the filler layer in the second patterned region. The thickness of the spacers in the first patterned region gradually decreases through the connecting region to the thickness of the spacers in the second patterned region.
[0007] An etch stop layer is formed on the structure to be planarized, and the etch stop layer located in the first pattern region and the connection region is etched away.
[0008] Using the etching stop layer located in the second pattern region as a mask, the spacing structure located in the first pattern region is etched until the thickness of the spacing structure located in the first pattern region is less than or equal to the thickness of the spacing structure located in the second pattern region;
[0009] The etching stop layer is removed by etching.
[0010] The preset thickness of the spacer structure is removed by etching to obtain a second spacer column with a thickness smaller than that of the protrusion structure.
[0011] Remove the filler layer.
[0012] Optionally, there is an etch selectivity ratio between the etch stop layer and the spacer structure;
[0013] When the etch stop layer located in the second pattern region is used as a mask to etch the spacer structure located in the first pattern region, the etch selectivity ratio between the spacer structure and the etch stop layer is greater than the first selectivity threshold.
[0014] Optionally, the thickness of the etching stop layer is less than or equal to a first thickness threshold.
[0015] Optionally, the thickness of the spacer structure located in the first graphic region is equal to the thickness of the spacer structure located in the second graphic region, and the thickness of the second spacer column located in the first graphic region is equal to the thickness of the second spacer column located in the second graphic region.
[0016] Optionally, the target thickness is defined as the thickness of the spacer structure located in the first graphic region being less than the thickness of the spacer structure located in the second graphic region, and the target thickness is defined as the thickness of the second spacer column located in the first graphic region being less than the thickness of the second spacer column located in the second graphic region.
[0017] Optionally, the target thickness is less than the second thickness threshold.
[0018] Optionally, before etching away the etch stop layer located in the first patterned region and the connection region, the method further includes:
[0019] A capping layer is formed on the etch stop layer, wherein the surface of the capping layer away from the substrate is flush with the surface of the etch stop layer away from the substrate;
[0020] The etching removal of the etching stop layer located in the first patterned region and the connection region includes:
[0021] The etching removes the etch stop layer and a portion of the cover layer located in the first patterned area;
[0022] Remove the covering layer;
[0023] The etching stop layer located in the connection region is removed by etching, while the etching stop layer located in the second pattern region is retained.
[0024] Optionally, the etching removal of the etch stop layer located in the connection region includes:
[0025] The etching stop layer located in the connection region is removed by ion beam sputtering.
[0026] Optionally, the material of the etching stop layer includes one or more of SiN, TiN, TiO, W, TaN, and Ta, and the material of the spacer layer is the same as the material of the first spacer pillar, wherein the material of the spacer layer includes a low-temperature oxide.
[0027] This application provides a semiconductor structure, the semiconductor structure including a first patterned region and a second patterned region;
[0028] The substrate and multiple protrusions located on one side of the substrate, with different densities of the protrusions located in the first patterned region and the second patterned region;
[0029] A plurality of second spacer columns, the plurality of second spacer columns being spaced apart from a plurality of protrusions located in the first graphic region and spaced apart from the plurality of protrusions located in the second graphic region;
[0030] The thickness of the second spacer located in the first graphic region is less than or equal to the thickness of the second spacer located in the second graphic region.
[0031] This application provides a planarization control method, the method comprising: providing a structure to be planarized, the structure to be planarized including a substrate, a plurality of protrusion structures, a spacer structure and a filling layer, the spacer structure including a plurality of first spacer pillars and a spacer layer, the plurality of first spacer pillars separating the plurality of protrusion structures, the filling layer covering the protrusion structures, the spacer layer covering the filling layer, the first spacer pillars penetrating the filling layer and contacting the spacer layer; the structure to be planarized includes a first patterned region, a second patterned region and a connecting region, the density of the protrusion structures located in the first patterned region and the second patterned region is different, the connecting region is located between the first patterned region and the second patterned region, the thickness of the filling layer located in the first patterned region gradually decreases through the connecting region to the thickness of the filling layer located in the second patterned region, the total thickness of the spacer layer and the first spacer pillars located in the first patterned region gradually decreases through the connecting region to the total thickness of the spacer layer and the first spacer pillars located in the second patterned region, that is, there is a thickness difference between the film layers in different patterned regions of the structure to be planarized. An etch stop layer is formed on the structure to be planarized. The etch stop layers located in the first patterned region and the connection region are etched away. Using the etch stop layer located in the second patterned region as a mask, the spacer structure located in the first patterned region is etched away, thereby reducing the total thickness of the film layer in the first patterned region until the thickness of the spacer structure located in the first patterned region is less than or equal to the thickness of the spacer structure located in the second patterned region. This reduces the thickness difference between the first and second patterned regions, and may even further achieve a reverse thickness difference between the first and second patterned regions to meet the requirements of various patterned region thickness variations. The etch stop layer is then etched away, and the spacer structure is etched away at a preset thickness to obtain a second spacer pillar with a thickness less than that of the protrusion structure. The filler layer is then removed, ultimately reducing the thickness difference of the second spacer pillar or even forming a reverse thickness difference to meet the requirements of further improving chip performance. Attached Figure Description
[0032] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0033] Figures 1(a) and 1(b) show schematic diagrams of a process for reducing the thickness difference between film layers in different patterned regions;
[0034] Figure 2 A schematic flowchart of a flattening control method provided in an embodiment of this application is shown;
[0035] Figures 3-17 A schematic diagram of a semiconductor structure manufactured according to the planarization control method provided in an embodiment of this application is shown.
[0036] Figure 18 This illustration shows a schematic diagram illustrating the effect of different processes on thickness difference optimization provided in an embodiment of this application. Detailed Implementation
[0037] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.
[0038] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.
[0039] This application is described in detail with reference to the schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not according to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.
[0040] Given that current chips have many film layers and there is a large thickness difference (loading) between film layers in different patterned areas, the process window will be narrowed, affecting subsequent processes and creating thickness differences, ultimately resulting in poor chip performance.
[0041] To improve chip performance, loading issues can be optimized. Specifically, inductively coupled plasma (ICP-POP) combined with chemical mechanical polishing (CMP) can reduce the thickness difference caused by subsequent processes. However, this method requires a relatively thick sacrificial layer, with the ratio of improved loading thickness to sacrificial layer thickness consumption being approximately 1:2, resulting in high process costs. Furthermore, ICP-POP can only reduce the thickness difference caused by subsequent processes to 20nm, which is insufficient to meet the requirements for further thickness difference reduction and thus cannot satisfy the need for further improvements in chip performance.
[0042] To optimize the loading problem, ion beam sputtering (IBS) can be used to reduce the thickness difference in subsequent processes resulting from different patterned regions. Referring to Figure 1(a), the total thickness of the film in regions with higher pattern density is greater than that in regions with lower pattern density. IBS planarization reduces this thickness difference (Δy). As shown in Figure 1(b), the thickness of the low-temperature oxide (LTO) film consumed in this process is the thickness of the sacrificial layer consumed (Δh). While ion beam sputtering can optimize loading below 20 nm, it still requires a relatively thick sacrificial layer. The ratio of the thickness improved by loading to the thickness consumed by the sacrificial layer is approximately 1:6, leading to higher process costs.
[0043] In other words, optimizing a thinner loading layer requires a thicker sacrificial layer. Furthermore, when the technology node is smaller, i.e. when transitioning from Self-aligned Double Patterning (SADP) to Self-aligned Quadruple Patterning (SAQP), the number of loading flattening operations will double continuously. At this point, the ratio of the sacrificial layer thickness consumed to the loading optimization thickness reaches >20:1, which greatly increases the process difficulty and cost.
[0044] Based on this, this application provides a planarization control method, the method comprising: providing a structure to be planarized, the structure to be planarized including a substrate, a plurality of protrusion structures, a spacer structure and a filling layer, the spacer structure including a plurality of first spacer pillars and a spacer layer, the plurality of first spacer pillars separating the plurality of protrusion structures, the filling layer covering the protrusion structures, the spacer layer covering the filling layer, the first spacer pillars penetrating the filling layer and contacting the spacer layer; the structure to be planarized includes a first patterned region, a second patterned region and a connecting region, the density of the protrusion structures located in the first patterned region and the second patterned region is different, the connecting region is located between the first patterned region and the second patterned region, the thickness of the filling layer located in the first patterned region gradually decreases through the connecting region to the thickness of the filling layer located in the second patterned region, the total thickness of the spacer layer and the first spacer pillars located in the first patterned region gradually decreases through the connecting region to the total thickness of the spacer layer and the first spacer pillars located in the second patterned region, that is, the structure to be planarized has a thickness difference between the film layers in different patterned regions. An etch stop layer is formed on the structure to be planarized. The etch stop layers located in the first patterned region and the connection region are etched away. Using the etch stop layer located in the second patterned region as a mask, the spacer structure located in the first patterned region is etched away, thereby reducing the total thickness of the film layer in the first patterned region until the thickness of the spacer structure located in the first patterned region is less than or equal to the thickness of the spacer structure located in the second patterned region. This reduces the thickness difference between the first and second patterned regions, and may even further achieve a reverse thickness difference between the first and second patterned regions to meet the requirements of various patterned region thickness variations. The etch stop layer is then etched away, and the spacer structure is etched away at a preset thickness to obtain a second spacer pillar with a thickness less than that of the protrusion structure. The filler layer is then removed, ultimately reducing the thickness difference of the second spacer pillar or even forming a reverse thickness difference to meet the requirements of further improving chip performance.
[0045] To better understand the technical solution and effects of this application, the specific embodiments will be described in detail below with reference to the accompanying drawings.
[0046] See Figure 2 The figure is a schematic flowchart of a flattening control method provided in an embodiment of this application.
[0047] The flattening control method provided in this embodiment includes the following steps:
[0048] S101, a structure to be planarized is provided. The structure to be planarized includes a substrate, multiple protrusions, spacers, and a filler layer. The spacers include multiple first spacers and a spacer layer. The multiple first spacers separate the multiple protrusions. The filler layer covers the protrusions. The spacers cover the filler layer. The first spacers penetrate the filler layer and contact the spacers. The structure to be planarized includes a first patterned region, a second patterned region, and a connecting region. The protrusions in the first and second patterned regions have different densities. The connecting region is located between the first and second patterned regions. The thickness of the filler layer in the first patterned region gradually decreases through the connecting region to the thickness of the filler layer in the second patterned region. The thickness of the spacers in the first patterned region gradually decreases through the connecting region to the thickness of the spacers in the second patterned region.
[0049] In embodiments of this application, a structure to be planarized can be provided for planarization. (See reference...) Figure 3 As shown, the structure to be planarized includes a substrate 110, multiple protrusions 120, spacer structures 130, and a filler layer 140. The spacer structure 130 includes multiple first spacer pillars 131 and spacer layers 132. The structure to be planarized includes a first patterned region 100, a second patterned region 200, and a connecting region 300. The connecting region 300 is located between the first patterned region 100 and the second patterned region 200. The protrusions 120 in the first patterned region 100 and the second patterned region 200 have different densities; that is, different patterned regions of the structure to be planarized are distinguished according to their pattern density. The connecting region 300 may not have protrusions 120, i.e., the connecting region 300 may not have pattern density.
[0050] As an example, the density of the protrusion structure 120 located in the first graphic region 100 is greater than the density of the protrusion structure 120 located in the second graphic region 200, that is, the first graphic region 100 is a dense graphic region and the second graphic region 200 is a sparse graphic region.
[0051] In practical applications, the size of the protrusion 120 located in the first graphic region 100 can be smaller than the size of the protrusion 120 located in the second graphic region 200. For example, the width of the protrusion 120 located in the first graphic region 100 can be smaller than the width of the protrusion 120 located in the second graphic region 200, and the height of the protrusion 120 located in the first graphic region 100 can be the same as the height of the protrusion 120 located in the second graphic region 200. (Refer to...) Figure 3 As shown.
[0052] Multiple first spacers 131 separate multiple protruding structures 120. In the first graphic region 100 and the second graphic region 200, adjacent protruding structures 120 can be separated by the first spacers 131. A filling layer 140 covers the protruding structures 120, and a spacer layer 132 covers the filling layer 140. The first spacers 131 penetrate the filling layer 140 and contact the spacer layer 132.
[0053] The thickness of the filler layer 140 in the first patterned region 100 gradually decreases through the connecting region 300 to the thickness of the filler layer 140 in the second patterned region 200. Similarly, the thickness of the spacer structure 130 in the first patterned region 100 gradually decreases through the connecting region 300 to the thickness of the spacer structure 130 in the second patterned region 200. In other words, the height of the filler layer 140 in the first patterned region 100 is greater than the height of the filler layer 140 in the second patterned region 200, and the height of the spacer structure 130 in the first patterned region 100 is greater than the height of the spacer structure 130 in the second patterned region 200. This height refers to the distance between the upper surface of the filler layer 140 or spacer layer 132 and the substrate 110. Thus, there is a thickness difference between the film layers in the first patterned region 100 and the second patterned region 200 of the structure to be planarized; that is, there is a thickness difference between the film layers in different patterned regions of the structure to be planarized.
[0054] In one possible implementation, the spacer layer 132 is made of the same material as the first spacer pillar 131, and the spacer layer 132 and the first spacer pillar 131 are integral structures formed using the same manufacturing process; that is, the spacer structure 130 is an integral structure. The material of the spacer layer 132 includes low-temperature oxide (LTO). The substrate 110 can be a semiconductor substrate, and the substrate 110 may also include multiple pre-fabricated film layers or devices. The bump structure 120 may include a core structure 121 and an outer structure 122, with the outer structure 122 covering the core structure 121. The material of the outer structure 122 includes metal oxide, and the material of the core structure 121 includes polysilicon. The material of the filler layer 140 includes carbon. For example, the filler layer 140 can be a carbon film layer (SOC) formed using a spin-coating process.
[0055] S102, an etch stop layer is formed on the structure to be planarized, and the etch stop layer located in the first pattern region and the connection region is removed by etching.
[0056] In the embodiments of this application, to achieve planarization of the structure to be planarized, an etch stop layer 160 can be formed on the structure to be planarized, and the etch stop layer 160 covers the spacer layer 132, as shown in the reference. Figure 4 As shown. The material of the etch stop layer 160 includes one or more of SiN, TiN, TiO, W, TaN, and Ta.
[0057] The etching removes the etch stop layer 160 located in the first patterned region 100 and the connecting region 300, while retaining the etch stop layer 160 located in the second patterned region 200. This allows the etch stop layer 160 in the second patterned region 200 to be used to remove the spacer structure 130 located in the first patterned region 100, thereby reducing the thickness difference between the spacer structure 130 between the first patterned region 100 and the second patterned region 200.
[0058] Specifically, before etching away the etch stop layer 160 located in the first pattern region 100 and the connecting region 300, a cover layer 170 may be applied to the etch stop layer 160, as shown in the reference. Figure 5 As shown, the etch stop layer 160 can be etched, and the surface of the resulting capping layer 170 away from the substrate 110 is flush with the surface of the etch stop layer 160 away from the substrate 110. (Refer to...) Figure 6 As shown, this is done so that at least the etch stop layer 160 located in the first pattern region 100 is exposed, thereby facilitating the subsequent use of the cover layer 170 as a protective layer to protect the etch stop layer 160 located in the second pattern region 200 when the etch stop layer 160 in the first pattern region 100 is removed.
[0059] The capping layer 170 can be made of the same material as the filler layer 140, meaning the material of the capping layer 170 includes carbon. For example, the filler layer 140 can be a carbon film layer (SOC) formed using a spin coating process. Choosing carbon as the material for both the capping layer 170 and the filler layer 140 facilitates their removal and subsequent removal.
[0060] As an example, the capping layer 170 can be etched using an inductively coupled plasma (ICP) process, with the surface of the etched capping layer 170 away from the substrate 110 flush with the surface of the etch stop layer 160 away from the substrate 110, as referenced. Figure 6 As shown.
[0061] The specific process steps for etching away the etch stop layer 160 located in the first pattern area 100 and the connection area 300 are as follows.
[0062] First, the etch stop layer 160 and a portion of the cover layer 170 located in the first patterned region 100 are etched away. (Refer to...) Figure 7 As shown, the etch stop layer 160, which is located in the second patterned region 200, is not etched by the capping layer 170. For example, the etch stop layer 160 located in the first patterned region 100 can be etched away from the side of the spacer layer 132 away from the substrate 110 by an ICP process.
[0063] Then the cover layer 170 is removed to expose the etch stop layer 160 located in the second pattern region 200, as shown in the reference. Figure 8 As shown. For example, the capping layer 170 can be removed by etching using an ICP process.
[0064] In practical applications, ICP etching mainly uses inert gases, nitrogen, oxygen, fluorine-based gases, chlorine-based gases, bromine-based gases, or combinations thereof. The upper RF power ranges from 100 to 1000W, the lower RF power ranges from 0 to 200W, the total intake flow rate ranges from 50 to 250 sccm, the cavity pressure ranges from 3 mT to 20 mT, and the coolant temperature ranges from 30 to 80℃.
[0065] The etch stop layer 160 located in the connection region 300 is removed, while the etch stop layer 160 located in the second pattern region 200 is retained. (Refer to...) Figure 9 As shown, this facilitates the subsequent removal of the spacer layer 132 located in the first patterned region 100 using the etch stop layer 160 located in the second patterned region 200. To achieve the removal of only the etch stop layer 160 located in the connection region 300, based on the good ion beam directionality of the ion beam sputtering (IBS) process, the etch stop layer 160 located in the connection region 300 can be removed by ion beam sputtering, thereby achieving the removal of the etch stop layer 160 located in the connection region 300 without affecting the etch stop layer 160 located in the second patterned region 200.
[0066] In practical applications, IBS etching employs different ion beam angles, such as 0-90 degrees, with a screen grid voltage (BMV) range of 200-1500V, an accelerating grid voltage (ACV) range of 100-1500V, a screen grid current (BMI) range of 0.1-1.6A, and an etching chamber pressure range of 0.05mT-5mT. The etching gas is selected from one or more of inert gases, fluorine-based gases, and chlorine-based gases.
[0067] S103, using the etch stop layer located in the second pattern region as a mask, etch the spacer structure located in the first pattern region until the total thickness of the spacer layer and the first spacer pillar located in the first pattern region is less than or equal to the total thickness of the spacer layer and the first spacer pillar located in the second pattern region.
[0068] In embodiments of this application, after etching away the etch stop layer 160 located in the connection region 300 and retaining the etch stop layer 160 located in the second pattern region 200, the spacer structure 130 located in the first pattern region 100 can be etched using the etch stop layer 160 located in the second pattern region 200 as a mask, until the thickness of the spacer structure 130 located in the first pattern region 100 is less than or equal to the thickness of the spacer structure 130 located in the second pattern region 200, referencing... Figure 10 or Figure 11 As shown.
[0069] There is an etch selectivity ratio between the etch stop layer 160 and the spacer structure 130. Therefore, the thinner etch stop layer 160 located in the second patterned region 200 can be used as a mask to etch away the thicker spacer structure 130 located in the first patterned region 100. In other words, the etch stop layer 160 is used to reduce the thickness difference between the spacer structures 130 between the first patterned region 100 and the second patterned region 200.
[0070] As one possible implementation, when the etch stop layer 160 located in the second pattern region 200 is used as a mask to etch the spacer structure 130 located in the first pattern region 100, the etch selectivity ratio between the spacer structure 130 and the etch stop layer 160 is greater than the first selectivity threshold. That is, the etch selectivity ratio between the spacer structure 130 and the etch stop layer 160 is large, so less thickness of the etch stop layer 160 can be used to etch and remove more spacer structures 130, thereby reducing the process cost.
[0071] As an example, the first selectivity threshold can be 15:1, and the etch selectivity between the spacer structure 130 and the etch stop layer 160 can be 16:1.
[0072] In practical applications, the ICP process is used to etch the spacer structure 130. The ICP etching mainly uses a gas combination of 10-25 sccm C4F6, 5-10 sccm O2, 300-400 sccm Ar and 300-400 sccm He, with a cavity pressure of 5-15 mT, an upper RF power of 100-400W and a lower RF power of 400-800W.
[0073] Since the etch selectivity ratio between the spacer structure 130 and the etch stop layer 160 is greater than a first selectivity threshold, the thickness of the etch stop layer 160 can be calculated based on the thickness difference between the spacer structure 130 located in the first patterned region 100 and the second patterned region 200, and the etch selectivity ratio between the etch stop layer 160 and the spacer structure 130. The thickness of the etch stop layer 160 is less than or equal to the first thickness threshold, meaning that a thinner etch stop layer 160 can reduce the thickness difference between the spacer structure 130 located in the first patterned region 100 and the second patterned region 200. The first thickness threshold can be 2 nm.
[0074] In the embodiments of this application, when etching away the spacer structure 130 located in the first pattern region 100 and the connecting region 300 using the etch stop layer 160 located in the second pattern region 200 as a mask, the etching progress can be controlled so as to control the thickness difference between the thickness of the spacer structure 130 located in the first pattern region 100 and the thickness of the spacer structure 130 located in the second pattern region 200.
[0075] As one possible implementation, to reduce the thickness difference between different patterned regions, etching of the spacer structure 130 in the first patterned region 100 is stopped when the thickness of the spacer structure 130 in the first patterned region 100 is equal to the thickness of the spacer structure 130 in the second patterned region 200, i.e., when the surfaces of the spacer structures 130 in the first patterned region 100, the second patterned region 200, and the connecting region 300 are flush with the side of the spacer structure 130 away from the substrate 110. This reduces the thickness difference between the thickness of the spacer structure 130 in the first patterned region 100 and the thickness of the spacer structure 130 in the second patterned region 200 to zero. Figure 10 As shown.
[0076] In practical applications, when the thickness difference between the thickness of the spacer structure 130 in the first patterned region 100 and the thickness of the spacer structure 130 in the second patterned region 200 is reduced to 0, the first patterned region 100 may still have a spacer layer 132 with remaining thickness, thereby achieving that the side surface of the spacer layer 132 in the first patterned region 100 away from the substrate 110 and the side surface of the spacer layer 132 in the second patterned region 100 away from the substrate 110 are flush.
[0077] As another possible implementation, to meet other chip performance improvement requirements, such as forming reverse thickness differences between different patterned regions, etching of the spacer structure 130 in the first patterned region 100 is stopped when the thickness of the spacer structure 130 in the first patterned region 100 is less than the thickness of the spacer structure 130 in the second patterned region 200. Specifically, when the surface of the spacer structure 130 in the first patterned region 100 away from the substrate 110 is lower than the surface of the spacer structure 130 in the second patterned region 200 away from the substrate 110. This achieves a reverse thickness difference between the thickness of the spacer structure 130 in the first patterned region 100 and the thickness of the spacer structure 130 in the second patterned region 200, adjusting the total thickness of the film layer in the first patterned region 100 to be higher than the total thickness of the film layer in the second patterned region 200. Figure 11 As shown.
[0078] Specifically, the target thickness is defined as the thickness of the spacer structure 130 in the first patterned region 100 being less than the thickness of the spacer structure 130 in the second patterned region 200. That is, the target thickness is the inverse thickness difference between the total thickness of the film layers in the first patterned region 100 and the total thickness of the film layers in the second patterned region 200. The target thickness is less than a second thickness threshold, which can be the initial thickness difference between the thickness of the spacer structure 130 in the first patterned region 100 and the thickness of the spacer structure 130 in the second patterned region 200. This initial thickness difference is the thickness difference before the structure to be planarized is planarized. For example, the second thickness threshold can be 15 nm.
[0079] In practical applications, when the thickness of the spacer structure 130 in the first patterned region 100 is less than the thickness of the spacer structure 130 in the second patterned region 200, the first patterned region 100 may not have a spacer layer 132, and the first spacer pillar 131 in the first patterned region 100 may have been etched. This results in the surface of the first spacer pillar 131 in the first patterned region 100 away from the substrate 110 being smaller than the surface of the spacer layer 132 in the second patterned region 100 away from the substrate 110.
[0080] S104, etching to remove the etch stop layer.
[0081] In embodiments of this application, after etching away the spacer layer 132 located in the first pattern region 100 using the etch stop layer 160 located in the second pattern region 200 and reducing the thickness difference or even forming a reverse thickness difference, the etch stop layer 160 can be etched away. (Refer to...) Figure 12 or Figure 13 As shown.
[0082] As one possible implementation, when the thickness of the spacer structure 130 in the first patterned region 100 is equal to the thickness of the spacer structure 130 in the second patterned region 200, the etch stop layer 160 is removed without affecting the thickness difference between the thickness of the spacer structure 130 in the first patterned region 100 and the thickness of the spacer structure 130 in the second patterned region 200, which is 0. Figure 12 As shown.
[0083] As another possible implementation, when the thickness of the spacer structure 130 in the first pattern region 100 is less than the thickness of the spacer structure 130 in the second pattern region 200, the etch stop layer 160 is removed without affecting the formation of a reverse thickness difference with a target thickness between the thicknesses of the spacer structure 130 in the first pattern region 100 and the spacer structure 130 in the second pattern region 200. Figure 13 As shown.
[0084] The etching removal of the etch stop layer 160 can be based on the etch selectivity ratio between the etch stop layer 160 and the spacer structure 130. If the etch selectivity ratio between the etch stop layer 160 and the spacer structure 130 is greater than a second etch selectivity threshold, then based on the larger second etch selectivity threshold and the etch stop layer 160 being smaller than a first thickness threshold, the removal of the etch stop layer 160 can have a smaller impact on the thickness of the spacer structure 130.
[0085] As an example, the second selectivity threshold can be 40:1, and the etch selectivity ratio between the etch stop layer 160 and the spacer structure 130 can be 41:1.
[0086] As an example, the etch stop layer 160 can be removed using ICP etching. ICP etching mainly uses a gas combination of 180-250 sccm CH3F, 180-250 sccm O2 and 100-150 sccm He, with a cavity pressure of 30-45 mT, an upper RF power of 100-400 W and a lower RF power of 0-50 W.
[0087] S105, etching away the preset thickness of the spacer structure to obtain a second spacer column with a thickness less than that of the protrusion structure.
[0088] In the embodiments of this application, after removing the etch stop layer 160, the spacer structure 130 can be etched away at a predetermined thickness to obtain a second spacer post 133 with a thickness less than that of the protrusion structure 120, as shown in the reference. Figure 14 As shown and Figure 15 As shown.
[0089] If there is remaining thickness in the spacer layer 132, the spacer layer 132 and the first spacer pillar 131 are etched away to a predetermined thickness, and the remaining thickness of the first spacer pillar 131 forms the second spacer pillar 133. (Refer to...) Figure 14 As shown.
[0090] If the spacer layer 132 is absent, the first spacer pillar 131 is etched away to a predetermined thickness, and the remaining thickness of the first spacer pillar 131 forms the second spacer pillar 133. (Refer to...) Figure 15 As shown.
[0091] In the embodiments of this application, when etching away the spacer structure 130 at a preset thickness, the thickness difference between the spacer structures 130 in different patterned regions remains constant. That is, when the thickness of the spacer structure 130 in the first patterned region 100 is equal to the thickness of the spacer structure 130 in the second patterned region 200, then the thickness of the second spacer pillar 133 in the first patterned region 100 is equal to the thickness of the second spacer pillar 133 in the second patterned region 200. When the thickness of the spacer structure 130 in the first patterned region 100 is less than the thickness of the spacer structure 130 in the second patterned region 200 (which is the target thickness), then the thickness of the second spacer pillar 133 in the first patterned region 100 is less than the thickness of the second spacer pillar 133 in the second patterned region 200 (which is the target thickness).
[0092] As an example, the etch spacer structure 130 can be removed by etching using an ICP process.
[0093] S106, Remove fill layer.
[0094] In embodiments of this application, after etching to obtain a thickness difference of 0 or a reverse thickness difference between the second spacer 133 located in the first patterned region 100 and the second spacer 133 located in the second patterned region 200, the filler layer 140 is removed, thereby exposing the protrusion structure 120. (Refer to...) Figure 16 or Figure 17 As shown.
[0095] As an example, the etch fill layer 140 can be removed by etching using an ICP process.
[0096] refer to Figure 16 As shown, the thickness difference between the thickness of the second spacer 133 located in the first graphic region 100 and the thickness of the second spacer 133 located in the second graphic region 200 is 0.
[0097] refer to Figure 17 As shown, the thickness of the second spacer 133 located in the first graphic region 100 is less than the thickness of the second spacer 133 located in the second graphic region 200, forming a reverse thickness difference.
[0098] Therefore, by forming an etch stop layer on the structure to be planarized, etching away the etch stop layers located in the first patterned region and the connection region, and using the etch stop layer located in the second patterned region as a mask, etching the spacer structure located in the first patterned region, the total thickness of the film layer in the first patterned region is reduced until the thickness of the spacer structure located in the first patterned region is less than or equal to the thickness of the spacer structure located in the second patterned region. This reduces the thickness difference between the first and second patterned regions, and may even further achieve a reverse thickness difference between the first and second patterned regions to meet the requirements of various patterned region thickness variations. The thickness difference between the spacer structure located in the first patterned region and the spacer structure located in the second patterned region is not affected in subsequent etching processes such as removing the etch stop layer, removing the preset thickness of the spacer structure, and removing the filler layer. This results in a second spacer pillar with a corresponding thickness difference between the first and second patterned regions, ultimately reducing the thickness difference of the second spacer pillar or even forming a reverse thickness difference to meet the requirements for further improvement of chip performance.
[0099] refer to Figure 18 As shown, Figure 18 The diagram illustrates the effects of three loading optimization schemes. Figure 18 The three processes for optimizing thickness difference include inductively coupled plasma (ICP) combined with chemical mechanical polishing (CMP+Etching Back), ion beam sputtering (IBS), and ICP combined with ion beam sputtering (Etching Back+IBS). Among them, ICP combined with ion beam sputtering is the thickness difference optimization method provided in this application. Figure 18 The vertical axis includes the Sacrifical Layer Thickness (THK), the initial thickness difference between dense and sparse graphic regions (Dense and ISO Loading), and the optimized thickness difference (Loading Optimization Value). Figure 18 For each optimized thickness difference process, the leftmost bar chart represents the sacrifice layer thickness consumption, the middle bar chart represents the initial thickness difference between dense and sparse pattern regions, and the rightmost bar chart represents the optimized thickness difference. Figure 18 It can be seen that among the three processes for optimizing thickness difference, only the thickness difference optimization process provided in this application embodiment consumes the least amount of sacrificial layer thickness and can reduce the thickness difference to 0, or even form a reverse thickness difference, to meet the need for further improvement of chip performance.
[0100] Based on the planarization control method provided in the above embodiments, this application also provides a semiconductor structure, which will be described in detail below with reference to the accompanying drawings.
[0101] See Figure 16 or Figure 17 As shown in the figure, this figure is a schematic diagram of a semiconductor structure provided in an embodiment of this application.
[0102] The semiconductor structure provided in this application embodiment is the structure after planarization of the structure to be planarized in the above embodiments. The semiconductor structure includes a first patterned region 100 and a second patterned region 200, and a connection region 300 is further provided between the first patterned region 100 and the second patterned region 200.
[0103] The semiconductor structure includes a substrate 110 and a plurality of protrusion structures 120 located on one side of the substrate 110, wherein the density of the protrusion structures 120 located in the first patterned region 100 and the second patterned region 200 is different.
[0104] Multiple second spacer pillars 133, the multiple second spacer pillars 133 are spaced apart from multiple protrusions 120 located in the first graphic region 100 and multiple protrusions 120 located in the second graphic region 200.
[0105] The thickness of the second spacer 133 located in the first graphic region 100 is less than or equal to the thickness of the second spacer 133 located in the second graphic region 200.
[0106] refer to Figure 16 As shown, the thickness difference between the thickness of the second spacer 133 located in the first graphic region 100 and the thickness of the second spacer 133 located in the second graphic region 200 is 0.
[0107] refer to Figure 17 As shown, the thickness of the second spacer 133 located in the first graphic region 100 is less than the thickness of the second spacer 133 located in the second graphic region 200, forming a reverse thickness difference.
[0108] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.
Claims
1. A flattening control method, characterized in that, The method includes: A structure to be planarized is provided, the structure to be planarized including a substrate, a plurality of protrusions, spacers, and a filler layer. The spacers include a plurality of first spacers and a spacer layer, the plurality of first spacers separating the plurality of protrusions. The filler layer covers the protrusions, the spacers cover the filler layer, and the first spacers penetrate the filler layer and contact the spacers. The structure to be planarized includes a first patterned region, a second patterned region, and a connecting region. The density of the protrusions in the first patterned region and the second patterned region is different. The connecting region is located between the first patterned region and the second patterned region. The thickness of the filler layer in the first patterned region gradually decreases through the connecting region to the thickness of the filler layer in the second patterned region. The thickness of the spacers in the first patterned region gradually decreases through the connecting region to the thickness of the spacers in the second patterned region. An etch stop layer is formed on the structure to be planarized, and the etch stop layer located in the first pattern region and the connection region is etched away. Using the etching stop layer located in the second pattern region as a mask, the spacing structure located in the first pattern region is etched until the thickness of the spacing structure located in the first pattern region is less than or equal to the thickness of the spacing structure located in the second pattern region; The etching stop layer is removed by etching. The preset thickness of the spacer structure is removed by etching to obtain a second spacer column with a thickness smaller than that of the protrusion structure. Remove the filler layer.
2. The method according to claim 1, characterized in that, There is an etching selectivity ratio between the etching stop layer and the spacer structure; When the etch stop layer located in the second pattern region is used as a mask to etch the spacer structure located in the first pattern region, the etch selectivity ratio between the spacer structure and the etch stop layer is greater than the first selectivity threshold.
3. The method according to claim 1, characterized in that, The thickness of the etching stop layer is less than or equal to a first thickness threshold.
4. The method according to claim 1, characterized in that, The thickness of the spacer structure located in the first graphic region is equal to the thickness of the spacer structure located in the second graphic region, and the thickness of the second spacer column located in the first graphic region is equal to the thickness of the second spacer column located in the second graphic region.
5. The method according to claim 1, characterized in that, The target thickness is defined as the thickness of the spacer structure located in the first graphic region being less than the thickness of the spacer structure located in the second graphic region, and the target thickness is defined as the thickness of the second spacer column located in the first graphic region being less than the thickness of the second spacer column located in the second graphic region.
6. The method according to claim 5, characterized in that, The target thickness is less than the second thickness threshold.
7. The method according to claim 1, characterized in that, Before etching away the etch stop layer located in the first patterned region and the connected region, the method further includes: A capping layer is formed on the etch stop layer, wherein the surface of the capping layer away from the substrate is flush with the surface of the etch stop layer away from the substrate; The etching removal of the etching stop layer located in the first patterned region and the connection region includes: The etching removes the etch stop layer and a portion of the cover layer located in the first patterned area; Remove the covering layer; The etching stop layer located in the connection region is removed by etching, while the etching stop layer located in the second pattern region is retained.
8. The method according to claim 7, characterized in that, The etching process to remove the etch stop layer located in the connection region includes: The etching stop layer located in the connection region is removed by ion beam sputtering.
9. The method according to any one of claims 1-8, characterized in that, The etching stop layer is made of one or more of SiN, TiN, TiO, W, TaN, and Ta. The spacer layer is made of the same material as the first spacer pillar, and the spacer layer is made of a low-temperature oxide.
10. A semiconductor structure, characterized in that, The semiconductor structure includes a first patterned region and a second patterned region; The substrate and multiple protrusions located on one side of the substrate, with different densities of the protrusions located in the first patterned region and the second patterned region; A plurality of second spacer columns, the plurality of second spacer columns being spaced apart from a plurality of protrusions located in the first graphic region and spaced apart from the plurality of protrusions located in the second graphic region; The thickness of the second spacer located in the first graphic region is less than or equal to the thickness of the second spacer located in the second graphic region.