Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure, comprising: forming a first dielectric material layer on a substrate surface, the first dielectric material layer being located on sidewalls of the first dummy gate structure and the second dummy gate structure, the first dielectric material layer thickness on the first region being greater than the second dielectric material layer thickness on the second region; forming a second dielectric material layer on the first dielectric material layer, the second dielectric material layer thickness on the first region being less than the second dielectric material layer thickness on the second region; planarizing the first dielectric material layer and the second dielectric material layer until the first dummy gate and the second dummy gate are exposed, a first transition dielectric layer being formed by the first dielectric material layer; etching back the first transition dielectric layer to form a first initial dielectric layer; forming a protective layer on a surface of the first initial dielectric layer. The method improves the control window of the gate forming process.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure. Background Technology

[0002] With the continuous development of integrated circuit manufacturing technology, in order to achieve faster computing speeds, larger data storage capacity, and more functions, integrated circuit chips are moving towards higher device density and higher integration. As the feature size of devices continues to shrink to the nanometer scale, polysilicon gate technology can no longer meet the requirements of existing technologies. The semiconductor industry uses metal gates (MG) to replace polysilicon gate electrodes to solve problems such as threshold voltage drift, polysilicon gate depletion effect, excessively high gate resistance, and Fermi level pinning.

[0003] As device feature sizes continue to decrease, there is a need to reduce the metal gate height to obtain lower effective capacitance. However, in metal-substituted gate processes, it is difficult to achieve precise control over low-height metal gates due to factors such as wafer uniformity and loading effects during etching.

[0004] Therefore, the existing metal gate forming process needs further improvement. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a method for forming a semiconductor structure to improve the performance of the formed semiconductor structure.

[0006] To solve the above-mentioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first region and a second region; forming a first dummy gate structure on the first region and a second dummy gate structure on the second region, the first dummy gate structure including a first dummy gate and the second dummy gate structure including a second dummy gate, wherein the distance between adjacent first dummy gate structures is smaller than the distance between adjacent second dummy gate structures; forming a first dielectric material layer on the surface of the substrate, the first dielectric material layer being located on the sidewalls of the first dummy gate structure and the second dummy gate structure, the surface of the first dielectric material layer being higher than or flush with the top surface of the second dummy gate structure, and the thickness of the first dielectric material layer on the first region being greater than that on the second region. The thickness of the second dielectric material layer; forming a second dielectric material layer on the first dielectric material layer, wherein the thickness of the second dielectric material layer on the first region is less than the thickness of the second dielectric material layer on the second region; planarizing the first dielectric material layer and the second dielectric material layer until the first dummy gate and the second dummy gate are exposed, forming a first transition dielectric layer with the first dielectric material layer; etching back the first transition dielectric layer to form a first initial dielectric layer; forming a protective layer on the surface of the first initial dielectric layer, the protective layer being located on the sidewalls of the first dummy gate and the second dummy gate and exposing the first dummy gate and the second dummy gate; after forming the protective layer, forming a first gate to replace the first dummy gate, and forming a second gate to replace the second dummy gate.

[0007] Optionally, the method for planarizing the first dielectric material layer and the second dielectric material layer includes: planarizing the second dielectric material layer using a first mechanochemical polishing process until the first dielectric material layer is exposed, wherein the polishing rate of the first mechanochemical polishing process on the second dielectric material layer is greater than the polishing rate on the first dielectric material layer; and after the first mechanochemical polishing process, planarizing the first dielectric material layer using a second mechanochemical polishing process until the first dummy gate and the second dummy gate are exposed.

[0008] Optionally, the material of the first dielectric material layer includes silicon oxide; the formation process of the first dielectric material layer includes fluid chemical vapor deposition; the material of the second dielectric material layer includes silicon oxide; the formation process of the second dielectric material layer includes plasma enhanced chemical vapor deposition.

[0009] Optionally, the first dummy gate structure further includes a first dummy gate dielectric layer located between the first dummy gate and the substrate; the second dummy gate structure further includes a second dummy gate dielectric layer located between the second dummy gate and the substrate; the material of the protective layer is different from the materials of the first dummy gate dielectric layer and the second dummy gate dielectric layer.

[0010] Optionally, the method for the first gate and the second gate includes: removing the first dummy gate, the second dummy gate, the first dummy gate dielectric layer, and the second dummy gate dielectric layer; forming a gate trench in the first initial dielectric layer and the protective layer; forming a gate material layer in the gate trench and on the surface of the protective layer; planarizing the gate material layer until the surface of the first initial dielectric layer on the first region is exposed; forming the first gate with the gate material layer on the first region; forming the second gate with the gate material layer on the second region; and forming the first dielectric layer with the first initial dielectric layer.

[0011] Optionally, the first region includes a first isolation region. After forming the first gate and the second gate, a first isolation structure is formed in the first dielectric layer and the first gate on the first isolation region. The method for forming the first isolation structure includes: forming a first hard mask layer on the surfaces of the first dielectric layer, the first gate, and the second gate, wherein the first hard mask layer exposes the first gate on the first isolation region; using the first hard mask layer as a mask, removing the first gate on the first isolation region, thereby forming a first isolation opening in the first dielectric layer and the first gate; and forming the first isolation structure in the first isolation opening.

[0012] Optionally, the substrate has fins, with the first gate spanning the fins over the first region and located on a portion of the fin sidewalls and top surface.

[0013] Optionally, the first region further includes a second isolation region, and the method further includes: after forming the first isolation structure, patterning the first hard mask layer to form a second hard mask layer, the second hard mask layer exposing the fin on the second isolation region; using the second hard mask layer as a mask, etching the fin to form a second isolation opening in the fin; and forming a second isolation structure in the second isolation opening.

[0014] Optionally, the method for planarizing the gate material layer includes: planarizing the gate material layer using a third mechanochemical polishing process until the surface of the protective layer is exposed to form an initial gate; and planarizing the initial gate using a fourth mechanochemical polishing process after the third mechanochemical polishing process.

[0015] Optionally, after the third mechanochemical polishing process and before the fourth mechanochemical polishing process, the process further includes: removing the protective layer.

[0016] Optionally, the method for forming the protective layer includes: forming a protective material layer on the top surfaces of the first initial dielectric layer, the first dummy gate, and the second dummy gate; planarizing the protective material layer until the surfaces of the first dummy gate and the second dummy gate are exposed.

[0017] Optionally, the process for forming the protective material layer includes atomic layer deposition.

[0018] Optionally, the material of the protective material layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride.

[0019] Optionally, the method for planarizing the protective material layer includes: forming a third dielectric material layer on the surface of the protective material layer, the material of the third dielectric material layer being different from the material of the protective material layer; planarizing the third dielectric material layer using a fifth mechanical-chemical polishing process until the surface of the protective material layer is exposed; and after the fifth mechanical-chemical polishing process, etching back the protective material layer until the top surfaces of the first dummy gate and the second dummy gate are exposed.

[0020] Optionally, the first region further includes an isolation region. After forming the protective material layer and before forming the protective layer, an isolation structure is formed within the first initial dielectric layer and the first dummy gate on the isolation region. The method for forming the isolation structure includes: patterning the protective material layer; forming a third hard mask layer with the protective material layer; exposing the first dummy gate on the isolation region with the third hard mask layer; etching the first dummy gate with the third hard mask layer as a mask; forming an isolation opening within the first initial dielectric layer and the first dummy gate; and forming an isolation structure within the isolation opening.

[0021] Optionally, the method for forming the isolation structure includes: forming an insulating material layer inside the isolation opening and on the surface of the third hard mask layer before planarizing the protective material layer; and forming the isolation structure with the insulating material layer after the planarization process of the protective material layer.

[0022] Optionally, the insulating material layer may be made of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride.

[0023] Optionally, the material of the first dielectric material layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride; the material of the second dielectric material layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0024] Optionally, before forming the first dielectric material layer, an etch stop layer is also formed on the surfaces of the substrate, the first dummy gate structure, and the second dummy gate structure.

[0025] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0026] In the semiconductor structure formation method provided by the present invention, on the one hand, a first dielectric material layer and a second dielectric material layer are formed on the surface of the substrate. The thickness of the first dielectric material layer on the first region is greater than the thickness of the second dielectric material layer on the second region, and the thickness of the second dielectric material layer on the first region is less than the thickness of the second dielectric material layer on the second region, so as to make the surface of the second dielectric material layer relatively flat and reduce the surface non-uniformity caused by the different film thicknesses in subsequent planarization. On the other hand, by planarizing the first dielectric material layer and the second dielectric material layer, the first dummy gate and the second dummy gate are exposed. Then, by controlling the gate height by controlling the height of the dummy gate, the etching difference of the sidewall height caused by the difference in device density in different regions is avoided in the process of controlling the gate height by the sidewall. In addition, a protective layer is formed on the surface of the first initial dielectric layer. The protective layer plays a role in protecting the first initial dielectric layer during the mechanochemical polishing process of replacing the first dummy gate to form the first gate and replacing the second dummy gate to form the second gate, further improving the control window of the gate formation process.

[0027] Furthermore, during the planarization process using the first and second mechanochemical polishing processes to expose the first and second dummy gates, the surface flatness can be increased by adjusting the polishing process. Specifically, since the device density in the first region is greater than that in the second region, after the first mechanochemical polishing process, there is a second dielectric material layer residue on the surface of the first dielectric material layer in the second region. In the second mechanochemical polishing process, a process with similar polishing and etching ratios for the first and second dielectric material layers can be selected to obtain a relatively flat surface, which is beneficial for precise control of the formed gate height.

[0028] Furthermore, the material of the first dielectric material layer includes silicon oxide; the formation process of the first dielectric material layer includes fluid chemical vapor deposition; the material of the second dielectric material layer includes silicon oxide; the formation process of the second dielectric material layer includes plasma enhanced chemical vapor deposition. The fluid chemical vapor deposition process facilitates the filling of the dielectric material layer between adjacent first gate structures and adjacent second gate structures, reducing the generation of abnormalities such as voids and defects. The plasma enhanced chemical vapor deposition process facilitates the formation of a smooth second dielectric material layer, which is beneficial for controlling the surface smoothness in subsequent planarization processes, thereby improving the process window for gate height control.

[0029] Furthermore, the first pseudo-gate structure further includes a first pseudo-gate dielectric layer, and the second pseudo-gate structure further includes a second pseudo-gate dielectric layer. During the etching process of removing the first pseudo-gate dielectric layer and the second pseudo-gate dielectric layer, the protective layer plays a role in protecting the first initial dielectric layer, reducing over-etching of the first initial dielectric layer, and preventing unevenness on the device surface.

[0030] Furthermore, a third hard mask layer is formed using the protective material layer, and the first dummy gate is etched using the third hard mask layer as a mask. An isolation opening is formed in the first initial dielectric layer and the first dummy gate, and an isolation structure is formed in the isolation opening. The protective material layer is used as the third hard mask layer when forming the protective layer and the isolation opening, which can save materials and reduce production costs.

[0031] Furthermore, the first hard mask layer is patterned to form a second hard mask layer. Using the second hard mask layer as a mask, the fin and the first gate on the second isolation region are etched, forming a second isolation opening within the fin, and a second isolation structure within the second isolation opening. The first hard mask layer serves as a mask when the first isolation opening is formed on the first gate, and also serves to form the second hard mask layer to cut off the fin and form the second isolation opening, saving mask material and helping to reduce production costs. Attached Figure Description

[0032] Figures 1 to 7 This is a schematic diagram of the steps in a method for forming an existing semiconductor structure.

[0033] Figures 8 to 25 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention;

[0034] Figures 26 to 35 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to another embodiment of the present invention. Detailed Implementation

[0035] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0036] As described in the background section, existing metal gate formation processes require further improvement. A method for forming a semiconductor structure will now be explained and analyzed.

[0037] Figures 1 to 7 This is a schematic diagram of the steps involved in forming an existing semiconductor structure.

[0038] Please refer to Figure 1 A substrate 100 is provided, the substrate 100 including a first region I and a second region II; a first dummy gate structure and a second dummy gate structure are formed on the substrate 100, the first dummy gate structure being located on the first region I and the second dummy gate structure being located on the second region II. The first dummy gate structure includes a first initial dummy gate 101, a first hard mask layer located on the first initial dummy gate 101, and a first initial sidewall 102 located on the sidewalls of the first initial dummy gate 101 and the first hard mask layer. The first hard mask layer includes a first silicon nitride layer 103 and a first silicon oxide layer 104 located on the first silicon nitride layer 103. The second dummy gate structure includes a second initial dummy gate 201, a second hard mask layer located on the second initial dummy gate 201, and a second initial sidewall 202 located on the sidewalls of the second initial dummy gate 201 and the second hard mask layer. The second hard mask layer includes a second silicon oxide layer 203 and a second silicon oxide layer 204 located on the second silicon nitride layer 203. The distance between adjacent first dummy gate structures is smaller than the distance between adjacent second dummy gate structures. An etch stop layer 105 is formed on the substrate, the first dummy gate structure, and the second dummy gate structure. A spin-coated carbon material layer 106 is formed on the surface of the etch stop layer 105.

[0039] Please refer to Figure 2 A patterned layer (not shown in the figure) is formed on the surface of the spin-coated carbon material layer 106, and the surface of the patterned layer exposes the etch stop layer 105 on the top surface of the first dummy gate structure and the second dummy gate structure. The etch stop layer 105, the first initial sidewall 102 and the second initial sidewall 202 are etched to form a first transition sidewall 107 with the first initial sidewall 102 and a second sidewall 207 with the second initial sidewall 202. After forming the first transition sidewall 107 and the second sidewall 207, the spin-coated carbon material layer 106 is removed.

[0040] Please refer to Figure 3After removing the spin-coated carbon material layer 106, a dielectric material layer 108 is formed on the surface of the substrate 100, and the dielectric material layer 108 exposes the first silicon nitride layer 103 and the second silicon nitride layer 203.

[0041] Please refer to Figure 4 After the dielectric material layer 108 is formed, the first silicon nitride layer 103 and the second silicon nitride layer 203 are removed by selective etching process, and the first transition sidewall 107 is etched to form the first intermediate sidewall 109.

[0042] Please refer to Figure 5 The first intermediate sidewall 109, the first initial dummy gate 101, and the second initial dummy gate 201 are etched back, and the first sidewall 110 is formed with the first intermediate sidewall 109, the first dummy gate 111 is formed with the first initial dummy gate 101, and the second dummy gate 211 is formed with the second initial dummy gate 201.

[0043] Please refer to Figure 6 Remove the first dummy gate 111 and the second dummy gate 211, and form a gate groove (not shown in the figure) in the dielectric material layer 108; form a gate material layer 112 on the surface of the gate groove and the dielectric material layer 108.

[0044] Please refer to Figure 7 The gate material layer 112 and the dielectric material layer 108 are planarized until the first sidewall 110 and the second sidewall 207 are exposed. A dielectric layer 113 is formed with the dielectric material layer 108, a first gate 114 is formed with the gate material layer 112 on the first region I, and a second gate 214 is formed with the gate material layer 112 on the second region II.

[0045] The above method is used in the metal gate replacement process, where the heights of the first gate 114 and the second gate 214 are controlled by controlling the heights of the first sidewall 110 and the second sidewall 207. The first region I is used to form a short-channel device region, and the second region II is used to form a long-channel device region. During the etching of the first initial sidewall 102 and the second initial sidewall 202 using the spin-coated carbon material layer 106 as a protective layer, due to the different pattern densities of the first region I and the second region II, the thickness of the spin-coated carbon material layer 106 on the second region II is lower than that on the first region I. Furthermore, the spin-coated carbon material layer 106 on the second region II is more easily consumed during etching, resulting in the second sidewall 207 formed on the second region II being lower than the first transition sidewall 107 formed on the first region I. This height difference between the second sidewall 207 and the first transition sidewall 107 is detrimental to the precise control of the metal gate height and reduces the flatness of the device surface.

[0046] To address the aforementioned problems, this invention provides a method for forming a semiconductor structure. On one hand, a first dielectric material layer and a second dielectric material layer are formed on the surface of a substrate. The thickness of the first dielectric material layer in the first region is greater than the thickness of the second dielectric material layer in the second region, and the thickness of the second dielectric material layer in the first region is less than the thickness of the second dielectric material layer in the second region. This makes the surface of the second dielectric material layer relatively flat, reducing surface inhomogeneity caused by the different film thicknesses during subsequent planarization. On the other hand, by planarizing the first and second dielectric material layers, the first and second dummy gates are exposed. The gate height is then controlled by controlling the height of the dummy gates, avoiding etching differences in sidewall height caused by device density differences in different regions during the sidewall-controlled gate height process. Furthermore, a protective layer is formed on the surface of the first initial dielectric layer. This protective layer protects the first initial dielectric layer during the mechanochemical polishing process, where the first dummy gate is replaced to form the first gate, and the second dummy gate is replaced to form the second gate, further improving the control window of the gate formation process.

[0047] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0048] Figures 8 to 25 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention.

[0049] Please refer to Figure 8 and Figure 9 , Figure 9 for Figure 8A top-view structural diagram. Figure 8 yes Figure 9 A cross-sectional structural diagram along the EE1 direction is provided, and the substrate 301 includes a first region I and a second region II.

[0050] The substrate 301 can be monocrystalline silicon, polycrystalline silicon, or amorphous silicon, or it can be a semiconductor material such as germanium, silicon germanide, or gallium arsenide, or it can be a semiconductor-on-insulator structure.

[0051] The substrate 301 can be a planar structure or a non-planar structure, such as having fins formed within it. In this embodiment, the substrate 301 is single-crystal silicon and has a planar structure.

[0052] The first region I is used to form a short-channel device; the second region II is used to form a long-channel device. In this embodiment, the first region I further includes an isolation region A.

[0053] Please continue to refer to this. Figure 8 and Figure 9 A first pseudo-gate structure is formed on the first region I, and a second pseudo-gate structure is formed on the second region II. The first pseudo-gate structure includes a first pseudo-gate 302, and the second pseudo-gate structure includes a second pseudo-gate 402. The distance between adjacent first pseudo-gate structures is smaller than the distance between adjacent second pseudo-gate structures.

[0054] The first dummy gate 302 is made of silicon; the second dummy gate 402 is also made of silicon. In this embodiment, both the first dummy gate 302 and the second dummy gate 402 are made of silicon. In other embodiments, the first dummy gate 302 may be made of polycrystalline silicon, amorphous carbon, etc.; and the second dummy gate 402 may be made of polycrystalline silicon, amorphous carbon, etc.

[0055] In this embodiment, the first pseudo gate structure further includes a first pseudo gate dielectric layer 303, which is located between the first pseudo gate 302 and the substrate 301; the second pseudo gate structure further includes a second pseudo gate dielectric layer 403, which is located between the second pseudo gate 402 and the substrate 301.

[0056] In this embodiment, the first dummy gate structure further includes a second hard mask layer 304 located on the first dummy gate 302; the second dummy gate structure further includes a third hard mask layer 404 located on the second dummy gate 402.

[0057] In this embodiment, the first dummy gate structure further includes a first sidewall 306 located on the sidewalls of the first dummy gate 302, the second hard mask layer 304, and the first dummy gate dielectric layer 303; the second dummy gate structure further includes a second sidewall 406 located on the sidewalls of the second dummy gate 402, the third hard mask layer 404, and the second dummy gate dielectric layer 403.

[0058] Subsequently, a first dielectric material layer is formed on the surface of the substrate 301.

[0059] In this embodiment, before forming the first dielectric material layer, an etch stop layer 305 is formed on the surfaces of the substrate 301, the first dummy gate structure, and the second dummy gate structure. In other embodiments, the etch stop layer 305 may not be formed.

[0060] It should be noted that, Figure 9 The etching stop layer 305 is omitted in the text.

[0061] Please refer to Figure 10 , Figure 10 The view direction is the same Figure 8 A first dielectric material layer 307 is formed on the surface of the substrate 301. The first dielectric material layer 307 is located on the sidewalls of the first dummy gate structure and the second dummy gate structure. The surface of the first dielectric material layer 307 is higher than or flush with the top surface of the second dummy gate structure. The thickness of the first dielectric material layer 307 on the first region I is greater than the thickness of the first dielectric material layer 307 on the second region II. A second dielectric material layer 308 is formed on the first dielectric material layer 307. The thickness of the second dielectric material layer 308 on the first region I is less than the thickness of the second dielectric material layer 308 on the second region II.

[0062] The thickness of the first dielectric material layer 307 on the first region I is greater than the thickness of the second dielectric material layer 308 on the second region II, and the thickness of the second dielectric material layer 308 on the first region I is less than the thickness of the second dielectric material layer 308 on the second region II, so that the surface of the second dielectric material layer 308 is relatively flat and the surface unevenness caused by the different film thicknesses in subsequent planarization is reduced.

[0063] The material of the first dielectric material layer 307 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, silicon carbonitride, and silicon carbonitride; the material of the second dielectric material layer 308 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, and silicon carbonitride.

[0064] In this embodiment, the material of the first dielectric material layer 307 includes silicon oxide; the formation process of the first dielectric material layer 307 includes a fluid chemical vapor deposition process; the material of the second dielectric material layer 308 includes silicon oxide; the formation process of the second dielectric material layer 308 includes a plasma enhanced chemical vapor deposition process.

[0065] The fluid chemical vapor deposition (FCVD) process facilitates filling between adjacent first gate structures and adjacent second gate structures, reducing the generation of void defects and other anomalies. Since the device density in the first region I is higher than that in the second region II, the thickness of the first dielectric material layer 307 on the first region I is greater than that on the second region II under the FCVD process. The plasma-enhanced chemical vapor deposition (PECVD) process facilitates the formation of a relatively flat surface for the second dielectric material layer 308, which is beneficial for controlling the surface flatness in subsequent planarization processes, thereby improving the process window for gate height control.

[0066] Subsequently, the first dielectric material layer 307 and the second dielectric material layer 308 are planarized until the first dummy gate 302 and the second dummy gate 402 are exposed, and the first dielectric material layer 307 forms the first transition dielectric layer.

[0067] For the method of planarizing the first dielectric material layer 307 and the second dielectric material layer 308, please refer to [reference needed]. Figure 11 .

[0068] Please refer to Figure 11 , Figure 11 The view direction is the same Figure 8 The second dielectric material layer 308 is planarized using a first mechanochemical polishing process until the first dielectric material layer 307 is exposed. The polishing rate of the first mechanochemical polishing process on the second dielectric material layer 308 is greater than the polishing rate on the first dielectric material layer 307. After the first mechanochemical polishing process, the first dielectric material layer 307 is planarized using a second mechanochemical polishing process until the first dummy gate 302 and the second dummy gate 402 are exposed.

[0069] In this embodiment, the first dielectric material layer 307 serves as the stop layer for planarization in the first mechanical-chemical polishing process. In other embodiments, the etching stop layer 305 can be used as the stop layer for planarization in the first mechanical-chemical polishing process.

[0070] During the planarization process using the first and second mechanochemical polishing processes to expose the first dummy gate 302 and the second dummy gate 402, the surface flatness is increased by adjusting the polishing process. Specifically, since the device density in the first region I is greater than that in the second region II, after the first mechanochemical polishing process, the surface of the first dielectric material layer 307 on the second region II has a second dielectric material layer 308 remaining. In the second mechanochemical polishing process, a process with a similar polishing and etching ratio for the first dielectric material layer 307 and the second dielectric material layer 308 is selected, which can obtain a first transition dielectric layer 309 with a relatively flat surface, which is beneficial for precise control of the formed gate height.

[0071] In this embodiment, the thickness difference between the first transition medium layer 309 on the second region II and the first transition medium layer 309 on the first region I is less than 50 angstroms, resulting in good flatness.

[0072] By planarizing the first dielectric material layer 307 and the second dielectric material layer 308, the first dummy gate 302 and the second dummy gate 402 are exposed. Then, by controlling the gate height by controlling the dummy gate height, the etching difference of the sidewall height caused by the difference in device density in different regions is avoided in the process of controlling the gate height by the sidewall.

[0073] Please refer to Figure 12 The first transition dielectric layer 309 is etched back to form the first initial dielectric layer 310.

[0074] The process of etching back the first transition dielectric layer 309 includes a dry etching process.

[0075] Subsequently, a protective layer is formed on the surface of the first initial dielectric layer 310. This protective layer is located on the sidewalls of the first dummy gate 302 and the second dummy gate 402, and exposes the first dummy gate 302 and the second dummy gate 402. For the method of forming the protective layer, please refer to [reference needed]. Figures 13 to 18 .

[0076] Please refer to Figure 13 A protective material layer 311 is formed on the top surface of the first initial dielectric layer 310, the first dummy gate 302 and the second dummy gate 402.

[0077] In this embodiment, the protective material layer 311 is formed using atomic layer deposition (ALD). ALD is beneficial for improving the quality of the protective material layer 311 and reducing the generation of defects.

[0078] The protective material layer 311 is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride. In this embodiment, the protective material layer 311 is made of silicon nitride.

[0079] The material of the protective material layer 311 is different from the materials of the first pseudo-gate dielectric layer 303 and the second pseudo-gate dielectric layer 403. The protective material layer 311 is used to form a protective layer.

[0080] Subsequently, the protective material layer 311 is planarized until the surfaces of the first dummy gate 302 and the second dummy gate 402 are exposed.

[0081] In this embodiment, after forming the protective material layer 311 and before forming the protective layer, an isolation structure is also formed within the first initial dielectric layer 310 and the first dummy gate 302 on the isolation region A. For the method of forming the isolation structure, please refer to... Figures 14 to 18 .

[0082] Please refer to Figure 14 and Figure 15 , Figure 14 for Figure 15 A schematic diagram of the cross-sectional structure along the EE1 direction. Figure 15 yes Figure 14 A top view of the structure is shown, illustrating the protective material layer 311. A third hard mask layer (not shown) is formed using the protective material layer 311, which exposes the first dummy gate 302 on the isolation region A. The first dummy gate 302 is etched using the third hard mask layer 312 as a mask, forming an isolation opening 313 within the first initial dielectric layer 310 and the first dummy gate 302.

[0083] The protective material layer 311 is used to form a protective layer, and the protective material layer 311 is also used to form the third hard mask layer, which is used to form the isolation opening 313. No additional mask material is required, which can save materials and reduce production costs.

[0084] Subsequently, an isolation structure is formed within the isolation opening 313. For the method of forming the isolation structure, please refer to [reference needed]. Figures 16 to 18 .

[0085] Please refer to Figure 16 Before planarizing the protective material layer 311, an insulating material layer 407 is formed inside the isolation opening 313 and on the surface of the third hard mask layer 312.

[0086] The insulating material layer 407 is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride.

[0087] Subsequently, the protective material layer 311 is planarized until the surfaces of the first dummy gate 302 and the second dummy gate 402 are exposed. After the planarization process of the protective material layer 311, the isolation layer is formed with the insulating material layer 407.

[0088] In this embodiment, the method for planarizing the protective material layer is described in reference [reference needed]. Figures 16 to 19 .

[0089] Please continue to refer to this. Figure 16 A third dielectric material layer 314 is formed on the surface of the protective material layer 311, and the material of the third dielectric material layer 314 is different from the material of the protective material layer 311.

[0090] The material of the third dielectric material layer 314 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the third dielectric material layer 314 is silicon oxide.

[0091] In this embodiment, the third dielectric material layer 314 is formed by plasma-enhanced chemical vapor deposition (PECVD). The PECVD process helps improve the smoothness of the surface of the third dielectric material layer 314 by addressing the unevenness of the preceding material film (i.e., the protective material layer 311).

[0092] Please refer to Figure 17 The third dielectric material layer 314 is planarized using a fifth mechanical chemical polishing process until the surface of the protective material layer 311 is exposed.

[0093] Because the surface of the protective material layer 311 is uneven, after the fifth mechanical and chemical polishing process, some of the third medium material layer 314 remains on the surface of the protective material layer 311.

[0094] Please refer to Figure 18 After the fifth mechanical-chemical polishing process, the protective material layer 311 is etched back until the top surfaces of the first dummy gate 302 and the second dummy gate 402 are exposed, forming the protective layer 315 with the protective material layer 311 and the isolation layer 408 with the isolation material layer 407.

[0095] The material of the protective layer 315 is different from the materials of the first pseudo-gate dielectric layer 303 and the second pseudo-gate dielectric layer 403. In this embodiment, the material of the protective layer 315 is silicon nitride.

[0096] The process of etching back the protective material layer 311 includes a non-selective dry etching process. The non-selective dry etching process has a similar etching rate for the protective material layer 311 and the third dielectric material 314, which can obtain a protective layer 315 with a relatively flat surface, so as to facilitate the subsequent precise control of the gate height.

[0097] Subsequently, after forming the protective layer 315, a first gate is formed to replace the first dummy gate 302, and a second gate is formed to replace the second dummy gate 402. For the methods of forming the first gate and the second gate, please refer to [reference needed]. Figures 19 to 25 .

[0098] Please refer to Figure 19 Remove the first dummy gate 302, the second dummy gate 402, the first dummy gate dielectric layer 303 and the second dummy gate dielectric layer 403, and form a gate trench 316 in the first initial dielectric layer 310 and the protective layer 315.

[0099] During the etching process of removing the first dummy gate dielectric layer 303 and the second dummy gate dielectric layer 403, the protective layer 315 serves to protect the first initial dielectric layer 310. An etching process with a large selectivity between the first dummy gate dielectric layer 303 and the second dummy gate dielectric layer 403 and the protective layer 315 can be selected to reduce over-etching of the first initial dielectric layer 310 and improve the flatness of the device surface.

[0100] Please refer to Figure 20 A gate material layer 317 is formed in the gate trench 316 and on the surface of the protective layer 315.

[0101] The material of the gate material layer 317 includes metal.

[0102] In this embodiment, before forming the gate material layer 317, a gate dielectric layer 407 is also formed at the bottom of the gate trench 316.

[0103] Subsequently, the gate material layer 317 is planarized until the surface of the first initial dielectric layer 310 on the first region I is exposed. The first gate is formed with the gate material layer 317 on the first region I, the second gate is formed with the gate material layer 317 on the second region II, and the first dielectric layer is formed with the first initial dielectric layer 310. For the method of planarizing the gate material layer, please refer to [reference needed]. Figures 21 to 25 .

[0104] Please refer to Figure 21 and Figure 22 , Figure 21 for Figure 22 A schematic diagram of the cross-sectional structure along the EE1 direction. Figure 22 yes Figure 21The top view of the structure shows that the gate material layer 317 is planarized using a third mechanical chemical polishing process until the surface of the protective layer 315 is exposed, forming the initial gate 318.

[0105] In the third mechanical-chemical polishing process, the protective layer 315 serves to protect the first initial dielectric layer 310, thereby improving the process window.

[0106] Subsequently, after the third mechatronic polishing process, a fourth mechatronic polishing process is used to planarize the initial gate 318. In this embodiment, after the third mechatronic polishing process and before the fourth mechatronic polishing process, please also refer to... Figure 23 .

[0107] Please refer to Figure 23 , Figure 23 View direction same Figure 8 Remove the protective layer 315.

[0108] The process for removing the protective layer 315 includes one or a combination of dry etching and wet etching. In this embodiment, the process for removing the protective layer 315 is a dry etching process.

[0109] The purpose of removing the protective layer 315 is to reduce the impact of the protective layer 315 on the subsequent fourth mechanical-chemical polishing process.

[0110] Please refer to Figure 24 and Figure 25 , Figure 24 for Figure 25 A schematic diagram of the cross-sectional structure along the EE1 direction. Figure 25 yes Figure 24 The top view of the structure shows that after the third mechanical-chemical polishing process, the initial gate 318 is planarized using a fourth mechanical-chemical polishing process.

[0111] The first gate 321 is formed with the gate material layer 317 on the first region I, the second gate 421 is formed with the gate material layer 317 on the second region II, and the first dielectric layer 322 is formed with the first initial dielectric layer 310.

[0112] Figures 26 to 35 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to another embodiment of the present invention.

[0113] Please refer to Figure 26 and Figure 27 , Figure 27 for Figure 26 A top-view structural diagram. Figure 26 yes Figure 27A cross-sectional view along the DD1 direction is provided, showing a substrate 501, which includes a first region I and a second region II. A first dummy gate structure is formed on the first region I, and a second dummy gate structure is formed on the second region II. The first dummy gate structure includes a first dummy gate 502, and the second dummy gate structure includes a second dummy gate 602. The distance between adjacent first dummy gate structures is smaller than the distance between adjacent second dummy gate structures.

[0114] In this embodiment, the first pseudo gate structure further includes a first pseudo gate dielectric layer 503, which is located between the first pseudo gate 502 and the substrate 501; the second pseudo gate structure further includes a second pseudo gate dielectric layer 603, which is located between the second pseudo gate 602 and the substrate 501.

[0115] In this embodiment, the substrate 501 has fins (not shown in the figure). The first dummy gate structure spans the fins on the first region I and is located on part of the fin sidewalls and top surface.

[0116] In this embodiment, the first region I includes a first isolation region M and a second isolation region (not shown in the figure). The first isolation region M is used to define the location of the gate cutoff, and the second isolation region is used to define the location of the fin cutoff.

[0117] Subsequently, a first dielectric material layer is formed on the surface of the substrate 501.

[0118] In this embodiment, before forming the first dielectric material layer, an etch stop layer 505 is formed on the surfaces of the substrate 501, the first dummy gate structure, and the second dummy gate structure. In other embodiments, the etch stop layer 505 may not be formed.

[0119] It should be noted here that... Figure 27 The etch stop layer 505 is omitted, and only the first dummy gate structure 502 is shown, while only the second dummy gate structure 602 is shown. In the following reference figures, Figures 28 to 35 The view directions are all the same Figure 26 .

[0120] Please refer to Figure 28A first dielectric material layer 507 is formed on the surface of the substrate 501. The first dielectric material layer 507 is located on the sidewalls of the first dummy gate structure and the second dummy gate structure. The surface of the first dielectric material layer 507 is higher than or flush with the top surface of the second dummy gate structure. The thickness of the first dielectric material layer 507 on the first region I is greater than the thickness of the first dielectric material layer 507 on the second region II. A second dielectric material layer 508 is formed on the first dielectric material layer 507. The thickness of the second dielectric material layer 508 on the first region I is less than the thickness of the second dielectric material layer 508 on the second region II.

[0121] Please refer to Figure 29 The first dielectric material layer 507 and the second dielectric material layer 508 are planarized until the first dummy gate 502 and the second dummy gate 602 are exposed, and the first dielectric material layer 507 is used to form the first transition dielectric layer 509.

[0122] The planarization method is the same as in the previous embodiment, and will not be described again here.

[0123] Please refer to Figure 30 The first transition dielectric layer 509 is etched back to form the first initial dielectric layer 510.

[0124] The method for re-etching the first transition dielectric layer is the same as in the previous embodiment, and will not be described again here.

[0125] Subsequently, a protective layer is formed on the surface of the first initial dielectric layer 510. This protective layer is located on the sidewalls of the first dummy gate 502 and the second dummy gate 602, and exposes the first dummy gate 502 and the second dummy gate 602. For the method of forming the protective layer, please refer to [reference needed]. Figures 31 to 33 .

[0126] Please refer to Figure 31 A protective material layer 511 is formed on the top surface of the first initial dielectric layer 510, the first dummy gate 502 and the second dummy gate 602.

[0127] Please refer to Figure 32 The protective material layer 511 is planarized until the surfaces of the first dummy gate 502 and the second dummy gate 602 are exposed, forming the protective layer 513.

[0128] The method for planarizing the protective material layer 511 includes: forming a third dielectric material layer (not shown in the figure) on the surface of the protective material layer 511, wherein the material of the third dielectric material layer is different from the material of the protective material layer 511; planarizing the third dielectric material layer using a fifth mechanical chemical polishing process until the surface of the protective material layer 511 is exposed; and after the fifth mechanical chemical polishing process, etching back the protective material layer 511 until the top surfaces of the first dummy gate 502 and the second dummy gate 602 are exposed.

[0129] Please refer to Figure 33 After the protective layer 513 is formed, a first gate 514 is formed to replace the first dummy gate 502, and a second gate 515 is formed to replace the second dummy gate 602.

[0130] The method for forming the first gate 514 and the second gate 515 includes: removing the first dummy gate 502, the second dummy gate 602, the first dummy gate dielectric layer 503, and the second dummy gate dielectric layer 603; forming a gate trench (not shown) within the first initial dielectric layer 510 and the protective layer 513; forming a gate material layer (not shown) within the gate trench and on the surface of the protective layer 513; planarizing the gate material layer until the surface of the first initial dielectric layer 510 on the first region I is exposed; forming the first gate 514 with the gate material layer on the first region I; forming the second gate 515 with the gate material layer on the second region II; and forming a first dielectric layer 516 with the first initial dielectric layer 510. The method for forming the first gate 514 and the second gate 515 is described in the previous embodiment and will not be repeated here.

[0131] In this embodiment, after forming the first gate 514 and the second gate 515, a first isolation structure is formed within the first dielectric layer 516 and the first gate 514 on the first isolation region M. For the method of forming the first isolation structure, please refer to... Figures 34 to 35 .

[0132] Please refer to Figure 34 A first hard mask layer 517 is formed on the surfaces of the first dielectric layer 516, the first gate 514 and the second gate 515, and the first hard mask layer 517 exposes the first gate 514 on the first isolation region M; using the first hard mask layer 517 as a mask, the first gate 514 on the first isolation region M is removed, and a first isolation opening 518 is formed in the first dielectric layer 516 and the first gate 514.

[0133] The material of the first hard mask layer 517 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride.

[0134] The method for forming the first hard mask layer 517 includes: forming a first hard mask material layer (not shown in the figure) on the surfaces of the first dielectric layer 516, the first gate 514 and the second gate 515; and patterning the first hard mask material layer to form the first hard mask layer 517.

[0135] In this embodiment, the first hard mask layer 517 has a two-layer structure, including an oxide material layer and a silicon nitride material layer located on the oxide material layer.

[0136] Please refer to Figure 35 A first isolation structure 519 is formed within the first isolation opening 518.

[0137] In this embodiment, after forming the first isolation structure 519, the first hard mask layer 517 is also patterned to form a second hard mask layer (not shown in the figure), the second hard mask layer exposes the fin on the second isolation region; the fin is etched using the second hard mask layer as a mask to form a second isolation opening (not shown in the figure) in the fin; a second isolation structure (not shown in the figure) is formed in the second isolation opening.

[0138] In this embodiment, the first hard mask layer 517 is used as a mask when forming the first isolation opening 518 in the first gate 514, and is also used to form the second hard mask layer to cut off the fin and form the second isolation opening, which saves mask material and helps to reduce production costs.

[0139] Both the first isolation structure 519 and the second isolation structure are formed using a first hard mask material layer to create a mask for forming an isolation opening. The order in which they are formed is not limited. In this embodiment, the first isolation structure 519 is formed first, followed by the second isolation structure. In another embodiment, the second isolation structure may be formed first, followed by the first isolation structure. The method further includes: before forming the first isolation structure, forming a second hard mask layer on the surfaces of the first dielectric layer, the first gate, and the second gate, the second hard mask layer exposing fins on the second isolation region; using the second hard mask layer as a mask, etching the fins to form a second isolation opening within the fins; forming the second isolation structure within the second isolation opening; and after forming the second isolation structure, patterning the second hard mask layer to form the first hard mask layer.

[0140] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a first region and a second region; A first pseudo-gate structure is formed on the first region, and a second pseudo-gate structure is formed on the second region. The first pseudo-gate structure includes a first pseudo-gate, and the second pseudo-gate structure includes a second pseudo-gate. The distance between adjacent first pseudo-gate structures is smaller than the distance between adjacent second pseudo-gate structures. A first dielectric material layer is formed on the surface of the substrate. The first dielectric material layer is located on the sidewalls of the first dummy gate structure and the second dummy gate structure. The surface of the first dielectric material layer is higher than or flush with the top surface of the second dummy gate structure. The thickness of the first dielectric material layer on the first region is greater than the thickness of the second dielectric material layer on the second region. A second dielectric material layer is formed on the first dielectric material layer, wherein the thickness of the second dielectric material layer on the first region is less than the thickness of the second dielectric material layer on the second region. Planarize the first dielectric material layer and the second dielectric material layer until the first dummy gate and the second dummy gate are exposed, and form a first transition dielectric layer with the first dielectric material layer; The first transition dielectric layer is etched back to form the first initial dielectric layer; A protective layer is formed on the surface of the first initial dielectric layer, the protective layer being located on the sidewalls of the first dummy gate and the second dummy gate, and exposing the first dummy gate and the second dummy gate; After the protective layer is formed, a first gate is formed to replace the first dummy gate, and a second gate is formed to replace the second dummy gate.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for planarizing the first dielectric material layer and the second dielectric material layer includes: planarizing the second dielectric material layer using a first mechanochemical polishing process until the first dielectric material layer is exposed, wherein the polishing rate of the first mechanochemical polishing process on the second dielectric material layer is greater than the polishing rate on the first dielectric material layer; and after the first mechanochemical polishing process, planarizing the first dielectric material layer using a second mechanochemical polishing process until the first dummy gate and the second dummy gate are exposed.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the first dielectric material layer includes silicon oxide; the formation process of the first dielectric material layer includes fluid chemical vapor deposition; the material of the second dielectric material layer includes silicon oxide; the formation process of the second dielectric material layer includes plasma enhanced chemical vapor deposition.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first dummy gate structure further includes a first dummy gate dielectric layer, which is located between the first dummy gate and the substrate; the second dummy gate structure further includes a second dummy gate dielectric layer, which is located between the second dummy gate and the substrate; the material of the protective layer is different from the materials of the first dummy gate dielectric layer and the second dummy gate dielectric layer.

5. The method for forming a semiconductor structure as described in claim 4, characterized in that, The method for the first gate and the second gate includes: removing the first dummy gate, the second dummy gate, the first dummy gate dielectric layer and the second dummy gate dielectric layer; forming a gate trench in the first initial dielectric layer and the protective layer; forming a gate material layer in the gate trench and on the surface of the protective layer; planarizing the gate material layer until the surface of the first initial dielectric layer on the first region is exposed; forming the first gate with the gate material layer on the first region; forming the second gate with the gate material layer on the second region; and forming the first dielectric layer with the first initial dielectric layer.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The first region includes a first isolation region. After the first gate and the second gate are formed, a first isolation structure is formed in the first dielectric layer on the first isolation region and in the first gate. The method of forming the first isolation structure includes: forming a first hard mask layer on the surfaces of the first dielectric layer, the first gate and the second gate, wherein the first hard mask layer exposes the first gate on the first isolation region; Using the first hard mask layer as a mask, the first gate on the first isolation region is removed, and a first isolation opening is formed in the first dielectric layer and the first gate; a first isolation structure is formed in the first isolation opening.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The substrate has fins, and the first gate crosses the fins in the first region and is located on a portion of the fin sidewalls and top surface.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The first region further includes a second isolation region, and the method further includes: after forming the first isolation structure, patterning the first hard mask layer to form a second hard mask layer, the second hard mask layer exposing the fin on the second isolation region; using the second hard mask layer as a mask, etching the fin to form a second isolation opening in the fin; and forming a second isolation structure in the second isolation opening.

9. The method for forming a semiconductor structure as described in claim 7, characterized in that, The first region further includes a second isolation region, and the method further includes: before forming the first isolation structure, forming a second hard mask layer on the surfaces of the first dielectric layer, the first gate, and the second gate, the second hard mask layer exposing fins on the second isolation region; using the second hard mask layer as a mask, etching the fins to form a second isolation opening in the fins; forming a second isolation structure in the second isolation opening; and after forming the second isolation structure, patterning the second hard mask layer to form the first hard mask layer.

10. The method for forming a semiconductor structure as described in claim 5, characterized in that, The method for planarizing the gate material layer includes: planarizing the gate material layer using a third mechanochemical polishing process until the surface of the protective layer is exposed to form an initial gate; and planarizing the initial gate using a fourth mechanochemical polishing process after the third mechanochemical polishing process.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, After the third mechanochemical polishing process and before the fourth mechanochemical polishing process, the process further includes: removing the protective layer.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the protective layer includes: forming a protective material layer on the top surfaces of the first initial dielectric layer, the first dummy gate, and the second dummy gate; and planarizing the protective material layer until the surfaces of the first dummy gate and the second dummy gate are exposed.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The process for forming the protective material layer includes atomic layer deposition.

14. The method for forming a semiconductor structure as described in claim 12, characterized in that, The material of the protective material layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride.

15. The method for forming a semiconductor structure as described in claim 12, characterized in that, The method for planarizing the protective material layer includes: forming a third dielectric material layer on the surface of the protective material layer, the material of the third dielectric material layer being different from the material of the protective material layer; planarizing the third dielectric material layer using a fifth mechanochemical polishing process until the surface of the protective material layer is exposed; and after the fifth mechanochemical polishing process, etching back the protective material layer until the top surfaces of the first dummy gate and the second dummy gate are exposed.

16. The method for forming a semiconductor structure as described in claim 12, characterized in that, The first region further includes an isolation region. After the protective material layer is formed, and before the protective layer is formed, an isolation structure is formed within the first initial dielectric layer and the first dummy gate on the isolation region. The method for forming the isolation structure includes: patterning the protective material layer; forming a third hard mask layer with the protective material layer; exposing the first dummy gate on the isolation region with the third hard mask layer; etching the first dummy gate with the third hard mask layer as a mask; forming an isolation opening within the first initial dielectric layer and the first dummy gate; and forming an isolation structure within the isolation opening.

17. The method for forming a semiconductor structure as described in claim 16, characterized in that, The method for forming the isolation structure includes: forming an insulating material layer inside the isolation opening and on the surface of the third hard mask layer before planarizing the protective material layer; and forming the isolation structure with the insulating material layer after the planarization process of the protective material layer.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, The insulating material layer is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride.

19. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the first dielectric material layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, silicon carbonitride, and silicon carbonitride; the material of the second dielectric material layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and silicon carbonitride.

20. The method for forming a semiconductor structure as described in claim 1, characterized in that, Before forming the first dielectric material layer, an etch stop layer is also formed on the surface of the substrate, the first dummy gate structure, and the second dummy gate structure.

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