A semiconductor device and a manufacturing method thereof

Abstract

Embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof. The method comprises: providing a semiconductor structure, the semiconductor structure comprising a substrate, a plurality of silicon pillars arranged in an array on the substrate, and an insulating structure between the silicon pillars; forming a metal layer on the silicon pillars and the insulating structure; annealing the metal layer, so that a metal silicide layer is formed at a top end of each of the silicon pillars; and etching the metal silicide layer and the silicon pillars, so that each of the silicon pillars is etched into two transistor pillars.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and more particularly to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] Typically, Dynamic Random Access Memory (DRAM) consists of multiple memory cells, each controlled by a transistor and a storage capacitor; that is, DRAM is a 1T1C memory cell. Within each memory cell, the transistor includes a gate, a source, and a drain. The gate of the transistor forms a word line, and the drain is connected to a bit line. The source of the transistor is connected to the first electrode layer of the storage capacitor, and the second electrode layer of the storage capacitor is connected to a common terminal. The storage capacitor is used to store data written into the memory cell. Summary of the Invention

[0003] In view of the above, this disclosure provides a semiconductor device and a method for manufacturing the same to solve at least one technical problem existing in the prior art.

[0004] To achieve the above objectives, the technical solution disclosed herein is implemented as follows:

[0005] This disclosure provides a method for manufacturing a semiconductor device, the method comprising:

[0006] A semiconductor structure is provided, the semiconductor structure comprising a substrate, a plurality of silicon pillars arranged in an array on the substrate, and an insulating structure between the silicon pillars;

[0007] A metal layer is formed on the silicon pillar and the insulating structure;

[0008] The metal layer is annealed to form a metal silicide layer at the top of each silicon pillar;

[0009] The metal silicide layer and the silicon pillars are etched to etch each silicon pillar into two transistor pillars.

[0010] In some embodiments, the silicon pillar extends perpendicularly to the substrate; prior to the formation of the metal layer, the surface of the insulating structure is flush with the surface of the silicon pillar.

[0011] In some embodiments, the metal silicide layer at the top of each transistor pillar is used to achieve an electrical connection between the source and the storage capacitor.

[0012] In some embodiments, prior to forming a metal layer on the silicon pillar and the insulating structure, the method further includes:

[0013] Ion implantation is performed on the top of each silicon pillar to form a doped layer at the top of each silicon pillar; wherein, along a direction perpendicular to the substrate, the thickness of the doped layer is greater than the thickness of the metal silicide layer.

[0014] In some embodiments, etching the metal silicide layer and the silicon pillars to etch each silicon pillar into two transistor pillars includes:

[0015] A hard mask layer is formed on the metal silicide layer and the insulating structure;

[0016] The metal silicide layer, the doped layer, and the silicon pillar are etched using the hard mask layer to form isolation trenches, so that the etched doped layer forms the source of two transistors respectively.

[0017] In some embodiments, prior to forming a metal layer on the silicon pillar and the insulating structure, the method further includes:

[0018] The top of each of the silicon pillars is etched to form a first groove, the sidewalls of which expose the insulating structure.

[0019] In some embodiments, after etching the tip of each of the silicon pillars to form a first groove, the method further includes:

[0020] A silicon liner is formed on the bottom and sidewalls of the first groove to form a second groove.

[0021] In some embodiments, after forming the second groove, the method further includes:

[0022] A metal layer is formed covering the insulating structure and the bottom and sidewalls of the second groove;

[0023] The metal layer is annealed to form the metal silicide layer at the bottom and sidewalls of the first groove.

[0024] In some embodiments, the metal silicide layer on the sidewall of the first groove serves as the metal silicide layer at the top of each transistor pillar, enabling an electrical connection between the source and the storage capacitor.

[0025] In some embodiments, before annealing the metal layer to form the metal silicide layer at the bottom and sidewalls of the first groove, the method further includes:

[0026] Ion implantation is performed on the top of each of the silicon pillars to form a doped layer at the top of each of the silicon pillars; wherein, along a direction perpendicular to the substrate, the depth of the doped layer is greater than the depth of the first groove.

[0027] In some embodiments, etching the metal silicide layer and the silicon pillars to etch each silicon pillar into two transistor pillars includes:

[0028] The first groove is filled to form a filling layer;

[0029] A hard mask layer is formed on the insulating structure, the metal silicide layer, and the filler layer;

[0030] The hard mask layer is used to etch the filling layer, the metal silicide layer, the doped layer, and the silicon pillar to form an isolation trench; the sidewalls of the isolation trench expose the metal silicide layer and the doped layer, so that the etched doped layer forms the source of two transistors respectively.

[0031] In some embodiments, after forming the isolation groove, the method further includes:

[0032] A protective layer and an isolation structure are sequentially formed in the isolation groove. The protective layer covers the bottom and sidewalls of the isolation groove. The isolation structure fills the isolation groove and isolates each silicon pillar into two transistor pillars. The surface of the isolation structure is flush with the surface of the hard mask layer.

[0033] In some embodiments, after forming the protective layer and the isolation structure, the method further includes:

[0034] A support layer is formed on the hard mask layer and the isolation structure;

[0035] The support layer and the hard mask layer are etched to form capacitor vias that expose the metal silicide layer;

[0036] A first electrode layer, a capacitor dielectric layer, and a second electrode layer are sequentially formed in the capacitor via to form a storage capacitor.

[0037] In some embodiments, after etching the metal silicide layer and the silicon pillars to etch each silicon pillar into two transistor pillars, the method further includes:

[0038] The storage capacitor is formed, wherein the first electrode layer of the storage capacitor is electrically connected to the source electrode through the metal silicide layer, and the second electrode layer of the storage capacitor is connected to the common terminal.

[0039] In some embodiments, annealing the metal layer to form a metal silicide layer at the top of each silicon pillar includes:

[0040] The metal layer is subjected to a first annealing treatment, which causes the atoms of the metal layer to react with the atoms of the silicon pillars to form a pre-metal silicide layer at the top of each silicon pillar.

[0041] The pre-metal silicide layer is subjected to a second annealing treatment, so that the pre-metal silicide layer forms the metal silicide layer; wherein the temperature of the first annealing treatment is lower than the temperature of the second annealing treatment.

[0042] In some embodiments, after performing the first annealing treatment on the metal layer, the method further includes:

[0043] The unreacted metal layer from the first annealing process is removed using a wet etching process.

[0044] In some embodiments, the material of the metal layer includes at least one of the following: nickel, cobalt, and titanium.

[0045] In some embodiments, after forming a metal layer on the silicon pillar and the insulating structure, the method further includes:

[0046] A titanium nitride layer is formed on the metal layer.

[0047] In some embodiments, the semiconductor device includes a vertical channel memory.

[0048] Secondly, this disclosure provides a semiconductor device, which is manufactured by the semiconductor device manufacturing method described in the above technical solution.

[0049] This disclosure provides a semiconductor device and a method for manufacturing the same. The method includes: providing a semiconductor structure, the semiconductor structure including a substrate, a plurality of silicon pillars arranged in an array on the substrate, and an insulating structure between the silicon pillars; forming a metal layer on the silicon pillars and the insulating structure; annealing the metal layer to form a metal silicide layer at the tip of each silicon pillar; and etching the metal silicide layer and the silicon pillars to etch each silicon pillar into two transistor pillars. In this disclosure, by first forming a metal silicide layer at the tip of the silicon pillar and then etching the metal silicide layer and the silicon pillars to etch each silicon pillar into two transistor pillars, the contact area between the metal layer and the silicon pillars is increased during the formation of the metal silicide layer. This reduces the small-size effect of the metal silicide layer and provides sufficient silicon source for the reaction, ensuring the formation of a stable crystalline phase metal silicide layer, thereby improving the thermal stability of the metal silicide layer. Furthermore, the stable metal silicide layer enables a stable electrical connection between the source of the transistor and the storage capacitor, thereby improving the reliability of the semiconductor device. Attached Figure Description

[0050] Figure 1A This is a schematic diagram of the three-dimensional structure of a vertical channel memory.

[0051] Figure 1B A three-dimensional structural diagram of a storage cell in a vertical channel memory (VDM).

[0052] Figure 2 A partial cross-sectional view of a vertical channel memory.

[0053] Figure 3A This is a graph showing the phase state of metal silicides as a function of annealing temperature.

[0054] Figure 3B The graph shows the variation of T1 and T2 with the thickness or linewidth of the metal silicide.

[0055] Figure 4 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this disclosure;

[0056] Figures 5A to 5J A partial cross-sectional view of the manufacturing process of a semiconductor device provided in this disclosure embodiment;

[0057] Figures 6A to 6L A partial cross-sectional view during the manufacturing process of another semiconductor device provided in this disclosure embodiment;

[0058] The figure includes: 101, channel; 102, 507, 707, gate layer; 103, storage capacitor; 104, common terminal; 105, word line; 106, bit line; 107, 506, 706, gate oxide layer; 108, insulating structure; 109, 522, 718, isolation structure; 110, 525, 722, first electrode layer; 111, 523, 719, air gap; 112, 520, 716, source electrode; 113, 512, 713, metal silicide layer; 114, tungsten layer; 501, 701, substrate; 502, 702, silicon pillar; 503, 703, first insulating structure; 504, 704. Second insulating structure; 505, 705, third insulating structure; 508, oxide layer; 509, 709, doped layer; 510, 712, metal layer; 511, titanium nitride layer; 513, 720, hard mask layer; 514, carbon layer; 515, silicon oxynitride layer; 516, patterned photoresist layer; 517, opening; 518, 715, isolation trench; 519, 717, transistor pillar; 521, protective layer; 524, 721, support layer; 526, 723, capacitor dielectric layer; 527, 724, second electrode layer; 708, first trench; 710, silicon substrate; 711, second trench; 714, filling layer. Detailed Implementation

[0059] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0060] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0061] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0062] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0063] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0064] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0065] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0066] Mainstream memory transistor arrays include planar transistor arrays and buried channel array transistors (BCAT). However, regardless of whether it is a planar transistor array or a buried channel transistor array, the source and drain are located on opposite sides of the gate. In this structure, the source and drain occupy different positions, resulting in a relatively large area for both planar and buried channel transistor arrays.

[0067] To further reduce the size of the transistor array, the transistor array of the memory can include a vertical gate transistor (VGT) array. In this structure, channels of the transistor array are formed on the substrate surface; wherein the extension direction of the channels is perpendicular to the substrate surface; the channels are arrayed along a first direction parallel to the substrate surface and a second direction parallel to the substrate surface; a gate oxide layer and a gate can also be sequentially formed on at least one side of each channel of the transistor array, and each channel of the transistor array has a source and a drain at its two ends along its extension direction. Specifically, the source can be formed by doping the first end of each channel of the transistor array; the substrate can also be thinned on the back side to expose the second end of each channel of the transistor array, and the exposed second end of each channel can be doped to form the drain of each transistor; wherein the first end and the second end are opposite ends of the channel along its extension direction.

[0068] Hereinafter, the thickness direction of the substrate is defined as the Z-direction. Intersecting X and Y directions are defined on the top or bottom surface of the substrate perpendicular to the Z-direction. Based on the X and Y directions, the top or bottom surface of the substrate perpendicular to the Z-direction can be determined. For example, the X and Y directions are mutually perpendicular, thus the X, Y, and Z directions are mutually perpendicular to each other. In this embodiment, the transistors and channels are arranged in an array, with the X-direction defined as the column direction and the Y-direction defined as the row direction. It should be noted that the row direction in the array arrangement can be perpendicular to the column direction or have a certain angle between them.

[0069] refer to Figure 1A and Figure 1B , Figure 1A This is a schematic diagram of the three-dimensional structure of a vertical channel memory. Figure 1B This is a three-dimensional structural diagram of a storage cell in a vertical channel memory (VDM). Figure 1A As shown, each channel 101 of the transistor array has a gate layer 102 formed on its sidewall. The gate layers 102 of each channel 101 located in the same column (i.e., each channel 101 arranged along the X direction) are connected to form a word line 105; the top of each channel 101 of the transistor array forms a source. Figure 1A and Figure 1B (Not shown in the image), the source is connected to the first electrode layer of the storage capacitor 103, and the second electrode layer of the storage capacitor 103 is connected to the common terminal 104; the bottom end of each channel 101 of the transistor array forms the drain ( Figure 1A and Figure 1B (Not shown in the image), the drains of each channel 101 located in the same row (i.e., each channel 101 arranged along the Y direction) are connected to form a bit line 106. Figure 1B The diagram illustrates the three-dimensional structure of a single storage unit.

[0070] In the aforementioned vertical channel memory, the channel extends in a direction perpendicular to the substrate, and the source and drain are formed at the upper and lower ends of the channel, respectively. The storage capacitor and bit line are located on the upper and lower sides of the channel, respectively. They can be fabricated on both sides of the substrate, improving the efficiency of process development.

[0071] refer to Figure 2 , Figure 2 This is a partial cross-sectional view of a vertical channel memory. (Example:) Figure 2 As shown, the channel 101 extends in the Z direction. A gate oxide layer 107 and a gate layer 102 are sequentially formed on the sidewall of the channel 101. An insulating structure 108 is formed between two adjacent gate layers 102, and an isolation structure 109 with an air gap 111 is formed between two adjacent channels 101. The top of the channel 101 can also be doped to form a source electrode. The source electrode is electrically connected to the first electrode layer 110 of the storage capacitor, and the second electrode layer of the storage capacitor is connected to the common terminal. Figure 2 The portion of the structure where the source electrode formed at the top of the channel 101, shown in the dashed box, contacts the first electrode layer 110 of the storage capacitor is magnified. The top of the channel 101 is doped to form the source electrode 112. A metal silicide layer 113 is formed on the source electrode 112, and the surface of the metal silicide layer 113 is lower than the surface of the gate oxide layer 107 (or, the isolation structure 109). A tungsten layer 114 is formed on the metal silicide layer 113, and the surface of the tungsten layer 114 is flush with the surface of the gate oxide layer 107 (or, the isolation structure 109). The first electrode layer 110 of the storage capacitor is formed on the tungsten layer 114.

[0072] Figure 2 The contact area between the schematic metal silicide layer 113 and the source electrode 112 is equal to the orthogonal projection area of ​​the source electrode 112 on the XY plane.

[0073] As the feature size of semiconductor processes continues to shrink, the dimensions of the gate, source, and drain of transistors also shrink accordingly, while their equivalent series resistance increases accordingly, thus affecting circuit speed. In this embodiment, the source of the transistor and the first electrode layer of the storage capacitor are electrically connected through a metal silicide layer and a tungsten layer. The metal silicide layer can reduce the contact resistance between the source (i.e., doped polysilicon) and the tungsten layer, thereby reducing the contact resistance between the source and the first electrode layer of the storage capacitor.

[0074] The following will combine Figure 3A and Figure 3B This paper details the phase change process of forming metal silicides directly on the source electrode. Figure 3A This is a graph showing the phase state of metal silicides as a function of annealing temperature. Figure 3B The graph shows the variation of T1 and T2 with the thickness or linewidth of the metal silicide.

[0075] First, a metal layer is formed covering the source (i.e., doped polysilicon), an isolation structure (e.g., silicon dioxide), and an insulating structure (e.g., silicon dioxide). The isolation and insulating structures are used to separate the channels of different transistors. The metal layer is in direct contact with both the doped polysilicon and silicon dioxide. Then, a first rapid thermal annealing (RTA) process is performed. The annealing temperature is controlled so that only the doped polysilicon reacts with the atoms of the metal layer to form a C-49 phase metal silicide, while the silicon dioxide does not react with the atoms of the metal layer. At this point, the C-49 phase metal silicide has a body-centered orthorhombic structure and high resistance (e.g., ...). Figure 3A (As shown); Next, a wet etching process is used to remove the unreacted metal layer on the silicon dioxide; Finally, a second rapid thermal annealing process is performed, controlling the annealing temperature to transform the C-49 phase metal silicide into the C-54 phase metal silicide. At this point, the C-54 phase metal silicide has a face-centered rhombic structure and low electrical resistance (as shown). Figure 3A (As shown).

[0076] like Figure 3A As shown, temperature T1 is the critical temperature at which the metal silicide transforms from the C-49 phase to the C-54 phase, and temperature T2 is the critical temperature at which the metal silicide agglomerates from the C-54 phase.

[0077] like Figure 3B As shown, as the thickness or linewidth of the metal silicide decreases, the critical temperature T1 for the transformation from the C-49 phase to the C-54 phase increases, while the critical temperature T2 for the agglomeration of the metal silicide from the C-54 phase decreases, potentially leading to a critical point where T1 = T2, or even T2 being less than T1. (Refer to...) Figure 3A As the thickness or linewidth of the metal silicide decreases, if T2 is less than T1, the metal silicide will directly clump together from the C-49 phase, and there will be no C-54 phase interval.

[0078] Due to the unique structure of vertical-channel memory (VCD) devices, the small size of the source electrode limits the available silicon source for subsequent reactions with the metal layers. This results in a small size of the metal silicide directly formed on the source electrode. Furthermore, the small size effect and high-temperature annealing process make it difficult to form C-54 phase metal silicides, leading to clumping and void defects. Moreover, clumped metal silicides make it difficult to achieve a good electrical connection between the transistor source and the first electrode layer of the storage capacitor, and may even cause the channel formed by the silicon pillar to break, resulting in an open circuit in the semiconductor device.

[0079] In view of the above, this disclosure provides a semiconductor device and a method for manufacturing the same.

[0080] refer to Figure 4 , Figure 4 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this disclosure.

[0081] like Figure 4 As shown, the method for manufacturing a semiconductor device includes the following steps:

[0082] Step S401: Provide a semiconductor structure, the semiconductor structure including a substrate, a plurality of silicon pillars arranged in an array on the substrate, and an insulating structure between the silicon pillars;

[0083] Step S402: Form a metal layer on the silicon pillar and insulating structure;

[0084] Step S403: Anneal the metal layer to form a metal silicide layer at the top of each silicon pillar;

[0085] Step S404: Etch the metal silicide layer and silicon pillars to etch each silicon pillar into two transistor pillars.

[0086] In some embodiments, the semiconductor device includes a vertical channel memory.

[0087] Here, we will use a vertical channel memory as an example to illustrate the semiconductor device provided in the embodiments of this disclosure.

[0088] Next, combine Figures 5A to 5J The present disclosure describes in detail the manufacturing method of the semiconductor device provided in the embodiments.

[0089] In this embodiment of the disclosure, a method for manufacturing a semiconductor device includes the following steps: etching from a substrate surface to form an array of silicon pillars and a first etched groove between the silicon pillars; wherein the extending direction of the silicon pillars is perpendicular to the substrate surface; the silicon pillars are arrayed along a first direction parallel to the substrate surface and a second direction parallel to the substrate surface; filling the first etched groove with an insulating material to form an insulating structure surrounding each silicon pillar; etching the insulating structure to form a second etched groove exposing at least two opposing sidewalls of each silicon pillar; and filling the second etched groove with a metal material to form a gate layer.

[0090] Here, the first direction can be the X direction, i.e., the column direction; the second direction can be the Y direction, i.e., the row direction.

[0091] In some embodiments, before filling the second etched groove with metal material, the method of manufacturing the semiconductor device further includes the step of oxidizing the exposed sidewalls of the silicon pillar through the second etched groove to form a gate oxide layer on the sidewalls of the silicon pillar. In other embodiments, before filling the second etched groove with metal material, the method of manufacturing the semiconductor device further includes the step of forming a gate oxide layer through the second etched groove, the gate oxide layer covering the exposed sidewalls of the silicon pillar.

[0092] In this embodiment, the exposed sidewalls of the silicon pillar can be oxidized in situ by heating or pressurizing, causing the silicon on the sidewalls to chemically react with a gas containing oxidizing agents at high temperature, thereby forming a dense silicon dioxide film on the surface of the silicon pillar to form a gate oxide layer. In this embodiment, silicon dioxide can also be directly deposited to form the gate oxide layer. This embodiment does not limit the method of forming the gate oxide layer.

[0093] In this embodiment of the present disclosure, before filling the first etched groove with insulating material to form an insulating structure surrounding each silicon pillar, the method for manufacturing the semiconductor device further includes the following steps: depositing and forming a first insulating structure covering the bottom and sidewalls of the first etched groove; wherein the first insulating structure only covers a portion of the sidewalls of the first etched groove near its bottom; depositing and forming a second insulating structure covering the first insulating structure; forming a third insulating structure covering the second insulating structure; wherein the third insulating structure fills the first etched groove. Here, the third insulating structure covers a portion of the sidewalls of the second insulating structure and the first etched groove.

[0094] In this embodiment of the disclosure, the first insulating structure, the second insulating structure, and the third insulating structure can together form a composite insulating structure. For example, the first insulating structure can be silicon dioxide, the second insulating structure can be silicon nitride, and the third insulating structure can be silicon dioxide.

[0095] In this embodiment of the present disclosure, in step S401, a semiconductor structure is provided, the semiconductor structure including a substrate, a plurality of silicon pillars arranged in an array on the substrate, and an insulating structure between the silicon pillars.

[0096] like Figure 5A As shown, the semiconductor structure includes a substrate 501, a plurality of silicon pillars 502 arranged in an array on the substrate 501, and a composite insulating structure (i.e., a first insulating structure 503, a second insulating structure 504, and a third insulating structure 505) between the silicon pillars 502; wherein the extending direction (i.e., the Z direction) of the silicon pillars 502 is perpendicular to the substrate 501; the surface of the composite insulating structure is flush with the surface of the top end of the silicon pillars 502. A gate oxide layer 506 and a gate layer 507 are sequentially formed on the two opposite sidewalls of the silicon pillars 502. Electrical isolation is achieved between two adjacent silicon pillars 502 through the composite insulating structure.

[0097] In this embodiment, the first insulating structure 503, the second insulating structure 504, and the third insulating structure 505 are all made of insulating materials. The first, second, and third insulating structures are located between two adjacent silicon pillars; more specifically, the third insulating structure is located between two adjacent gate layers for electrical isolation. Here, the first, second, and third insulating structures together form a composite insulating structure to achieve electrical isolation between adjacent silicon pillars.

[0098] Still Figure 5A As shown, an oxide layer 508 is formed on the silicon pillar 502 and the third insulating structure 505.

[0099] In this embodiment, the oxide layer is a high-temperature oxide (HTO). The oxide layer can block unwanted impurity ions, buffer the implantation rate, and reduce direct damage to the crystal lattice during ion implantation for subsequent ion implantation (IMP).

[0100] like Figure 5B As shown, ion implantation is performed on the tip of each silicon pillar 502 to form a doped layer 509 at the tip of each silicon pillar 502. The thickness of the doped layer 509 is H1 along the direction perpendicular to the substrate (i.e., the Z direction); the width of the doped layer 509 formed at the tip of each silicon pillar 502 along the Y direction is the width W1 of the tip of the silicon pillar 502. In subsequent processes, the doped layer can be used to form the source of a transistor.

[0101] Here, the silicon pillar has two ends in a direction perpendicular to the substrate, and the end of the silicon pillar away from the substrate surface is the top of the silicon pillar.

[0102] Here, an ion implantation process can be used to inject the particles to be doped into the silicon pillar using an ion beam. Through a series of physicochemical interactions, the doped particles will gradually lose energy and remain in the silicon pillar to form a doped layer.

[0103] like Figure 5C As shown, a chemical mechanical polishing (CMP) process can be used to remove the oxide layer to expose the surfaces of the doped layer 509 and the third insulating structure 505.

[0104] In this embodiment of the present disclosure, in step S402, a metal layer is formed on the silicon pillar and the insulating structure.

[0105] like Figure 5DAs shown, a metal layer 510 and a titanium nitride layer 511 are sequentially formed on the silicon pillar 502 and the third insulating structure 505. More specifically, a metal layer 510 and a titanium nitride layer 511 are sequentially formed on the doped layer 509 and the third insulating structure 505.

[0106] In some embodiments, the material of the metal layer includes at least one of the following: nickel, cobalt, and titanium.

[0107] In this embodiment of the disclosure, a metal layer or a titanium nitride layer can be deposited using processes including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0108] In this embodiment of the disclosure, forming a titanium nitride layer to cover the metal layer can prevent the metal layer from flowing during subsequent annealing.

[0109] In this embodiment of the present disclosure, in step S403, the metal layer is annealed to form a metal silicide layer at the top of each silicon pillar.

[0110] like Figure 5E As shown, the metal layer is annealed to form a metal silicide layer 512 at the top of each silicon pillar 502. The thickness of the metal silicide layer 512 is H2 along the direction perpendicular to the substrate (i.e., the Z direction). Along the Y direction, the width of the metal silicide layer 512 formed at the top of each silicon pillar 502 is the same as the width of the doped layer 509 formed at the top of each silicon pillar 502, which is W1. Specifically, along the direction perpendicular to the substrate (i.e., the Z direction), the thickness H1 of the doped layer 509 is greater than the thickness H2 of the metal silicide layer 512. After forming the metal silicide layer 512, the remaining thickness of the doped layer is (H1-H2). During the above process, a portion of the doped layer at the top of each silicon pillar reacts with the metal layer, and atoms from the metal layer diffuse into the doped layer to form a metal silicide layer. In subsequent processes, the doped layer at the top of each silicon pillar, located below the metal silicide layer, can be used to form the source of the transistor, while the metal silicide layer on the source of the transistor can be used to reduce the contact resistance between the source of the transistor and the first electrode layer of the storage capacitor.

[0111] In some embodiments, annealing the metal layer to form a metal silicide layer at the top of each silicon pillar includes the following steps: performing a first annealing treatment on the metal layer, causing the atoms of the metal layer to react with the atoms of the silicon pillar to form a pre-metal silicide layer at the top of each silicon pillar; removing the unreacted metal layer from the first annealing treatment using a wet etching process; and performing a second annealing treatment on the pre-metal silicide layer to form a metal silicide layer; wherein the temperature of the first annealing treatment is lower than the temperature of the second annealing treatment.

[0112] Here, the metal layer undergoes a first annealing process, and the annealing temperature is controlled so that only a portion of the doped layer (i.e., doped polysilicon) at the top of each silicon pillar reacts with the atoms of the metal layer to form a pre-metal silicide layer, while the third insulating structure between two adjacent silicon pillars does not react with the atoms of the metal layer. The unreacted metal layer from the first annealing process is removed using a wet etching process. The pre-metal silicide layer undergoes a second annealing process, and the annealing temperature is controlled so that the phase state of the pre-metal silicide layer changes to form a metal silicide layer with a more stable phase and lower resistance.

[0113] In this embodiment, the pre-metal silicide layer can be a C-49 phase metal silicide, which has a higher resistance; the metal silicide layer can be a C-54 phase metal silicide, which has a lower resistance.

[0114] In this embodiment of the disclosure, the temperature of the first annealing treatment is lower than the temperature of the second annealing treatment. The temperature of the first annealing treatment may be, for example, 450°C to 650°C, and the temperature of the second annealing treatment may be, for example, 750°C to 950°C.

[0115] Figure 5D The contact area between the schematic metal layer 510 and the top of each silicon pillar 502 (more specifically, the doped layer 509 at the top of each silicon pillar 502) is equal to the orthographic projection area of ​​the top of each silicon pillar 502 in the XY plane. Figure 5E The contact area between the schematic metal silicide layer 512 and the tip of each silicon pillar 502 (more specifically, the doped layer 509 at the tip of each silicon pillar 502) is equal to the orthographic projection area of ​​the tip of each silicon pillar 502 in the XY plane. It should be noted that in subsequent processes, the doped layer at the tip of each silicon pillar is etched into the source of two transistors.

[0116] In this embodiment of the present disclosure, in step S404, the metal silicide layer and silicon pillars are etched to etch each silicon pillar into two transistor pillars.

[0117] like Figure 5F and Figure 5GAs shown, a hard mask layer 513, a carbon layer 514, a silicon oxynitride layer 515, and a patterned photoresist layer 516 are sequentially formed on the metal silicide layer 512 and the third insulating structure 505. The silicon oxynitride layer 515, the carbon layer 514, and the hard mask layer 513 are sequentially etched using the openings 517 of the patterned photoresist layer 516. The metal silicide layer 512, the doped layer 509, and the silicon pillars 502 are then sequentially etched using the hard mask layer 513 to form an isolation groove 518, such that each silicon pillar is etched into two transistor pillars 519, and the doped layer 509 at the top of each silicon pillar is etched into the source 520 of two transistors.

[0118] In this embodiment of the disclosure, after forming the metal silicide layer 512 along the Z direction, the remaining thickness of the doped layer is (H1-H2). Figure 5G and Figure 5H The doped layer 509 located below the metal silicide layer 512 is etched to form the sources 520 of two transistors. That is, along the Z direction, the thickness of the source 520 is (H1-H2). In this embodiment, along the Y direction, the width W1 of the top of each silicon pillar (or the width W1 of the metal silicide layer formed at the top of each silicon pillar) is greater than the width W2 of the source. In a specific example, W1 = 4 * W2.

[0119] In this embodiment of the disclosure, a dry etching process can be used to sequentially etch the metal silicide layer, the doped layer, and the silicon pillar, for example, a plasma etching process or a reactive ion etching process.

[0120] In this embodiment, a metal silicide layer is formed at the top of the silicon pillar instead of only at the top of the source electrode. The contact area between the metal layer and the silicon pillar (i.e., the orthogonal projection area of ​​the silicon pillar in the XY plane) is larger than the contact area between the metal layer and the source electrode (i.e., the orthogonal projection area of ​​the source electrode in the XY plane). This increased contact area reduces the small-size effect of the metal silicide layer and provides sufficient silicon source for the reaction, ensuring the formation of a metal silicide layer with sufficient thickness and a stable crystalline phase, thereby improving the thermal stability of the metal silicide layer. Furthermore, in this embodiment, the size of the metal silicide layer formed at the top of the silicon pillar is significantly larger than that formed at the top of the source electrode, which reduces the impact of the small-size effect on the formation of a stable metal silicide layer.

[0121] like Figure 5G and Figure 5H As shown, a protective layer 521 and an isolation structure 522 are sequentially formed in the isolation groove 518. The protective layer 521 covers the bottom and sidewalls of the isolation groove 518, and the isolation structure 522 fills the isolation groove 518. The isolation structure 522 isolates each silicon pillar into two transistor pillars 519. The surface of the isolation structure 522 is flush with the surface of the hard mask layer 513.

[0122] In this embodiment of the disclosure, a protective layer is formed in the isolation groove, and the protective layer covers the bottom and sidewalls of the isolation groove. That is, the protective layer covers the doped layer (i.e., the source of the transistor) and the metal silicide layer exposed on the sidewalls of the isolation groove. In this way, the protective layer can protect the metal silicide layer and prevent the metal silicide layer from being oxidized when the transistor pillar is repaired at low temperature (below 750°C).

[0123] In this embodiment of the disclosure, the materials forming the protective layer and the isolation structure may include, but are not limited to, silicon dioxide, silicon nitride, or silicon oxynitride. In one specific example, the materials forming the protective layer and the isolation structure are the same. Figure 5H The protective layer and the isolation structure shown in the diagram are made of the same material.

[0124] like Figure 5H As shown, an air gap 523 can also be formed in the isolation structure 522.

[0125] Here, an air gap is formed in the isolation structure to obtain a lower dielectric constant, thereby reducing parasitic capacitance.

[0126] In this embodiment of the disclosure, after forming the source of the transistor, the hard mask layer used to form the isolation groove is retained so as to serve as an etch stop layer when a storage capacitor is subsequently formed on the source.

[0127] like Figure 5I As shown, a support layer 524 is formed on the hard mask layer 513 and the isolation structure 522; the support layer 524 and the hard mask layer 513 are etched to form a capacitor via that exposes the metal silicide layer; a first electrode layer 525 is deposited to cover the bottom and sidewalls of the capacitor via and the surface of the support layer 524.

[0128] In this embodiment, the first electrode layer covering the support layer can be removed to expose the surface of the support layer, leaving only the first electrode layer covering the bottom and sidewalls of the capacitor via; alternatively, the support layer can also be removed. Thus, the first electrode layer corresponding to each capacitor via can be used to form an independent storage capacitor, with different storage capacitors being insulated from each other.

[0129] like Figure 5J As shown, a capacitor dielectric layer 526 and a second electrode layer 527 are sequentially deposited on the hard mask layer 513 and the inner and outer sidewalls of the first electrode layer 525 to form a storage capacitor. This disclosure does not limit the structure of the storage capacitor, and the storage capacitor in the semiconductor device provided in this disclosure is not limited to the structure shown in Figure 5J.

[0130] In this embodiment of the present disclosure, after forming a capacitor via exposing a metal silicide layer, a first electrode layer is formed covering the bottom and sidewalls of the capacitor via, and the first electrode layer is connected to the source through the metal silicide layer; a capacitor dielectric layer covering the first electrode layer and a second electrode layer covering the capacitor dielectric layer are then formed, and the second electrode layer is connected to a common terminal.

[0131] This disclosure also provides a semiconductor device, which is manufactured by the semiconductor device manufacturing method described above.

[0132] This disclosure also provides another semiconductor device and a method for manufacturing the same.

[0133] In some embodiments, the semiconductor device includes a vertical channel memory.

[0134] Here, we will use a vertical channel memory as an example to illustrate the semiconductor device provided in the embodiments of this disclosure.

[0135] Next, combine Figures 6A to 6L The present disclosure describes in detail the manufacturing method of the semiconductor device provided in the embodiments.

[0136] In this embodiment of the disclosure, the method for manufacturing a semiconductor device further includes the following steps: etching from a substrate surface to form an array of silicon pillars and a first etched groove between the silicon pillars; wherein the extending direction of the silicon pillars is perpendicular to the substrate surface; the silicon pillars are arrayed along a first direction parallel to the substrate surface and a second direction parallel to the substrate surface; filling the first etched groove with an insulating material to form an insulating structure surrounding each silicon pillar; etching the insulating structure to form a second etched groove exposing at least two opposing sidewalls of each silicon pillar; and filling the second etched groove with a metal material to form a gate layer.

[0137] Here, the first direction can be the X direction, i.e., the column direction; the second direction can be the Y direction, i.e., the row direction.

[0138] In some embodiments, before filling the second etched groove with metal material, the method of manufacturing the semiconductor device further includes the step of oxidizing the exposed sidewalls of the silicon pillar through the second etched groove to form a gate oxide layer on the sidewalls of the silicon pillar. In other embodiments, before filling the second etched groove with metal material, the method of manufacturing the semiconductor device further includes the step of forming a gate oxide layer through the second etched groove, the gate oxide layer covering the exposed sidewalls of the silicon pillar.

[0139] In this embodiment, the exposed sidewalls of the silicon pillar can be oxidized in situ by heating or pressurizing, causing the silicon on the sidewalls to chemically react with a gas containing oxidizing agents at high temperature, thereby forming a dense silicon dioxide film on the surface of the silicon pillar to form a gate oxide layer. In this embodiment, silicon dioxide can also be directly deposited to form the gate oxide layer. This embodiment does not limit the method of forming the gate oxide layer.

[0140] In this embodiment of the present disclosure, before filling the first etched groove with insulating material to form an insulating structure surrounding each silicon pillar, the method for manufacturing the semiconductor device further includes the following step: sequentially forming a first insulating structure and a second insulating structure at the bottom of the first etched groove. Here, a third insulating structure is located above the first insulating structure and the second insulating structure.

[0141] In this embodiment of the disclosure, the first insulating structure, the second insulating structure, and the third insulating structure can form a composite insulating structure. For example, the first insulating structure can be silicon dioxide, the second insulating structure can be silicon nitride, and the third insulating structure can be silicon dioxide.

[0142] In this embodiment of the present disclosure, in step S401, a semiconductor structure is provided, the semiconductor structure including a substrate, a plurality of silicon pillars arranged in an array on the substrate, and an insulating structure between the silicon pillars.

[0143] like Figure 6A As shown, the semiconductor structure includes a substrate 701, a plurality of silicon pillars 702 arranged in an array on the substrate 701, and insulating structures between the silicon pillars 702 (i.e., a first insulating structure 703, a second insulating structure 704, and a third insulating structure 705); wherein the extending direction (i.e., the Z direction) of the silicon pillars 702 is perpendicular to the substrate 701; the surface of the third insulating structure 705 is flush with the surface of the top of the silicon pillars 702. A gate oxide layer 706 and a gate layer 707 are sequentially formed on the two opposite sidewalls of the silicon pillars 702. Electrical isolation is achieved between two adjacent silicon pillars 702 through a composite insulating structure.

[0144] In this embodiment, the first insulating structure 703, the second insulating structure 704, and the third insulating structure 705 are made of insulating material. The first, second, and third insulating structures are located between two adjacent silicon pillars; more specifically, the third insulating structure is located between two adjacent gate layers for electrical isolation. Here, the first insulating structure 703, the second insulating structure 704, and the third insulating structure 705 together form a composite insulating structure to achieve electrical isolation between adjacent silicon pillars.

[0145] In this embodiment of the present disclosure, in step S402, a metal layer is formed on the silicon pillars and the insulating structure. Prior to forming the metal layer on the silicon pillars and the insulating structure, the method further includes: etching the tip of each silicon pillar to form a first groove, the sidewalls of which expose the insulating structure.

[0146] like Figure 6B As shown, the top of the silicon pillar 702 is etched to form a first groove 708, and the sidewalls of the first groove 708 expose the gate oxide layer 706. The silicon pillar 702 is partially etched along a direction perpendicular to the substrate (i.e., the Z direction) to form the first groove 708, and the etching depth of the first groove 708 is less than the height of the silicon pillar 702. Figure 6B It is shown that the width of the opening of the first groove 708 along the Y direction is W3; and the depth of the first groove 708 along the Z direction is H3.

[0147] here, Figure 6B The surface of the gate oxide layer 706 is flush with the surface of the third insulating structure 705. A first groove 708 is formed by etching the silicon pillar, and the sidewalls of the first groove 708 expose the gate oxide layer 706. Of course, the surface of the gate oxide layer can also be lower than the surface of the third insulating structure. In this case, the first groove formed by etching the silicon pillar exposes the third insulating structure.

[0148] In this embodiment, the silicon pillar 702 is a trapezoid with a narrower top and a wider bottom in the YZ plane, and the width of the top end of the silicon pillar 702 is smaller than the width of the bottom end. In fact, this disclosure does not limit the shape of the silicon pillar in the YZ plane. Of course, the silicon pillar can also be rectangular in the YZ plane, in which case the width of both the opening and the bottom of the first groove would be W3.

[0149] Still Figure 6B As shown, ion implantation is performed on the top of the silicon pillars 702 exposed at the bottom of the first groove 708 to form a doped layer 709 at the top of each silicon pillar 702. The doping depth H5 of the doped layer 709 is greater than the depth H3 of the first groove 708. In subsequent processes, the doped layer can be used to form the source of a transistor.

[0150] Here, the silicon pillar has two ends in a direction perpendicular to the substrate, and the end of the silicon pillar away from the substrate surface is the top of the silicon pillar.

[0151] Here, an ion implantation process can be used to inject the particles to be doped into the silicon pillar using an ion beam. Through a series of physicochemical interactions, the doped particles will gradually lose energy and remain in the silicon pillar to form a doped layer.

[0152] like Figure 6CAs shown, a silicon substrate 710 is deposited on the bottom and sidewalls of the first groove and on the third insulating structure 705 to form the second groove 711.

[0153] Here, the material of the silicon substrate may include polycrystalline silicon or doped polycrystalline silicon. Figure 6C The diagram shows that the silicon substrate is made of the same material as the silicon pillar, which is polycrystalline silicon.

[0154] In some embodiments, the silicon substrate (i.e., polycrystalline silicon) may also be ion implanted to form a doped silicon substrate.

[0155] like Figure 6D As shown, the silicon substrate 710 covering the bottom and sidewalls of the first groove is retained. The silicon substrate 710 on the third insulating structure 705 is removed by chemical mechanical polishing to expose the surface of the third insulating structure 705. Figure 6D The diagram illustrates that along the Y direction, the width of the opening of the second groove 711 is W4; along the Z direction, the depth of the second groove 711 is H4. If the silicon pillar is rectangular in the YZ plane, then the width of both the opening and the bottom of the second groove is W4. Specifically, the width W3 of the opening of the first groove 708 is greater than the width W4 of the opening of the second groove 711, and the depth H3 of the first groove 708 is greater than the depth H4 of the second groove 711. Thus, Figure 6D As shown, along the Z direction, the thickness of the silicon substrate 710 covering the bottom of the first groove is (H3-H4); along the Y direction, the thickness of the silicon substrate 710 covering the sidewall of the first groove is [(W3-W4) / 2].

[0156] like Figure 6E As shown, a metal layer 712 is formed covering the bottom and sidewalls of the second groove and the third insulating structure 705. More specifically, a metal layer 712 is formed covering the silicon substrate 710 and the third insulating structure 705.

[0157] In some embodiments, the material of the metal layer includes at least one of the following: nickel, cobalt, and titanium.

[0158] In some embodiments, a titanium nitride layer is formed on the metal layer. Here, forming a titanium nitride layer over the metal layer can prevent the metal layer from flowing during subsequent annealing processes.

[0159] In this embodiment of the disclosure, a metal layer or a titanium nitride layer can be deposited using processes including but not limited to CVD, PVD, or ALD.

[0160] In this embodiment of the present disclosure, in step S403, the metal layer is annealed to form a metal silicide layer at the top of each silicon pillar.

[0161] During the annealing process, the depth of atomic diffusion from the metal layer into the silicon substrate can be controlled by adjusting parameters such as the annealing temperature and time, thereby controlling the thickness of the metal silicide layer. Here, the thickness of the metal silicide layer along the Y direction can be the same as the thickness of the silicon substrate covering the sidewall of the first groove, i.e., [(W3-W4) / 2]; the thickness of the metal silicide layer along the Z direction can be the same as the thickness of the silicon substrate covering the bottom of the first groove, i.e., (H3-H4). Thus, annealing the metal layer results in the formation of metal silicide layers at the bottom and sidewalls of the first groove.

[0162] like Figure 6E and Figure 6F As shown, the metal layer 712 is annealed, causing the atoms of the metal layer 712 to diffuse with the atoms of the silicon material (i.e., the silicon substrate) at the bottom and sidewalls of the first groove, forming a metal silicide layer 713 at the bottom and sidewalls of the first groove. The metal silicide layer 713 is divided into a first portion covering the bottom of the first groove and a second portion covering the sidewalls of the first groove. The first portion of the metal silicide layer has a dimension of W3 along the Y direction and a dimension of (H3-H4) along the Z direction; the second portion of the metal silicide layer has a dimension of [(W3-W4) / 2] along the Y direction and a dimension of H4 along the Z direction. Along the Z direction, the doping depth H5 of the doped layer 709 is greater than the depth H3 of the first groove. In the above process, the silicon substrate covering the bottom and sidewalls of the first groove at the top of each silicon pillar reacts with the metal layer to form a metal silicide layer. In subsequent processes, the doped layer at the top of each silicon pillar, located below the metal silicide layer, can be used to form the source of the transistor, while the metal silicide layer on the source of the transistor can be used to reduce the contact resistance between the source of the transistor and the upper electrode layer of the storage capacitor.

[0163] In some embodiments, annealing the metal layer to form a metal silicide layer at the top of each silicon pillar includes the following steps: performing a first annealing treatment on the metal layer, causing the atoms of the metal layer to react with the atoms of the silicon pillar (i.e., the silicon substrate) to form a pre-metal silicide layer covering the bottom and sidewalls of the first recess at the top of each silicon pillar; removing the unreacted metal layer from the first annealing treatment using a wet etching process; and performing a second annealing treatment on the pre-metal silicide layer to form a metal silicide layer; wherein the temperature of the first annealing treatment is lower than the temperature of the second annealing treatment.

[0164] Here, the metal layer undergoes a first annealing process, with the annealing temperature controlled so that only the silicon substrate (i.e., polycrystalline silicon or doped polycrystalline silicon) at the top of each silicon pillar reacts with the atoms of the metal layer to form a pre-metallized silicide layer, while the third insulating structure between two adjacent silicon pillars does not react with the atoms of the metal layer. The first metal layer that did not react in the first annealing process is removed using a wet etching process. The pre-metallized silicide layer undergoes a second annealing process, with the annealing temperature controlled so that the phase state of the pre-metallized silicide layer changes, forming a metallized silicide layer with a more stable phase and lower resistance.

[0165] In this embodiment, the pre-metal silicide layer can be a C-49 phase metal silicide, which has a higher resistance; the metal silicide layer can be a C-54 phase metal silicide, which has a lower resistance.

[0166] In this embodiment of the disclosure, the temperature of the first annealing treatment is lower than the temperature of the second annealing treatment. The temperature of the first annealing treatment may be, for example, 450°C to 650°C, and the temperature of the second annealing treatment may be, for example, 750°C to 950°C.

[0167] Figure 6E The contact area between the schematic metal layer 712 and the top of each silicon pillar 702 (more specifically, the silicon liner 710 at the top of each silicon pillar 702) is equal to the sum of the areas of the bottom and sidewalls of the second recess. Figure 6F The schematic metal silicide layer 713 covers the bottom and sidewalls of the first groove. The metal silicide layer includes a first portion covering the bottom of the first groove and a second portion covering the sidewalls of the first groove. Thus, Figure 6F The contact area between the illustrated metal silicide layer 713 and the tip of each silicon pillar 702 is the sum of the orthogonal projection area of ​​the first portion covering the bottom of the first groove in the XY plane (i.e., the orthogonal projection area of ​​the tip of each silicon pillar 702 in the XY plane, more specifically, the orthogonal projection area of ​​the doped layer 709 at the tip of each silicon pillar 702 in the XY plane) and the orthogonal projection area of ​​the second portion covering the sidewall of the first groove in the XZ plane. In other words, the contact area between the metal silicide layer 713 and the tip of each silicon pillar 702 is equal to the sum of the areas of the bottom and sidewalls of the first groove. It should be noted that in subsequent processes, the doped layer at the tip of each silicon pillar is etched to form the sources of two transistors.

[0168] like Figure 6G As shown, after forming a metal silicide layer 713 covering the sidewalls and bottom of the first groove, the first groove is further filled to form a filling layer 714.

[0169] In this embodiment of the disclosure, the material of the filling layer may include silicon nitride.

[0170] like Figure 6H As shown, the filler layer 714 located within the first groove is retained. A chemical mechanical polishing process is used to remove the filler layer 714 located above the third insulating structure 705, thereby exposing the surface of the third insulating structure 705. Along the Y direction, the width of the filler layer 714 is W4; along the Z direction, the thickness of the filler layer 714 is H4.

[0171] In this embodiment of the present disclosure, in step S404, the metal silicide layer and silicon pillars are etched to etch each silicon pillar into two transistor pillars.

[0172] like Figure 6H and Figure 6I As shown, a hard mask layer can be formed on the third insulating structure 705, the metal silicide layer 713, and the filler layer 714. Figure 6H and Figure 6I (Not shown in the image); the filling layer 714, the metal silicide layer 713 and the silicon pillar 702 are etched sequentially through a hard mask layer to form an isolation trench 715; the sidewalls of the isolation trench 715 expose the metal silicide layer 713, the doped layer 709 and the silicon pillar 702; so that the etched doped layer 709 forms the source 716 of two transistors respectively.

[0173] Figure 6I The isolation groove 715 exposes a second portion of the metal silicide layer 713 covering the sidewall of the first groove; in other words, the width of the isolation groove 715 along the Y direction is at least W4. Thus, the sidewall of the isolation groove 715 can expose a second portion of the metal silicide layer 713.

[0174] In this embodiment of the disclosure, after forming the metal silicide layer 713 along the Z direction, the thickness of the doped layer 709 is (H5-H3). Figure 6I The doped layer 709 located below the metal silicide layer 713 is etched to form the sources 716 of two transistors. That is, the thickness of the source along the Z direction is (H5-H3). In this embodiment of the present disclosure, the width of the source along the Y direction is at most [(W3-W4) / 2].

[0175] In this embodiment of the disclosure, a dry etching process can be used to sequentially etch the metal silicide layer, the doped layer, and the silicon pillar, for example, a plasma etching process or a reactive ion etching process.

[0176] In this embodiment, a metal silicide layer is formed on the sidewalls and bottom of the first groove at the top of the silicon pillar, instead of only at the top of the source. The contact area between the metal layer and the silicon substrate (i.e., the sum of the areas of the bottom and sidewalls of the second groove) is larger than the contact area between the metal layer and the source (i.e., the orthogonal projection area of ​​the source on the XY plane). This increased contact area reduces the small-size effect of the metal silicide layer and provides sufficient silicon source for the reaction, ensuring the formation of a metal silicide layer with sufficient thickness and a stable crystalline phase, thereby improving the thermal stability of the metal silicide layer. Furthermore, in this embodiment, the size of the metal silicide layer formed after etching the first groove at the top of the silicon pillar is significantly larger than that formed directly at the top of the source, which reduces the impact of the small-size effect on the formation of a stable metal silicide layer.

[0177] like Figure 6J As shown, insulating material is filled into the isolation groove to form an isolation structure 718, which isolates each silicon pillar into two transistor pillars 717. The surface of the isolation structure 718 is flush with the surface of the third insulating structure 705.

[0178] In this embodiment of the disclosure, before filling the isolation groove with insulating material to form an isolation structure, a protective layer covering the bottom and sidewalls of the isolation groove may also be formed.

[0179] In this embodiment of the disclosure, the material forming the isolation structure may include, but is not limited to, silicon dioxide, silicon nitride, or silicon oxynitride.

[0180] like Figure 6J As shown, an air gap 719 can also be formed in the isolation structure 718.

[0181] Here, an air gap is formed in the isolation structure to obtain a lower dielectric constant, thereby reducing parasitic capacitance.

[0182] like Figure 6K As shown, a hard mask layer 720 and a support layer 721 are formed on the isolation structure 718, the metal silicide layer 713 and the third insulating structure 705; the support layer 721 and the hard mask layer 720 are etched in sequence to form capacitor vias that expose the metal silicide layer; a first electrode layer 722 is deposited to cover the bottom and sidewalls of the capacitor vias and the surface of the support layer 721.

[0183] Here, after forming the isolation groove using a hard mask layer through etching, the hard mask layer can be removed. The surface of the isolation structure filling the isolation groove is flush with the surface of the third insulating structure. Figure 6KThe diagram illustrates the formation of a hard mask layer and a support layer on the isolation structure, the metal silicide layer, and the third insulating structure to form capacitor vias. Alternatively, the hard mask layer can be etched to form isolation grooves, while the hard mask layer remains. The surface of the isolation structure filling the isolation grooves is flush with the surface of the hard mask layer. In this way, a support layer can be directly formed on the isolation structure and the hard mask layer to form capacitor vias. This saves one step in forming the hard mask layer.

[0184] In this embodiment, the first electrode layer covering the support layer can be removed to expose the surface of the support layer, leaving only the first electrode layer covering the bottom and sidewalls of the capacitor via. Thus, the first electrode layer corresponding to each capacitor via can be used to form an independent storage capacitor, with different storage capacitors being insulated from each other.

[0185] like Figure 6L As shown, a capacitor dielectric layer 723 and a second electrode layer 724 are sequentially deposited on the hard mask layer 720 and the inner and outer sidewalls of the first electrode layer 722 to form a storage capacitor. This disclosure does not limit the structure of the storage capacitor, and the storage capacitor in the semiconductor device provided in this disclosure is not limited to... Figure 6L The structure shown.

[0186] In this embodiment of the present disclosure, after forming a capacitor via exposing a metal silicide layer, an upper electrode layer is formed covering the bottom and sidewalls of the capacitor via, and the upper electrode layer is connected to the source through the metal silicide layer; a capacitor dielectric layer covering the upper electrode layer and a lower electrode layer covering the capacitor dielectric layer are then formed, and the lower electrode layer is connected to a common terminal.

[0187] This disclosure provides a semiconductor device, which is manufactured using the semiconductor device manufacturing method described above.

[0188] This disclosure provides a semiconductor device and a method for manufacturing the same. The method includes: providing a semiconductor structure, the semiconductor structure including a substrate, a plurality of silicon pillars arranged in an array on the substrate, and an insulating structure between the silicon pillars; forming a metal layer on the silicon pillars and the insulating structure; annealing the metal layer to form a metal silicide layer at the tip of each silicon pillar; and etching the metal silicide layer and the silicon pillars to etch each silicon pillar into two transistor pillars. In this disclosure, by first forming a metal silicide layer at the tip of the silicon pillar and then etching the metal silicide layer and the silicon pillars to etch each silicon pillar into two transistor pillars, the contact area between the metal layer and the silicon pillars is increased during the formation of the metal silicide layer. This reduces the small-size effect of the metal silicide layer and provides sufficient silicon source for the reaction, ensuring the formation of a stable crystalline phase metal silicide layer, thereby improving the thermal stability of the metal silicide layer. Furthermore, the stable metal silicide layer enables a stable electrical connection between the source of the transistor and the storage capacitor, thereby improving the reliability of the semiconductor device.

[0189] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0190] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The method includes: A semiconductor structure is provided, the semiconductor structure comprising a substrate, a plurality of silicon pillars arranged in an array on the substrate, and an insulating structure between the silicon pillars; A metal layer is formed on the silicon pillar and the insulating structure; The metal layer is annealed to form a metal silicide layer at the top of each silicon pillar; The metal silicide layer and the silicon pillars are etched to etch each silicon pillar into two transistor pillars.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The silicon pillar extends perpendicularly to the substrate; before the metal layer is formed, the surface of the insulating structure is flush with the surface of the silicon pillar.

3. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The metal silicide layer at the top of each transistor pillar is used to achieve an electrical connection between the source and the storage capacitor.

4. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Before forming a metal layer on the silicon pillar and the insulating structure, the method further includes: Ion implantation is performed on the top of each silicon pillar to form a doped layer at the top of each silicon pillar; wherein, along a direction perpendicular to the substrate, the thickness of the doped layer is greater than the thickness of the metal silicide layer.

5. The method for manufacturing a semiconductor device according to claim 4, characterized in that, The etching of the metal silicide layer and the silicon pillars to etch each silicon pillar into two transistor pillars includes: A hard mask layer is formed on the metal silicide layer and the insulating structure; The metal silicide layer, the doped layer, and the silicon pillar are etched using the hard mask layer to form isolation trenches, so that the etched doped layer forms the source of two transistors respectively.

6. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Before forming a metal layer on the silicon pillar and the insulating structure, the method further includes: The top of each of the silicon pillars is etched to form a first groove, the sidewalls of which expose the insulating structure.

7. The method for manufacturing a semiconductor device according to claim 6, characterized in that, After etching the tip of each of the silicon pillars to form a first groove, the method further includes: A silicon liner is formed on the bottom and sidewalls of the first groove to form a second groove.

8. The method for manufacturing a semiconductor device according to claim 7, characterized in that, After forming the second groove, the method further includes: A metal layer is formed covering the insulating structure and the bottom and sidewalls of the second groove; The metal layer is annealed to form the metal silicide layer at the bottom and sidewalls of the first groove.

9. The method for manufacturing a semiconductor device according to claim 8, characterized in that, The metal silicide layer on the sidewall of the first groove serves as the metal silicide layer at the top of each transistor pillar, enabling electrical connection between the source and the storage capacitor.

10. The method for manufacturing a semiconductor device according to claim 8, characterized in that, Before annealing the metal layer to form the metal silicide layer at the bottom and sidewalls of the first groove, the method further includes: Ion implantation is performed on the top of each of the silicon pillars to form a doped layer at the top of each of the silicon pillars; wherein, along a direction perpendicular to the substrate, the depth of the doped layer is greater than the depth of the first groove.

11. The method for manufacturing a semiconductor device according to claim 10, characterized in that, The etching of the metal silicide layer and the silicon pillars to etch each silicon pillar into two transistor pillars includes: The first groove is filled to form a filling layer; A hard mask layer is formed on the metal silicide layer, the insulating structure, and the filler layer; The hard mask layer is used to etch the filling layer, the metal silicide layer, the doped layer, and the silicon pillar to form an isolation trench; the sidewalls of the isolation trench expose the metal silicide layer and the doped layer, so that the etched doped layer forms the source of two transistors respectively.

12. The method for manufacturing a semiconductor device according to claim 5 or 11, characterized in that, After forming the isolation groove, the method further includes: A protective layer and an isolation structure are sequentially formed in the isolation groove. The protective layer covers the bottom and sidewalls of the isolation groove. The isolation structure fills the isolation groove and isolates each silicon pillar into two transistor pillars. The surface of the isolation structure is flush with the surface of the hard mask layer.

13. The method for manufacturing a semiconductor device according to claim 12, characterized in that, After forming the protective layer and the isolation structure, the method further includes: A support layer is formed on the hard mask layer and the isolation structure; The support layer and the hard mask layer are etched to form capacitor vias that expose the metal silicide layer; A first electrode layer, a capacitor dielectric layer, and a second electrode layer are sequentially formed in the capacitor via to form a storage capacitor.

14. The method for manufacturing a semiconductor device according to claim 13, characterized in that, After etching the metal silicide layer and the silicon pillars to etch each silicon pillar into two transistor pillars, the method further includes: The storage capacitor is formed, wherein the first electrode layer of the storage capacitor is electrically connected to the source electrode through the metal silicide layer, and the second electrode layer of the storage capacitor is connected to the common terminal.

15. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The annealing process performed on the metal layer to form a metal silicide layer at the top of each silicon pillar includes: The metal layer is subjected to a first annealing treatment, which causes the atoms of the metal layer to react with the atoms of the silicon pillars to form a pre-metal silicide layer at the top of each silicon pillar. The pre-metal silicide layer is subjected to a second annealing treatment, so that the pre-metal silicide layer forms the metal silicide layer; wherein the temperature of the first annealing treatment is lower than the temperature of the second annealing treatment.

16. The method for manufacturing a semiconductor device according to claim 15, characterized in that, After performing the first annealing treatment on the metal layer, the method further includes: The unreacted metal layer from the first annealing process is removed using a wet etching process.

17. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The material of the metal layer includes at least one of the following: nickel, cobalt, and titanium.

18. The method for manufacturing a semiconductor device according to claim 1, characterized in that, After forming a metal layer on the silicon pillar and the insulating structure, the method further includes: A titanium nitride layer is formed on the metal layer.

19. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The semiconductor device includes a vertical channel memory.

20. A semiconductor device, characterized in that, The semiconductor device is manufactured by the semiconductor device manufacturing method as described in any one of claims 1 to 19.

Images