Method of manufacturing a semiconductor structure

Abstract

The application discloses a manufacturing method of a semiconductor structure, comprising the following steps: providing a substrate, wherein the substrate comprises electrode columns arranged at intervals; arranging the substrate in a first cavity, and forming a first dielectric layer on the substrate, wherein the first dielectric layer covers the electrode columns; transferring the substrate into a second cavity, and introducing inert gas into the second cavity to remove water vapor in the second cavity; introducing a precursor and a reaction gas into the second cavity to form a second dielectric layer on the first dielectric layer; and performing vacuumizing treatment on the second cavity to remove water vapor in the second cavity, and the pressure in the second cavity is less than the pressure in the second cavity when the inert gas is introduced. According to the manufacturing method of the semiconductor structure, the dielectric layer can be deposited more uniformly, and the anti-creeping performance of the semiconductor structure is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a method for manufacturing a semiconductor structure. Background Technology

[0002] Existing capacitor structures generally consist of an upper electrode, a dielectric layer, and a lower electrode. According to the capacitance calculation formula, the capacitance value is directly proportional to the area between the upper and lower electrodes and the dielectric layer. With the development of semiconductor structures, the pursuit of high speed, high integration density, and low power consumption has become a trend. This leads to a reduction in the area of ​​the memory cell, a decrease in the amount of charge that the memory cell can store, resulting in higher read / write frequencies and increased energy consumption. Furthermore, with the miniaturization of semiconductor structures, especially in the manufacturing process of DRAM with critical dimensions less than 20nm, the oxide layer thickness is approaching the limit of the quantum tunneling effect, causing leakage current to increase exponentially with decreasing oxide thickness.

[0003] In capacitors using related technologies, uneven deposition of the dielectric layer can easily lead to high leakage current. Summary of the Invention

[0004] The purpose of this invention is to provide a method for manufacturing a semiconductor structure, which enables more uniform deposition of the dielectric layer and improves the leakage protection performance of the semiconductor structure.

[0005] A method for manufacturing a semiconductor structure according to an embodiment of the present invention includes: providing a substrate, the substrate including spaced-apart electrode pillars; disposing the substrate in a first cavity and forming a first dielectric layer on the substrate, the first dielectric layer covering the electrode pillars; transferring the substrate to a second cavity and introducing an inert gas into the second cavity to remove moisture from the second cavity; introducing a precursor and a reactive gas into the second cavity to form a second dielectric layer on the first dielectric layer; and evacuating the second cavity to remove moisture from the second cavity, wherein the pressure in the second cavity is lower than the pressure in the second cavity when the inert gas is introduced.

[0006] According to some embodiments of the present invention, after the vacuuming process, the method further includes: forming a third dielectric layer on the second dielectric layer, wherein the material of the third dielectric layer is the same as that of the first dielectric layer.

[0007] According to some embodiments of the present invention, the thickness of the third dielectric layer is less than the thickness of the first dielectric layer.

[0008] According to some embodiments of the present invention, the third dielectric layer is an amorphous structure.

[0009] According to some embodiments of the present invention, the thickness of the first dielectric layer is greater than the thickness of the second dielectric layer, and the bandwidth of the second dielectric layer is greater than the bandwidth of the first dielectric layer.

[0010] According to some embodiments of the present invention, after forming the third dielectric layer, the method further includes forming the fourth dielectric layer on the third dielectric layer, wherein the material of the fourth dielectric layer is the same as that of the second dielectric layer.

[0011] According to some embodiments of the present invention, after forming the third dielectric layer and before forming the fourth dielectric layer, the method further includes: re-introducing an inert gas into the second cavity to remove moisture from the second cavity; wherein the time for introducing the inert gas into the second cavity before forming the fourth dielectric layer is less than the time for introducing the inert gas into the second cavity before forming the second dielectric layer.

[0012] According to some embodiments of the present invention, after forming the fourth dielectric layer, the method further includes: performing a vacuuming process on the second cavity again to remove water vapor from the second cavity; wherein the vacuuming process of the cavity after forming the second dielectric layer takes longer than the vacuuming process of the cavity after forming the fourth dielectric layer.

[0013] According to some embodiments of the present invention, after forming the fourth dielectric layer, an electrode layer is further formed on the fourth dielectric layer.

[0014] According to some embodiments of the present invention, when the inert gas is introduced into the cavity, the flow rate of the inert gas is 800 sccm-2000 sccm, and the pressure in the cavity is 0.5 torr-2.0 torr.

[0015] According to some embodiments of the present invention, after the cavity is evacuated, the pressure inside the cavity is 0.2 torr-2.0 torr.

[0016] According to some embodiments of the present invention, the flow rate of the reaction gas is 2000 sccm-4000 sccm, the pressure inside the cavity is 0.5 torr-2.0 torr, and the temperature inside the cavity is 300-400 degrees Celsius.

[0017] According to some embodiments of the present invention, the flow rate of the precursor is 80 sccm-200 sccm, the pressure inside the cavity is 0.5 torr-2.0 torr, and the temperature inside the cavity is 300-400 degrees Celsius.

[0018] According to some embodiments of the present invention, the inert gas is introduced into the cavity for 8s-20s before the second dielectric layer is formed; and the inert gas is introduced into the cavity for 4s-8s before the fourth dielectric layer is formed.

[0019] According to some embodiments of the present invention, the first dielectric layer comprises a zirconium oxide layer, and the second dielectric layer comprises an aluminum oxide layer.

[0020] According to the semiconductor structure manufacturing method of the present invention, a first dielectric layer is first formed in a first cavity, and then the substrate with the first dielectric layer formed is transferred to a second cavity. Since the second cavity needs to be opened during maintenance, exposing it to the external environment, external moisture may enter. Therefore, before forming the second dielectric layer, an inert gas is introduced into the second cavity to remove moisture. Then, a precursor and a reactant gas are introduced into the second cavity to form the second dielectric layer on the first dielectric layer. Because moisture is removed from the second cavity, a second dielectric layer of uniform thickness is formed on the first dielectric layer. Furthermore, after forming the second dielectric layer, the present invention performs a vacuum treatment on the second cavity to reduce the pressure within the second cavity. After vacuum treatment, the pressure in the second cavity is lower than the pressure when the inert gas was introduced, thereby further removing residual reactant gas and moisture from the second cavity, which is beneficial for the deposition of the fourth dielectric layer. Attached Figure Description

[0021] Figure 1 This is a flowchart of a method for manufacturing a semiconductor structure according to an embodiment of the present invention;

[0022] Figures 2-8 This is a schematic diagram of the various steps in forming a semiconductor structure according to an embodiment of the present invention;

[0023] Figure 9 This is a schematic diagram of the dielectric layer of a semiconductor structure according to another embodiment of the present invention;

[0024] Figure label:

[0025] 100: Semiconductor structure;

[0026] 1: Base;

[0027] 11: Substrate, 12: Metal interconnect structure, 13: First support layer, 14: Sacrificial layer, 15: Second support layer, 16: Capacitor hole, 17: Lower electrode layer, 18: Electrode post;

[0028] 2: Dielectric layer, 21: First dielectric layer, 22: Second dielectric layer, 23: Third dielectric layer, 24: Fourth dielectric layer, 25: Fifth dielectric layer, 26: Sixth dielectric layer. Detailed Implementation

[0029] The following describes in further detail a method for manufacturing a semiconductor structure 100 according to the present invention, with reference to the accompanying drawings and specific embodiments.

[0030] As described in the background art, in the manufacturing process of semiconductor structures in related technologies, uneven deposition of the dielectric layer during the deposition of the dielectric layer can easily lead to high leakage current in the semiconductor structure.

[0031] The inventors discovered that although high-dielectric materials have high dielectric constants, their low bandgap can cause high leakage current in capacitors. Therefore, in the fabrication of semiconductor structures, high-k and wide-bandgap materials are combined to form capacitor structures. However, during the deposition of wide-bandgap materials, the presence of moisture in the manufacturing cavity leads to uneven thickness of the thin film layers deposited above and below the wide-bandgap material, with the top layer being thicker than the bottom layer. The thinner bottom layer is more prone to leakage current, thus affecting the performance of the semiconductor structure.

[0032] The present invention proposes a method for manufacturing a semiconductor structure 100, which enables more uniform deposition of wide bandgap materials, resulting in more uniform thickness of the upper and lower dielectric layers and reducing leakage current in the formed semiconductor structure 100.

[0033] like Figure 1 As shown, a method for manufacturing a semiconductor structure 100 according to an embodiment of the present invention may include the following steps: providing a substrate 1, wherein the substrate 1 includes spaced electrode pillars 18; disposing the substrate 1 in a first cavity and forming a first dielectric layer 21 on the substrate 1, the first dielectric layer 21 covering the electrode pillars 18; transferring the substrate to a second cavity and introducing an inert gas into the second cavity to remove moisture from the second cavity; introducing a precursor and a reactive gas into the second cavity to form a second dielectric layer 22 on the first dielectric layer 21; and performing a vacuum treatment on the second cavity to remove moisture from the second cavity, wherein the pressure in the second cavity is less than the pressure in the second cavity when the inert gas is introduced.

[0034] like Figures 2-8 The diagram shown is a cross-sectional view of each step in the manufacturing process of the semiconductor structure 100 according to an embodiment of the present invention. Figure 7 As shown, the substrate 1 may include a substrate 11 and a device structure formed on the substrate 11, specifically, in conjunction with Figures 2-7 As shown, the method for forming substrate 1 may include the following steps:

[0035] like Figure 2 As shown, a substrate 11 is provided. The substrate 11 may be, but is not limited to, a silicon substrate 11. In this specific embodiment, the substrate 11 may be a silicon substrate. In other examples, the substrate 11 may be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. A metal interconnect structure 12 for connecting a capacitor and a lower device is formed within the substrate 11. The metal interconnect structure 12 may be made of tungsten material.

[0036] Subsequently, a first support layer 13, a sacrificial layer 14, and a second support layer 15 are sequentially formed along a direction perpendicular to the surface of the substrate 11 using chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The first support layer 13 and the second support layer 15 include, but are not limited to, silicon nitride material, and the sacrificial layer 14 includes, but is not limited to, a silicon oxide layer.

[0037] like Figure 3 As shown, a capacitor hole 16 is formed to expose the metal interconnect structure 12. The capacitor hole 16 penetrates the first support layer 13, the sacrificial layer 14 and the second support layer 15 along the direction perpendicular to the surface of the substrate 11. In this step, wet etching or dry etching can be used to etch the first support layer 13, the sacrificial layer 14 and the second support layer 15 in the area where the metal interconnect structure 12 is located.

[0038] like Figure 4 As shown, a lower electrode layer 17 is formed on the surface of the capacitor hole 16 and the second support layer 15. The lower electrode layer 17 covers the surface of the second support layer 15, fills the capacitor hole 16, and contacts the metal interconnect structure 12.

[0039] like Figure 5 As shown, the lower electrode layer 17 located on the surface of the second support layer 15 is removed, leaving only the lower electrode layer 17 located within the capacitor hole 16; as Figure 6 As shown, the second support layer 15 is removed, as... Figure 7 As shown, the sacrificial layer 14 is removed to form a plurality of spaced electrode posts 18 on the substrate 1.

[0040] like Figure 1 In the flowchart of the manufacturing method of the semiconductor structure 100 shown, a substrate 1 is disposed in a first cavity, and a first dielectric layer 21 is formed on the substrate 1. The first dielectric layer 21 covers the electrode post 18, specifically as follows: Figure 8As shown, the first dielectric layer 21 covers the surface of the electrode post 18 and the surface of the first support layer 13. The first dielectric layer 21 can be a high-k dielectric material, such as zirconium oxide. In some embodiments, the first dielectric layer 21 is formed in a first cavity, such as an ALD deposition cavity. After the first dielectric layer 21 is formed, the substrate 1 is transferred to a second cavity to form a second dielectric layer 22. In some embodiments, when the second cavity is under maintenance, a large amount of external moisture may enter the second cavity, which may affect the deposition uniformity of the second dielectric layer 22. The first cavity and the second cavity are different cavities, each used to deposit different dielectric layers.

[0041] Therefore, after transferring substrate 1 to the second cavity, an inert gas is introduced into the second cavity to remove moisture. The inert gas can be nitrogen, argon, a mixture of nitrogen and argon, or any other gas, as long as it does not affect subsequent reactions and can remove moisture from the cavity. This invention does not impose any particular limitation on this. Of course, in some embodiments, nitrogen can also be introduced into the second cavity after maintenance or repair, that is, before transferring the substrate to the second cavity, to remove moisture from the second cavity.

[0042] Combination Figure 1 and Figure 8 As shown, after removing the water vapor from the second cavity, a precursor and a reactive gas are introduced into the second cavity to form a second dielectric layer 22 on the first dielectric layer 21. The second dielectric layer 22 covers the surface of the first dielectric layer 21. The second dielectric layer 22 can be a wide bandgap material, such as aluminum oxide. The first dielectric layer 21 and the second dielectric layer 22 can together form the dielectric layer 2 of the semiconductor structure 100. The reactive gas can be ozone.

[0043] Therefore, by removing moisture from the second cavity before forming the second dielectric layer 22, it is possible to avoid uneven deposition thickness of the second dielectric layer 22 due to the presence of moisture during the formation of the second dielectric layer 22, especially avoiding the problem of the second dielectric layer 22 being thicker at the top and thinner at the bottom located on the sidewall of the first dielectric layer 21, so as to obtain a second dielectric layer 22 with a more uniform film thickness, thereby avoiding leakage problems caused by the thin bottom of the formed dielectric layer 2 and improving the performance of the semiconductor structure 100.

[0044] like Figure 1As shown, the second chamber is then evacuated to remove moisture. This evacuation removes residual gases from the second chamber after the formation of the second dielectric layer 22, ensuring the complete removal of reactive gases from the second chamber and preventing interference with subsequent reactions and processes. In this step, the pressure within the second chamber is lower than the pressure when inert gas is introduced. Specifically, the pressure after evacuation is lower than the pressure after inert gas is introduced during the formation of the second dielectric layer 22. This evacuation process after the formation of the second dielectric layer 22 achieves a higher vacuum level, allowing for a cleaner chamber and thorough removal of residual reactive gases and moisture, thus preventing interference with subsequent processes. The pressure within the second chamber can be controlled during inert gas introduction to prevent excessively low pressure from affecting the introduction of precursors and reactive gases.

[0045] Therefore, in the semiconductor structure manufacturing method according to the present invention, by introducing an inert gas into the second cavity before introducing the precursor and reactive gas into the second cavity to form the second dielectric layer 22, moisture in the cavity is removed, thereby avoiding uneven film thickness of the second dielectric layer 22 and preventing the bottom film of the second dielectric layer 22 from being too thin, which would cause high leakage current in the semiconductor structure 100. Moreover, after forming the second dielectric layer 22, the cavity is evacuated to remove residual reactive gas and moisture in the second cavity, thereby avoiding affecting subsequent processes and preventing uneven film deposition caused by moisture. Furthermore, the pressure in the second cavity after evacuation is lower than the pressure in the second cavity when the inert gas is introduced. This improves the vacuum level of the cavity after evacuation, allowing for more thorough removal of residual reactive gas and moisture in the second cavity. On the other hand, by controlling the pressure in the cavity when the inert gas is introduced, turbulence in the second cavity after the reactive gas is introduced during subsequent processes is avoided, which would affect the reaction film formation.

[0046] In some embodiments of the present invention, the dielectric layer 2 may include a multilayer structure. For example, the dielectric layer 2 may include a multilayer structure in which high-K dielectric material and wide bandgap material are alternately arranged. Selecting wide bandgap material and high-K material to form an alternating layered structure can be more beneficial to improving leakage current. For example, the dielectric layer 2 may include a stacked structure in which multiple zirconium oxide layers and aluminum oxide layers are alternately arranged.

[0047] Combination Figure 8 and Figure 9 As shown, after the vacuuming process, the manufacturing method of the semiconductor structure 100 further includes the following steps:

[0048] A third dielectric layer 23 is formed on the second dielectric layer 22. The material of the third dielectric layer 23 is the same as that of the first dielectric layer 21. For example, both the first dielectric layer 21 and the third dielectric layer 23 can be zirconium oxide layers. In this way, the first dielectric layer 21, the second dielectric layer 22, and the third dielectric layer 23 together form the dielectric layer 2 of the semiconductor structure 100 covering the electrode post 18, thereby increasing the thickness of the dielectric layer 2 to further prevent leakage current in the semiconductor structure 100. It should be noted that both the first dielectric layer 21 and the third dielectric layer 23 can be formed within the first cavity. That is, after the second dielectric layer 22 is formed, the substrate 1 is transferred to the first cavity to form the third dielectric layer 23, for example, by transferring it from the second cavity to the first cavity. The first dielectric layer 21 has a crystalline structure, which is beneficial for obtaining a higher K value, while the third dielectric layer 23 has an amorphous structure, which is beneficial for reducing leakage current.

[0049] In some examples, the thickness of the third dielectric layer 23 is less than the thickness of the first dielectric layer 21, which is formed on and in contact with the surface of the electrode post 18. The thickness of the first dielectric layer 21 is the effective thickness for forming the crystal structure of the dielectric layer 2, thus achieving a higher K value. To further prevent leakage current in the semiconductor structure 100, in some examples, the third dielectric layer 23 is an amorphous structure. In this case, the thickness of the third dielectric layer 23 is the effective thickness for forming an amorphous structure. If the third dielectric layer 23 is too thick, it may eventually transform into a crystalline structure, affecting the leakage current prevention performance of the semiconductor structure 100.

[0050] In some embodiments of the present invention, the thickness of the first dielectric layer 21 is greater than the thickness of the second dielectric layer 22, and the bandwidth of the second dielectric layer 22 is greater than the bandwidth of the first dielectric layer 21. Bandwidth is a factor affecting leakage current; the larger the band gap, the smaller the leakage current. The thickness of the first dielectric layer 21 forms the effective thickness of the crystal structure, which can obtain a higher K value. The second dielectric layer 22 is used for leakage protection. Thus, the first dielectric layer 21 has a high dielectric constant but a small bandwidth, which can improve the dielectric constant of the dielectric layer 2. The second dielectric layer 22 has a high dielectric constant but a large bandwidth, which can improve the leakage protection performance of the dielectric layer 2. By controlling the thickness of the second dielectric layer 22 to be small, the thickness of the dielectric layer 2 can be reduced while achieving a high dielectric constant and improving leakage protection performance.

[0051] In some embodiments of the present invention, after forming the third dielectric layer 23, the method further includes forming a fourth dielectric layer 24 on the third dielectric layer 23. The material of the fourth dielectric layer 24 is the same as that of the second dielectric layer 22. For example, both the fourth dielectric layer 24 and the second dielectric layer 22 can be aluminum oxide layers, thereby further improving the leakage protection performance of the semiconductor structure 100. It should be noted that the second dielectric layer 22 and the fourth dielectric layer 24 can both be formed in the second cavity, for example. That is, after forming the third dielectric layer 23, the substrate 1 is transferred to the second cavity to form the fourth dielectric layer 24. For example, the substrate 1 is transferred from the first cavity to the second cavity. The second cavity is, for example, an ALD cavity.

[0052] In some examples of the present invention, after the formation of the third dielectric layer 23 and before the formation of the fourth dielectric layer 24, the following steps are included: inert gas is introduced into the second cavity again to remove moisture in the second cavity. That is, before the precursor and reactant gas for forming the fourth dielectric layer 24 are introduced into the second cavity, an inert gas can be introduced into the cavity again. The inert gas can be the same as the inert gas introduced before the formation of the second dielectric layer 22, for example, at least one of nitrogen and argon. The inert gas can remove moisture in the cavity after the formation of the third dielectric layer 23, thereby avoiding uneven deposition thickness of the fourth dielectric layer 24 due to the presence of moisture during the formation of the fourth dielectric layer 24, thereby improving the uniformity of the thickness of the fourth dielectric layer 24 and preventing leakage caused by a thinner bottom of the fourth dielectric layer 24.

[0053] Specifically, the time for introducing inert gas into the cavity after the formation of the third dielectric layer 23 is less than the time for introducing inert gas into the cavity after the formation of the first dielectric layer 21. That is, the time for introducing inert gas to remove moisture before the formation of the fourth dielectric layer 24 is less than the time for introducing inert gas to remove moisture before the formation of the second dielectric layer 22. In particular, the longer the inert gas is introduced, the more heat the semiconductor device receives. Heat can affect the lattice transformation, so different inert gas introduction times can be used for different layers. For example, the first dielectric layer 21 is a crystal structure and the third dielectric layer 23 is an amorphous structure. If the time for introducing inert gas after the third dielectric layer 23 is too long, the third dielectric layer 23 will be overheated, which may cause the third dielectric layer 23 to transform into a crystal structure, thereby making leakage current more likely and affecting the performance of the semiconductor structure 100.

[0054] In some embodiments, the thickness of the first dielectric layer 21 can be 3.5nm-5.5nm, the thickness of the second dielectric layer 22 can be 0.1nm-0.5nm, the thickness of the third dielectric layer 23 can be 0.5nm-1nm, and the thickness of the fourth dielectric layer 24 can be 0.1nm-0.5nm. The thickness of each dielectric layer can be set according to actual needs.

[0055] In some examples of the present invention, after forming the fourth dielectric layer 24, the following steps are further included: vacuuming the second cavity again to remove moisture from the second cavity. Due to the vacuuming process, a higher vacuum level is achieved in the second cavity, allowing for a cleaner extraction and thorough removal of residual reactive gases and moisture from the second cavity after the formation of the fourth dielectric layer 24, thus avoiding any impact on subsequent processes. Specifically, the vacuuming time for the cavity after forming the second dielectric layer 22 is longer than the vacuuming time for the cavity after forming the fourth dielectric layer 24, ensuring a more complete and thorough removal of residual reactive gases and moisture from the cavity after multiple forming processes.

[0056] In some examples of the present invention, after forming the fourth dielectric layer 24, an electrode layer (not shown) is further formed on the fourth dielectric layer 24, thereby forming the first dielectric layer 21, the second dielectric layer 22, the third dielectric layer 23 and the fourth dielectric layer 24 between the electrode post 18 and the electrode layer to form the dielectric layer 2. The electrode layer, the electrode post 18 and the dielectric layer 2 together form a capacitor structure, and the thickness of the fourth dielectric layer 24 and the second dielectric layer 22 is more uniform, which can also improve the leakage protection performance of the semiconductor structure 100.

[0057] In some embodiments of the present invention, when an inert gas is introduced into the second chamber, the flow rate of the inert gas is 800 sccm-2000 sccm. For example, the flow rate of the inert gas can be 800 sccm, 1000 sccm, 1200 sccm, 1500 sccm, and 2000 sccm. The pressure in the second chamber is 0.5 torr-2.0 torr, that is, after the inert gas is introduced, the pressure in the second chamber can be controlled to be 0.5 torr-2.0 torr. For example, the pressure in the second chamber can be 0.5 torr, 0.8 torr, 1.0 torr, 1.5 torr, and 2.0 torr. By controlling the flow rate of the inert gas and the pressure in the chamber, a certain pressure and gas stability can be maintained in the chamber, preventing turbulence in the chamber from affecting the reaction film formation.

[0058] It should be noted that, after the formation of the third dielectric layer 23 and before the formation of the fourth dielectric layer 24, the flow rate of the inert gas introduced into the second cavity and the pressure range within the second cavity can be the same as the flow rate of the inert gas introduced into the second cavity and the pressure range within the second cavity before the formation of the second dielectric layer 22.

[0059] In some embodiments of the present invention, after evacuating the second cavity, the pressure inside the cavity is 0.2 torr to 2.0 torr, for example, the pressure inside the cavity can be 0.2 torr, 0.7 torr, 1.2 torr, 1.5 torr, and 2.0 torr. This ensures that the second cavity has a certain degree of vacuum, allowing for more thorough removal of residual reaction gases and water vapor. When evacuating the cavity after forming the fourth dielectric layer 24, the pressure inside the second cavity can also be 0.2 torr to 2.0 torr.

[0060] In some embodiments of the present invention, the flow rate of the reactant gas is 2000 sccm-4000 sccm, the pressure in the second chamber is 0.5 torr-2.0 torr, and the temperature in the second chamber is 300-400 degrees Celsius. This means the flow rate of the reactant gas reacting with the precursor can be controlled at 2000 sccm-4000 sccm. When the precursor reacts with the reactant gas to form a film, the pressure in the second chamber is in the range of 0.5 torr-2.0 torr, and the temperature in the second chamber is in the range of 300-400 degrees Celsius. This allows for the maintenance of a certain level of pressure and gas flow stability within the second chamber, which is beneficial for the formation of the second dielectric layer 22. Optionally, when the fourth dielectric layer 24 is formed, the flow rate of the reactant gas can also be 2000 sccm-4000 sccm, the pressure in the second chamber can be 0.5 torr-2.0 torr, and the temperature in the second chamber can be 300-400 degrees Celsius.

[0061] In some embodiments of the present invention, the flow rate of the precursor is 80 sccm-200 sccm, the pressure in the second chamber is 0.5 torr-2.0 torr, and the temperature in the second chamber is 300-400 degrees Celsius.

[0062] In some embodiments of the present invention, before forming the second dielectric layer 22, the inert gas is introduced into the second cavity for 8-20 seconds. For example, the inert gas can be introduced into the second cavity for 8, 12, 16, or 20 seconds before forming the second dielectric layer 22. Before forming the fourth dielectric layer 24, the inert gas is introduced into the second cavity for 4-8 seconds. For example, the inert gas can be introduced into the second cavity for 4, 5, 6, 7, or 8 seconds before forming the fourth dielectric layer 24. This removes moisture from the second cavity, resulting in a film of uniform thickness, while avoiding the influence of lattice thermal effects. The time for introducing the inert gas into the second cavity before forming the second dielectric layer 22 is longer than the time for introducing the inert gas into the second cavity before forming the fourth dielectric layer 24, to avoid the lattice transformation of the third dielectric layer 23 due to excessively long inert gas introduction time before forming the fourth dielectric layer 24, which would affect the leakage protection performance.

[0063] Furthermore, such as Figure 9 As shown, after the fourth dielectric layer 24 is formed, a fifth dielectric layer 25 and a sixth dielectric layer 26 can be formed sequentially on the surface of the fourth dielectric layer 24. The material of the fifth dielectric layer 25 is the same as that of the first dielectric layer 21 and the third dielectric layer 23, and the material of the sixth dielectric layer 26 can be the same as that of the second dielectric layer 22 and the fourth dielectric layer 24. Before the formation of the sixth dielectric layer 26, an inert gas can be introduced into the second cavity. The time for introducing the inert gas is less than the time for introducing the inert gas before the formation of the second dielectric layer 22. After the formation of the sixth dielectric layer 26, the second cavity can be evacuated.

[0064] In some embodiments, when the first cavity is under maintenance, moisture in the first cavity can be removed before the first dielectric layer 21 is formed, thereby improving the deposition uniformity of the first dielectric layer 21 or the third dielectric layer 23, which is beneficial to improving the performance of the device.

[0065] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate is provided, wherein the substrate includes spaced-apart electrode posts; The substrate is disposed in the first cavity, and a first dielectric layer is formed on the substrate, the first dielectric layer covering the electrode post; The substrate is transferred into the second cavity, and an inert gas is introduced into the second cavity to remove moisture from the second cavity. A precursor and a reactive gas are introduced into the second cavity to form a second dielectric layer on the first dielectric layer; The second cavity is evacuated to remove water vapor, and the pressure inside the second cavity is lower than the pressure inside the second cavity when the inert gas is introduced. The process includes, after vacuuming, forming a third dielectric layer on the second dielectric layer, wherein the material of the third dielectric layer is the same as that of the first dielectric layer, the third dielectric layer is formed within the first cavity, and the third dielectric layer is an amorphous structure. After the formation of the third dielectric layer, the process also includes: A fourth dielectric layer is formed on the third dielectric layer, the fourth dielectric layer being made of the same material as the second dielectric layer, and the fourth dielectric layer is formed within the second cavity; The process, which involves forming the third dielectric layer and before forming the fourth dielectric layer, further includes: Inert gas is introduced into the second cavity again to remove the water vapor inside the second cavity; Specifically, the time for introducing the inert gas into the second cavity before forming the fourth dielectric layer is less than the time for introducing the inert gas into the second cavity before forming the second dielectric layer, so as to avoid the lattice transformation of the third dielectric layer caused by introducing the inert gas for too long before forming the fourth dielectric layer.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The thickness of the third dielectric layer is less than the thickness of the first dielectric layer.

3. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The thickness of the first dielectric layer is greater than the thickness of the second dielectric layer, and the band gap width of the second dielectric layer is greater than the band gap width of the first dielectric layer.

4. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, After forming the fourth dielectric layer, the method further includes: The second cavity is evacuated again to remove moisture from it. The time for vacuuming the cavity after the formation of the second dielectric layer is longer than the time for vacuuming the second cavity after the formation of the fourth dielectric layer.

5. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, After forming the fourth dielectric layer, an electrode layer is also formed on the fourth dielectric layer.

6. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, When the inert gas is introduced into the second cavity, the flow rate of the inert gas is 800 sccm - 2000 sccm, and the pressure in the second cavity is 0.5 torr - 2.0 torr.

7. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, After the second cavity is evacuated, the pressure inside the second cavity is 0.2 torr-2.0 torr.

8. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The flow rate of the reaction gas is 2000 sccm-4000 sccm, the pressure in the second chamber is 0.5 torr-2.0 torr, and the temperature in the second chamber is 300-400 degrees Celsius.

9. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The flow rate of the precursor is 80 sccm - 200 sccm, the pressure in the second cavity is 0.5 torr - 2.0 torr, and the temperature in the second cavity is 300-400 degrees Celsius.

10. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, Before the formation of the second dielectric layer, the inert gas is introduced into the second cavity for 8 s - 20 s; before the formation of the fourth dielectric layer, the inert gas is introduced into the second cavity for 4 s - 8 s.

11. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The first dielectric layer includes a zirconium oxide layer, and the second dielectric layer includes an aluminum oxide layer.

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