A driving backplane, a manufacturing method thereof, a detection substrate, and a detection device

Abstract

The present invention provides a driving backplane and a method for manufacturing the same, a detection substrate, and a detection device, and relates to the field of optoelectronic technology. The present invention provides multiple driving modules on a substrate, each of which includes a reset transistor, a read transistor, an amplifier transistor, and a storage capacitor, and the active layer of the amplifier transistor is made of amorphous silicon or an oxide semiconductor. By providing multiple amplifier transistors in the driving backplane and using amorphous silicon or an oxide semiconductor as the material of the active layer of the amplifier transistor, the carrier mobility in each amplifier transistor in the driving backplane is relatively uniform, thereby improving the gain uniformity of each amplifier transistor in the driving backplane, avoiding image noise or even bad pixels and bad lines caused by uneven intensity of the electrical signal amplified by the amplifier transistor, and thus improving the imaging quality of the image generated based on the amplified signal line.

Description

Technical Field

[0001] The present invention relates to the technical field of optoelectronic technology, and in particular to a driving backplane and a manufacturing method thereof, a detection substrate and a detection device. Background Art

[0002] In the field of digital medical imaging, detection substrates are widely used as light detection sensing components. The driving backplane in the detection substrate can read the electrical signals generated by the photosensitive devices. However, due to the influence of the transistors in the driving backplane's own structure and electrical properties, the detection substrate will cause high noise. Especially at low doses, the signal-to-noise ratio of the detection substrate is relatively low.

[0003] Currently, in order to reduce noise, an amplifier transistor can be set in the driver backplane, and the noise can be reduced equivalently through the signal gain effect of the amplifier transistor.

[0004] However, the carrier mobility of each amplifier transistor in the current driving backplane is different, resulting in different signal gains of each amplifier transistor. The signal gains of the amplifier transistors in the driving backplane are uneven, and the strength of each electrical signal amplified by the amplifier transistors is also uneven, thereby generating fixed image noise and even bad pixels and bad lines, resulting in poor imaging quality of the image generated based on the amplified signal lines. Summary of the Invention

[0005] The present invention provides a driving backplane and a manufacturing method thereof, a detection substrate and a detection device, so as to solve the problem that the signal gains of various amplifying transistors arranged in the existing driving backplane are different, which will generate fixed image noise and even bad pixels and bad lines, resulting in poor imaging quality of images generated according to the amplified signal lines.

[0006] In order to solve the above problems, the present invention discloses a driving backplane, comprising: a base substrate and a plurality of driving modules arranged on the base substrate, each of the driving modules comprising a reset transistor, a read transistor, an amplifying transistor and a storage capacitor;

[0007] The reset transistor is connected to the storage capacitor and is configured to reset the storage capacitor;

[0008] The storage capacitor is connected to the photosensitive device and is configured to store the electrical signal generated by the photosensitive device;

[0009] The amplifying transistor is connected to the storage capacitor and is configured to amplify the electrical signal stored in the storage capacitor;

[0010] The reading transistor is connected to the amplifying transistor and is configured to read the electrical signal amplified by the amplifying transistor;

[0011] Wherein, the material of the active layer in the amplifying transistor is amorphous silicon or oxide semiconductor.

[0012] Optionally, the reset transistor includes a first active layer, a first gate insulating layer, a first gate, an interlayer dielectric layer and a first source-drain electrode sequentially arranged on one side of the substrate;

[0013] The first source electrode in the first source-drain electrode is connected to the first active layer through a first via hole penetrating the interlayer dielectric layer, and the first drain electrode in the first source-drain electrode is connected to the first active layer through a second via hole penetrating the interlayer dielectric layer.

[0014] Optionally, the read transistor includes a second active layer, the first gate insulating layer, a second gate, the interlayer dielectric layer, and a second source-drain electrode sequentially arranged on one side of the substrate;

[0015] The second source electrode in the second source-drain electrode is connected to the second active layer through a third via hole penetrating the interlayer dielectric layer, and the second drain electrode in the second source-drain electrode is connected to the second active layer through a fourth via hole penetrating the interlayer dielectric layer;

[0016] The first active layer and the second active layer are arranged in the same layer, the first gate and the second gate are arranged in the same layer, and the first source-drain electrode and the second source-drain electrode are arranged in the same layer.

[0017] Optionally, the driving backplane further comprises a buffer layer and a second gate insulating layer disposed between the base substrate and the first active layer, wherein the buffer layer is disposed on a side of the second gate insulating layer away from the base substrate;

[0018] The amplifying transistor includes a third gate, a second gate insulating layer, a third active layer, and a third source-drain electrode sequentially arranged on the substrate; a second source electrode in the second source-drain electrode is connected to a third drain electrode in the third source-drain electrode via a fifth via hole penetrating the interlayer dielectric layer;

[0019] The orthographic projection of the third active layer on the base substrate does not overlap with the orthographic projection of the buffer layer on the base substrate.

[0020] Optionally, the material of the third active layer is amorphous silicon, and the third active layer includes a first undoped amorphous silicon layer disposed on the second gate insulating layer, and a first doped amorphous silicon layer disposed on the first undoped amorphous silicon layer;

[0021] Alternatively, the material of the third active layer is an oxide semiconductor.

[0022] Optionally, the driving backplane further includes a second passivation layer covering the interlayer dielectric layer, the first source-drain electrode and the second source-drain electrode;

[0023] The amplifying transistor includes a fourth gate, the second passivation layer, a fourth active layer and a fourth source-drain electrode sequentially arranged on the interlayer dielectric layer;

[0024] In which, the fourth gate is arranged in the same layer as the first source-drain electrode and the second source-drain electrode, and the fourth gate is connected to the first source in the first source-drain electrode; the fourth drain in the fourth source-drain electrode is connected to the second source in the second source-drain electrode through a sixth via hole penetrating the second passivation layer.

[0025] Optionally, the material of the fourth active layer is amorphous silicon, and the fourth active layer includes a second undoped amorphous silicon layer disposed on the second passivation layer, and a second doped amorphous silicon layer disposed on the second undoped amorphous silicon layer;

[0026] Alternatively, the material of the fourth active layer is an oxide semiconductor.

[0027] Optionally, the storage capacitor includes a first electrode plate and a second electrode plate arranged opposite to each other, the first electrode plate and the first source-drain electrode are arranged in the same layer, the second electrode plate and the fourth source-drain electrode or the third source-drain electrode are arranged in the same layer, and the first electrode plate is connected to the first source electrode of the first source-drain electrode;

[0028] The orthographic projection of the first electrode plate on the base substrate at least partially overlaps with the orthographic projection of the second electrode plate on the base substrate.

[0029] In order to solve the above problems, the present invention further discloses a method for manufacturing a driving backplane, comprising:

[0030] providing a substrate;

[0031] A plurality of driving modules are formed on the substrate; each of the driving modules includes a reset transistor, a read transistor, an amplifying transistor and a storage capacitor;

[0032] Among them, the reset transistor is connected to the storage capacitor and is configured to reset the storage capacitor; the storage capacitor is connected to the photosensitive device and is configured to store the electrical signal generated by the photosensitive device; the amplifying transistor is connected to the storage capacitor and is configured to amplify the electrical signal stored in the storage capacitor; the reading transistor is connected to the amplifying transistor and is configured to read the electrical signal amplified by the amplifying transistor; the material of the active layer in the amplifying transistor is amorphous silicon or an oxide semiconductor.

[0033] In order to solve the above problem, the present invention further discloses a detection substrate, comprising a photosensitive device and the above-mentioned driving backplane, wherein the photosensitive device is connected to the driving backplane.

[0034] In order to solve the above problem, the present invention further discloses a detection device, including the above detection substrate.

[0035] Compared with the prior art, the present invention has the following advantages:

[0036] Multiple drive modules are provided on a substrate, each of which includes a reset transistor, a read transistor, an amplifier transistor, and a storage capacitor. The reset transistor is connected to the storage capacitor and configured to reset the storage capacitor. The storage capacitor is connected to a photosensitive device and configured to store an electrical signal generated by the photosensitive device. The amplifier transistor is connected to the storage capacitor and configured to amplify the electrical signal stored in the storage capacitor. The read transistor is connected to the amplifier transistor and configured to read the electrical signal amplified by the amplifier transistor. The active layer of the amplifier transistor is made of amorphous silicon or an oxide semiconductor. By providing multiple amplifier transistors in a drive backplane and using amorphous silicon or an oxide semiconductor as the material for the active layer of the amplifier transistor, the carrier mobility in each amplifier transistor in the drive backplane is relatively uniform. Therefore, the gain uniformity of each amplifier transistor in the drive backplane can be improved, and image noise or even bad pixels and bad lines caused by uneven intensity of the electrical signal amplified by the amplifier transistor can be avoided, thereby improving the imaging quality of the image generated based on the amplified signal line. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A cross-sectional view of a read transistor and an amplifier transistor in a first driving backplane according to an embodiment of the present invention is shown;

[0038] Figure 2 A cross-sectional view of a reset transistor and an amplifier transistor in a first driving backplane according to an embodiment of the present invention is shown;

[0039] Figure 3 A cross-sectional view of a read transistor and an amplifier transistor in a second driving backplane according to an embodiment of the present invention is shown;

[0040] Figure 4 A cross-sectional view of a reset transistor and an amplifier transistor in a second driving backplane according to an embodiment of the present invention is shown;

[0041] Figure 5 shows a cross-sectional view of a read transistor and an amplifier transistor in a third driving backplane according to an embodiment of the present invention;

[0042] Figure 6shows a cross-sectional view of a reset transistor and an amplifier transistor in a third driving backplane according to an embodiment of the present invention;

[0043] Figure 7 Shown Figures 1 to 6 The equivalent circuit diagram of the driving backplane shown;

[0044] Figure 8 A flow chart showing a method for manufacturing a driving backplane according to an embodiment of the present invention is shown;

[0045] Figure 9 Shown Figure 1 A cross-sectional view of the detection substrate corresponding to the driving backplane shown;

[0046] Figure 10 Shown Figure 2 A cross-sectional view of the detection substrate corresponding to the driving backplane shown;

[0047] Figure 11 Shown Figure 3 A cross-sectional view of the detection substrate corresponding to the driving backplane shown;

[0048] Figure 12 Shown Figure 4 The cross-sectional view of the detection substrate corresponding to the driving backplane is shown. DETAILED DESCRIPTION

[0049] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0050] In the related art, the material of the active layer of each amplifier transistor in the driving backplane is polycrystalline silicon, and the specific manufacturing process of the active layer in the amplifier transistor is: first depositing a layer of amorphous silicon layer, and then crystallizing the amorphous silicon layer through the ELA (Excimer Laser Annealing) process, thereby converting the amorphous silicon layer into a polycrystalline silicon layer.

[0051] However, due to the influence of factors such as the equipment and process of the crystallization treatment, when the laser annealing process is used for crystallization treatment, the crystallinity of the active layers of the various amplifying transistors in the driving backplane is inconsistent, which makes the carrier mobility of each amplifying transistor different, and further leads to different signal gains of each amplifying transistor, that is, the signal gain uniformity of each amplifying transistor in the driving backplane is poor. Therefore, after the electrical signal generated by the photosensitive device is amplified by the amplifying transistor, the intensity of each amplified electrical signal is also uneven, which is easy to generate fixed image noise or even bad pixels and bad lines, and the imaging quality of the image generated based on the amplified signal line is poor.

[0052] Therefore, the embodiment of the present invention provides multiple amplifier transistors in the driving backplane and uses amorphous silicon or oxide semiconductor as the material of the active layer in the amplifier transistors, so that the carrier mobility in each amplifier transistor in the driving backplane is relatively uniform. Therefore, the gain uniformity of each amplifier transistor in the driving backplane can be improved, and image noise or even bad pixels and bad lines caused by uneven intensity of the electrical signals amplified by the amplifier transistors can be avoided, thereby improving the imaging quality of the image generated based on the amplified signal lines.

[0053] Example 1

[0054] Reference Figure 1 , showing a cross-sectional view of a read transistor and an amplifying transistor in a first driving backplane according to an embodiment of the present invention, Figure 2 A cross-sectional view of a reset transistor and an amplifier transistor in a first driving backplane according to an embodiment of the present invention is shown; Figure 3 FIG2 shows a cross-sectional view of a read transistor and an amplifier transistor in a second driving backplane according to an embodiment of the present invention. Figure 4 A cross-sectional view of a reset transistor and an amplifier transistor in a second driving backplane according to an embodiment of the present invention is shown; Figure 5 FIG2 shows a cross-sectional view of a read transistor and an amplifier transistor in a third driving backplane according to an embodiment of the present invention. Figure 6 A cross-sectional view of a reset transistor and an amplifier transistor in a third driving backplane according to an embodiment of the present invention is shown.

[0055] An embodiment of the present invention provides a driving backplane, including: a base substrate 10 and a plurality of driving modules arranged on the base substrate 10 , each driving module including a reset transistor 20 , a read transistor 30 , an amplifying transistor 40 and a storage capacitor 50 .

[0056] The reset transistor 20 is connected to the storage capacitor 50 and is configured to reset the storage capacitor 50; the storage capacitor 50 is connected to the photosensitive device and is configured to store the electrical signal generated by the photosensitive device; the amplifier transistor 40 is connected to the storage capacitor 50 and is configured to amplify the electrical signal stored in the storage capacitor 50; the read transistor 30 is connected to the amplifier transistor 40 and is configured to read the electrical signal amplified by the amplifier transistor 40; wherein the material of the active layer in the amplifier transistor 40 is amorphous silicon or an oxide semiconductor.

[0057] In actual products, the base substrate 10 may be a glass substrate. A plurality of driving modules distributed in an array are provided on the base substrate 10 . Each driving module includes a reset transistor 20 , a read transistor 30 , an amplifying transistor 40 and a storage capacitor 50 .

[0058] During the actual driving process, the reset transistor 20 is first controlled to open, and the storage capacitor 50 is reset by the reset transistor 20 to release the charge stored in the storage capacitor 50; after the photosensitive device converts the light signal into an electrical signal, the storage capacitor 50 stores the electrical signal generated by the photosensitive device. The storage capacitor 50 can control the gate voltage of the amplifier transistor 40 based on the electrical signal generated by the photosensitive device. Based on the gate voltage of the amplifier transistor 40 and the Vdd voltage provided by the source of the amplifier transistor, the amplifier transistor 40 operates in the saturation region, and then the electrical signal stored in the storage capacitor 50 is amplified by the amplifier transistor 40; finally, the read transistor 30 is controlled to open to read the electrical signal amplified by the amplifier transistor 40.

[0059] The active layers of the reset transistor 20 and the read transistor 30 are both made of polysilicon, while the active layer of the amplifier transistor 40 is made of amorphous silicon or oxide semiconductor.

[0060] By adding an amplifier transistor 40 to the driving backplane, the noise is equivalently reduced through the signal gain effect of the amplifier transistor 40, thereby providing a higher signal-to-noise ratio at a low dose; and by setting the material of the active layer in the amplifier transistor 40 to amorphous silicon or an oxide semiconductor, the active layer in the amplifier transistor 40 will not be crystallized using a laser annealing process, which can make the carrier mobility in each amplifier transistor 40 in the driving backplane more uniform, improve the gain uniformity of each amplifier transistor 40 in the driving backplane, avoid image noise or even bad pixels and bad lines caused by uneven intensity of the electrical signal amplified by the amplifier transistor 40, thereby improving the imaging quality of the image generated according to the amplified signal line.

[0061] like Figure 2 、 Figure 4 and Figure 6 As shown, the reset transistor 20 includes a first active layer 21, a first gate insulating layer 22, a first gate electrode 23, an interlayer dielectric layer 24 and a first source-drain electrode arranged in sequence on one side of the base substrate 10; the first source-drain electrode includes a first source 251 and a first drain 252 arranged in the same layer; wherein, the first source 251 in the first source-drain electrode is connected to the first active layer 21 through a first via hole penetrating the interlayer dielectric layer 24, and the first drain 252 in the first source-drain electrode is connected to the first active layer 21 through a second via hole penetrating the interlayer dielectric layer 24.

[0062] The first active layer 21 is also the active layer of the reset transistor 20, and its material is polycrystalline silicon; and the first active layer 21 includes a non-doped area and doped areas located on both sides of the non-doped area. The first active layer 21 at the connection position with the first source 251 is the first active layer 21 located in the doped area, and the first active layer 21 at the connection position with the first drain 252 is also the first active layer 21 located in the doped area. By doping the first active layer 21 at the contact position of the first source 251 and the first drain 252, the ohmic contact between the first active layer 21 and the first source 251 and the first drain 252 is increased.

[0063] like Figure 1 、 Figure 3 and Figure 5 As shown, the reading transistor 30 includes a second active layer 31, a first gate insulating layer 22, a second gate electrode 33, an interlayer dielectric layer 24 and a second source-drain electrode arranged in sequence on one side of the base substrate 10; the second source-drain electrode includes a second source 351 and a second drain 352 arranged in the same layer; the second source 351 in the second source-drain electrode is connected to the second active layer 31 through a third via hole penetrating the interlayer dielectric layer 24, and the second drain 352 in the second source-drain electrode is connected to the second active layer 31 through a fourth via hole penetrating the interlayer dielectric layer 24; wherein, the first active layer 21 and the second active layer 31 are arranged in the same layer, the first gate electrode 23 and the second gate electrode 33 are arranged in the same layer, and the first source-drain electrode and the second source-drain electrode are arranged in the same layer.

[0064] The second active layer 31 is also the active layer of the read transistor 30, and its material is polycrystalline silicon; and the second active layer 31 includes a non-doped area and doped areas located on both sides of the non-doped area. The second active layer 31 at the connection position with the second source 351 is the second active layer 31 located in the doped area, and the second active layer 31 at the connection position with the second drain 352 is also the second active layer 31 located in the doped area. By doping the second active layer 31 at the contact position between the second source 351 and the second drain 352, the ohmic contact between the second active layer 31 and the second source 351 and the second drain 352 is increased.

[0065] It should be noted that the reset transistor 20 and the read transistor 30 can be either N-type transistors or P-type transistors. When the reset transistor 20 is a P-type transistor, the ions doped in the doping region of the first active layer 21 can be boron ions; when the reset transistor 20 is an N-type transistor, the ions doped in the doping region of the first active layer 21 can be phosphorus ions. Correspondingly, when the read transistor 30 is a P-type transistor, the ions doped in the doping region of the second active layer 31 can be boron ions; when the read transistor 30 is an N-type transistor, the ions doped in the doping region of the second active layer 31 can be phosphorus ions.

[0066] In an optional embodiment of the present invention, Figure 1 and Figure 2 As shown, the driving backplane also includes a buffer layer 72 and a second gate insulating layer 71 arranged between the base substrate 10 and the first active layer 21, and the buffer layer 72 is arranged on the side of the second gate insulating layer 71 away from the base substrate 10; the amplifying transistor 40 includes a third gate 41, a second gate insulating layer 71, a third active layer 42 and a third source-drain electrode arranged in sequence on the base substrate 10; the third source-drain electrode includes a third source 431 and a third drain 432 arranged in the same layer; the second source 351 in the second source-drain electrode is connected to the third drain 432 in the third source-drain electrode through a fifth via hole penetrating the interlayer dielectric layer 24; wherein, the orthographic projection of the third active layer 42 on the base substrate 10 and the orthographic projection of the buffer layer 72 on the base substrate 10 do not overlap.

[0067] Specifically, the third gate 41 in the amplifying transistor 40 is arranged on the base substrate 10, the second gate insulating layer 71 covers the third gate 41 and the base substrate 10, the buffer layer 72 is arranged on the second gate insulating layer 71, the first active layer 21 and the second active layer 31 are both arranged on the buffer layer 72, that is, the first active layer 21 and the second active layer 31 are both arranged on the side of the buffer layer 72 away from the base substrate 10; the first gate insulating layer 22 is arranged on the first active layer 21 and the second active layer 31, and the first gate 23 and the second gate 31 are arranged on the first active layer 21 and the second active layer 31. 3 is disposed on the first gate insulating layer 22; the third active layer 42 is disposed on the second gate insulating layer 71, and the third source-drain electrode is also disposed on the second gate insulating layer 71, and the third source-drain electrode partially covers the third active layer 42; the interlayer dielectric layer 24 covers the buffer layer 72, the first active layer 21, the second active layer 31, the first gate insulating layer 22, the first gate electrode 23, the second gate electrode 33, the third source-drain electrode, the third active layer 42, and the second gate insulating layer 71; the first source-drain electrode and the second source-drain electrode are disposed on the interlayer dielectric layer 24.

[0068] It is worth noting that there is no overlapping area between the orthographic projection of the third active layer 42 on the base substrate 10 and the orthographic projection of the buffer layer 72 on the base substrate 10, that is, the buffer layer 72 is only located in the area where the reset transistor 20 and the read transistor 30 are located, and the buffer layer material in the area where the amplifying transistor 40 is located is etched away. Therefore, the amplifying transistor 40 only includes the stacked third gate 41, the second gate insulating layer 71, the third active layer 42 and the third source-drain electrode.

[0069] The buffer layer 72 is a stacked structure including silicon nitride and silicon oxide, which has a heat preservation effect. In the actual manufacturing process, the film layers corresponding to the first active layer 21 of the reset transistor 20, the second active layer 31 of the read transistor 30 and the third active layer 42 of the amplifier transistor 40 are deposited simultaneously, that is, after the buffer layer 72 is formed by the composition process, a layer of amorphous silicon film is deposited. The amorphous silicon film is located in the area where the reset transistor 20, the read transistor 30 and the amplifier transistor 40 are located; the amorphous silicon film is patterned to form patterns corresponding to the first active layer 21, the second active layer 31 and the third active layer 42; then, the entire driving backplane including the patterned amorphous silicon film is subjected to excimer laser annealing. The region where the reset transistor 20 and the read transistor 30 are located has a buffer layer 72. The buffer layer 72 can keep the amorphous silicon in the region where the reset transistor 20 and the read transistor 30 are located at a higher temperature, so that the amorphous silicon in the region where the reset transistor 20 and the read transistor 30 are located can complete the crystallization process and change from amorphous silicon to polycrystalline silicon. However, the position where the amplifier transistor 40 is located does not have the buffer layer 72, so the amorphous silicon in the position where the amplifier transistor 40 is located cannot be in a high temperature environment for a long time. Therefore, the amorphous silicon in the position where the amplifier transistor 40 is located cannot complete the crystallization process, and the amorphous silicon in the position where the amplifier transistor 40 is located is not crystallized and remains amorphous silicon.

[0070] Therefore, by providing a buffer layer 72 in the region where the reset transistor 20 and the read transistor 30 are located, the process steps can be simplified while the materials of the first active layer 21 and the second active layer 31 can be made of polycrystalline silicon, while the third active layer 42 can be made of amorphous silicon. It should be noted that the third active layer 42 in this case refers to the first undoped amorphous silicon layer 421 in the third active layer 42.

[0071] like Figure 1 and Figure 2 As shown, the material of the third active layer 42 is amorphous silicon, and the third active layer 42 includes a first undoped amorphous silicon layer 421 disposed on the second gate insulating layer 71 , and a first doped amorphous silicon layer 422 disposed on the first undoped amorphous silicon layer 421 .

[0072] Specifically, the first doped amorphous silicon layer 422 is located in a partial area on the first undoped amorphous silicon layer 421. In the channel region of the first undoped amorphous silicon layer 421, the first doped amorphous silicon layer 422 is etched away, and the third source-drain electrode actually covers the first doped amorphous silicon layer 422 in the third active layer 42.

[0073] The material of the first undoped amorphous silicon layer 421 is amorphous silicon, which is not doped with any ions; and the material of the first doped amorphous silicon layer 422 is also amorphous silicon, which is doped with N-type ions, such as phosphorus ions.

[0074] The third active layer 42 is also the active layer of the amplifier transistor 40. When the material of the third active layer 42 in the amplifier transistor 40 is amorphous silicon, the first undoped amorphous silicon layer 421 in the third active layer 42 is not crystallized during the laser annealing process of the first active layer 21 and the second active layer 31. The subsequent formation of the first doped amorphous silicon layer 422 does not involve the laser annealing process. Therefore, the crystallinity of the third active layer 42 in the amplifier transistor 40 is not involved. The carrier mobility of each amplifier transistor 40 is relatively uniform, thereby improving the gain uniformity of each amplifier transistor 40 of the driving backplane.

[0075] The material of the third active layer 42 is an oxide semiconductor, which may specifically be IGZO (Indium Gallium Zinc Oxide), ITGO (Indium Tin Gallium Oxide), or other materials. When the third active layer 42 in the amplifier transistor 40 is made of an oxide semiconductor, it does not require laser annealing for crystallization, and the crystallinity of the third active layer 42 in the amplifier transistor 40 is not affected. As a result, the carrier mobility of each amplifier transistor 40 is more uniform, thereby improving the gain uniformity of each amplifier transistor 40 in the driver backplane.

[0076] Further, such as Figure 1 and Figure 2 As shown, the driving backplane further includes a light shielding layer 73 disposed on the base substrate 10 , and the light shielding layer 73 and the third gate 41 are disposed on the same layer; the second gate insulating layer 71 covers the light shielding layer 73 .

[0077] A light-shielding layer 73 is provided on the base substrate 10. The light-shielding layer 73 is located in the channel region of the reset transistor 20 and the read transistor 30. By providing the light-shielding layer 73, the channel region of the reset transistor 20 and the read transistor 30 is shielded from light, thereby preventing external ambient light from being irradiated from the base substrate 10 to the channel region of the reset transistor 20 and the read transistor 30, thereby preventing the performance of the reset transistor 20 and the read transistor 30 from being affected.

[0078] In the embodiment of the present invention, Figure 1 and Figure 2 As shown, the driving backplane further includes a first passivation layer 74 covering the interlayer dielectric layer 24, the first source-drain electrode, and the second source-drain electrode, and a first planarization layer 75 disposed on the first passivation layer 71. The material of the first passivation layer 74 can be silicon nitride and / or silicon oxide, and the material of the first planarization layer 75 is resin.

[0079] In addition, the driving backplane also has a seventh via 751 that penetrates the first flat layer 75, the first passivation layer 74, the interlayer dielectric layer 24 and the second gate insulation layer 71, and an eighth via 752 that penetrates the first flat layer 75 and the first passivation layer 74. The seventh via 751 is used to connect the third gate 41 of the amplifying transistor 40 to the first photosensitive electrode (i.e., the lower electrode) of the photosensitive device, and the eighth via 752 is used to connect the first source 251 in the first source-drain electrode of the reset transistor 20 to the first photosensitive electrode (i.e., the lower electrode) of the photosensitive device, so that the third gate 41 of the amplifying transistor 40 can be connected to the first source 251 in the first source-drain electrode of the reset transistor 20 through the first photosensitive electrode.

[0080] In another optional embodiment of the present invention, Figures 3 to 6 As shown, the driving backplane also includes a second passivation layer 76 covering the interlayer dielectric layer 24, the first source-drain electrode and the second source-drain electrode; the amplifying transistor 40 includes a fourth gate 44, a second passivation layer 76, a fourth active layer 45 and a fourth source-drain electrode arranged in sequence on the interlayer dielectric layer 24; the fourth source-drain electrode includes a fourth source 461 and a fourth drain 462 arranged in the same layer; wherein the fourth gate 44 and the first source-drain electrode and the second source-drain electrode are all arranged in the same layer, and the fourth gate 44 is connected to the first source 251 in the first source-drain electrode; the fourth drain 462 in the fourth source-drain electrode is connected to the second source 351 in the second source-drain electrode through a sixth via hole penetrating the second passivation layer 76.

[0081] Specifically, the first active layer 21 and the second active layer 31 are both directly arranged on the base substrate 10, the first gate insulating layer 22 is arranged on the first active layer 21 and the second active layer 31, and the first gate 23 and the second gate 33 are arranged on the first gate insulating layer 22; the interlayer dielectric layer 24 covers the first active layer 21, the second active layer 31, the first gate insulating layer 22, the first gate 23, the second gate 33 and the base substrate 10, and the first source-drain electrode, the second source-drain electrode and the fourth gate 44 are all arranged on the interlayer dielectric layer 24; the second passivation layer 76 covers the interlayer dielectric layer 24, the first source-drain electrode, the second source-drain electrode and the fourth gate 44, the fourth active layer 45 is arranged on the second passivation layer 76, the fourth source-drain electrode is also arranged on the second passivation layer 76, and the fourth source-drain electrode partially covers the fourth active layer 45.

[0082] like Figure 3 and Figure 4 As shown, the material of the fourth active layer 45 is amorphous silicon, and the fourth active layer 45 includes a second undoped amorphous silicon layer 451 disposed on the second passivation layer 76 , and a second doped amorphous silicon layer 452 disposed on the second undoped amorphous silicon layer 451 .

[0083] Specifically, the second doped amorphous silicon layer 452 is located in a partial area on the second undoped amorphous silicon layer 451. In the channel region of the second undoped amorphous silicon layer 451, the second doped amorphous silicon layer 452 is etched away, and the fourth source-drain electrode actually covers the second doped amorphous silicon layer 452 in the fourth active layer 45.

[0084] The material of the second undoped amorphous silicon layer 451 is amorphous silicon, which is not doped with any ions; and the material of the second doped amorphous silicon layer 452 is also amorphous silicon, which is doped with N-type ions.

[0085] The fourth active layer 45 is also the active layer of the amplifier transistor 40. When the material of the fourth active layer 45 in the amplifier transistor 40 is amorphous silicon, the second undoped amorphous silicon layer 451 and the second doped amorphous silicon layer 452 only need to be formed through a thin film deposition process and a composition process. There is no need to use a laser annealing process for crystallization treatment, and it does not involve the crystallinity of the fourth active layer 45 in the amplifier transistor 40. Then, the carrier mobility of each amplifier transistor 40 is relatively uniform, thereby improving the gain uniformity of each amplifier transistor 40 of the driving backplane.

[0086] It should be noted that when the material of the fourth active layer 45 is amorphous silicon, the fourth active layer 45 may also include only one amorphous silicon layer, with no ions doped in the channel region and N-type ions doped in the non-channel region.

[0087] like Figure 5 and Figure 6 As shown, the material of the fourth active layer 45 is an oxide semiconductor, which can be IGZO, ITGO, or other materials. When the material of the fourth active layer 45 in the amplifier transistor 40 is an oxide semiconductor, the fourth active layer 45 includes only one oxide semiconductor layer, which can be formed only through a thin film deposition process and a patterning process. It does not require a laser annealing process for crystallization, and the crystallinity of the fourth active layer 45 in the amplifier transistor 40 is not affected. As a result, the carrier mobility of each amplifier transistor 40 is relatively uniform, thereby improving the gain uniformity of each amplifier transistor 40 of the driving backplane.

[0088] It should be noted that when the material of the fourth active layer 45 is amorphous silicon, the material of the second passivation layer 76 can be silicon nitride or silicon oxide. Since the dielectric constant of silicon nitride is greater than the dielectric constant of silicon oxide, the material of the second passivation layer 76 is preferably silicon nitride, and its thickness can be 300nm to 500nm; when the material of the fourth active layer 45 is an oxide semiconductor, the material of the second passivation layer 76 is silicon oxide, and its thickness is 100nm to 200nm.

[0089] In the embodiment of the present invention, Figures 3 to 6As shown, the driving backplane further includes a second planar layer 77 covering the second passivation layer 76, the fourth active layer 45 and the fourth source-drain electrode. The material of the second planar layer 77 is resin.

[0090] In addition, the driving backplane also has a ninth via hole 771 penetrating the second planar layer 77 and the second passivation layer 76, and the ninth via hole 771 is used to connect the fourth gate 44 of the amplifying transistor 40 and the first source 251 of the reset transistor 20 to the first photosensitive electrode (ie, the lower electrode) of the photosensitive device.

[0091] In an embodiment of the present invention, the storage capacitor 50 includes a first electrode plate 51 and a second electrode plate 52 arranged relatively to each other, the first electrode plate 51 is arranged in the same layer as the first source-drain electrode, the second electrode plate 52 is arranged in the same layer as the fourth source-drain electrode or the third source-drain electrode, and the first electrode plate 51 is connected to the first source 251 in the first source-drain electrode; wherein the orthographic projection of the first electrode plate 51 on the base substrate 10 at least partially overlaps with the orthographic projection of the second electrode plate 52 on the base substrate 10.

[0092] like Figure 2 As shown, the first electrode plate 51 is arranged in the same layer as the first source-drain electrode, and the second electrode plate 52 is arranged in the same layer as the third source-drain electrode. By arranging the orthographic projection of the first electrode plate 51 on the base substrate 10 and the orthographic projection of the second electrode plate 52 on the base substrate 10 to at least partially overlap, the first electrode plate 51 and the second electrode plate 52 can form a storage capacitor 50. At this time, the interlayer dielectric layer 24 serves as an insulating dielectric layer between the first electrode plate 51 and the second electrode plate 52.

[0093] pass Figure 1 and Figure 2 The relationship between the film layers shown in Figure 7 As shown in the equivalent circuit diagram, it can be seen that the second source 351 in the read transistor 30 is connected to the third drain 432 in the amplifying transistor 40, and the first plate 51 of the storage capacitor 50 is connected to the first source 251 in the reset transistor 20; and since the first photosensitive electrode of the photosensor subsequently formed on the first flat layer 75 is respectively connected to the third gate 41 of the amplifying transistor 40 and the first source 251 of the reset transistor 20, the first photosensitive electrode of the photosensor 60, the third gate 41 of the amplifying transistor 40, the first source 251 of the reset transistor 20 and the first plate 51 of the storage capacitor 50 are all connected to each other.

[0094] like Figure 4 and Figure 6As shown, the first electrode 51 is arranged in the same layer as the first source-drain electrode, and the second electrode 52 is arranged in the same layer as the fourth source-drain electrode. By arranging the orthographic projection of the first electrode 51 on the base substrate 10 and the orthographic projection of the second electrode 52 on the base substrate 10 to at least partially overlap, the first electrode 51 and the second electrode 52 can form a storage capacitor 50. At this time, the second passivation layer 76 serves as an insulating dielectric layer between the first electrode 51 and the second electrode 52.

[0095] pass Figure 3 and Figure 4 The film relationship shown, or Figure 5 and Figure 6 The film layer relationships shown in Figure 7 As shown in the equivalent circuit diagram, it can be seen that the second source 351 in the read transistor 30 is connected to the fourth drain 462 in the amplifying transistor 40, and the first plate 51 of the storage capacitor 50, the fourth gate 44 of the amplifying transistor 40 and the first source 251 of the reset transistor 20 are all connected to each other; and since the first photosensitive electrode of the photosensor subsequently formed on the second flat layer 77 is respectively connected to the first source 251 of the reset transistor 20 and the fourth gate 44 of the amplifying transistor 40, the first photosensitive electrode of the photosensor 60, the fourth gate 44 of the amplifying transistor 40, the first source 251 of the reset transistor 20 and the first plate 51 of the storage capacitor 50 are all connected to each other.

[0096] In addition, Figure 7 In the embodiment, the second plate 52 of the storage capacitor 50 is connected to the first power signal line V0, and the first power signal line V0 is used to provide a constant voltage to the second plate 52 of the storage capacitor 50, and the first power signal line V0 and the second plate 52 are arranged on the same layer; the first gate 23 of the reset transistor 20 is connected to the reset signal line Reset, and the first drain 252 of the reset transistor 20 is connected to the initialization signal line Vinit, and the first gate 23 of the reset transistor 20 is arranged on the same layer as the reset signal line Reset, and the first drain 252 of the reset transistor 20 is also arranged on the same layer as the initialization signal line Vinit; the second gate 33 of the read transistor 30 is connected to the gate Gate is connected, the second drain 352 of the reading transistor 30 is connected to the reading signal line Read, the second gate 33 of the reading transistor 30 is set on the same layer as the gate Gate, and the second drain 352 of the reading transistor 30 is also set on the same layer as the reading signal line Read; the third source 431 or the fourth source 461 of the amplifying transistor 40 is connected to the second power signal line VDD, and the second power signal line VDD is used to provide a fixed high-level signal to the third source 431 or the fourth source 461 of the amplifying transistor 40, and the second power signal line VDD is set on the same layer as the third source 431 of the amplifying transistor 40 or the fourth source 461 of the amplifying transistor 40.

[0097] Furthermore, the driving backplane includes M rows and N columns of driving modules. At this time, the driving backplane includes M gate lines Gate and N read signal lines Read, and the gate lines Gate are distributed along the row direction of the driving backplane, and the read signal lines Read are distributed along the column direction of the driving backplane. The second gate 33 of the read transistor 30 in the driving module located in the same row is connected to the same gate Gate, and the second drain 352 of the read transistor 30 in the driving module located in the same column is connected to the same read signal line Read, and M and N are both positive integers greater than 1.

[0098] It should be noted that the above only gives two setting positions corresponding to the storage capacitor 50. Of course, the specific setting position of the storage capacitor 50 in the embodiment of the present invention is not limited to the above two positions. The first electrode 51 and the second electrode 52 can be respectively set on both sides of any one or more insulating dielectric layers. For example, the first photosensitive electrode set on the second flat layer 77 can also be used as the first electrode 51, and the second electrode 52 and the fourth source-drain electrode are set on the same layer on the second passivation layer 76. At this time, the second flat layer 77 serves as the insulating dielectric layer between the first electrode 51 and the second electrode 52.

[0099] In an embodiment of the present invention, by providing a plurality of amplifying transistors in a driving backplane and using amorphous silicon or oxide semiconductor as the material of the active layer in the amplifying transistors, the carrier mobility in each amplifying transistor in the driving backplane is made relatively uniform. Therefore, the gain uniformity of each amplifying transistor in the driving backplane can be improved, and image noise or even bad pixels and bad lines caused by uneven intensity of the electrical signals amplified by the amplifying transistors can be avoided, thereby improving the imaging quality of images generated based on the amplified signal lines.

[0100] Example 2

[0101] Reference Figure 8 , shows a flow chart of a method for manufacturing a driving backplane according to an embodiment of the present invention, which may specifically include the following steps:

[0102] Step 801: Provide a base substrate.

[0103] In the embodiment of the present invention, when manufacturing the driving backplane, a base substrate 10 is first provided. The base substrate 10 may be a glass substrate.

[0104] Step 802 : forming a plurality of driving modules on the substrate; each of the driving modules includes a reset transistor, a read transistor, an amplifying transistor, and a storage capacitor.

[0105] In an embodiment of the present invention, a plurality of driving modules are formed on the base substrate 10, and each driving module includes a reset transistor 20, a read transistor 30, an amplifying transistor 40 and a storage capacitor 50. That is, a plurality of reset transistors 20, a plurality of read transistors 30, a plurality of amplifying transistors 40 and a plurality of storage capacitors 50 are respectively formed on the base substrate 10.

[0106] Among them, the reset transistor 20 is connected to the storage capacitor 50 and is configured to reset the storage capacitor 50; the storage capacitor 50 is connected to the photosensitive device and is configured to store the electrical signal generated by the photosensitive device; the amplifier transistor 40 is connected to the storage capacitor 50 and is configured to amplify the electrical signal stored in the storage capacitor 50; the read transistor 30 is connected to the amplifier transistor 40 and is configured to read the electrical signal amplified by the amplifier transistor 40; wherein the material of the active layer in the amplifier transistor 40 is amorphous silicon or an oxide semiconductor.

[0107] In an optional embodiment of the present invention, step 802 specifically includes sub-steps S8021 to S8029:

[0108] Sub-step S8021, forming a third gate on the base substrate;

[0109] Sub-step S8022, forming a second gate insulating layer covering the third gate;

[0110] Sub-step S8023, forming a buffer layer on the second gate insulating layer;

[0111] Sub-step S8024, forming a first active layer and a second active layer on the buffer layer, and forming a third active layer on the second gate insulating layer;

[0112] Sub-step S8025, forming a first gate insulating layer on the first active layer and the second active layer;

[0113] Sub-step S8026, forming a first gate and a second gate on the first gate insulating layer;

[0114] Sub-step S8027, forming a second electrode plate and a third source-drain electrode partially covering the third active layer on the second gate insulating layer;

[0115] Sub-step S8028, forming an interlayer dielectric layer; the interlayer dielectric layer covers the buffer layer, the first active layer, the second active layer, the first gate insulating layer, the first gate electrode, the second gate electrode, the third active layer, the third source-drain electrode, the second electrode plate, and the second gate insulating layer;

[0116] Sub-step S8029, forming a first source-drain electrode, a second source-drain electrode and a first electrode plate on the interlayer dielectric layer; wherein the first electrode plate is connected to the first source in the first source-drain electrode; the second source in the second source-drain electrode is connected to the third drain in the third source-drain electrode through a fifth via hole penetrating the interlayer dielectric layer.

[0117] First, a third gate 41 is formed on the base substrate 10 by a patterning process, and then a second gate insulating layer 71 covering the third gate 41 and the base substrate 10 is formed. A buffer layer 72 is further formed on the second gate insulating layer 71 by a patterning process, so that the buffer layer 72 is only located in the area where the reset transistor 20 and the read transistor 30 are located, and the buffer layer material in the area where the amplifier transistor 40 is located is etched away; then, a layer of amorphous silicon thin film is deposited, and the amorphous silicon thin film is located in the reset transistor 20, the read transistor 30 and the amplifier transistor 40. 0, the amorphous silicon thin film is patterned to form a first active layer 21 and a second active layer 31 on the buffer layer 72, and a third active layer 42 on the second gate insulating layer 71. The entire driver backplane, including the first active layer 21, the second active layer 31, and the third active layer 42, is then subjected to excimer laser annealing. This changes the first active layer 21 of the reset transistor 20 and the second active layer 31 of the read transistor 30 from amorphous silicon to polycrystalline silicon, while the third active layer 42 of the amplifier transistor 40 remains amorphous silicon. It should be noted that the third active layer 42 formed at this time refers to the first undoped amorphous silicon layer 421 in the third active layer 42.

[0118] After forming the first active layer 21, the second active layer 31 and the third active layer 42, a first gate insulating layer 22 is formed on the first active layer 21 and the second active layer 31 by a patterning process. Then, a first gate electrode 23 and a second gate electrode 33 are formed on the first gate insulating layer 22 by a patterning process, and ion implantation is performed on the doped regions in the first active layer 21 and the second active layer 31 by a self-alignment process.

[0119] Next, a first doped amorphous silicon layer 422 is formed on the first undoped amorphous silicon layer 421 in the third active layer 42 by a patterning process; then a second electrode 52 and a third source-drain electrode partially covering the third active layer 42 are formed on the second gate insulating layer 71 by a patterning process.

[0120] Then, an interlayer dielectric layer 24 is formed, which covers the buffer layer 72, the first active layer 21, the second active layer 31, the first gate insulation layer 22, the first gate 23, the second gate 33, the third source-drain electrode, the third active layer 42, the second electrode 52 and the second gate insulation layer 71, and forms a first via hole, a second via hole, a third via hole, a fourth via hole and a fifth via hole penetrating the interlayer dielectric layer 24.

[0121] Finally, a first source-drain electrode, a second source-drain electrode, and a first electrode plate 51 are formed on the interlayer dielectric layer 24 through a patterning process. The first source electrode 251 in the first source-drain electrode is connected to the first active layer 21 through a first via hole penetrating the interlayer dielectric layer 24, and the first drain electrode 252 in the first source-drain electrode is connected to the first active layer 21 through a second via hole penetrating the interlayer dielectric layer 24. The second source electrode 351 in the second source-drain electrode is connected to the second active layer 31 through a third via hole penetrating the interlayer dielectric layer 24, and the second drain electrode 352 in the second source-drain electrode is connected to the second active layer 31 through a fourth via hole penetrating the interlayer dielectric layer 24. The second source electrode 351 in the second source-drain electrode is connected to the third drain electrode 432 in the third source-drain electrode through a fifth via hole penetrating the interlayer dielectric layer 24. Furthermore, the first electrode plate 51 is connected to the first source electrode 251 in the first source-drain electrode.

[0122] Furthermore, after forming the first source-drain electrode, the second source-drain electrode, and the first electrode plate 51 on the interlayer dielectric layer 24, a first passivation layer 74 is formed to cover the interlayer dielectric layer 24, the first source-drain electrode, the second source-drain electrode, and the first electrode plate 51. Then, a first planarization layer 75 is formed on the first passivation layer 74. Furthermore, the first planarization layer 75 is exposed and developed to remove portions of the first planarization layer 75, thereby exposing the first passivation layer 74. The exposed first passivation layer 74 is etched to form an eighth via hole 752 penetrating the first planarization layer 75 and the first passivation layer 74. Furthermore, the exposed first passivation layer 74, the interlayer dielectric layer 24 below the first passivation layer 74, and the second gate insulation layer 71 are etched to form a seventh via hole 751 penetrating the first planarization layer 75, the first passivation layer 74, the interlayer dielectric layer 24, and the second gate insulation layer 71.

[0123] Of course, when the third gate 41 is formed on the base substrate 10 through a patterning process, a light shielding layer 73 may also be formed on the base substrate 10 at the same time. The light shielding layer 73 and the third gate 41 are formed simultaneously through the same patterning process.

[0124] It should be noted that the above only provides a specific manufacturing process when the material of the third active layer 42 is amorphous silicon. When the material of the third active layer 42 is an oxide semiconductor, it is formed using a separate patterning process. The third active layer 42 can be manufactured after the first gate 23 and the second gate 33 are formed, or before the first gate 23 and the second gate 33 are formed. The embodiment of the present invention does not impose any restrictions on this.

[0125] In another optional embodiment of the present invention, step 802 specifically includes sub-steps S8031 to S8038:

[0126] Sub-step S8031, forming a first active layer and a second active layer on the base substrate;

[0127] Sub-step S8032, forming a first gate insulating layer on the first active layer and the second active layer;

[0128] Sub-step S8033, forming a first gate and a second gate on the first gate insulating layer;

[0129] Sub-step S8034: forming an interlayer dielectric layer; the interlayer dielectric layer covers the first active layer, the second active layer, the first gate insulating layer, the first gate electrode, the second gate electrode, and the base substrate;

[0130] Sub-step S8035, forming a first source-drain electrode, a second source-drain electrode, a fourth gate and a first electrode plate on the interlayer dielectric layer;

[0131] Sub-step S8036, forming a second passivation layer; the second passivation layer covers the interlayer dielectric layer, the first source-drain electrode, the second source-drain electrode, the fourth gate and the first electrode;

[0132] Sub-step S8037, forming a fourth active layer on the second passivation layer;

[0133] Sub-step S8038, forming a second electrode on the second passivation layer and a fourth source-drain electrode partially covering the fourth active layer; wherein the fourth gate is connected to the first source in the first source-drain electrode; the fourth drain in the fourth source-drain electrode is connected to the second source in the second source-drain electrode through a sixth via hole penetrating the second passivation layer; and the first electrode is connected to the first source in the first source-drain electrode.

[0134] First, a first active layer 21 and a second active layer 31 are formed on the base substrate 10 by a patterning process, and the first active layer 21 and the second active layer 31 are subjected to excimer laser annealing treatment, so that the first active layer 21 and the second active layer 31 are changed from amorphous silicon to polycrystalline silicon; then, a first gate insulating layer 22 is formed on the first active layer 21 and the second active layer 31 by a patterning process, a first gate electrode 23 and a second gate electrode 33 are formed on the first gate insulating layer 22 by a patterning process, and ion implantation is performed on the doped regions in the first active layer 21 and the second active layer 31 by a self-aligned process; then, an interlayer dielectric layer 24 is formed, which covers the first active layer 21, the second active layer 31, the first gate insulating layer 22, the first gate electrode 23, the second gate electrode 33 and the base substrate 10, and a first via hole, a second via hole, a third via hole and a fourth via hole are formed through the interlayer dielectric layer 24.

[0135] Then, a first source-drain electrode, a second source-drain electrode, a fourth gate electrode 44, and a first electrode plate 51 are formed on the interlayer dielectric layer 24 through a patterning process. The first source electrode 251 in the first source-drain electrode is connected to the first active layer 21 through a first via hole penetrating the interlayer dielectric layer 24, and the first drain electrode 252 in the first source-drain electrode is connected to the first active layer 21 through a second via hole penetrating the interlayer dielectric layer 24. The second source electrode 351 in the second source-drain electrode is connected to the second active layer 31 through a third via hole penetrating the interlayer dielectric layer 24, and the second drain electrode 352 in the second source-drain electrode is connected to the second active layer 31 through a fourth via hole penetrating the interlayer dielectric layer 24. Furthermore, the fourth gate electrode 44, the first electrode plate 51, and the first source electrode 251 in the first source-drain electrode are all connected to each other.

[0136] Next, a second passivation layer 76 is formed. The second passivation layer 76 covers the interlayer dielectric layer 24 , the first source-drain electrode, the second source-drain electrode, the fourth gate 44 and the first electrode 51 .

[0137] After the second passivation layer 76 is formed, a fourth active layer 45 is formed on the second passivation layer 76 by a patterning process. The material of the fourth active layer 45 is amorphous silicon or an oxide semiconductor. When the material of the fourth active layer 45 is amorphous silicon, it can be formed into an amorphous silicon layer by a single patterning process and then ion implanted into the amorphous silicon layer, or it can be formed into a second undoped amorphous silicon layer 451 and a second doped amorphous silicon layer 452 by two patterning processes.

[0138] Then, a sixth via hole is formed through the second passivation layer 76, and then a second electrode 52 and a fourth source-drain electrode partially covering the fourth active layer 45 are formed on the second passivation layer 76 by a patterning process, so that the fourth source-drain electrode is connected to the second source 351 in the second source-drain electrode through the sixth via hole through the second passivation layer 76.

[0139] Furthermore, after forming the second electrode 52 and the fourth source-drain electrode partially covering the fourth active layer 45 on the second passivation layer 76, it is necessary to form a second flat layer 77 covering the second passivation layer 76, the fourth active layer 45 and the fourth source-drain electrode, and form a ninth via hole 771 passing through the second flat layer 77 and the second passivation layer 76.

[0140] In an embodiment of the present invention, by providing a plurality of amplifying transistors in a driving backplane and using amorphous silicon or oxide semiconductor as the material of the active layer in the amplifying transistors, the carrier mobility in each amplifying transistor in the driving backplane is made relatively uniform. Therefore, the gain uniformity of each amplifying transistor in the driving backplane can be improved, and image noise or even bad pixels and bad lines caused by uneven intensity of the electrical signals amplified by the amplifying transistors can be avoided, thereby improving the imaging quality of images generated based on the amplified signal lines.

[0141] Example 3

[0142] Reference Figure 9 , showing Figure 1 The cross-sectional view of the detection substrate corresponding to the driving backplane shown, Figure 10 Shown Figure 2 The cross-sectional view of the detection substrate corresponding to the driving backplane shown, Figure 11 Shown Figure 3 The cross-sectional view of the detection substrate corresponding to the driving backplane shown, Figure 12 Shown Figure 4 The cross-sectional view of the detection substrate corresponding to the driving backplane is shown.

[0143] The embodiment of the present invention provides a detection substrate, comprising a photosensitive device 60 and the aforementioned driving backplane, wherein the photosensitive device 60 is connected to the driving backplane. Specifically, the photosensitive device 60 is connected to the reset transistor 20, the amplifying transistor 40 and the storage capacitor 50 in the driving backplane.

[0144] In the embodiment of the present invention, the photosensitive device 60 includes a first photosensitive electrode 61 , a second photosensitive electrode 63 , and a photosensitive layer 62 disposed between the first photosensitive electrode 61 and the second photosensitive electrode 63 .

[0145] like Figure 9 and Figure 10 As shown, the first photosensitive electrode 61 is connected to the third gate 41 through a seventh via hole 751 that penetrates the first planar layer 75, the first passivation layer 74, the interlayer dielectric layer 24, and the second gate insulating layer 71. The first photosensitive electrode 61 is also connected to the first source electrode 251 of the first source-drain electrode through an eighth via hole 752 that penetrates the first planar layer 75 and the first passivation layer 74. In this case, the first photosensitive electrode 61 is disposed on a side of the first planar layer 75 away from the base substrate 10.

[0146] like Figure 11 and Figure 12 As shown, the first photosensitive electrode 61 is connected to the fourth gate 44 through a ninth via hole 771 penetrating the second planar layer 77 and the second passivation layer 76. At this time, the first photosensitive electrode 61 is disposed on a side of the second planar layer 77 away from the base substrate 10.

[0147] Among them, the first photosensitive electrode 61 serves as the lower electrode of the photosensitive device 60, and the second photosensitive electrode 63 serves as the upper electrode of the photosensitive device 60. In order to ensure that the rays can normally pass through the second photosensitive electrode 63 and be incident on the photosensitive layer 62, it is necessary to use a transparent conductive material to make the second photosensitive electrode 63, that is, the material of the second photosensitive electrode 63 is a transparent conductive material, such as ITO (Indium Tin Oxides, indium tin oxide) and the like.

[0148] In an optional embodiment of the present invention, the material of the photosensitive layer 62 is a direct conversion material, such as an organic material, perovskite, mercuric iodide, lead iodide, lead oxide, bismuth iodide or Cd 1-x Zn x Te (cadmium zinc telluride), etc., which can directly convert X-rays, gamma rays or other rays into electrical signals. At this time, a third passivation layer 81 is further provided on the side of the second photosensitive electrode 63 away from the photosensitive layer 62 .

[0149] In another optional embodiment of the present invention, the detection substrate also includes a third passivation layer 81 and a scintillator layer 82 which are sequentially arranged on the side of the second photosensitive electrode 63 away from the photosensitive layer 62; the photosensitive layer 62 includes a first doped layer 621, an intrinsic layer 622 and a second doped layer 623 which are sequentially arranged on the side of the first photosensitive electrode 61 away from the driving backplane.

[0150] At this time, the photosensitive layer 62 is actually a photodiode, which cannot directly convert X-rays, gamma rays or other rays into electrical signals, but can only convert visible light into electrical signals. Therefore, a scintillator layer 82 needs to be added. X-rays, gamma rays or other rays are converted into visible light through the scintillator layer 82, and the visible light is then irradiated onto the photosensitive layer 62 through the third passivation layer 81 and the second photosensitive electrode 63, thereby converting the visible light into electrical signals through the photosensitive layer 62.

[0151] The first doped layer 621 may be a P-type layer, the intrinsic layer 622 may be an I-type layer, and the second doped layer 623 may be an N-type layer; alternatively, the first doped layer 621 may be an N-type layer, the intrinsic layer 622 may be an I-type layer, and the second doped layer 623 may be an I-type layer. Furthermore, the material of the I-type layer is perovskite, and the materials of the P-type layer and the N-type layer are organic or inorganic materials; alternatively, the materials of the P-type layer, the I-type layer, and the N-type layer are all organic materials.

[0152] It should be noted that Figure 9 and Figure 10 The structure shown is that the photosensitive layer 62 is a direct conversion material, that is, a direct conversion type photosensitive layer 62. Figure 11 and Figure 12 The photosensitive layer 62 is a photodiode structure, that is, an indirect conversion type photosensitive layer 62. Both types of photosensitive layers 62 can be arranged in Figures 1 to 6 Any of the drive backplanes, not limited to Figure 1 and Figure 2 The driving backplane shown in FIG. 1 is provided with a direct conversion photosensitive layer 62, and Figure 3 and Figure 4 The driving backplane shown is provided with an indirect conversion type photosensitive layer 62.

[0153] like Figures 9 to 12As shown, the orthographic projection of the photosensitive device 60 on the base substrate 10 covers the orthographic projections of the reset transistor 20, the read transistor 30, the amplifying transistor 40, and the storage capacitor 50 on the base substrate 10. That is, the photosensitive device 60 is provided on the entire driving backplane, and the photosensitive device 60 occupies substantially 100% of the area of the entire detection substrate, thereby improving the fill factor of the detection substrate, preventing the reset transistor 20, the read transistor 30, the amplifying transistor 40, and the storage capacitor 50 in the driving backplane from excessively occupying the photosensitive area, and improving the photoelectric conversion efficiency.

[0154] Alternatively, the orthographic projection of the photosensitive device 60 on the base substrate 10 does not overlap with the orthographic projections of the reset transistor 20 , the read transistor 30 , the amplifying transistor 40 and the storage capacitor 50 on the base substrate 10 .

[0155] At this time, the area of the detection substrate is the sum of the areas of the reset transistor 20, the read transistor 30, the amplifying transistor 40 and the storage capacitor 50, and the area of the photosensitive device 60, and the area of the photosensitive device 60 accounts for 60% to 70% of the area of the detection substrate.

[0156] An embodiment of the present invention further provides a detection device, including the above-mentioned detection substrate. The detection device may be an FPD (Flat Panel Detector).

[0157] In an embodiment of the present invention, by providing a plurality of amplifying transistors in a driving backplane and using amorphous silicon or oxide semiconductor as the material of the active layer in the amplifying transistors, the carrier mobility in each amplifying transistor in the driving backplane is made relatively uniform. Therefore, the gain uniformity of each amplifying transistor in the driving backplane can be improved, and image noise or even bad pixels and bad lines caused by uneven intensity of the electrical signals amplified by the amplifying transistors can be avoided, thereby improving the imaging quality of images generated based on the amplified signal lines.

[0158] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0159] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity, or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, commodity, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, commodity, or device that includes the element.

[0160] The above is a detailed introduction to a driving backplane and its manufacturing method, a detection substrate and a detection device provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for general technical personnel in this field, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A driving backplane, characterized in that: include: A base substrate and a plurality of driving modules disposed on the base substrate, each of the driving modules comprising a reset transistor, a read transistor, an amplifying transistor and a storage capacitor; The reset transistor is connected to the storage capacitor and is configured to reset the storage capacitor; The storage capacitor is connected to the photosensitive device and is configured to store the electrical signal generated by the photosensitive device; The amplifying transistor is connected to the storage capacitor and is configured to amplify the electrical signal stored in the storage capacitor; The reading transistor is connected to the amplifying transistor and is configured to read the electrical signal amplified by the amplifying transistor; Wherein, the material of the active layer in the amplifying transistor is amorphous silicon or oxide semiconductor; The reset transistor comprises a first active layer, a first gate insulating layer, a first gate, an interlayer dielectric layer and a first source-drain electrode sequentially arranged on one side of the substrate; The first source electrode of the first source-drain electrode is connected to the first active layer through a first via hole penetrating the interlayer dielectric layer, and the first drain electrode of the first source-drain electrode is connected to the first active layer through a second via hole penetrating the interlayer dielectric layer. The read transistor includes a second active layer, the first gate insulating layer, a second gate, the interlayer dielectric layer and a second source-drain electrode sequentially arranged on one side of the substrate; The second source electrode in the second source-drain electrode is connected to the second active layer through a third via hole penetrating the interlayer dielectric layer, and the second drain electrode in the second source-drain electrode is connected to the second active layer through a fourth via hole penetrating the interlayer dielectric layer; Wherein, the first active layer and the second active layer are provided in the same layer, the first gate and the second gate are provided in the same layer, and the first source-drain electrode and the second source-drain electrode are provided in the same layer; The driving backplane further includes a buffer layer and a second gate insulating layer disposed between the base substrate and the first active layer, wherein the buffer layer is disposed on a side of the second gate insulating layer away from the base substrate; The amplifying transistor includes a third gate, a second gate insulating layer, a third active layer, and a third source-drain electrode sequentially arranged on the substrate; a second source electrode in the second source-drain electrode is connected to a third drain electrode in the third source-drain electrode via a fifth via hole penetrating the interlayer dielectric layer; The orthographic projection of the third active layer on the base substrate does not overlap with the orthographic projection of the buffer layer on the base substrate.

2. The driving backplane according to claim 1, characterized in that: The material of the third active layer is amorphous silicon, and the third active layer includes a first undoped amorphous silicon layer disposed on the second gate insulating layer, and a first doped amorphous silicon layer disposed on the first undoped amorphous silicon layer; Alternatively, the material of the third active layer is an oxide semiconductor.

3. The driving backplane according to claim 1, characterized in that: The driving backplane further includes a second passivation layer covering the interlayer dielectric layer, the first source-drain electrode and the second source-drain electrode; The amplifying transistor includes a fourth gate, the second passivation layer, a fourth active layer and a fourth source-drain electrode sequentially arranged on the interlayer dielectric layer; In which, the fourth gate is arranged in the same layer as the first source-drain electrode and the second source-drain electrode, and the fourth gate is connected to the first source in the first source-drain electrode; the fourth drain in the fourth source-drain electrode is connected to the second source in the second source-drain electrode through a sixth via hole penetrating the second passivation layer.

4. The driving backplane according to claim 3, characterized in that: The material of the fourth active layer is amorphous silicon, and the fourth active layer includes a second undoped amorphous silicon layer disposed on the second passivation layer, and a second doped amorphous silicon layer disposed on the second undoped amorphous silicon layer; Alternatively, the material of the fourth active layer is an oxide semiconductor.

5. The driving backplane according to claim 1, characterized in that: The storage capacitor includes a first plate and a second plate arranged opposite to each other, the first plate and the first source-drain electrode are arranged in the same layer, the second plate and the third source-drain electrode are arranged in the same layer, and the first plate is connected to the first source electrode of the first source-drain electrode; The orthographic projection of the first electrode plate on the base substrate at least partially overlaps with the orthographic projection of the second electrode plate on the base substrate.

6. The driving backplane according to claim 3, characterized in that: The storage capacitor includes a first plate and a second plate arranged opposite to each other, the first plate and the first source-drain electrode are arranged in the same layer, the second plate and the fourth source-drain electrode are arranged in the same layer, and the first plate is connected to the first source electrode of the first source-drain electrode; The orthographic projection of the first electrode plate on the base substrate at least partially overlaps with the orthographic projection of the second electrode plate on the base substrate.

7. A method for manufacturing a driving backplane, characterized in that: include: providing a substrate; forming a plurality of driving modules on the base substrate; Each of the driving modules includes a reset transistor, a read transistor, an amplifying transistor and a storage capacitor; The reset transistor is connected to the storage capacitor and is configured to reset the storage capacitor; the storage capacitor is connected to the photosensitive device and is configured to store the electrical signal generated by the photosensitive device; the amplifier transistor is connected to the storage capacitor and is configured to amplify the electrical signal stored in the storage capacitor; the read transistor is connected to the amplifier transistor and is configured to read the electrical signal amplified by the amplifier transistor; the active layer in the amplifier transistor is made of amorphous silicon or an oxide semiconductor; The reset transistor includes a first active layer, a first gate insulating layer, a first gate, an interlayer dielectric layer, and a first source-drain electrode sequentially arranged on one side of the substrate; wherein a first source electrode of the first source-drain electrode is connected to the first active layer via a first via hole penetrating the interlayer dielectric layer, and a first drain electrode of the first source-drain electrode is connected to the first active layer via a second via hole penetrating the interlayer dielectric layer; The read transistor includes a second active layer, the first gate insulating layer, a second gate, the interlayer dielectric layer, and a second source-drain electrode sequentially arranged on one side of the substrate; a second source electrode in the second source-drain electrode is connected to the second active layer via a third via hole penetrating the interlayer dielectric layer, and a second drain electrode in the second source-drain electrode is connected to the second active layer via a fourth via hole penetrating the interlayer dielectric layer; wherein the first active layer and the second active layer are arranged in the same layer, the first gate and the second gate are arranged in the same layer, and the first source-drain electrode and the second source-drain electrode are arranged in the same layer; The driving backplane also includes a buffer layer and a second gate insulating layer arranged between the base substrate and the first active layer, and the buffer layer is arranged on the side of the second gate insulating layer away from the base substrate; the amplifying transistor includes a third gate, a second gate insulating layer, a third active layer and a third source-drain electrode arranged in sequence on the base substrate; the second source in the second source-drain electrode is connected to the third drain in the third source-drain electrode through a fifth via hole penetrating the interlayer dielectric layer; wherein, the orthographic projection of the third active layer on the base substrate and the orthographic projection of the buffer layer on the base substrate do not overlap with each other.

8. A detection substrate, characterized in that The device comprises a photosensitive device and a driving backplane according to any one of claims 1 to 6, wherein the photosensitive device is connected to the driving backplane.

9. A detection device, characterized in that: Comprising the detection substrate as claimed in claim 8.

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