Signal equalization method, signal equalization unit and data receiving interface device

Abstract

The present application discloses a signal equalization method, a signal equalization unit, a data receiving interface device, and a data acquisition device. The signal equalization method includes the following steps: receiving a test signal in a correction phase; compensating the test signal based on a preset compensation coefficient; correcting the preset compensation coefficient according to the compensated test signal and a preset reference signal to obtain an application compensation coefficient; and receiving a working signal in a working phase, and compensating the working signal according to the application compensation coefficient. In each signal equalization cycle, the signal equalization method can obtain an application compensation coefficient that matches the signal transmission channel by correcting the preset compensation coefficient in the correction phase, so that the working signal can be compensated directly according to the application compensation coefficient in the working phase, thereby eliminating the need to continuously or multiple times obtain the compensation coefficient for equalizing the working signal in the working phase. In this way, the power consumption during the signal equalization process can be reduced.

Description

[0001] This application claims priority for the application number 202210108627.3 filed with the China Patent Office on January 28, 2022, and named "Data interface device, and applicable data acquisition equipment, sensor system", which is incorporated by reference into this application with all the contents of this application. Technical Field

[0002] The embodiments of the present application relate to data transmission technology, and specifically to a signal equalization method, a signal equalization unit, a data receiving interface device, a sensor system, and a data acquisition device. Background Art

[0003] The data interface device includes a data interface device for transmitting analog signals, which is used to convert the received digital signals into analog signals based on the transmission medium, the length of the transmission path, etc., so as to facilitate transmission over the transmission medium. The data interface device also includes a data interface device for receiving analog signals, which is used to restore the analog signals from the transmission medium into digital signals.

[0004] In some data transmission technologies, high-speed signals often suffer severe attenuation at high frequencies after passing through the low-pass channel. The receiver needs a mechanism to compensate for the signal energy at high frequencies. However, different channels have different characteristics and attenuate high-frequency signals differently, necessitating different compensation methods.

[0005] Therefore, how to achieve adaptive equalization of signals at the receiving end is a problem that needs to be solved urgently. Summary of the Invention

[0006] The present application provides a signal equalization method, a signal equalization unit, a data receiving interface device, a sensor system and a data acquisition device to achieve adaptive equalization of signals at a receiving end.

[0007] In a first aspect, the present application provides a signal equalization method, characterized in that it is applied to any signal equalization cycle; the signal equalization cycle includes a calibration phase and a working phase; wherein the signal equalization method includes:

[0008] In the calibration phase: receiving a test signal; compensating the test signal based on a preset compensation coefficient; calibrating the preset compensation coefficient according to the compensated test signal and a preset reference signal to obtain an applied compensation coefficient;

[0009] During the working phase: receiving a working signal, and compensating the working signal according to the applied compensation coefficient.

[0010] The signal equalization method in the above embodiment is applicable to any signal equalization cycle. During each signal equalization cycle, the calibration phase corrects the preset compensation coefficients to obtain an application compensation coefficient that matches the signal transmission channel. This allows the operating signal to be compensated directly according to the application compensation coefficients during the operating phase, eliminating the need to continuously or repeatedly obtain the compensation coefficients used to equalize the operating signal. This reduces power consumption during the signal equalization process.

[0011] As described above, the signal equalization method in the above embodiment is applicable to low-power consumption scenarios and multi-channel scenarios, especially to scenarios with variable channel characteristics.

[0012] In a second aspect, the present application provides a signal equalization unit, comprising an equalization circuit and a correction circuit; wherein

[0013] The equalization circuit is used to receive a test signal during a calibration phase and compensate the test signal based on a preset compensation coefficient to obtain a compensated test signal; and is also used to receive a working signal during a working phase and compensate the working signal according to the applied compensation coefficient;

[0014] The correction circuit is connected to the equalization circuit to form an electrical loop, and is used to correct the preset compensation coefficient according to the test signal compensated by the equalization circuit and a preset reference signal to obtain the applied compensation coefficient;

[0015] The correction circuit is closed during the working phase.

[0016] In the signal equalizing unit of the above embodiment, the correction circuit only needs to be turned on during the correction phase of each signal equalization cycle to calibrate the preset compensation coefficient to obtain the application compensation coefficient. Afterwards, the correction circuit can be turned off. Thus, during the working phase, the working signal is directly compensated according to the application compensation coefficient. This eliminates the need to continuously or repeatedly utilize the correction circuit during the working phase to obtain the compensation coefficient for equalizing the working signal. This effectively reduces power consumption during the signal equalization process, making the signal equalizing unit of the above embodiment suitable for low-power scenarios. Furthermore, because the signal equalizing unit of the above embodiment can receive a test signal after power-on and derive the application compensation coefficient applicable to the signal transmission channel based on the test signal, the signal equalizing unit of the above embodiment can also be applied to different channels, particularly in scenarios with variable channel characteristics.

[0017] In a third aspect, the present application provides a data receiving interface device, comprising the signal equalization unit provided by any of the aforementioned embodiments; and

[0018] a sampling unit connected to the signal equalization unit, and configured to sample the received second analog signal according to the received clock signal to output a first digital signal and the clock signal;

[0019] a clock recovery control unit, coupled to the sampling unit, configured to detect the received first digital signal and output a clock recovery control signal reflecting a phase deviation between the second analog signal and one of the clock signals;

[0020] The output unit is coupled to the sampling unit, and is used to convert the first digital signal collected correspondingly into a second digital signal under the control of the received clock signal, and output the second digital signal.

[0021] The data receiving interface device of the above embodiment includes the signal equalization unit provided by the above embodiment. Therefore, the technical effects that can be achieved by the above signal equalization unit can also be achieved by the data receiving interface device, which will not be described in detail here.

[0022] In a fourth aspect, the present application provides a sensor system, comprising:

[0023] A first radar sensor includes a first data interface device; the first data interface device is configured to transmit a measurement signal detected by the first radar sensor; wherein the measurement signal is configured to reflect at least one of the following data: a baseband digital signal detected by the first radar sensor, at least one of a distance, a velocity, and an azimuth between the first radar sensor and a target, and target detection data of the target;

[0024] The second radar sensor includes a second data interface device and a third data interface device; wherein the second data interface device is connected to the first data interface device via a channel; the second data interface device includes the data receiving interface device provided in the aforementioned embodiment, which is used to receive the measurement signal; and the third data interface device is used to forward the measurement signal.

[0025] The sensor system of the above embodiment includes the data receiving interface device provided by the above embodiment. Therefore, the technical effects that can be achieved by the above data receiving interface device can also be achieved by the data acquisition device, which will not be described in detail here.

[0026] In a fifth aspect, the present application provides a data acquisition device, characterized in that it includes the data receiving interface device provided by any of the aforementioned embodiments; and

[0027] The data transmitting interface device is connected to the data receiving interface device and is used to send the test signal and the working signal.

[0028] The data acquisition device of the above embodiment includes the data receiving interface device provided by the above embodiment. Therefore, the technical effects that can be achieved by the above data receiving interface device can also be achieved by the data acquisition device, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is a hardware architecture block diagram of a data transmission interface device of the present application.

[0030] Figure 2 This is a schematic diagram of the circuit structure of a parallel-to-serial conversion unit of the present application.

[0031] Figure 3 This is a circuit structure diagram of the first serial signal outputter of the present application.

[0032] Figure 4 This is a circuit structure diagram of the second serial signal output device of this application.

[0033] Figure 5 This is a schematic diagram of the circuit structure of an encoding unit in this application.

[0034] Figure 6 Schematic diagram of the waveform of the third analog signal after equalization processing in this application.

[0035] Figure 7 This is a schematic diagram of a circuit structure of the output drive unit of this application.

[0036] Figure 8 This is another circuit structure diagram of the output drive unit of this application.

[0037] Figure 9 Combined for this application Figure 2 and 8 A circuit structure diagram of a data transmission interface device is provided based on the example provided.

[0038] Figure 10 This is a schematic diagram of the circuit structure of a data receiving interface device of the present application.

[0039] Figure 11 This is a flow chart of a signal equalization method of the present application.

[0040] Figure 12 The present invention provides a logic flow chart of processing at least one detection signal by the correction control subcircuit.

[0041] Figure 13 This is a schematic diagram of the circuit structure of an equalizer unit in the present application.

[0042] Figure 14 This is a schematic diagram of the spectrum in the equalizer unit of this application.

[0043] Figure 15 This is a schematic diagram of the circuit structure of the input unit in the data interface device of this application.

[0044] Figure 16 This is another circuit structure diagram of the input unit in the data interface device of this application.

[0045] Figure 17 This is a schematic diagram of the circuit structure of the correction circuit in the data interface device of this application.

[0046] Figure 18 This is a schematic diagram of the circuit structure of the detection sub-circuit in the correction circuit of this application.

[0047] Figure 19 This is another hardware architecture diagram of the data receiving interface device of this application.

[0048] Figure 20 This is a circuit structure diagram of a clock recovery control unit in the data receiving interface device of this application.

[0049] Figure 21 This is a timing diagram of the phase shift detection circuit structure in the data receiving interface device of this application.

[0050] Figure 22 This is a circuit structure diagram of a phase shift control circuit structure in the data receiving interface device of this application.

[0051] Figure 23 This is a circuit structure diagram of the second shift decision circuit in the data receiving interface device of this application.

[0052] Figure 24 Schematic diagram of the condition-state transition of the second phase adjustment circuit adjusting the phase interval in the data receiving interface device of the present application.

[0053] Figure 25 This is a schematic diagram of the circuit structure of the clock recovery control unit in the data receiving interface device of this application.

[0054] Figure 26 Schematic diagram of the condition-state transition for adjusting the binary phase value of the first phase adjustment circuit in the data receiving interface device of the present application.

[0055] Figure 27 This is a schematic diagram of the hardware structure of the sensor system for this application.

[0056] Figure 28 This is a schematic diagram of the hardware structure of the data acquisition equipment for this application. DETAILED DESCRIPTION

[0057] The present application will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are intended only to illustrate the present application and are not intended to limit the present application. It should also be noted that, for ease of description, the accompanying drawings only illustrate portions of the present application, not all of the components.

[0058] In some data transmission technologies, a data interface device is coupled to a channel made of a signal-conducting material to transmit an analog signal to another data interface device through the channel. Examples of the channel include microstrip lines, coaxial cables, or optical fibers.

[0059] The term "coupled" or "coupling" can have several different meanings depending on the context in which the term is used. For example, the term coupling can have the meaning of mechanical coupling or electrical coupling. As used herein, the term "coupled" or "coupling" can mean that two elements or devices can be directly connected to each other or connected to each other through one or more intermediate elements or devices via electrical elements, electrical signals or mechanical elements (such as, but not limited to, for example, wires or cables, depending on the specific application). Examples of coupling described herein include: direct electrical connection, electrical induction connection, or optical coupling connection, etc. For example, the electrical connection between two electrical devices is achieved using the connection method used in the semiconductor manufacturing process. For another example, the signal connection between two electrical devices is achieved using a non-contact connection method such as an optical coupling component or an inductive sensing component. For another example, the electrical connection or signal connection between two electrical devices is assisted by the connection method between the chip pins and the slot.

[0060] For ease of description, in the embodiment of the present application, the data interface device that sends analog signals is referred to as a data transmitting interface device, and the data interface that receives analog signals is referred to as a data receiving interface device.

[0061] In some data transmission technologies, a data transmitting interface device and a data receiving interface device utilize channels to transmit analog signals represented by differential signals, thereby reducing the number of channels used to transmit clock signals. Such data transmitting interface devices and data receiving interface devices include LVDS interface devices or SerDes interface devices. When transmitting analog signals represented by differential signals, two channels are typically used to transmit the differential signals. When these two channels are long, high-frequency signal filtering, and / or signal interference and attenuation can occur. This situation is particularly prominent when transmitting analog signals with frequencies of 10 GHz or above.

[0062] To this end, the present application provides a data transmission interface device, intended for use in a sensing system, such as one in which a sensor resides, to convert digital signals such as baseband digital signals, measurement data, or target detection data generated by the sensor into analog signals. The device also ensures that the corresponding analog signals, when transmitted via a channel to a data receiving interface device, facilitate accurate interpretation by the data receiving interface device. The accuracy of the data transmission interface device meets the error precision requirements of the sensing system. For example, in an automatic assisted driving system for a vehicle, the length of the channel between the data processing device and the sensor in the sensing system is related to, among other factors, the sensor's installation position on the vehicle body and the vehicle body length. When the data transmission interface device transmits the various digital signals generated by the sensor to the data receiving interface device via the channel (or via the channel and a repeater on the channel), the data receiving interface device can easily and accurately extract the digital signals from the received swinging analog signals, thereby meeting the automatic assisted driving system's requirements for sensor output data / signals.

[0063] For ease of description, in this application, the analog signal transmitted by the data transmission interface device to the channel is referred to as the third analog signal, and the analog signal received by the data reception interface device is referred to as the first analog signal. The first analog signal is the attenuated third analog signal after transmission through the channel and superimposed with channel noise.

[0064] See also Figure 1 , which shows a hardware architecture block diagram of a data transmission interface device. The data transmission interface device 1 includes: a parallel-to-serial conversion unit 11, an encoding unit 112, and an output driving unit 13.

[0065] The parallel-to-serial conversion unit is used to convert the parallel digital signal generated in the sensor into a first serial digital signal and a second serial digital signal and output them.

[0066] Here, the parallel-to-serial conversion unit outputs a first serial digital signal and a second serial digital signal in a bit order from high to low or from low to high in the parallel digital signal. The first serial digital signal and the second serial digital signal have the same level change and a set time gap. In other words, the first serial digital signal and the second serial digital signal are codirectional signals (or reverse direction signals) separated by a preset delay time. The delay time (also known as the symbol time gap) is determined based on the pulse width of the working clock signal of the parallel-to-serial conversion unit. For example, the delay time is half a cycle of the working clock signal.

[0067] See also Figure 2, which shows a circuit structure diagram of a parallel-to-serial conversion unit. The parallel-to-serial conversion unit 11 includes a parallel-to-serial converter 110, and a cascaded first serial outputter 111 and a second serial outputter 112. The parallel-to-serial converter 110 operates under the control of a first working clock signal DIV_1, and the first serial outputter 111 and the second serial outputter 112 operate under the control of a second working clock signal DIV_2. The first working clock signal DIV_1 and the second working clock signal DIV_2 have a frequency division / multiplication relationship. Taking the full-rate output of the serial signal by the parallel-to-serial conversion unit 11 as an example, if the parallel-to-serial converter converts the parallel digital signal as a 10-bit digital signal into a 2-bit serial digital signal, and the first serial outputter and the second serial outputter output the 2-bit serial digital signal, then the frequency ratio of the first working clock signal DIV_1 and the second working clock signal DIV_2 is 1:5.

[0068] The parallel-to-serial converter is used to convert the received parallel digital signal TXD <n:0>The parity bits are converted into two serial digital signals, where n is an integer greater than 1, for example, n=8 or 10.

[0069] The first serial signal outputter is coupled to the parallel-to-serial converter, and is configured to output the received parity bit signals in sequence under the control of the received second working clock signal to form the first serial digital signal D_MAIN.

[0070] Here, under the control of the second operating clock signal DIV_2, the parallel-to-serial converter outputs the odd and even signals in the parallel digital signal in a high-to-low order (or low-to-high order) through the corresponding odd signal output terminal EVEN and even signal output terminal ODD, respectively. Under the control of the second operating clock signal DIV_2, the first serial signal outputter sequentially outputs the received odd and even signals. For example, if the first serial signal outputter outputs the first serial digital signal at full rate, the first serial signal outputter outputs the serial digital signal according to the clock cycle of the second operating clock signal DIV_2 only in response to the rising or falling edge of the second operating clock signal DIV_2. For example, if the first serial signal outputter outputs the first serial digital signal at half rate, the first serial signal outputter outputs the serial digital signal according to the clock half cycle of the second operating clock signal DIV_2 in response to the rising and falling edges of the second operating clock signal DIV_2.

[0071] See also Figure 3 , which shows a circuit structure diagram of the first serial signal output. The first serial signal output includes two triggers D11 and D12, a controller C1, and an output device P1. Among them, the input end of the trigger D11 is connected to the odd signal output end EVEN, the control end (also called the enable end) of the trigger D11 receives the second working clock signal DIV_2, and the output end of the trigger D11 is respectively connected to the first input end of the controller C1 and the second serial signal output device. The input end of the trigger D12 is connected to the even signal output end ODD, the control end (also called the enable end) of the trigger D12 receives the inverted signal of the second working clock signal DIV_2, and the output end of the trigger D12 is respectively connected to the second input end of the controller C1 and the second serial signal output device. The output device P1 can optionally be a comparator or an AND gate device to improve the level stability of the output signal. In some examples, such as Figure 3 As shown in the dotted box, the first serial signal outputter further includes a duty cycle calibration circuit DCC1 to improve the stability of the pulse width ratio in the second working clock signal DIV_2; correspondingly, the duty cycle calibration circuit DCC1 receives the second working clock signal DIV_2 and outputs it to the control end of the controller C1.

[0072] Under the control of the second working clock signal DIV_2, taking the half-rate transmission of a serial digital signal as an example, within one clock cycle of the second working clock signal DIV_2: during the high-level effective period of the second working clock signal DIV_2, the signal path formed by the trigger D11, the controller C1, and the output P1 outputs an odd-bit signal; and during the low-level effective period of the second working clock signal DIV_2, the signal path formed by the trigger D12, the controller C1, and the output P1 outputs an even-bit signal.

[0073] The second serial signal outputter is cascaded with the first serial signal outputter, and is configured to output the first serial digital signal D_MAIN transmitted by the first serial signal converter as the second serial digital signal D_POST according to the delay time.

[0074] Under the control of the second working clock signal DIV_2, the second serial signal outputter sequentially outputs the received odd-bit signal and even-bit signal to form a second serial digital signal D_POST. Taking the example of the second serial signal outputter outputting the second serial digital signal at full rate, the second serial signal outputter outputs the second serial digital signal D_POST according to the clock cycle of the second working clock signal DIV_2 only in response to the falling edge or rising edge of the second working clock signal DIV_2. Taking the example of the second serial signal outputter outputting the second serial digital signal at half rate, the second serial signal outputter outputs the second serial digital signal D_POST according to the clock half cycle of the second working clock signal DIV_2 in response to the falling edge and rising edge of the second working clock signal DIV_2. The second serial signal outputter delays the first serial signal outputter by one symbol time interval (i.e., the clock half cycle of the second working clock signal DIV_2).

[0075] See also Figure 4 , which shows a circuit structure diagram of the second serial signal output. The second serial signal output includes two triggers D21 and D22, a controller C2, and an outputter P2. Among them, the input end of the trigger D21 is connected to the output end D11_output of the trigger D11 of the first serial signal outputter, the control end (also called the enable end) of the trigger D21 receives the inverse signal of the second working clock signal DIV_2, and the output end of the trigger D21 is connected to the first input end of the controller C2. The input end of the trigger D22 is connected to the output end D12_output of the trigger D12 of the first serial signal outputter, the control end (also called the enable end) of the trigger D22 receives the second working clock signal DIV_2, and the output end of the trigger D22 is connected to the second input end of the controller C2. The outputter P2 can optionally be a comparator or an AND gate device to improve the level stability of the output signal. In some examples, such as Figure 4 As shown in the dashed box, the second serial signal output device further includes a duty cycle calibration circuit DCC2 to improve the pulse width stability of the second operating clock signal DIV_2. Accordingly, the duty cycle calibration circuit DCC2 receives the second operating clock signal DIV_2 and outputs it to the control terminal of the controller C2. The duty cycle calibration circuit DCC2 and the duty cycle calibration circuit DCC1 may be the same device or two independent devices.

[0076] Under the control of the second working clock signal DIV_2, taking the half-rate transmission of the serial digital signal as an example, within one clock cycle of the second working clock signal DIV_2: during the low-level effective period of the second working clock signal DIV_2, the signal path formed by the trigger D21, the controller C2, and the output P2 outputs an odd-bit signal; during the high-level effective period of the second working clock signal DIV_2, the signal path formed by the trigger D22, the controller C2, and the output P2 outputs an even-bit signal.

[0077] The parallel-to-serial conversion unit, employing a half-rate architecture, first converts the received n-bit parallel digital signal into a two-bit odd-even digital signal, which is then converted into a single-bit serial digital signal via a controller (e.g., a selector). The half-rate architecture requires a clock frequency of half the serial data rate, which reduces clock requirements. However, due to the use of high and low clock levels, it is very sensitive to the clock duty cycle, which directly affects the jitter of the output serial data eye diagram. Therefore, a DCC is added to the clock path to correct the clock duty cycle, keeping its deviation within a certain range. In the figure, D_MAIN is the final output first serial digital signal. D_POST is delayed by one symbol time interval compared to D_MAIN and is primarily used for subsequent channel equalization. Signals P_0 and P_1 control the polarity of D_MAIN and D_POST, respectively. The first and second serial digital signals D_MAIN and D_POST are output to the encoding unit of the data transmission interface device.

[0078] The encoding unit is coupled to the parallel-to-serial conversion unit and is configured to encode the first and second serial data into first and second drive control digital signals according to preset equalization coefficients, and output the signals. The equalization coefficients are intended to allow the output driver unit to adjust the voltage swing of a portion of the output third analog signal to improve its anti-filtering capability in the high-frequency region during channel transmission. Examples of the equalization coefficients include equalization coefficients for pre-emphasis and de-emphasis. The equalization coefficients are pre-set based on the transmission distance between the data transmitting interface device and the data receiving interface device, the channel medium, and other factors. For example, the encoding unit provides an editable equalization coefficient encoder, such as a thermometer encoder. The equalization coefficient encoder generates a control signal based on an externally input encoding instruction, for the encoding unit to perform encoding operations on the received first and second serial digital signals D_MAIN and D_POST.

[0079] The encoding unit encodes the first serial digital signal D_MAIN and the second serial digital signal D_POST by using a multi-channel digital circuit encoding method, effectively utilizing semiconductor manufacturing technology to integrate the data transmission interface device and the sensor into a chip within a limited size range.

[0080] See also Figure 5 , which shows a schematic diagram of the circuit structure of an encoding unit. The encoding unit includes two paths: differential converters SD1 and SD2, and an encoder group MUX1 <m:1>、MUX2 <m:1>, where m>1, for example, m=14. The differential converter SD1 converts the first serial digital signal D_MAIN into differential serial signals DP_MAIN and DN_MAIN. The differential converter SD2 converts the second serial digital signal D_POST into differential serial signals DP_POST and DN_POST. For ease of description, the first serial digital signal D_MAIN and the second serial digital signal D_POST are identical signals with a delayed duration. For example, the serial signals DP_MAIN and DP_POST are identical signals with a delayed duration, and the serial signals DN_MAIN and DN_POST are identical signals with a delayed duration; and the serial signals DP_MAIN and DN_MAIN are synchronized inverse signals, while the serial signals DP_POST and DN_POST are synchronized inverse signals.

[0081] Encoder group MUX1 <m:1>Receive serial signals DP_MAIN and DN_POST, encode the serial signals DP_MAIN and DN_POST according to the control bits in the received control signal, and output the first drive control digital signal DP_INT. Each encoder group is controlled by the control signal output by the equalization coefficient encoder. Encoder group MUX2 <m:1>The serial signals DN_MAIN and DP_POST are received, and the serial signals DN_MAIN and DP_POST are encoded according to each control bit in the received control signal, and a second driving control digital signal DN_INT is output.

[0082] Among them, the encoder group MUX1 <m:1>and encoder group MUX2 <m:1>Can have the same circuit structure. <m:1>For example, the encoder group consisting of m binary selectors, encoder group MUX1 <m:1>Each selector in selects the serial signals DP_MAIN and DN_POST according to the high level or low level of the corresponding control bit in the received control signal to output the m-bit first driving control digital signal DP_INT.

[0083] In this example, a thermometer decoder is used to control a binary selector, generating the control signals required by the output driver. For example, signals D_MAIN and D_POST are converted to DP_MAIN and DN_MAIN, and DP_POST and DN_POSTN, respectively, via a single-ended-to-differential converter. These signals are then fed through 15 binary selectors, ultimately converting them into DP_INT and DN_INT outputs. The binary selectors are controlled by thermometer codes. When a channel requires a high level of compensation, the binary selectors can select more DP_POST and DN_POST outputs. Furthermore, the equalization amount can be incrementally increased using the thermometer code, achieving very precise results.

[0084] Because the first drive control digital signal DP_INT and the second drive control digital signal DN_INT are respectively encoded using the same encoding method based on the received differential signal pairs {DP_MAIN, DN_POST} and {DN_MAIN, DP_POST} with delayed durations, the first drive control digital signal DP_INT and the second drive control digital signal DN_INT contain control changes within a clock cycle that can be used by subsequent circuits to perform pre-emphasis (or pre-de-emphasis) processing based on the delay duration. Under the control of the first drive control digital signal DP_INT and the second drive control digital signal DN_INT, the output drive unit outputs a differential signal that has undergone equalized voltage swings, i.e., a third analog signal.

[0085] The output driving unit is coupled to the encoding unit and is configured to select, under the driving control of the first driving control digital signal, to generate an analog signal representing one of 0 or 1 in the first serial digital signal; or, under the driving control of the second driving control digital signal, to generate an analog signal representing the other of 0 or 1 in the first serial digital signal; and to output the corresponding analog signal in a time sequence to form a third analog signal. The energy amplitude of the third analog signal within the extended time period after the selection switching is processed by the pre-emphasis / de-emphasis equalization. For example, see Figure 6 , which shows a waveform diagram of the third analog signal after equalization processing, wherein time slots T1 and T2 are level signals output from the differential signal after equalization processing by the output driving unit.

[0086] Here, the output drive unit includes multiple controlled power supply circuits (e.g., digital-to-analog converter drivers, DAC drivers) to generate balanced differential analog signals under the control of a first drive control digital signal and a second drive control digital signal. By selecting multiple controlled power supply circuits to meet the signal output requirements for large swings, the difficulty of integrating electrical components in high-power drive circuits is reduced while also effectively improving control accuracy. Each controlled power supply circuit can generate the same electrical signal or be configured to generate different electrical signals. The output drive unit includes two groups of controlled power supply circuits: a first controlled power supply circuit group and a second controlled power supply circuit group. The number of controlled power supply circuits in each group corresponds to the maximum number of bits of the received first or second drive control digital signal, respectively. The first controlled power supply circuit group is connected to the positive output terminal of the output drive unit, while the second controlled power supply circuit group is connected to the negative output terminal of the output drive unit. This outputs a single-channel third analog signal represented by a differential signal.

[0087] To output a third analog signal with symmetrical energy amplitude swing, in some examples, see Figure 7 , which shows a schematic diagram of a circuit structure of an output drive unit. The first controlled power circuit group and the second controlled power circuit group have the same circuit structure. Taking the first controlled power circuit group as an example, the first controlled power circuit group includes m parallel first controlled power circuits, and each control bit in the first drive control digital signal controls a controlled switch in the first controlled power circuit. Under the control of two sets of first drive control digital signals DP_INT separated by the delay time, the m parallel first controlled power circuits generate balanced analog signals and output them to the positive output terminal TXP of the output drive unit 13. Unlike the first controlled power circuit group, the second controlled power circuit group generates balanced analog signals and outputs them to the negative output terminal TXN of the output drive unit 13.

[0088] For other examples, see Figure 8 , which is another circuit structure diagram of the output drive unit. The output drive unit includes a first controlled power circuit group 131, a second controlled power circuit group 132, and a swing compensation circuit 133.

[0089] and Figure 7 The illustrated example differs in that the swing compensation circuit is connected to the positive and negative output terminals of the output driver unit and is controlled by a first drive control digital signal and a second drive control digital signal. A control bit in the first drive control digital signal and a control bit in the second drive control digital signal are connected to the two control terminals of the swing compensation circuit, respectively. These two control bits are inverted signals, so that when the output analog signal level swings in a positive direction, the swing compensation circuit compensates the voltage at the positive output terminal of the output driver unit, and when the output analog signal level swings in a negative direction, the swing compensation circuit compensates the voltage at the negative output terminal of the output driver unit.

[0090] like Figure 8 As shown, the swing compensation circuit 133 includes a power supply IS and two controlled switches in parallel, and the control end of each controlled switch receives a control bit in the first drive control digital signal and a control bit in the second drive control digital signal, so that the two controlled switches are not turned on at the same time.

[0091] See also Figure 9 , which is shown as a combination Figure 2 and 8 The circuit structure diagram of a data transmission interface device is provided as an example. The output driver unit has a full-rate structure. This output driver only needs to generate differential serial signals under the control of a first drive control digital signal and a second drive control digital signal, eliminating the need for simultaneous clock and data processing. This greatly simplifies the output driver structure. The output driver unit is composed of two DAC driver arrays connected as shown. Each DAC driver array consists of 15 DAC drivers, forming a 4-bit voltage-mode DAC driver. The relationship between the voltage divider resistor RU and the load resistor RT in the figure is: RU = n*RT.

[0092] If for an N-bit voltage mode DAC driver, the following relationship is used: n = 2 N -1. Since this example uses a 4-bit voltage-mode DAC driver, the above formula shows that n equals 15. RT is generally chosen to be 50 ohms, and RU can also be calculated to be 750 ohms. In addition to RU, the DAC driver also has two switches, a PMOS and an NMOS. Assuming the switch on-resistance is zero, the peak-to-peak differential output voltage of the DAC driver can be calculated to be VS. VS can be obtained through a regulator. By adjusting the regulator's output voltage, the driver's output swing is also changed. To further increase the output swing, a swing boost module, as shown in the figure, is added. The output swing can be increased from VS to VS + IS * 2 * RT.

[0093] The differential signals output by the data transmission interface devices provided in the above examples effectively solve the swing requirement for transmitting high-speed serial signals in the circuit system where the sensor is located.

[0094] This application also provides a data receiving interface device, which is intended to accurately recover the differential signal transmitted through the channel. Figure 10 , which is a schematic diagram of a circuit structure of a data receiving interface device, wherein the data receiving interface device 2 includes: an input unit 21, a sampling unit 22, a clock recovery control unit 23, a clock generating unit 24, and an output unit 25.

[0095] The input unit is configured to receive a first analog signal from a channel. The first analog signal is transmitted in the channel as a wave and is affected by the channel environment, channel material, and channel length. This influence can easily filter out high-frequency components of the first analog signal during transmission. In some examples, the data transmission interface device reduces the potential for miscoding and other issues caused by this influence on the data receiving side by increasing the voltage swing of the transmitted first analog signal. In other examples, the input unit configures a compensation mechanism based on predetermined parameters / information related to the channel environment. For example, the input unit may be configured with a feedback circuit for compensating the level of the first analog signal, where the electrical parameters of the reference signal in the feedback circuit are determined based on the channel material, length, and other factors. In another example, the feedback circuit in the input unit suppresses noise generated by the channel environment through feedback during the reception of the first analog signal, thereby enabling the input unit to accurately output the second analog signal.

[0096] Taking the example of a differential signal as the first analog signal, the input unit includes two signal leads and an equalization circuit connected to the signal leads. The two signal leads are coupled to the channel to receive the first analog signal represented by a differential signal from the channel. The equalization circuit is configured to equalize the received first analog signal to output the second analog signal. To distinguish the equalization circuit (e.g., DAC driver array) in the data transmission interface device from the first equalization circuit in the data reception interface device, the equalization circuit in the data reception interface device is referred to as the second equalization circuit.

[0097] The second equalization circuit includes at least one equalizer unit. A gate device in the equalizer unit responds to the voltage difference between two inverse signals within the received first analog signal. The equalizer unit outputs a differential signal that is the inverse of the first analog signal, i.e., a second analog signal. If there are multiple equalizer units in the second equalization circuit, the equalizer units are connected in cascade.

[0098] To output a differential signal that is inversely proportional to the first analog signal and has undergone equalization and compensation, the equalizer unit includes switches M1 and M2, respectively controlled by two inversely proportional signals within the first analog signal. The equalizer unit is also connected to a constant voltage VDD. Circuit branch L1, containing switch M1, is connected to the positive output terminal, while circuit branch L2, containing switch M2, is connected to the negative output terminal. An isolation circuit branch is connected between the two circuit branches. Circuit branches L1 and L2 are configured with electrical components having the same electrical parameters to achieve symmetry in the differential signal.

[0099] To improve the shaping effect of the output second analog signal and facilitate accurate signal extraction by the subsequent sampling circuit, in some examples, the equalizer unit also includes a compensation circuit, which is connected to the positive output terminal and the negative output terminal, respectively, and performs corresponding equalization compensation based on the level output by the positive input terminal or the level output by the negative output terminal. For example, when the positive output terminal outputs a high level, the compensation circuit pulls down the level of the negative output terminal; alternatively, when the negative output terminal outputs a high level, the compensation circuit pulls down the level of the positive output terminal. This achieves the purpose of increasing the common-mode voltage difference. In other examples, the second equalization circuit utilizes multiple cascaded equalizer units to provide high-frequency second analog signal shaping. For example, each cascaded equalizer unit provides a different equalization compensation voltage to achieve the purpose of improving the shaping of the high-frequency second analog signal.

[0100] To enable the equalizer unit to adapt to interference caused by the channel environment, the equalizer unit includes a device that is adjusted by an external correction circuit; and the second equalizing circuit also includes the correction circuit. The adjustable device is configured based on the circuit structure of the equalizer unit and is, for example, at least one of a power amplifier, a capacitor, or a resistor. The adjustable device adjusts the voltage, current, or properties (such as capacitance or resistance) of the device, enabling the second equalizing circuit to output a second analog signal in response to correction by the correction circuit.

[0101] According to some embodiments of the present application, an input unit is provided. For ease of description, the input unit is also referred to as a signal equalization unit in the embodiments of the present application.

[0102] See also Figure 15 , which shows a circuit structure diagram of a signal equalizing unit. In one embodiment, the signal equalizing unit may specifically include an equalizing circuit 210 (also called a second equalizing circuit) and a correction circuit 211. The equalizing circuit 210 may be configured to: receive a test signal during a calibration phase; compensate the test signal based on a preset compensation coefficient to obtain a compensated test signal; receive a working signal during a working phase and compensate the working signal based on the applied compensation coefficient; and the correction circuit 211 may be configured to: turn on during the calibration phase, calibrate the preset compensation coefficient based on the compensated test signal and a preset reference signal to obtain the applied compensation coefficient; and turn off during the working phase.

[0103] In the signal equalizing unit of the above embodiment, the correction circuit only needs to be turned on during the correction phase of each signal equalization cycle to calibrate the preset compensation coefficient to obtain the application compensation coefficient. Afterwards, the correction circuit can be turned off. Thus, during the working phase, the working signal is directly compensated according to the application compensation coefficient. This eliminates the need to continuously or repeatedly utilize the correction circuit during the working phase to obtain the compensation coefficient for equalizing the working signal. This effectively reduces power consumption during the signal equalization process, making the signal equalizing unit of the above embodiment suitable for low-power scenarios. Furthermore, because the signal equalizing unit of the above embodiment can receive a test signal after power-on and derive the application compensation coefficient applicable to the signal transmission channel based on the test signal, the signal equalizing unit of the above embodiment can also be applied to different channels, particularly in scenarios with variable channel characteristics.

[0104] It can be understood that compared with the traditional analog equalizer adaptive equalization method, the signal equalization unit in the above embodiment can greatly reduce its own power consumption because it can turn off the correction circuit 211 during the working phase after obtaining the applied compensation coefficient during the correction phase.

[0105] For example, after the chip is powered on, the signal equalization unit in the above embodiment only needs to be calibrated once. After the application compensation coefficient is obtained, the application compensation coefficient can be provided to the device for direct use in subsequent normal operation without the need to continuously or multiple times obtain the compensation coefficient for equalization during the working stage.

[0106] In one embodiment, the signal equalization unit may further include a storage module, and the storage module may be used to store the applied compensation coefficients during the correction phase.

[0107] In the signal equalization unit of the above embodiment, the storage module can store the application compensation coefficients after obtaining them during the calibration phase. Storing the application compensation coefficients helps extend the signal equalization period, allowing the application compensation coefficients to be directly retrieved and used to compensate the operating signal during longer operating phases. This can further reduce power consumption during the signal equalization process.

[0108] It should be understood that the present application does not specifically limit the form of the storage module; illustratively, the storage module may include but is not limited to random access memory (RAM), registers, cache, memory management unit (MMU) or any other storage device with storage function, etc.

[0109] The present application does not impose any specific limitation on the form of the equalization circuit 210, as long as it can obtain a test signal during the calibration phase, compensate the test signal based on a preset compensation coefficient, and obtain a compensated test signal; and can compensate the received signal according to the applied compensation coefficient during the working phase.

[0110] For example, Figure 15 As shown, the equalization circuit 210 may include multiple cascaded equalizer units 212, which can enhance the high-frequency compensation capability of the signal equalization unit. The number of cascaded equalizer units 212 is related to the number of bits of the correction signal provided by the correction circuit 211. The equalizer unit 212 can, for example, have the circuit structure of the equalizer unit described in any of the above examples. The correction circuit 211 performs correction detection on the second analog signal output by the cascaded equalizer units, so that at least one equalizer unit 212 adjusts the amplitude of the output differential signal.

[0111] In some examples, during the process in which the signal equalization unit receives the first analog signal representing the measurement signal of the sensor, the correction circuit performs correction detection and outputs a real-time correction signal.

[0112] In other examples, before receiving the first analog signal representing the measurement signal of the sensor, the correction circuit receives the first analog signal for testing the channel interference signal transmitted by the above-mentioned data transmission interface device to correct the interference of the channel environment on the analog signal.

[0113] See also Figure 16 , which is another circuit structure diagram of the signal equalization unit. In one embodiment, the correction circuit 211 may include an amplitude detection and decision module 2121 and a digital control module 2124.

[0114] Specifically, one end of the amplitude detection and decision module 2121 is connected to the equalization circuit 210, and the other end is connected to one end of the digital control module 2124. This module can use a preset reference signal to detect the common-mode voltage of the test signal after compensation to generate a detection signal. This detection signal can be used to indicate whether the current compensation operation is over-compensated or under-compensated. The other end of the digital control module 2124 is connected to the equalization circuit 210 and can correct the current preset compensation coefficient based on the detection signal. The module can also cumulatively count compensation operations to obtain an updated preset compensation coefficient until the calibration phase ends. The preset compensation coefficient after the calibration phase ends serves as the applied compensation coefficient.

[0115] The signal equalization unit in the above embodiment determines the common-mode voltage of the test signal after compensation through the amplitude detection and judgment module 2121, and generates a detection signal based on this common-mode voltage to determine whether the current compensation operation is under-compensated or over-compensated; the digital control module 2124 can be used to correct the preset compensation coefficient, and can determine that the current preset compensation coefficient is the applied compensation coefficient when the conditions are met.

[0116] That is to say, during the chip power-on stage, the signal equalization unit in the above embodiment can detect the compensated test signal through the amplitude detection and judgment module 2121 in the correction circuit 211, and compare the compensated test signal with the preset reference signal. The digital control module 2124 determines the state of the signal equalization unit at this time based on the comparison result, and makes corresponding adjustments to it until the correction stage is completed.

[0117] It should be understood that the present application does not impose any specific restrictions on the conditions for the end of the calibration phase. For example, the conditions for the end of the calibration phase may include the detection signal meeting a preset condition, or the number of compensation operations reaching a maximum value.

[0118] The signal equalization unit in the above embodiment can avoid falling into an infinite loop when approaching compensation lock by setting a preset number of cycles.

[0119] It should also be understood that the test signals involved in this application may include but are not limited to serial differential signals.

[0120] See also Figure 17 , which shows a possible circuit structure diagram of the correction circuit 211. In this embodiment, the amplitude detection and judgment module is also called the detection subcircuit; the digital control module is also called the correction control subcircuit. Figure 17 As shown, the correction circuit may include: a detection subcircuit 2121 and a correction control subcircuit 2124.

[0121] The detection subcircuit is coupled to the output terminal of the input unit and is configured to detect the common-mode voltage of the second analog signal (VOP and VON) outputted from the output terminal, thereby outputting a detection signal reflecting whether the input unit is overcompensated or undercompensated. The detection signal may be, for example, a level signal indicating overcompensation or undercompensation using a high or low level, or a level signal indicating the amount of overcompensation or undercompensation.

[0122] Here, the detection subcircuit may include: a common-mode voltage detection module, a reference signal generation module, and a detection output module (also known as a decision module). The common-mode voltage detection module detects the common-mode voltage (VCM) of the second analog signal and outputs a fluctuating electrical signal reflecting changes in the common-mode voltage. The reference signal generation module outputs a reference electrical signal (also known as a preset reference signal). The detection output module is connected to the common-mode voltage detection module and the reference signal generation module, respectively, and is configured to output a detection signal by detecting the fluctuating electrical signal and the reference electrical signal.

[0123] See also Figure 18 , which shows a circuit structure diagram of the detection subcircuit. The common-mode voltage detection module includes a common-mode detection submodule 2122 (also known as the common-mode detection module) and a first amplitude detection submodule 2123 (also known as the test signal amplitude detection module). The reference signal generation module includes a reference signal generation submodule 2125 (also known as the preset reference signal generation module) and a second amplitude detection submodule 2126 (also known as the preset reference signal amplitude detection module). The detection output module 2127 includes a comparator.

[0124] The common-mode detection submodule receives the second analog signals RXP and RXN and outputs a common-mode voltage (VCM) to the reference signal generation submodule and the first amplitude detection submodule. The first amplitude detection submodule outputs a signal S1 reflecting the common-mode voltage (VCM) of the second analog signals RXP and RXN. The reference signal generation submodule receives a pair of reference differential signals C1 and C2 (also known as preset reference signals) and, based on the common-mode voltage VCM detected by the common-mode detection submodule, converts the reference differential signals (C1 and C2) into reference differential signals C1' and C2', such that the amplitudes of the reference differential signals C1' and C2' vary with changes in the common-mode voltage VCM. The second amplitude detection submodule outputs a signal S2 (i.e., a reference electrical signal) reflecting the common-mode voltage (VCM') of the reference differential signals C1' and C2'. The outputs of the first and second amplitude detection submodules are connected to the positive and negative inputs of a comparator in the detection output module, respectively, allowing the detection output module to output high and low level detection signals.

[0125] For example, the first amplitude detection submodule and the second amplitude detection submodule output single-ended level signals S1 and S2 proportional to the peak swing amplitudes of the received serial differential signals RXP and RXN and the reference differential signals C1' and C2', respectively. A comparator compares the level signals output by the first and second amplitude detection submodules to determine whether the swing amplitude of the input serial differential signal is greater than the swing amplitude of the reference differential signal, thereby determining whether the current state of the cascaded equalizer units as a whole is overcompensated or undercompensated relative to the pre-adjustment state.

[0126] It should be noted that Figure 18 The examples shown are merely examples. In the design of some integrated circuits, some circuits in the examples (such as the circuit for common-mode detection) may be common circuits or independently configured.

[0127] The correction control subcircuit is connected to the detection subcircuit and the adjustment terminals of each equalizer unit in the input unit, and is configured to utilize at least one detection signal to perform feedback compensation processing to transmit a corresponding control signal to each adjustment terminal. The adjustment terminal is, for example, the connection terminal between the adjustment circuit and the correction circuit mentioned in the above example.

[0128] The correction control subcircuit can be formed by connecting digital electrical devices such as counters, registers, comparators, and encoders that can perform logic operations to execute the correction control logic. Figure 12 , which shows a processing logic flow chart of the correction control subcircuit processing at least one detection signal. After the chip is powered on or other trigger conditions are met, the chip is set to correction mode, that is, the initial compensation coefficient is set to 0. The digital transmission interface device begins sending test data and transmits it to each equalizer unit through the channel, causing it to begin operation. At the same time, the detection subcircuit compares the amplitude of the second analog signal with the threshold value. The digital circuit within the correction control subcircuit determines the state of the equalizer composed of the cascaded equalizer units based on the comparison result. If it is determined to be in an undercompensated state, the compensation coefficient is increased. If it is determined to be in an overcompensated state, the compensation coefficient is decreased until it is determined that compensation is no longer needed or other cut-off conditions are met, and the correction circuit is shut down, completing the correction. The current preset compensation coefficient is stored as the applied compensation coefficient, and the detection subcircuit enters the normal operation phase. The stored applied compensation coefficient is used as the coefficient for the normal operation of each subsequent equalizer unit to compensate for the gain of the high-frequency signal. Among them, examples of the other trigger conditions include: handshake communication between the data transmitting interface device and the data receiving interface device before transmitting the effective measurement signal of the sensor; or trigger instructions generated based on other measurement data affecting the channel environment such as temperature and humidity, etc.

[0129] Combined with the above Figure 12 The operating process of the correction control subcircuit is as follows: upon power-up, registers, counters, etc. in the correction control subcircuit are reset to initial values ​​(e.g., 0). Each digital electronic device in the correction control subcircuit samples the received detection signal, determines whether the sampled detection signal is overcompensated or undercompensated, and adjusts the count value of the corresponding counter based on the determination result. The above process is executed cyclically at the step frequency of the clock signal until the count value or the number of determinations meets a preset cutoff condition. The encoder in the correction control subcircuit encodes the count value after the loop ends, wherein the count value or the encoded count value obtained after the loop ends can be used as a compensation coefficient and stored. The correction phase ends, and a corresponding binary correction signal is output according to the number of equalizer units. Each equalizer unit receives the first analog signal representing the sensor's measurement signal (i.e., during the working phase). The encoder outputs a binary correction signal corresponding to the compensation coefficient according to the number of equalizer units, so that each equalizer unit performs equalization compensation according to each signal bit of the binary correction signal. Examples of the cutoff condition include no change in the count value (ie, the detection signal has met the preset condition), or the number of judgments reaching a maximum value (ie, the number of compensation operations reaching a maximum value).

[0130] It should be understood that the present application does not impose any specific limitation on the form of the correction signal. For example, the correction signal may include a binary correction signal.

[0131] Based on this, the present application also provides a signal equalization method, which can be used in the process of adjusting the equalizer unit by an external correction circuit; and it can be understood that the signal equalization method can be applied to any signal equalization cycle.

[0132] The signal equalization method may include a calibration phase and an operating phase. For ease of description, in the embodiment of the present application, the first analog signal received by the equalizer unit in the calibration phase is referred to as a test signal, and the first analog signal received by the equalizer unit in the operating phase is referred to as an operating signal.

[0133] For details, please refer to Figure 11 In the calibration phase, the signal equalization method may specifically include the following steps:

[0134] S11: Receive a test signal.

[0135] S12: Compensating the test signal based on a preset compensation coefficient.

[0136] S13: calibrating the preset compensation coefficient according to the compensated test signal and the preset reference signal to obtain an applied compensation coefficient.

[0137] During the working phase, the signal equalization method may specifically include the following steps:

[0138] S21: Receive working signal.

[0139] S22: Compensating the working signal according to the applied compensation coefficient.

[0140] The signal equalization method in the above embodiment can be applied to any signal equalization cycle. During each signal equalization cycle, the calibration phase corrects the preset compensation coefficients to obtain an application compensation coefficient that matches the signal transmission channel. This allows the operating signal to be compensated directly according to the application compensation coefficients during the operating phase, eliminating the need to continuously or repeatedly obtain the compensation coefficients used to equalize the operating signal. This reduces power consumption during the signal equalization process.

[0141] As described above, the signal equalization method in the above embodiment is applicable to low-power consumption scenarios and multi-channel scenarios, especially to scenarios with variable channel characteristics.

[0142] At the same time, corresponding to different signal transmission channels, after power-on, the application compensation coefficient suitable for the current signal transmission channel can be obtained by receiving the test signal and executing the steps of the signal equalization method in the correction stage in the above embodiment. The signal equalization method in the above embodiment can also be applied to different channels and applied to scenarios with changing channel characteristics.

[0143] It should be understood that the signal equalization method involved in the present application can receive signals multiple times during the working stage; on this basis, the signal equalization method can compensate for each received signal multiple times according to the application compensation coefficient during the working stage; it should also be understood that the present application does not specifically limit the form of the test signal. For example, the test signal can be a signal for testing received from the outside by the chip to obtain the application compensation coefficient, or it can be a working signal received from the outside for the first time after the chip starts to power on.

[0144] It should be noted that the present application does not limit the form of the signal equalization cycle, and the signal equalization cycle can be set according to actual conditions; illustratively, the chip can start a correction phase of a signal equalization cycle after power-on, and enter the working phase after the correction is completed and the application compensation coefficient is obtained; optionally, a correction phase can be performed each time the chip is powered on to adapt to the diversity of external cable characteristics; in another possible embodiment, the signal equalization cycle can be set to a preset time, that is, the chip can enter the correction phase periodically after power-on to obtain the current application compensation coefficient, which can improve the accuracy of signal equalization; that is, the embodiment of the present application can obtain the application compensation coefficient periodically, or it can only obtain it once. The embodiment of the present application does not limit the frequency of the chip obtaining the application compensation coefficient during operation.

[0145] It should also be noted that, in a possible embodiment of the present application, the calibration phase and the working phase do not overlap in timing.

[0146] The present application does not impose any specific limitation on the initial value of the preset compensation coefficient in the calibration phase; in one embodiment, the initial value of the preset compensation coefficient is 0.

[0147] Please continue reading Figure 11 In one embodiment, the signal equalization method may further include the following steps during the calibration phase:

[0148] S14: Storing the application compensation coefficient.

[0149] On this basis, the step of compensating the working signal according to the applied compensation coefficient in the working phase may specifically include the following steps:

[0150] converting the applied compensation coefficient into a correction signal, the correction signal comprising signal bits; and

[0151] Under the balanced control of each signal bit of the correction signal, balanced compensation is performed on the signal electrical parameters of the working signal.

[0152] The signal equalization method in the above embodiment can output a correction signal after the correction phase is completed to perform equalization compensation on the signal electrical parameters of the working signal.

[0153] Specifically, in one embodiment, step S13 may include the following steps:

[0154] Using a preset reference signal, detecting the compensated common-mode voltage of the test signal to generate a detection signal; and

[0155] The preset compensation coefficient is corrected according to the detection signal, and the compensation operations are cumulatively counted to obtain an updated preset compensation coefficient until the correction phase ends; wherein the preset compensation coefficient after the correction phase ends is the applied compensation coefficient.

[0156] It should be noted that the detection signal involved in this application can reflect whether the current compensation operation is over-compensation or under-compensation.

[0157] The signal equalization method in the above embodiment determines the common-mode voltage of the test signal after compensation based on a preset reference signal, and generates a detection signal based on this common-mode voltage to determine whether the current compensation operation is under-compensated or over-compensated; then, the preset compensation coefficient can be corrected based on the detection signal, and it can be determined that the current preset compensation coefficient is the applied compensation coefficient when the conditions are met.

[0158] That is to say, during the chip power-on stage, the signal equalization method in the above embodiment can detect the compensated test signal and compare the compensated test signal with the preset reference signal, and then determine the state of the compensation operation at this time based on the comparison result, and make corresponding adjustments to it until the correction stage is completed.

[0159] The specific steps involved in the above embodiment are described in more detail below:

[0160] In one embodiment, the process of detecting the common mode voltage using the preset reference signal to generate the detection signal may specifically include the following steps:

[0161] detecting the common-mode voltage to generate a fluctuation signal reflecting changes in the common-mode voltage; and using the common-mode voltage to convert a reference signal into a reference electrical signal that follows changes in the common-mode voltage; and

[0162] The reference electrical signal and the fluctuation signal are compared and a detection signal is output.

[0163] In the above embodiment, the current preset compensation coefficient is corrected and optimized to obtain a new preset compensation coefficient; steps S11 and S12 are repeated based on the new preset compensation coefficient until the detection signal meets the preset conditions, that is, the current preset compensation coefficient is used as the application compensation coefficient.

[0164] By detecting the common-mode voltage of the compensated test signal, a detection signal is outputted indicating whether the current compensation operation is overcompensated or undercompensated. Specifically, the detection signal may be, for example, a level signal indicating overcompensation or undercompensation using a high or low level, or a level signal indicating the amount of overcompensation or undercompensation.

[0165] In one embodiment, the step of correcting the preset compensation coefficient according to the detection signal may specifically include the following steps:

[0166] Sampling the detection signal and determining whether the sampled detection signal is overcompensated or undercompensated;

[0167] If it is judged to be in an under-compensation state, the compensation coefficient is increased; if it is judged to be in an over-compensation state, the compensation coefficient is decreased.

[0168] If the amplitude of the compensated test signal is smaller than the amplitude of the preset reference signal, the preset compensation coefficient is increased, and the increased preset compensation coefficient is used as the new preset compensation coefficient; if the amplitude of the compensated test signal is larger than the amplitude of the preset reference signal, the preset compensation coefficient is reduced, and the reduced preset compensation coefficient is used as the new preset compensation coefficient.

[0169] It can be understood that the test signals involved in this application may include but are not limited to serial differential signals.

[0170] In one embodiment, the test signal includes a serial differential signal; based on this, the method may further include a step of generating a preset reference signal according to a common mode level of the compensated test signal.

[0171] It should be noted that, in the above embodiment, the preset reference signal includes a preset reference differential signal.

[0172] In the signal equalization method in the above embodiment, a preset reference signal is generated based on the common-mode level of the compensated test signal. The common-mode level of the preset reference signal can change with the change of the common-mode level of the compensated test signal, so that in the subsequent process of comparing the test signal and the preset reference signal, the application compensation coefficient can be determined based on the amplitude difference variable to avoid other variables from having an adverse effect on the determination of the application compensation coefficient, thereby improving the accuracy of the application compensation coefficient.

[0173] Specifically, generating a preset reference signal according to the common mode level of the compensated test signal may include the following steps:

[0174] The amplitude and common-mode level of the compensated test signal are detected, and a preset reference signal is generated according to the common-mode level of the compensated test signal.

[0175] Figure 12 This is a processing logic flow chart of a signal equalization method provided in one embodiment of this application. This embodiment partially involves the calibration phase. It should be noted that in this example, the chip in the calibration phase can be referred to as being in calibration mode, and the chip in the operating phase can be referred to as being in operating mode. In this example, the test signal can be referred to as test data.

[0176] After the chip is powered on or other trigger conditions are met, it is set to calibration mode, i.e., the initial compensation coefficient is set to 0. The digital transmission interface device begins sending test data and transmits it to each equalizer unit via a channel, causing it to begin operation. During operation, each equalizer unit compensates the test signal based on the preset compensation coefficient and compares the amplitude difference between the compensated test signal and the preset reference signal with a preset range to determine the current signal equalization state based on the comparison result. If it is determined to be in an undercompensated state, the preset compensation coefficient is increased and used as the new preset compensation coefficient. If it is determined to be in an overcompensated state, the compensation coefficient is decreased and used as the new preset compensation coefficient. This process continues until it is determined that compensation is no longer needed or other cutoff conditions are met, at which point calibration ends. The current preset compensation coefficient is stored as the applied compensation coefficient. When the chip is in operating mode, the stored applied compensation coefficient can be used as the compensation coefficient for the normal operation of the current signal transmission channel to compensate for the gain of high-frequency signals.

[0177] The equalizer unit in the embodiment of the present application is described in more detail below.

[0178] For example, the equalizer unit may include: a circuit branch L1, a circuit branch L2, an adjustment circuit, and a correction circuit. Circuit branches L1 and L2 are respectively connected to the positive output terminal and the negative output terminal of the equalizer unit, and switches M1 and M2 are respectively configured on circuit branches L1 and L2, and the control terminals of switches M1 and M2 receive differential signals respectively. The adjustment circuit is connected to the correction circuit and is used to adjust the signal electrical parameters of the positive output terminal or the negative output terminal according to the correction signal output by the correction circuit. The correction circuit is connected to both the positive output terminal and the negative output terminal and is used to output a correction signal indicating an increase or decrease in the common-mode voltage difference by detecting the common-mode voltage difference between the positive output terminal and the negative output terminal. In some examples, the equalizer unit further includes a compensation circuit as described in the above examples.

[0179] See also Figure 13 , which shows a schematic diagram of the circuit structure of an equalizer unit. Circuit branch L1 also includes resistor RL1 and switch M5; circuit branch L2 also includes resistor RL2 and switch M6. Resistors RL1 and RL2 have equal resistance values; switches M5 and M6 have the same electrical parameters. VDD is the reference high voltage, VSS is the reference ground voltage, and VBN is the bias voltage.

[0180] like Figure 13 As shown, the regulation circuit 2111 is coupled between the output terminals of switches M1 and M2 and includes energy storage devices (such as capacitors) C0_1 and C0_2 connected in series. The connection between energy storage devices C0_1 and C0_2 receives a correction signal. The compensation circuit 2112 includes, for example: switches M3 and M7 connected in series to the negative output terminal of the equalizer unit, and switches M4 and M8 connected in series to the positive output terminal of the equalizer unit; wherein the control terminal of switch M3 is connected to the positive output terminal of the equalizer unit, and the control terminal of switch M4 is connected to the negative output terminal of the equalizer unit. To further increase the common-mode voltage difference, the compensation circuit also includes energy storage devices Cc_1 and Cc_2 connected in series between the output terminals of switches M3 and M4, wherein the connection between energy storage devices Cc_1 and Cc_2 receives a correction signal. Similar to energy storage devices C0_1 and C0_2, when the correction signal is high, the energy stored in energy storage devices Cc_1 and Cc_2 increases the level of the valid signal output from the positive output terminal, or increases the level of the valid signal output from the negative output terminal. When the correction signal is low, Cc_1 and Cc_2 in the regulation circuit do not store energy, that is, the level of the valid signal output from the positive output terminal does not increase, or the level of the valid signal output from the negative output terminal does not increase.

[0181] To improve the high-frequency compensation capability of the equalizer unit, in this example, the equalizer unit is implemented using a four-stage cascade based on negative capacitance technology. In the figure, VIN and VOUT are the input and output of the equalizer unit, respectively. Since R0 in this example uses a fixed resistor, there is only one control voltage VC used to adjust the circuit's variable capacitors C0 and Cc, thereby adjusting the high-frequency compensation gain of the equalizer unit. The dotted line in the figure is the negative capacitor structure, and its equivalent impedance is:

[0182]

[0183] Among them, gmNC and CgsNC are the transconductance and gate-source capacitance of the MOS tube M3 (M4) respectively.

[0184] Among them, Z NC It can be expressed as negative capacitance -C C and a negative resistor -R C series, where R C The values ​​are:

[0185]

[0186] Therefore, the output impedance of the negative capacitance equalizer unit is:

[0187]

[0188] Z NC The output impedance of the equalizer unit is increased by a zero and a pole, which is located approximately at On both sides of the spectrum, the spectrum of the equalization filter using negative capacitance is as follows Figure 14 As shown (where the dotted line is the frequency response of the basic equalizer unit without negative capacitance), where W n for W n The zeros and poles on both sides are Z NC Obviously, the negative capacitance structure increases the high-frequency compensation gain and the bandwidth of the high-frequency gain of the equalizer unit.

[0189] During the working phase, the input unit performs equalization compensation on the first analog signal from the channel and then outputs the second analog signal to the sampling unit, so that the sampling unit can restore the digital measurement signal processed by the data transmission interface device.

[0190] The sampling unit is coupled to the input unit, and is configured to sample the received second analog signal according to the received clock signal to output a first digital signal and the clock signal.

[0191] Here, the sampling unit responds to the transition edge of the received clock signal and outputs a first digital signal having an inverse relationship. In the example where the first analog signal is a differential signal, since the clock signal is not synchronized with the potential representing data / information in the first analog signal, the first digital signal output by the sampling unit has a large bit error.

[0192] To this end, the sampling unit samples the second analog signal according to multiple clock signals with phase offsets. The first digital signal output by the sampling unit includes: high / low levels obtained by sampling according to the time corresponding to different clock signals; the output first digital signal and one of the clock signals are output to the output unit for subsequent circuits to perform digital signal processing; the sampled first digital signal is output to the clock recovery control unit, which then performs phase detection on the first digital signal generated within a preset number of clock half cycles. The phase offset (also known as phase difference) is less than 180°, for example, the phase offset includes 30°, 45°, or 90°.

[0193] The clock recovery control unit is coupled to the sampling unit, and outputs a clock recovery control signal reflecting a phase deviation between the second analog signal and one of the clock signals by detecting the received first digital signal.

[0194] Here, the clock recovery control unit detects the first digital signal sampled at different phases over a period of time to determine whether any of the clock signals leads or lags in phase with the second analog signal, and outputs a corresponding clock recovery control signal. The period of time is determined based on the duration required to sample a preset number of first digital signals. For example, the period of time can be an integer multiple of a clock half-cycle, or can be determined based on the sum of the phase deviations of multiple clock signals.

[0195] The clock recovery control unit utilizes digital electronic components such as registers, flip-flops, and comparators to construct a detection logic circuit to detect whether the second analog signal has a phase lead or lag relative to the sampled clock signal, and outputs a corresponding clock recovery control signal to the clock generation unit. The clock recovery control unit can detect the phase lead or lag, or obtain an identifier of the phase lead or lag, and represent this information using information such as the amplitude and encoding of the clock recovery control signal.

[0196] The clock generating unit is coupled to the clock recovery control unit and the sampling unit, and is configured to adjust the generated clock signal according to the received clock recovery control signal, and output the adjusted clock signal to the sampling unit.

[0197] Here, the clock generation unit adjusts the frequency and / or initial phase of each output clock signal according to the received clock recovery control signal.

[0198] Taking the identifier indicating the phase advance or lag of the clock recovery control signal as an example, the clock generation unit adjusts the frequency (and / or initial phase) of each clock signal according to a preset frequency step (and / or phase step).

[0199] Taking the phase amount of the phase advance or lag represented by the clock recovery control signal as an example, the clock generation unit adjusts the initial phase of each clock signal according to the phase amount, or converts the phase amount into a frequency change and adjusts the generated clock signals.

[0200] The clock generation unit may include, for example, a regulation circuit, a signal generator, and a phase-locked circuit. The regulation circuit adjusts the frequency division ratio in the phase-locked circuit according to the clock recovery control signal. The phase-locked circuit performs phase-locking and phase-shifting operations on the square wave signal provided by the signal generator based on the frequency division ratio, and outputs multiple clock signals with phase shifts.

[0201] The sampling unit adjusts the phase position of the second analog signal by using the clock signal generated by the clock generating unit to accurately sample the digital signal reflecting the digital signal sent by the data transmission interface device. The sampled first digital signal is transmitted to the output unit.

[0202] The output unit is coupled to the sampling unit, and is used for converting the corresponding collected first digital signal into a second digital signal under the control of the received clock signal, and outputting the second digital signal.

[0203] The clock signal received by the output unit is one of the multiple clock signals, and 0 and 1 data are extracted from the first digital signal according to the clock signal, and converted into a second digital signal for subsequent circuit processing.

[0204] For example, if the output unit includes a differential serial output terminal, the second digital signal obtained by sampling the first digital signal according to the corresponding clock signal is output.

[0205] For another example, if the output unit includes a parallel output terminal, the output unit includes a serial-to-parallel conversion circuit coupled to the sampling unit, the serial-to-parallel conversion circuit being configured to convert a received first digital signal represented by a differential signal into a second digital signal represented by a plurality of parallel signals and output the second digital signal. The serial-to-parallel conversion circuit may, for example, include a circuit having an 8-bit or 10-bit parallel output terminal.

[0206] As described in the above examples, the data receiving interface device and the data transmitting interface device use a test transmission signal to test the channel environment between transmitting valid data, thereby achieving pre-adjustment of the data receiving interface device to suppress channel noise and improve the accuracy of the transmission signal. Balanced compensation operation.

[0207] In a data interface device for an automotive radar sensor, for example, when the radar sensor is triggered to transmit detected measurement data, it uses a data transmission interface device and a data reception interface device to transmit a first analog signal representing the measurement data in real time. Given the extremely high real-time requirements for measurement data in automobiles, the data transmission interface device and the data reception interface device include a signal processing process for clock recovery during differential signal transmission according to a serial transmission protocol. Therefore, shortening this process can effectively reduce the delay in data transmission.

[0208] To this end, the present application also provides a data interface device (also known as a data receiving interface device) designed to shorten the time required to recover a clock signal from a received analog signal. This data interface device enables sensors used in applications such as automotive and traffic monitoring to transmit data (or signals) within milliseconds or even nanoseconds, effectively shortening the time required.

[0209] See also Figure 19 , which is another hardware architecture diagram of a data receiving interface device. The data receiving interface device 3 includes: an input unit 31, a sampling unit 32, a clock recovery control unit 33, a clock generating unit 34, and an output unit 35.

[0210] The input unit may also be referred to as a signal equalizing unit, which is configured to couple with a channel to receive a first analog signal from the channel and output a corresponding second analog signal to be converted. Exemplarily, the input unit 31 may include the input unit (signal equalizing unit) provided in any of the aforementioned embodiments.

[0211] The sampling unit is coupled to the input unit, and is configured to sample the received second analog signal according to the received clock signal to output a first digital signal and the clock signal.

[0212] The clock recovery control unit is coupled to the sampling unit, and outputs a K-bit clock recovery control signal reflecting the phase deviation between the second analog signal and the clock signal by detecting the received first digital signal within a preset number of clock half cycles; wherein the clock recovery control signal uses a field to represent the phase value of the adjusted clock signal.

[0213] The clock generating unit is coupled to the clock recovery control unit and the sampling unit, and is configured to adjust the generated clock signal according to the received clock recovery control signal, and output the adjusted clock signal to the sampling unit.

[0214] The output unit is coupled to the sampling unit, and is configured to convert the corresponding collected first digital signal into a second digital signal under the control of the received clock signal, and output the second digital signal.

[0215] Wherein, the input unit, sampling unit and output unit are the same as those mentioned above. Figures 10-18 The present invention is the same as or similar to any of the data receiving interface devices mentioned in the respective examples. For example, the input unit utilizes a cascaded equalizer unit pre-configured through a test channel to perform swing compensation on the received first analog signal and output a second analog signal. The sampling unit samples the second analog signal according to the received clock signal to output a paired inverse first digital signal. The output unit converts two of the inverse first digital signals into multiple parallel second digital signals. The second digital signals are, for example, 8 or 10 parallel digital signals.

[0216] As described above, the sampling unit responds to the transition edge of the received clock signal and outputs a corresponding inverted first digital signal. When the sampling unit receives multiple clock signals with phase offsets, the first digital signal output by the sampling unit in response to each clock signal includes: a high / low level obtained by sampling at the time corresponding to the different clock signals; the output first digital signal and one of the clock signals are output to the output unit for subsequent circuitry to perform digital signal processing; the sampled first digital signal is output to the clock recovery control unit, which then performs phase detection on the first digital signal generated within a preset number of clock half-cycles. The phase offset (also known as phase difference) is less than 180°, for example, 30°, 45°, or 90°.

[0217] Unlike the aforementioned examples, the clock signal is output by the clock generation unit based on a clock recovery control signal comprising a phase interval and a phase value provided by the clock recovery control unit. The clock recovery control unit performs clock phase detection on the received first digital signal according to the half-cycle (also known as the clock half-cycle) of the currently received clock signal and generates a clock recovery control signal that is fed back to the clock generation unit. The clock generation unit adjusts the phase of the clock signal accordingly to synchronize it with the clock signal used by the data transmission interface device to transmit the analog signal. Because the clock recovery control signal provides both the phase interval and the phase value within the phase interval, the clock recovery control unit and the clock generation unit simultaneously adjust the phase interval and the accurate phase value during the feedback-adjustment process, significantly shortening the feedback-adjustment duration of the clock recovery process.

[0218] In some examples, the clock recovery control unit includes: an N-bit first register and an output circuit. The N-bit first register is used to provide a phase value for a corresponding field. N is an integer greater than 1, indicating the precision of the binary phase value that the N-bit first register can provide. The N-bit first register can be a cascade of multiple registers to implement a shift operation, or can be a shift register. The N-bit first register is used to adjust the temporarily stored binary phase value using shift interpolation. The shift interpolation methods include: shift interpolation from a high bit to a low bit, and / or shift interpolation from a low bit to a high bit. The shift interpolation from a high bit to a low bit or from a low bit to a high bit is used to indicate a clockwise or counterclockwise shift within a phase interval. For example, a shift interpolation value of 1 from a high bit to a low bit indicates that the N-bit first register shifts the phase value counterclockwise; a shift interpolation value of 0 from a low bit to a high bit indicates that the N-bit first register shifts the phase value clockwise.

[0219] The output circuit is connected to the N-bit first register and the clock generation unit, and is configured to generate the clock recovery control signal according to the binary phase value stored in the N-bit first register, and output the signal to the clock generation unit. The output circuit may include, for example, a circuit comprising a flip-flop. For example, each output terminal of the N-bit first register is connected to a flip-flop, and each flip-flop is triggered to output the binary phase value in response to a transition edge of the clock signal.

[0220] Here, the clock recovery control unit can perform an interpolation operation by detecting the clock phase of the second analog signal within a preset number of clock half-cycles to control the N-bit first register to shift from a high-order bit to a low-order bit, or from a low-order bit to a high-order bit. The preset number can be determined based on indicators such as system stability and robustness of the entire data receiving interface device. For example, the number is 8.

[0221] In some examples, the clock generation unit generates multiple clock signals at the current moment based on a clock recovery control signal from a previous moment. The multiple clock signals have a certain phase difference, allowing the sampling unit to sample the received second analog signal multiple times within a single clock half-cycle and output the sampled high and low levels to the clock recovery control unit. A comparison circuit, etc. within the clock recovery control unit selectively controls the N-bit first register to interpolate from the high side or the low side by comparing the high and low levels. When a preset number of times are executed, the output circuit outputs the binary phase value stored in the N-bit first register. Thus, the clock generation unit maintains outputting a clock signal with a certain phase for at least the preset number and the clock half-cycle.

[0222] In some other examples, different from the previous example, the clock recovery control unit counts all high and low levels within a period of a preset number of clock half cycles received; controls the N-bit first register to interpolate from the high side or the low side by comparing the count values, and outputs it by the output circuit.

[0223] To do this, see Figure 20 , which shows a circuit structure diagram of the clock recovery control unit; the clock recovery control unit includes: a first shift decision circuit 331, a first phase adjustment circuit 332, an N-bit first register 333, and an output circuit 334.

[0224] The first shift decision circuit is coupled to the sampling unit, detects the first digital signal within a preset number of clock half cycles, and outputs a control signal determined according to level logic of the number.

[0225] Here, the first digital signal received by the first shift decision circuit is obtained by a sampling unit sampling the second analog signal according to multiple clock signals. For example, the first shift decision circuit and the sampling unit are connected via two differential lines to receive the first digital signal; wherein the first digital signal is obtained by the sampling unit sampling the second analog signal at different times according to the clock phase offsets between the multiple clock signals.

[0226] The first shift decision circuit utilizes circuit components such as a counter and a comparator to perform level counting on the first digital signal and output a control signal based on the level count within at least the preset number of clock half-cycles, wherein the control signal includes at least an identification signal for indicating whether the phase of the first digital signal is ahead of or behind the phase of the clock signal. For example, the identification signal is a 2-bit signal configured based on a preset truth table for phase advance, phase lag, and phase alignment, or is a level signal corresponding to different levels in the truth table.

[0227] In some examples, the first shift decision circuit includes: a phase shift detection circuit structure and a phase shift control circuit structure.

[0228] The phase shift detection circuit structure is coupled to the sampling unit to detect the first digital signal within a preset number of clock half cycles to obtain phase detection data.

[0229] Here, the phase-shift detection circuit structure includes a phase-detection logic circuit for phase detection (also known as phase discrimination) constructed using multiple comparators according to a preset truth table. The phase-shift detection circuit structure also includes a temporary storage circuit constructed from multiple flip-flops / registers to temporarily store the phase-detection results of each phase-detection logic operation. The phase-shift detection circuit structure also includes an output control circuit that outputs the data temporarily stored by each flip-flop as the phase-detection detection data after a preset number of tests.

[0230] In some specific examples, the logic circuit in the phase-shift detection circuit structure generates an n-bit phase-detection result (n≥1) based on the high / low level of the reverse first digital signal detected in each clock half cycle; the phase-detection result is output to a low-order / high-order trigger in a temporary storage circuit; wherein the temporary storage circuit uses a shifting circuit structure to temporarily store the phase-detection result received each time; when the output control circuit detects that a preset number of phase-detection detections have been performed, the phase-detection detection results of each bit in the temporary storage circuit are output, that is, the phase-detection detection data is output, and the temporary storage circuit is reset.

[0231] In yet other specific examples, the phase-shift detection circuit structure utilizes the first and / or last level detected in the first digital signal during the (n-1)th clock half cycle to perform counting detection during the nth clock half cycle, thereby effectively reducing the data transmission rate of the phase-detection data. For example, the phase-shift detection circuit structure can reduce the data transmission rate of the phase-detection data to half the frequency of the clock signal.

[0232] Based on the above circuit structure examples, in some examples, the phase-shift detection circuit structure utilizes different received clock signals to perform phase-shift detection on the levels of corresponding moments in the inverted first digital signal, and performs a preset number of counting operations. In other examples, the phase-shift detection circuit structure utilizes an internal clock signal to sample the received first digital signal, wherein the frequency of the internal clock signal is at least twice the frequency of the clock signal used by the sampling unit; and utilizes the sampled data to perform phase-shift detection, etc.

[0233] See also Figure 21 , which is a timing diagram of the phase-shift detection circuit structure. Using the timing diagram, the phase-shift detection circuit structure can utilize a circuit structure including the above-mentioned circuit structure to achieve the purpose of performing phase detection on a preset number of first digital signals. Among them, within the clock half cycle, the first digital signal received by the phase-shift detection circuit structure is obtained by sampling the second analog signal D using a multi-channel clock signal (CLK0, CLK90, CLK180, CLK270) with a 90° phase shift. The phase-shift detection circuit structure performs shift phase detection on three adjacent first digital signals received in sequence as a group. As shown Figure 21 As shown in FIG, {D0, E0, D1} are the sampling levels of the second analog signal D obtained by sampling the transition edges of the three clock signals with a phase shift of 90° in the first digital signal. Based on the preset phase detection logic, a 2-bit phase detection result is output, as shown in Table 1 below:

[0234] Table 1

[0235] Phase detection logic Phase detection results explain D0≠E0=D1 10 Data Leads Clock D0=E0≠D1 01 Data lags clock D0=E0=D1 00 / 11 No data jump

[0236] The phase shift detection circuit structure continues to detect {D1, E1, D2}, ..., {Dn-1, En-1, Dn} groups of sampling levels; and caches each group of phase detection results; when the number of detections reaches a preset number, the output is up<n,0> and dn<n,0> The phase-locked detection data is composed of the phase-locked detection data; wherein each pair {up(i), dn(i)} in the phase-locked detection data represents the phase-locked detection data of one detection, i∈[n,0].

[0237] The phase shift detection circuit structure sends the generated phase discrimination detection data to the phase shift control circuit structure. The phase shift control circuit structure is coupled to the phase shift detection circuit structure and the first phase adjustment circuit, counts the bit values in the phase discrimination detection data, and outputs a control signal reflecting the counting result, so that the first phase adjustment circuit selects to adjust the stored binary phase value from the high side or the low side of the N-bit first register.

[0238] Here, the phase shift control circuit structure includes a counter for counting 0 or 1 in each digit of the received phase discrimination detection data; and a comparator for outputting the control signal to the first phase adjustment circuit by comparing the counting result with a preset reference level, or by comparing two counting results obtained by respectively counting each digit in up<n,0> and dn<n,0>.

[0239] For example, please refer to Figure 22 , which shows a schematic circuit diagram of a phase shift control circuit structure. The phase shift control circuit structure includes two counters (Count_vote_1 and Count_vote_2) and a comparator CP_vote_1. Among them, the counter Count_vote_1 is used to count the number of 1 or 0 in the bit of up<n,0>; the counter Count_vote_2 is used to count the number of 1 or 0 in the bit of dn<n,0>; the comparator CP_vote_1 receives the level signals reflecting the count values output by the two counters and outputs a control signal including UPV and DNV. Refer to Table 2 for an example. If UPV = 1 & DNV = 0, it means that N(up = 1)>N(dn = 1), that is, the data is ahead of the clock. Under the control of the control signal, the first phase adjustment circuit performs interpolation from the high side of the N-bit first register; if UPV = 0 & DNV = 1, it means that N(up = 1)<N(dn = 1), that is, the data lags behind the clock. Under the control of the control signal, the first phase adjustment circuit performs interpolation from the low side of the N-bit first register; if UPV = 0 & DNV = 0, it means that N(up = 1) = N(dn = 1), that is, the data has no change. Under the control of the control signal, the first phase adjustment circuit does not perform the interpolation operation. Among them, N(*) represents the number of 1 in the bit of up<n,0> or dn<n,0>.

[0240] Table 2

[0241] control signal Phase detection results explain UPV=1&DNV=0 N(up=1)>N(dn=1) Data Leads Clock UPV=0&DNV=1 N(up=1)<N(dn=1) Data lags clock UPV=0&DNV=0 N(up=1)=N(dn=1) No phase difference between data and clock

[0242] The number of interpolated bits of the first phase adjustment circuit can be one or more. To quickly and accurately adjust the binary phase value, the first phase adjustment circuit further includes: a selection circuit structure connected to the first shift decision circuit, configured to select, based on the control signal, the adjustment of the values ​​of a bits on the high-order side or the low-order side of the first register, or the adjustment of the values ​​of b bits on the high-order side or the low-order side of the first register; where a and b are integers less than N, and a≠b. In other words, the selection circuit structure is configured to select either coarse adjustment or fine adjustment of the binary phase value in the first register.

[0243] The specific values ​​of a and b can be adjusted according to the total time limit of actual clock recovery.

[0244] In some specific examples, the number of interpolation bits a or b provided by the selection circuit structure is a fixed value. For example, the logic circuit structure includes a parser that outputs a or b interpolation data based on a received control signal and inserts them from the high-order side or the low-order side of the first register accordingly. The first register adjusts the stored binary phase value based on the shift mode of the first register.

[0245] In some further specific examples, the number of interpolation bits a or b provided by the selection circuit structure can be externally set. For example, the selection circuit structure includes an encoder or decoder (e.g., a temperature encoder) coupled to the phase shift control circuit structure, which receives an external input instruction, encodes the external input instruction into a value of a or b, and performs the interpolation operation as described above upon receiving a control signal.

[0246] An N-bit first register provides 32 bits of storage. When a received external instruction includes instruction information for setting the value a using a 4-bit step value, the thermometer encoder encodes the 4-bit step value, resulting in a being 2. When a received external instruction includes instruction information for setting the value b using a 5-bit step value, the thermometer encoder encodes the 5-bit step value, resulting in b being 1. The numerical values ​​and temperature encoders set above are examples; the encoder used and the step value set can be selected based on actual clock recovery control requirements, process requirements, and so on.

[0247] In order to select a coarse adjustment or a fine adjustment mode to control the number of shift bits a or b in the N-bit first register, in some specific examples, the selection circuit structure determines whether to select coarse adjustment or fine adjustment by performing level logic processing on at least one control signal received.

[0248] In some further specific examples, the control signal includes a control bit for selecting coarse adjustment or fine adjustment for selection circuit structure identification.

[0249] For example, the clock recovery control unit also includes: a second shift decision circuit, which is coupled to the phase shift detection circuit structure and the selection circuit structure, and is used to perform data advance and data lag counting statistics on at least one set of phase detection data received, and output a control signal for selecting coarse adjustment or fine adjustment accordingly, so that the selection circuit structure can perform a selection operation accordingly.

[0250] Among them, the second shift decision circuit uses digital and analog electronic devices such as pulse counting circuits, adders / subtractors, comparators, capacitors, charge and discharge control circuits, isolation circuits, etc. to construct a circuit structure to execute the judgment logic for selecting coarse adjustment or fine adjustment.

[0251] The judgment logic includes, for example:<n,0> and dn<n,0> ) to count; determine whether the difference between the accumulated count values ​​reflecting the data advance and data lag reaches a preset threshold, and select and output a control signal for selecting coarse adjustment or fine adjustment based on the determination result. The threshold is related to the number of coarse adjustment shifts and can be represented by a level signal.

[0252] Taking the second shift decision circuit as an example, the circuit includes: a judgment logic circuit structure, a comparator, etc., wherein the judgment logic circuit structure is coupled to the phase shift detection circuit structure, and is used to perform pulse counting statistics of data advance and data lag for at least one set of phase detection data received, and output a level signal reflecting the phase deviation amplitude obtained after multiple phase detections; the comparator is coupled to the judgment logic circuit structure and the phase shift control circuit structure, and is used to compare the level signal with a preset reference level to output a control signal including selection of coarse adjustment or fine adjustment.

[0253] To this end, the phase shift detection circuit structure provides two phase detection data representing data advance and data lag respectively, such as up<n,0> and dn<n,0> See Figure 23 , which shows a schematic diagram of the circuit structure of the second shift decision circuit 335. The decision logic circuit structure includes two pulse counters (3351_a, 3351_b) that respectively accumulate and count the number of data advances or lags in each phase detection data, and output the counted numbers as level signals / digital signals. The decision logic circuit structure also includes a difference calculation circuit component 3352 that performs signal processing by controlling the level. It subtracts the received level signals / digital signals representing the number of times to detect the amplitude of the phase deviation obtained from multiple phase detections, and converts the amplitude of the phase deviation into a level signal and outputs it. A comparator 3353 compares the level signal with a preset reference level and outputs a high or low level. The high / low level signal serves as the control signal LOCK for selecting coarse or fine adjustment. This control signal, combined with the control signal output by the first phase shift decision circuit, forms a control signal containing multiple control bits, which is output to the first phase adjustment circuit.

[0254] In order to improve the phase alignment accuracy between the phase of the clock signal and the level reflecting valid data in the second analog signal, the clock recovery control unit further includes: an M-bit second register and a second phase adjustment circuit.

[0255] The M-bit second register is used to store the binary phase interval value of the clock signal. The second phase adjustment circuit is coupled to the N-bit first register, the M-bit second register, and the first shift decision circuit, and is used to selectively adjust the binary phase interval value in the M-bit second register based on the binary phase value in the N-bit first register and the control logic composed of the control signal. The control logic is used to indicate that when the binary phase value in the N-bit first register reaches a boundary value, and the control signal indicates to continue adjusting the phase beyond the current boundary value, the binary phase interval value in the M-bit second register is adjusted. In this way, by synchronously adjusting the phase interval value and the phase value, the purpose of achieving phase alignment between the clock signal and the second analog signal is achieved faster and more accurately.

[0256] See also Figure 24 , which shows a condition-state transition diagram for the second phase adjustment circuit adjusting the phase interval. The N-bit first register includes 32 bits: C0, C1, ..., C31. The control signals received by the second phase adjustment circuit include UPV and DNV. Based on the four preset phase intervals (Z0, Z1, Z2, and Z3), the M-bit second register is preset to store the numbering information of the current phase interval. Examples of this numbering information include: information about the two boundaries of the phase interval, or identification information that can correspond to the phase boundaries of the phase interval.

[0257] like Figure 24 As shown, when the current N-bit first register stores all 1s and (UPV=1 & DNV=0), the phase interval is adjusted along the positive direction of the preset phase interval cycle; when the current N-bit first register stores all 0s and (UPV=0 & DNV=1), the phase interval is adjusted along the negative direction of the preset phase interval cycle; when the current first register stores neither all 1s nor all 0s, the current phase interval is maintained. The above condition-state transition mode also applies to a clock recovery control unit that provides coarse and fine adjustment.

[0258] Here, the output circuit is further connected to the M-bit second register to generate the clock recovery control signal according to the phase intervals and corresponding phase values ​​stored in the M-bit second register and the N-bit first register, and output it to the clock generation unit.

[0259] According to one of the above examples, this application provides an example of a clock recovery control unit. Figure 25 , which shows a schematic diagram of the circuit structure of a clock recovery control unit. The clock recovery control unit includes a first shift decision circuit 331, a second shift decision circuit 335 (LD), a first phase adjustment circuit 332, an N-bit first register 333, a second phase adjustment circuit 336, an M-bit second register 337, and an output circuit 334'. The first shift decision circuit 331 includes a phase shift detection circuit structure PD and a phase shift control circuit structure Vote.

[0260] When the sampling unit outputs the first digital signal, the phase shift detection circuit structure detects the sampling levels {D0, E0, D1} of the first digital signal according to the preset number T sampled in the clock half cycle according to the phase detection logic in Table 1 to obtain a phase detection result representing the 2-bit value of the clock in the clock half cycle, where j∈T; all 2-bit values ​​of the preset number T are up<n,0> and dn<n,0> The composed phase detection data is output to the phase shift control circuit structure.

[0261] The phase shift control circuit structure respectively detects the phase detection data up each time it is received.<n,0> and dn<n,0> The first phase adjustment circuit comprises a first control circuit and a second phase adjustment circuit. ...

[0262] The first phase adjustment circuit is under the control of coarse adjustment according to the coarse adjustment bit a and reference Figure 24 Condition-state transition diagram, shift adjusts the binary phase value stored in the N-bit first register. Alternatively, the first phase adjustment circuit is controlled by fine adjustment according to the fine adjustment bit b and reference Figure 24 Schematic diagram of condition-state transition, shifting and adjusting the binary phase value stored in the N-bit first register.

[0263] See also Figure 26 , which shows a condition-state transition diagram of a first phase adjustment circuit adjusting a binary phase value. Taking the coarse adjustment bit a=2 and the fine adjustment bit b=1 as an example, the received control signal includes a first control signal and a second control signal. When UPV=1&DNV=0 in the first control signal, and the second control signal indicates fine phase adjustment, the first phase adjustment circuit selects to shift from the C0 bit to the C31 bit in the N-bit first register according to the number of bits, and inserts the value 0 into the C0 bit; when UPV=0&DNV=1 in the first control signal, and the second control signal indicates fine phase adjustment, the first phase adjustment circuit selects to shift from the C31 bit to the C0 bit in the N-bit first register according to the number of bits, and inserts the value 1 into the C31 bit. Similarly, when the value stored in the N-bit first register is as follows: Figure 24 As shown in Figure 1, all 1s are shown, and when UPV=1&DNV=0 in the first control signal, the second phase adjustment circuit adjusts the value in the M-bit second register in the positive direction of the cycle of the phase interval to adjust a phase interval; when the value stored in the N-bit first register is as shown in Figure 2, Figure 24 When all 0s are shown, and UPV = 1 & DNV = 0 in the first control signal, the second phase adjustment circuit adjusts the value in the M-bit second register in the negative direction of the phase interval cycle to adjust the phase interval. When the first control signal indicates fine adjustment and UPV = 0 & DNV = 0 in the second control signal, phase adjustment is complete. Each time the N-bit first register or the M-bit second register is adjusted, the output circuit generates a clock recovery control signal and outputs it to the clock generation unit.

[0264] The clock generation unit generates multiple clock signals with phase differences within a clock half-cycle based on the received phase interval and the binary phase value within the corresponding phase interval, and feeds these signals back to the sampling unit. The sampling unit outputs one of the clock signals and the first digital signal to the output unit, thereby outputting a second digital signal that can be recognized by subsequent circuits.

[0265] Using the signal transmission methods mentioned in the above examples, before transmitting valid data, the data transmitting interface device and the data receiving interface device transmit a preset amount of test data according to a preset transmission protocol to recover the clock signal and test the current channel environment noise, thereby recovering an accurate second digital signal from the channel.

[0266] In some electronic devices, the data interface device integrates both a data transmission interface and a data reception interface to achieve bidirectional communication. In other electronic devices, the interface device and the data reception interface device are configured in different hardware modules, depending on the data transmission design between the hardware modules of the electronic device.

[0267] See also Figure 27 , which shows a schematic diagram of the hardware structure of a sensor system. The sensor system 4 includes a first radar sensor 41 and a second radar sensor 42. The first radar sensor 41 or the second radar sensor 42 is, for example, a chip-level sensor, or a printed circuit board integrated with multifunctional components such as an antenna and a signal transceiver chip. The two are connected via the data transmission interface device 411 and the data reception interface device 421 to achieve purposes such as expanding the sensor system's detection range and improving resolution. The sensor system is, for example, a cascade connection of the first and second radar sensors using a printed circuit board, or a cascade connection of the chip-level first and second radar sensors using system-on-chip (SoC) technology.

[0268] At least one of the first and second radar sensors further includes an antenna assembly and a signal transceiver. Driven by the signal transceiver, the antenna assembly transmits a detection signal wave and receives an echo signal wave reflected from a target. The signal transceiver outputs a baseband digital signal corresponding to the echo signal wave. For example, the signal transceiver comprises a signal transmitter and a signal receiver. Both the antenna assembly and the signal transceiver are integrated into the first or second radar sensor at the chip level, for example, using a circuit structure fabricated using a semiconductor manufacturing process. The signal transmitter transmits the detection signal wave via the antenna assembly within a preset frequency band or at a fixed frequency. The signal receiver performs signal processing on the echo electrical signal corresponding to the echo signal wave, including mixing, filtering, and automatic gain adjustment, and performs analog-to-digital conversion on the analog signal to output the baseband digital signal. The echo signal wave is generated by the detection signal wave reflecting from an object, and the echo electrical signal is generated by the receiving antenna sensing the echo signal wave.

[0269] In some examples, at least one of the first radar sensor and the second radar sensor may further include a signal processing device for processing the baseband digital signal and outputting measurement data. The signal processing device performs signal processing including a fast Fourier transform (FFT) operation on the baseband digital signal to output measurement data including at least one of angle, distance, and velocity.

[0270] In yet other examples, at least one of the first radar sensor and the second radar sensor may further include a target detection device configured to perform target detection, target tracking, or other data processing on the measurement data to output target detection data. The target detection device is configured to perform target detection processing on the received measurement data to output corresponding target detection data.

[0271] The first radar sensor further includes a first data interface device, such as the data transmission interface device described in any of the above examples, configured to transmit a measurement signal detected by the first radar sensor. The measurement signal reflects at least one of the following data: a baseband digital signal detected by the first radar sensor; at least one of the following measurement data: the distance, velocity, and azimuth between the first radar sensor and a target; and target detection data of the target.

[0272] The second radar sensor further includes a second data interface device and a third data interface device; the second data interface device is connected to the first data interface device via a channel; the second data interface device is configured to receive the measurement signal, such as the data receiving interface device described in any of the above examples; and the third data interface device is configured to forward the measurement signal. The channel is a medium through which the first and second radar sensors transmit measurement signals, and examples thereof include a microstrip line, a coaxial cable, or an optical fiber.

[0273] Here, the third data interface device may be the data transmission interface device as described in any of the above examples; or other data interface devices, such as a CAN bus interface.

[0274] A sensor system comprising multiple radar sensors typically consists of a master and slave devices. The master manages the operating status of the slave devices and coordinates the data / signals generated by itself and the slave devices, allowing them to be input / output through designated data interface devices. Examples of such operating states include at least one of the following: a state in which the signal transceiver is transmitting and receiving signals using at least one transceiver channel; a standby state; or a data read / write state.

[0275] For example, in a cascade sensor system, one of the first or second radar sensors serves as the master device, and the other serves as the slave device. Under the control of the master device, both the first and second radar sensors utilize a third data interface device to transmit data with an external device. For example, measurement signals detected by the first and second radar sensors are transmitted via the third data interface device. To provide a more complete perception solution, in some examples, the sensor system further includes a data processing device coupled to the third data interface device for performing at least one type of data processing on the measurement signals and outputting corresponding target detection results, interaction data, or control instructions via the third data interface device.

[0276] The target detection results are information extracted from the measurement data that describes dynamic and / or static objects in the surrounding environment detected by the sensor system, including but not limited to vital sign information, movement information, boundary information, identification information, etc. for a single target (or multiple targets). The interactive data is data determined for the purpose of delivering the measurement data or target detection results to the user, including but not limited to at least one of the following data for the user to perceive: reminders, warnings, graphics, or sounds. The control instructions are information generated by processing the received measurement data or target detection results according to preset trigger conditions, used to cause other hardware systems to change their operating states; the trigger conditions are related to the purpose of processing the measurement data or target detection results. For example, the control instructions include but are not limited to at least one of the following: a control instruction for slowing down or turning a car, a control instruction for detecting life activities within a cabin (or indoors), etc.

[0277] To this end, the operating process of the sensor system is exemplified as follows: Taking the second radar sensor as the master and the first radar sensor as the slave, the second radar sensor manages the synchronous transmission and reception of signal waves by the first radar sensor and performs signal processing such as mixing and filtering on the electrical signals provided by their respective assigned virtual transceiver channels to output baseband digital signals. The first and second radar sensors also perform digital signal processing on the baseband digital signals to generate measurement data. Under the management and control of the second radar sensor, the first radar sensor utilizes the physical link of the first data interface device, the channel, and the second data interface device to establish a communication mechanism for outputting the generated measurement data to the second radar sensor. For example, during the handshake phase of the signal transmission protocol, the first radar sensor establishes a communication link with the second radar sensor by transmitting a handshake signal via the first data interface device to transmit the measurement data obtained by the first radar sensor. Furthermore, the handshake signal enables the equalization circuit in the second data interface device to preset a compensation amplitude based on the noise level detected in the current channel. Furthermore, the clock recovery unit and the clock unit in the second data interface device recover a clock signal from the handshake signal for sampling subsequent measurement signals. After the communication link is established, the first and second data interface devices accurately transmit and receive measurement signals. The measurement signal is a transmission-friendly analog signal generated after the measurement data undergoes communication processing by the first data interface device. Under the management and control of the second radar sensor, the second radar sensor also transmits the measurement data obtained by the first radar sensor and itself to the data processing device, which extracts target detection data from the measurement data provided by both radar sensors and uses the target detection data to obtain target detection results, interaction data, or control instructions. This target detection result, interaction data, or control instruction information is output via the third data interface device for subsequent hardware circuitry to execute corresponding operations.

[0278] The present application also provides a data acquisition device that connects a chip-level radar sensor to peripheral circuits to enable the radar sensor to operate and forward or further process any of the baseband digital signals, measurement data, or target detection results provided by the radar sensor.

[0279] To this end, the data acquisition device includes: the data receiving interface device and data processing device mentioned in the above example; it may also include a data transmitting interface device, Out_Port_1. For ease of description, in this example, the data receiving interface device is also referred to as the fourth data interface device, and the data transmitting interface device is also referred to as the fifth data interface device. The fourth data interface device is connected to the data transmitting interface device, Out_Port_2 (also referred to as the sixth data interface device), in the radar sensor via a channel.

[0280] It can be understood that the data transmission interface device in the above example should be able to be used to send test signals and working signals.

[0281] See also Figure 28 , which shows a hardware structure diagram of a data acquisition device 5, wherein a third radar sensor 51, a fourth data interface device 52, a data processing device 53, and a fifth data interface device 54 are all configured on a printed circuit board. Specifically, the sixth data interface device 511 of the third radar sensor 51 is coupled to the fourth data interface device 52. (Not shown in the figure), the third radar sensor and its peripheral circuits are configured on one printed circuit board, while the fourth data interface device 52, the data processing device 53, and the fifth data interface device 54 are configured on another printed circuit board. The two printed circuit boards are coupled to the fourth data interface device 52 via the sixth data interface device 511 of the third radar sensor 51.

[0282] The third radar sensor is exemplified by the first radar sensor, the second radar sensor, or the sensor system in the aforementioned examples; it includes a sixth data interface device, which is coupled to the fourth data interface device via a channel. The sixth data interface device is any of the data receiving interface devices provided in the aforementioned examples; the fourth data interface device is any of the data transmitting interface devices provided in the aforementioned examples. Examples of the fifth data interface device include, but are not limited to, at least one of the following: a USB interface, a CAN interface, and a SerDes interface.

[0283] The third radar sensor transmits the measurement signal to a data processing device via the coupled sixth data interface device and the fourth data interface device. The data processing device is an electronic device that forwards or further processes any of the baseband digital signals, measurement data, and target detection results provided by the fourth data interface device. Examples of the data processing device include at least one of the following: a programmable processor such as a CPU, an MCU, a DSP, and an FPGA. Examples of forwarding operations include at least one of the following: converting the parallel data output by the fourth data interface device into at least one data format supported by a USB interface, converting the parallel data into a data format supported by a CAN interface, etc. The further processing operation involves performing data processing based on the received digital signal. For example, if the received digital signal is a baseband digital signal, the further processing operation may include at least one of the following: detecting interference signals in the baseband digital signal; processing the baseband digital signal to obtain measurement data including at least one of distance, velocity, and angle. For another example, if the received digital signal is measurement data, then the continued processing operation may include data processing for a single target (or multiple targets): vital sign information, movement information, or boundary information, identification information, interactive processing, etc. For another example, if the received digital signal is a target detection result, then the continued processing operation may include at least one of the following: interactive processing, control processing, etc. The interactive data obtained through interactive processing is data determined for the purpose of delivering the measurement data or target detection result to the user, including but not limited to at least one of the following data for the user to perceive: reminders, warnings, graphics, or sounds. The control instructions obtained through control processing are information generated after data processing of the received measurement data or target detection result according to a preset trigger condition, which is used to cause other hardware systems to change their operating status; wherein the trigger condition is related to the data processing purpose of the measurement data or target detection result.

[0284] In any of the above examples, the signal generated by the continued processing operation is output by the fifth data interface device for subsequent circuit equipment to perform corresponding processing.

[0285] In one embodiment, the present application also provides an electronic device equipped with the sensor system or data acquisition device, which includes: an antenna; a carrier; a sensor system or data acquisition device as described in the above embodiment. The antenna is arranged on the carrier; or the chip or integrated circuit integrated with the sensor is then arranged on the carrier (that is, the antenna can be the antenna provided in the AiP or AoC structure). The chip or the integrated circuit is connected to the peripheral circuit device through a fifth data interface device (that is, the chip or integrated circuit does not have an integrated antenna at this time, and can be a SoC, etc.). The carrier can be a printed circuit board PCB (such as a development board, a data acquisition board or a mainboard of a device, etc.), and the printed circuit board provides a channel such as a PCB trace.

[0286] The electronic device transmits measurement signals between various electronic devices based on at least one pair of the data transmission interface device and the data reception interface device provided in the above examples. This allows for interaction between a target object that is not within the same spatial range and a user, or for automatic control of the electronic device based on the detected target object. For example, target detection information is marked on a map and displayed to a terminal device held by the user. The map is a coordinate system that abstractly describes the measurement spatial range and can be displayed in a patterned manner on the terminal device. The position, speed, and other information corresponding to the target detection information are indicated on the patterned map interface. For another example, when abnormal information such as slowed breathing is detected through analysis of the target detection information, the corresponding user is reminded to provide emergency assistance using interactive methods such as audio and video. For another example, when vital signs such as respiration are detected through analysis of target detection information within a room, the output power or position of electronic devices within the room is adjusted.

[0287] In some embodiments, the electronic devices described above may be components and products used in fields such as smart housing, transportation, smart home, consumer electronics, monitoring, industrial automation, in-cabin detection, and health care. For example, the device body may be intelligent transportation equipment (such as cars, bicycles, motorcycles, ships, subways, trains, etc.), security equipment (such as cameras), liquid level / flow rate detection equipment, smart wearable devices (such as bracelets, glasses, etc.), smart home devices (such as sweeping robots, door locks, televisions, air conditioners, smart lights, etc.), various communication devices (such as mobile phones, tablets, etc.), as well as gates, smart traffic lights, smart signs, traffic cameras, and various industrial robotic arms (or robots). It can also be various instruments for detecting vital signs and various devices equipped with such instruments, such as in-cabin detection in automobiles, indoor personnel monitoring, smart medical equipment, consumer electronic devices, etc.

[0288] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0289] Note that the above are only preferred embodiments of the present application and the technical principles employed. Those skilled in the art will understand that the present application is not limited to the specific embodiments herein, and that various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present application. Therefore, although the present application has been described in more detail through the above embodiments, the present application is not limited to the above embodiments and may include many other equivalent embodiments without departing from the scope of the present application. The scope of the present application is determined by the scope of the appended claims.

Claims

1. A signal equalization method, characterized in that: Applicable to any signal equalization cycle; the signal equalization cycle includes a calibration phase and a working phase; wherein the signal equalization method includes: In the calibration phase: receiving a test signal; compensating the test signal based on a preset compensation coefficient; correcting the preset compensation coefficient according to the compensated test signal and a preset reference signal to obtain an applied compensation coefficient; correcting the preset compensation coefficient according to the compensated test signal and the preset reference signal to obtain an applied compensation coefficient, including: using the preset reference signal to detect a common-mode voltage of the compensated test signal to generate a detection signal; wherein the detection signal reflects whether the current compensation operation is over-compensated or under-compensated; correcting the preset compensation coefficient according to the detection signal; wherein the preset compensation coefficient after the calibration phase is the applied compensation coefficient; During the working phase: receiving a working signal, and compensating the working signal according to the applied compensation coefficient.

2. The signal equalization method according to claim 1, wherein: The signal equalization method further comprises: in a correction phase, storing the applied compensation coefficient; In the working stage, compensating the working signal according to the application compensation coefficient includes: converting the applied compensation coefficient into a correction signal, wherein the correction signal includes a signal bit; Under the balanced control of each signal bit of the correction signal, balanced compensation is performed on the signal electrical parameters of the working signal.

3. The signal equalization method according to claim 1, wherein: The calibration phase and the working phase do not overlap in timing.

4. The signal equalization method according to claim 1, wherein: The step of correcting the preset compensation coefficient according to the compensated test signal and the preset reference signal to obtain an applied compensation coefficient further includes: The compensation operations are cumulatively counted to obtain and update the preset compensation coefficient until the correction phase ends.

5. The signal equalization method according to claim 4, characterized in that: The conditions for the end of the correction phase include: The detection signal meets a preset condition; or the number of compensation operations reaches a maximum value.

6. The signal equalization method according to claim 4, characterized in that: The detecting the common mode voltage by using the preset reference signal to generate the detection signal includes: detecting the common-mode voltage to generate a fluctuation signal reflecting a change in the common-mode voltage; and utilizing the common-mode voltage to convert a reference differential signal into a reference electrical signal that follows a change in the common-mode voltage; The reference electrical signal and the fluctuation signal are compared, and the detection signal is output.

7. A signal equalization unit, characterized in that: Including equalization circuit and correction circuit; in The equalization circuit is used to receive a test signal during a calibration phase and compensate the test signal based on a preset compensation coefficient to obtain a compensated test signal; and is also used to receive a working signal during a working phase and compensate the working signal according to the applied compensation coefficient; The correction circuit is connected to the equalizing circuit and forms an electrical loop, and is used to correct the preset compensation coefficient according to the test signal after compensation by the equalizing circuit and a preset reference signal to obtain the applied compensation coefficient; the correction circuit includes an amplitude detection and judgment module and a digital control module; one end of the amplitude detection and judgment module is connected to the equalizing circuit, and the other end is connected to one end of the digital control module, and is used to use the preset reference signal to detect the common-mode voltage of the compensated test signal to generate a detection signal; wherein the detection signal reflects whether the current compensation operation is over-compensated or under-compensated; the other end of the digital control module is connected to the equalizing circuit, and is used to correct the preset compensation coefficient according to the detection signal; wherein the preset compensation coefficient after the correction stage is completed is the applied compensation coefficient; The correction circuit is closed during the working phase.

8. The signal equalization unit according to claim 7, characterized in that: The signal equalization unit further includes a storage module; the storage module is used to store the application compensation coefficient determined in the correction stage.

9. The signal equalization unit according to claim 7, characterized in that: The digital control module is further configured to cumulatively count the compensation operations to obtain and update the preset compensation coefficient until the correction phase is completed.

10. The signal equalization unit according to claim 9, characterized in that: The conditions for the end of the correction phase include: The detection signal meets a preset condition; or the number of compensation operations reaches a maximum value.

11. The signal equalization unit according to claim 7, characterized in that: The test signal includes a serial differential signal; the amplitude detection and decision module includes: A common mode detection module, configured to obtain the common mode voltage of the test signal; a preset reference signal generating module, connected to the common mode detection module, for utilizing the common mode voltage to convert the reference signal into a reference electrical signal that changes with the common mode voltage; a test signal amplitude detection module, configured to detect the common mode voltage to generate a fluctuation signal reflecting a change in the common mode voltage; a preset reference signal amplitude detection module, connected to the preset reference signal generation module, and configured to output the reference electrical signal; The decision module is connected to the test signal amplitude detection module and the preset reference signal amplitude detection module, and is used to compare the reference electrical signal with the fluctuation signal and output the detection signal.

12. A data receiving interface device, characterized in that: comprising a signal equalization unit according to any one of claims 7 to 11; as well as a sampling unit connected to the signal equalization unit, and configured to sample the received second analog signal according to the received clock signal to output a first digital signal and the clock signal; a clock recovery control unit, coupled to the sampling unit, configured to detect the received first digital signal and output a clock recovery control signal reflecting a phase deviation between the second analog signal and one of the clock signals; The output unit is coupled to the sampling unit, and is used to convert the first digital signal collected correspondingly into a second digital signal under the control of the received clock signal, and output the second digital signal.

13. A sensor system, characterized in that: include: A first radar sensor including a first data interface device; The first data interface device is configured to transmit a measurement signal obtained by detection by the first radar sensor; wherein the measurement signal is configured to reflect at least one of the following data: a baseband digital signal obtained by detection by the first radar sensor, at least one of a distance, a speed, and an azimuth between the first radar sensor and a target, and target detection data of the target; The second radar sensor includes a second data interface device and a third data interface device; wherein the second data interface device is connected to the first data interface device via a channel; the second data interface device includes the data receiving interface device as described in claim 12, which is used to receive the measurement signal; and the third data interface device is used to forward the measurement signal.

14. A data acquisition device, characterized in that: include: a first data interface device configured to transmit a measurement signal obtained by detection by a first radar sensor; wherein the measurement signal is configured to reflect at least one of the following data: a baseband digital signal obtained by detection by the first radar sensor, at least one of a distance, a speed, and an azimuth between the first radar sensor and a target, and target detection data of the target; The second data interface device according to claim 12, configured to receive the measurement signal sent by the first data interface device.

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