Memory allocation and recovery method, device and storage medium for reconfigurable processor

Abstract

The present invention relates to the field of memory management of reconfigurable processors, and discloses a memory allocation and recycling method, device and storage medium of a reconfigurable processor. The memory allocation and recycling method of a reconfigurable processor comprises: parsing the data in the input data set and the output data set to determine the life cycle of each input data and each output data; allocating memory to the data in the input data set and the output data set according to the life cycle, determining the memory block information allocated to the data in the input data set and the output data set; and calculating the memory blocks allocated to the data in the subgraph input data set and the output data set in the subgraph set one by one according to the life cycle and the memory block information of the input data set and the output data set for recycling. The method solves the technical problem that when the existing reconfigurable processor processes data, conflicts occur due to simultaneous access of banks and the lack of timely recycling, resulting in excessively long access time for external data.

Description

Technical Field

[0001] The present invention relates to the technical field of memory management of reconfigurable processors, and in particular to a memory allocation and recovery method, device and storage medium of a reconfigurable processor. Background Art

[0002] Modern computing systems increasingly rely on hardware accelerators to work in conjunction with central processing units (CPUs) to meet the growing demand for computing efficiency. Coarse-grained reconfigurable arrays (CGRAs) have become a prominent accelerator because they provide a good blend of computing throughput, power efficiency, and reconfigurability. CGRAs are designed as arrays of processing elements (PEs) connected using a 2D mesh network. PEs typically consist of an arithmetic logic unit (ALU), a register file, and a configuration memory. As one of the most effective means of improving performance, software pipelining technology fully exploits instruction-level parallelism by overlapping operations from different loop iterations. In this case, the data elements required by different operations need to be accessed and processed from memory at the same time. Since a bank can only be accessed by one operation at a time, access conflicts may occur when accessing at the same time. If the data on the bank is not processed, when the amount of data involved in the program is large, it will cause the PE to access data from outside the CGRA, increasing the time overhead of accessing data.

[0003] With respect to the technical problem in the prior art that, when the existing reconstructed processor processes data, conflicts occur due to simultaneous access of banks and failure to recycle them in time, resulting in excessively long access times for external data access, no effective solution has been proposed yet. Summary of the invention

[0004] The embodiments of the present disclosure provide a memory allocation and recycling method, device and storage medium for a reconfigurable processor, so as to at least solve the technical problem in the prior art that when an existing reconfigurable processor processes data, conflicts occur due to simultaneous access to banks and the banks are not recycled in time, resulting in excessively long access time for external data.

[0005] According to one aspect of an embodiment of the present disclosure, a memory allocation and recycling method for a reconfigurable processor is provided, comprising: parsing data in an input data set and an output data set to determine the life cycle of each input data and each output data; allocating memory for the data in the input data set and the output data set based on the life cycle, and determining memory block information allocated to the data in the input data set and the output data set; and calculating memory blocks allocated to the data in the subgraph input data set and the output data set in a subgraph set one by one based on the life cycle and memory block information of the input data set and the output data set for recycling, wherein the subgraph set is a set of all subgraphs of a point graph.

[0006] According to another aspect of an embodiment of the present disclosure, a storage medium is further provided, the storage medium including a stored program, wherein when the program is running, a processor executes any one of the methods described above.

[0007] According to another aspect of an embodiment of the present disclosure, a memory allocation and recycling device for a reconfigurable processor is also provided, including: a first determination module, used to parse the data in the input data set and the output data set, and determine the life cycle of each input data and each output data; a second determination module, used to allocate memory to the data in the input data set and the output data set according to the life cycle, and determine the memory block information allocated to the data in the input data set and the output data set; and a recycling module, used to calculate the memory blocks allocated to the data in the subgraph input data set and the output data set in the subgraph set one by one according to the life cycle and memory block information of the input data set and the output data set for recycling, wherein the subgraph set is the set of all subgraphs of the point graph.

[0008] According to another aspect of an embodiment of the present disclosure, a memory allocation and recycling device for a reconfigurable processor is also provided, including: a processor; and a memory, connected to the processor, for providing the processor with instructions for processing the following processing steps: parsing the data in the input data set and the output data set to determine the life cycle of each input data and each output data; allocating memory for the data in the input data set and the output data set based on the life cycle, and determining memory block information allocated to the data in the input data set and the output data set; and calculating the memory blocks allocated to the data in the subgraph input data set and the output data set in the subgraph set one by one based on the life cycle and memory block information of the input data set and the output data set for recycling, wherein the subgraph set is the set of all subgraphs of the point graph.

[0009] In the disclosed embodiment, by mining the usage and life cycle of the array (input data and output data), the memory bank space utilization is maximized, the work efficiency of the entire CGRA is improved, and the time spent on accessing data is reduced. The life cycle of each data is further obtained by studying the relationship between the data involved in different subgraphs. Based on this life cycle, after each subgraph is finished running, the data at the end of the life cycle is recycled, achieving the technical effect of maximizing the utilization of the memory space, and by reasonably recycling the memory space, the working performance of the reconstruction processor is greatly improved, avoiding the problem of long time consumption caused by external storage of data. This solves the technical problem that when the existing reconstruction processor processes data in the prior art, due to conflicts caused by simultaneous access to the bank and no timely recycling, the external access of data causes the access time to be too long. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The illustrative embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation on the present disclosure. In the drawings:

[0011] Figure 1 is a hardware structure block diagram of a computing device for implementing the method according to Embodiment 1 of the present disclosure;

[0012] Figure 2 is a flowchart of a memory allocation and recycling method for a reconfigurable processor according to the first aspect of Embodiment 1 of the present disclosure;

[0013] Figure 3A It is a flowchart of allocation and recovery of data memory according to Embodiment 1 of the present disclosure;

[0014] Figure 3B and Figure 3C is a schematic diagram of an exemplary sub-graph of the sub-graph described in Embodiment 1 of the present disclosure;

[0015] Figure 4 is a schematic diagram of a process of traversing a subgraph set according to Embodiment 1 of the present disclosure;

[0016] Figure 5 is a schematic diagram of a memory allocation and recycling device for a reconfigurable processor according to Embodiment 2 of the present disclosure; and

[0017] Figure 6 It is a schematic diagram of a memory allocation and recovery device of a reconfigurable processor according to Embodiment 3 of the present disclosure. DETAILED DESCRIPTION

[0018] In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only embodiments of a part of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work should fall within the scope of protection of the present disclosure.

[0019] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products, or devices.

[0020] Example 1

[0021] According to this embodiment, a memory allocation and recovery method embodiment of a reconfigurable processor is also provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0022] The method embodiment provided in this embodiment can be executed in a mobile terminal, a computer terminal, a server or a similar computing device. Figure 1 The hardware structure block diagram of a computing device for implementing a memory allocation and recycling method for a reconfigurable processor is shown. Figure 1 As shown, the computing device may include one or more processors (the processor may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA), a memory for storing data, and a transmission device for communication functions. In addition, it may also include: a display, an input / output interface (I / O interface), a universal serial bus (USB) port (which may be included as one of the ports of the I / O interface), a network interface, a power supply and / or a camera. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above electronic device. Figure 1More or fewer components as shown, or with Figure 1 Different configurations shown.

[0023] It should be noted that the one or more processors and / or other data processing circuits described above may generally be referred to herein as "data processing circuitry". The data processing circuitry may be embodied in whole or in part as software, hardware, firmware, or any other combination thereof. In addition, the data processing circuitry may be a single independent processing module, or may be incorporated in whole or in part into any of the other components of the computing device. As involved in the embodiments of the present disclosure, the data processing circuitry acts as a processor control (e.g., selection of a variable resistor terminal path connected to an interface).

[0024] The memory can be used to store software programs and modules of application software, such as the program instructions / data storage device corresponding to the memory allocation and recovery method of the reconfigurable processor in the embodiment of the present disclosure. The processor executes various functional applications and data processing by running the software programs and modules stored in the memory, that is, the memory allocation and recovery method of the reconfigurable processor of the above-mentioned application is realized. The memory may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory may further include a memory remotely arranged relative to the processor, and these remote memories can be connected to the computing device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0025] The transmission device is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of the computing device. In one example, the transmission device includes a network adapter (Network Interface Controller, NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device can be a radio frequency (Radio Frequency, RF) module, which is used to communicate with the Internet wirelessly.

[0026] The display may be, for example, a touch screen liquid crystal display (LCD) that may enable a user to interact with a user interface of the computing device.

[0027] It should be noted that, in some optional embodiments, the above Figure 1 The computing device shown may include hardware elements (including circuits), software elements (including computer code stored on a computer-readable medium), or a combination of both hardware elements and software elements. Figure 1This is merely one example of a particular embodiment and is intended to illustrate the types of components that may be present in the computing devices described above.

[0028] In the above operating environment, according to the first aspect of this embodiment, a memory allocation and recycling method for a reconfigurable processor is provided. Figure 2 A schematic diagram showing the process of the method is shown in FIG. Figure 2 As shown, the method includes:

[0029] S202: Parse the data in the input data set and the output data set to determine the life cycle of each input data and each output data;

[0030] S204: performing memory allocation for the data in the input data set and the output data set according to the life cycle, and determining memory block information allocated to the data in the input data set and the output data set; and

[0031] S206: According to the life cycle and memory block information of the input data set and the output data set, the memory blocks allocated for the data in the subgraph input data set and the output data set in the subgraph set are calculated one by one for recycling, wherein the subgraph set is the set of all subgraphs of the point graph.

[0032] As described in the background technology, as one of the most effective means to improve performance, software pipelining technology fully utilizes instruction-level parallelism by overlapping operations from different loop iterations. In this case, the data elements required by different operations need to be accessed and processed from the memory at the same time. Since a bank can only be accessed by one operation at the same time, access conflicts may occur when accessing at the same time. If the data on the bank is not processed, when the amount of data involved in the program is large, it will cause PE to access data from outside the CGRA, increasing the time overhead of accessing data.

[0033] In view of this, an embodiment of the present application provides a memory allocation and recycling method for a reconstruction processor. First, the computing device parses the data in the input data set and the output data set to determine the life cycle of each input data and each output data (S202).

[0034] Specifically, the life cycle of data refers to the number of subgraphs in which the data will be used. Measured by the subgraph sequence number, for any data, after division, its life cycle may be 0, 1, or even until the end of the program. First, different data need to be classified and identified, mainly divided into two categories: input data and output data. For each data, its life cycle is converted into which subgraphs the data will be used in. Based on this information, the subgraph number that last used the data is obtained to replace the role of the life cycle.

[0035] For example, the subgraph set includes 10 subgraphs, and input data 1 is in subgraph Figure 1 , 2 , 5, 7, so the life cycle of input data 1 can be counted as {1,2,5,7}. Thus, by determining the life cycle of data, it is convenient to allocate and recycle memory for later data.

[0036] In addition, not simply using the life cycle, you can also quickly and easily determine whether this data will cause access conflicts with other data. Not simply using the life cycle: for example, the life cycle of a certain data may be 4, which means that the entire data is used in subgraph No. 4 at most, and then it can be recycled; and not simply using the life cycle means recording which subgraphs each data is used by, and using this to calculate the life cycle (the last subgraph number that uses this data is the life cycle of this data). Quickly obtain data that does not conflict with other data: for example, use the variable "which subgraphs are used by" just recorded for each data, and find the intersection of this variable for each data. Data with intersections cannot exist in the same bank, otherwise conflicts will occur.

[0037] Furthermore, the computing device performs memory allocation on the data in the input data set and the output data set according to the life cycle, and determines memory block information allocated to the data in the input data set and the output data set (S204).

[0038] Specifically, refer to Figure 3A As shown, the process of data memory allocation and recovery is shown. According to the life cycle of the data obtained by parsing the data, it is determined whether to allocate memory for the data, thereby avoiding memory allocation for data that does not need to be calculated, which leads to unreasonable use of memory.

[0039] Furthermore, the computing device calculates the memory blocks allocated for the data in the subgraph input data set and the output data set in the subgraph set one by one according to the life cycle and memory block information of the input data set and the output data set, where the subgraph set is the set of all subgraphs of the point graph.

[0040] Specifically, the point graph can be a dynamic graph. For example, the subgraph set includes 10 subgraphs, and input data 1 is in the subgraph. Figure 1 , 2 , 5, 7, so the life cycle of input data 1 can be counted as {1,2,5,7}. Therefore, when the operation of subgraph 7 is completed, the life cycle of input data 1 ends. Thus, the memory of input data 1 is recycled. Thus, through the above method, the data life cycle is used as a basis for real-time data memory recycling, thereby improving memory utilization.

[0041] also, Figure 3B and Figure 3C The example shows Figure 1 Kazuko Figure 2 Schematic diagram of the allocation and recycling process, refer to Figure 3B and Figure 3C As shown, with sub Figure 1 Kazuko Figure 2 For example, the memory allocation and recycling process is as follows: first allocate ld1, then ld2, ld3, st7, and st8. Figure 1 After the allocation is completed, you need to Figure 2 To distribute; in pairs Figure 2 Before allocation, it is necessary to reclaim some data that does not participate in the operation, that is, the bank space occupied by the data of ld1, ld2, and st8; assuming that ld1 is allocated to the bank address 0-9; ld2 is allocated to the bank address 10-19; ld3 is allocated to the bank address 20-29, and st7 is allocated to the bank address 30-39... (This is only used to illustrate the artificial result of the recycling mechanism, and the bank conflict problem needs to be considered in practice). Therefore, when recycling, it is necessary to reclaim: 0-9, 10-19, 40-49 address spaces, and merge the bank segments 0-9 and 10-19. Therefore, when performing subsequent allocations, the bank segments 0-19 and 40-49 can be used as free segments to be allocated to other data.

[0042] Thus, through the above-mentioned method, by mining the usage and life cycle of the array (input data and output data), the memory bank space utilization is maximized, the work efficiency of the entire CGRA is improved, and the time spent on accessing data is reduced. The life cycle of each data is further obtained by studying the relationship between the data involved in different subgraphs. Based on this life cycle, after each subgraph is finished running, the data at the end of the life cycle is recycled, achieving the technical effect of maximizing the utilization of memory space, and by reasonably recycling memory space, the working performance of the reconstruction processor is greatly improved, avoiding the problem of long time consumption caused by external storage of data. This solves the technical problem that when the existing reconstruction processor processes data in the prior art, due to conflicts caused by simultaneous access to the bank and no timely recycling, the external access of data causes the access time to be too long.

[0043] Optionally, the data in the input data set is parsed to determine the operation of the life cycle of each input data, including: traversing the input data subsets of the subgraphs in the subgraph set one by one, and parsing the input data in the input data subsets to obtain attribute information of the input data, wherein the attribute information includes an operation label, an array name of the operation, an array length of the operation, a starting position of the array of the operation, a step size of the operation data, and subgraph information used by the operation data, wherein the subgraph information used by the operation data is used to indicate the life cycle of the operation data; determining the first subgraph information corresponding to the input data in the input data set based on the attribute information; and determining the life cycle of the input data in the input data set based on the first subgraph information corresponding to the input data in the input data set.

[0044] Specifically, for example, before obtaining the data life cycle, you can define the data attributes: operation label label, operation array name arrayName, operation array length arraySize, operation array starting position start, operation array step length stride, in which subgraphs the operation data is used invokedPartitionNo, etc.

[0045] First, refer to Figure 4 As shown, a schematic diagram of the process of traversing a subgraph set is shown, refer to Figure 4 As shown in the figure, traverse each subgraph, parse each input data first, get the label, start, stride, arrayName, arraySize and other attributes, and then traverse the inputdata in the unparsed subgraph to determine whether the number part of its label attribute is the same as the label number part in the current inputdata. If they are the same, it is considered that the operation is the same array, and the subgraph sequence number of this subgraph is added to the subgraph number used by this inputdata, and the subgraph information using this input data is obtained in turn, that is, the life cycle of the input data is obtained. For example, the subgraph set includes 10 subgraphs, and input data 1 is in subgraph Figure 1 , 2 , 5, 7, so the life cycle of input data 1 can be counted as {1,2,5,7}. Figure 4 As shown, repeat the above operation for all subgraphs to obtain the attributes of all data and the information on which subgraphs they are used in. Thus, the life cycle of the input data in the input data set is obtained.

[0046] In addition, after the subgraph set is divided, for the result of the subgraph division, we first need to parse out the data information involved in the load operation and store operation in each subgraph (i.e., the input data subset and the output data subset), and analyze the life cycle of each data, and then allocate a memory block bank to each data, and after any subgraph ends, recycle the data whose life cycle ends. Therefore, before reclaiming the bank memory space, a very important step is to parse the data information. In parsing the data information, a very critical step is to obtain the life cycle of the data.

[0047] In addition, each Ld of a subgraph is the input data of this subgraph, and each St is the output data of this subgraph. Figure 3B As shown, Figure 1 :Ld1, Ld2, Ld3 are all sub Figure 1 Input data, St7 and St8 are sub Figure 1 Output data.

[0048] Optionally, the data in the output data set is parsed to determine the operation of the life cycle of each output data, including: traversing the output data subsets and input data subsets of the subgraphs in the subgraph set one by one, and parsing the output data subsets and the input data and output data in the input data subsets to obtain attribute information of the output data, wherein the attribute information includes an operation label, an array name of the operation, an array length of the operation, a starting position of the array of the operation, a step size of the operation data, and subgraph information used by the operation data, wherein the subgraph information used by the operation data is used to indicate the life cycle of the operation data; determining the second subgraph information corresponding to the input data in the output data set based on the attribute information; and determining the life cycle of the output data in the output data set based on the second subgraph information corresponding to the output data in the output data set.

[0049] Specifically, for example, before obtaining the data life cycle, you can define the data attributes: operation label label, operation array name arrayName, operation array length arraySize, operation array starting position start, operation array step length stride, in which subgraphs the operation data is used invokedPartitionNo, etc.

[0050] First, refer to Figure 4 As shown, a schematic diagram of the process of traversing a subgraph set is shown, refer to Figure 4As shown, traverse each subgraph, parse each output data outputdata first, get the label, start, stride, arrayName, arraySize and other attributes, and then traverse the inputdata and outputdata in the unparsed subgraphs to determine whether the numeric part of the label attribute is the same as the numeric part of the label in the current outputdata. If they are the same, it is considered that the operation is the same array, and the subgraph serial number is added to the subgraph number used by this outputdata, and the subgraph information using the input data is obtained in turn, that is, the life cycle of the output data is obtained, and the label of each operation data can be set to: ld[0-9] for inputdat and: st[0-9] for outputdata, and for the operation of the same data of ld and st, it is agreed that the numeric part of the label is the same, for example, ld9 and st9 - indicating that ld9 and st9 operate on the same array (in this case, st9 must appear first, and then ld9, so the bank allocation information of ld9 can directly follow the allocation information of st9). Reference Figure 4 As shown, repeat the above operation for all subgraphs to obtain the attributes of all data and the information on which subgraphs they are used in. Thus, the life cycle of the output data in the output data set is obtained.

[0051] Optionally, based on the life cycle, memory is allocated to the data in the input data set and the output data set, and the operation of determining the memory block information allocated to the data in the input data set and the output data set includes: determining whether the life cycle of the data in the input data set and the output data set is 0, and if the life cycle of the data in the input data set and the output data set is 0, no memory allocation is performed; and if the life cycle of the data in the input data set and the output data set is not 0, memory is allocated to the data in the input data set and the output data set, and the memory block information allocated to the data in the input data set and the output data set is determined.

[0052] Specifically, the life cycle of data refers to the number of subgraphs in which the data will be used. It is measured by the subgraph sequence number. For any data, after being divided, its life cycle may be 0, 1, or even until the end of the program. When the life cycle of data is 0, it means that it is not involved in the operation of the subgraph set, so there is no need to allocate content for the data, thereby improving the utilization rate of the reconstruction processor memory.

[0053] Optionally, allocating memory to data in the input data set and the output data set based on the life cycle, and determining the memory block information allocated to the data in the input data set and the output data set, also includes: extracting required data from the data using a data retrieval mode based on attribute information of the data in the input data set and the output data set, and determining valid data; and allocating memory to the valid data based on the life cycle, and determining the memory block information allocated to the data in the input data set and the output data set.

[0054] Specifically, if all the data of an array is moved to the memory bank every time, not all the data will be used in many cases. In this case, only the required part should be moved to the memory bank to participate in the calculation. For example, in the description information of the array, the start field and the stride field are added to describe the data access mode for a certain array. Then the computing device accesses the data on the register DDR according to the data access mode to obtain the corresponding data needed, and then moves the valid data to the memory bank. Therefore, through the above method, when moving the array in the DDR register, only the data used in the code is moved, thereby improving the bank space utilization.

[0055] In addition, after the input and output data of all sub-graphs are allocated, the array needs to be moved to the bank. If the data retrieval / storage rules are known in advance, the required part of the data can be moved to the bank according to this method. If the data retrieval / storage rules are unknown, the entire array is moved to the bank.

[0056] In addition, reference Figure 1 As shown, according to the second aspect of this embodiment, a storage medium is provided, wherein the storage medium includes a stored program, wherein when the program is run, a processor executes any one of the above methods.

[0057] Therefore, according to this embodiment, by mining the usage and life cycle of the array (input data and output data), the memory bank space utilization is maximized, the work efficiency of the entire CGRA is improved, and the time spent on accessing data is reduced. The life cycle of each data is further obtained by studying the relationship between the data involved in different subgraphs. Based on this life cycle, after each subgraph is finished running, the data at the end of the life cycle is recycled, achieving the technical effect of maximizing the utilization of the memory space, and by reasonably recycling the memory space, the working performance of the reconstruction processor is greatly improved, avoiding the problem of long time consumption caused by external storage of data. This solves the technical problem that when the existing reconstruction processor processes data in the prior art, due to conflicts caused by simultaneous access to the bank and no timely recycling, the external access of data causes the access time to be too long.

[0058] It should be noted that, for the above-mentioned method embodiments, for the sake of simplicity, they are all described as a series of action combinations, but those skilled in the art should know that the present invention is not limited by the described action sequence, because according to the present invention, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present invention.

[0059] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present invention.

[0060] Example 2

[0061] Figure 5 The memory allocation and recovery method device 500 of the reconfigurable processor according to this embodiment is shown, and the device 500 corresponds to the method according to the first aspect of embodiment 1. Figure 5 As shown, the device 500 includes: a first determination module 510, which is used to parse the data in the input data set and the output data set, and determine the life cycle of each input data and each output data; a second determination module 520, which is used to allocate memory to the data in the input data set and the output data set according to the life cycle, and determine the memory block information allocated to the data in the input data set and the output data set; and a recycling module 530, which is used to calculate the memory blocks allocated to the data in the subgraph input data set and the output data set in the subgraph set one by one according to the life cycle and memory block information of the input data set and the output data set for recycling, wherein the subgraph set is the set of all subgraphs of the point graph.

[0062] Optionally, the first determination module 510 includes: a first determination submodule, used to traverse the input data subsets of the subgraphs in the subgraph set one by one, and parse the input data in the input data subsets to determine attribute information of the input data, wherein the attribute information includes an operation label, an array name of the operation, an array length of the operation, a starting position of the array of the operation, a step size of the operation data, and subgraph information used by the operation data, wherein the subgraph information used by the operation data is used to indicate the life cycle of the operation data; a second determination submodule, used to determine the first subgraph information corresponding to the input data in the input data set based on the attribute information; and a third determination submodule, used to determine the life cycle of the input data in the input data set based on the first subgraph information corresponding to the input data in the input data set.

[0063] Optionally, the first determination module 510 includes: a fourth determination submodule, used to traverse the output data subsets and input data subsets of the subgraphs in the subgraph set one by one, and parse the input data and output data in the output data subsets and the input data subsets to determine attribute information of the output data, wherein the attribute information includes an operation label, an array name of the operation, an array length of the operation, a starting position of the array of the operation, a step size of the operation data, and subgraph information used by the operation data, wherein the subgraph information used by the operation data is used to indicate the life cycle of the operation data; a fifth determination submodule, used to determine, based on the attribute information, the second subgraph information corresponding to the input data in the output data set; and a sixth determination submodule, used to determine, based on the second subgraph information corresponding to the output data in the output data set, the life cycle of the output data in the output data set.

[0064] Optionally, the second determination module 520 includes: a judgment module, used to judge whether the life cycle of the data of the input data set and the output data set is 0, and if the life cycle of the data of the input data set and the output data set is 0, no memory allocation is performed; and a seventh determination sub-module, used to allocate memory to the data in the input data set and the output data set if the life cycle of the data of the input data set and the output data set is not 0, and determine the memory block information allocated to the data in the input data set and the output data set.

[0065] Optionally, the second determination module 520 also includes: an eighth determination sub-module, which is used to extract required data from the data using a data retrieval mode based on attribute information of the data of the input data set and the output data set, and determine valid data; and a ninth determination sub-module, which is used to allocate memory for valid data based on the life cycle, and determine memory block information allocated to the data in the input data set and the output data set.

[0066] Therefore, according to this embodiment, by mining the usage and life cycle of the array (input data and output data), the memory bank space utilization is maximized, the work efficiency of the entire CGRA is improved, and the time spent on accessing data is reduced. The life cycle of each data is further obtained by studying the relationship between the data involved in different subgraphs. Based on this life cycle, after each subgraph is finished running, the data at the end of the life cycle is recycled, achieving the technical effect of maximizing the utilization of the memory space, and by reasonably recycling the memory space, the working performance of the reconstruction processor is greatly improved, avoiding the problem of long time consumption caused by external storage of data. This solves the technical problem that when the existing reconstruction processor processes data in the prior art, due to conflicts caused by simultaneous access to the bank and no timely recycling, the external access of data causes the access time to be too long.

[0067] Example 3

[0068] Figure 6 The memory allocation and recovery method device 600 of the reconfigurable processor according to this embodiment is shown, and the device 600 corresponds to the method according to the first aspect of embodiment 1. Figure 6 As shown, the device 600 includes: a processor 610; and a memory 620, which is connected to the processor 610 and is used to provide the processor 610 with instructions for processing the following processing steps: parsing the data in the input data set and the output data set to determine the life cycle of each input data and each output data; allocating memory for the data in the input data set and the output data set according to the life cycle, and determining the memory block information allocated to the data in the input data set and the output data set; and calculating the memory blocks allocated to the data in the subgraph input data set and the output data set in the subgraph set one by one according to the life cycle and memory block information of the input data set and the output data set for recycling, wherein the subgraph set is the set of all subgraphs of the point graph.

[0069] Optionally, the data in the input data set is parsed to determine the operation of the life cycle of each input data, including: traversing the input data subsets of the subgraphs in the subgraph set one by one, and parsing the input data in the input data subsets to obtain attribute information of the input data, wherein the attribute information includes an operation label, an array name of the operation, an array length of the operation, a starting position of the array of the operation, a step size of the operation data, and subgraph information used by the operation data, wherein the subgraph information used by the operation data is used to indicate the life cycle of the operation data; determining the first subgraph information corresponding to the input data in the input data set based on the attribute information; and determining the life cycle of the input data in the input data set based on the first subgraph information corresponding to the input data in the input data set.

[0070] Optionally, the data in the output data set is parsed to determine the operation of the life cycle of each output data, including: traversing the output data subsets and input data subsets of the subgraphs in the subgraph set one by one, and parsing the output data subsets and the input data and output data in the input data subsets to obtain attribute information of the output data, wherein the attribute information includes an operation label, an array name of the operation, an array length of the operation, a starting position of the array of the operation, a step size of the operation data, and subgraph information used by the operation data, wherein the subgraph information used by the operation data is used to indicate the life cycle of the operation data; determining the second subgraph information corresponding to the input data in the output data set based on the attribute information; and determining the life cycle of the output data in the output data set based on the second subgraph information corresponding to the output data in the output data set.

[0071] Optionally, based on the life cycle, memory is allocated to the data in the input data set and the output data set, and the operation of determining the memory block information allocated to the data in the input data set and the output data set includes: determining whether the life cycle of the data in the input data set and the output data set is 0, and if the life cycle of the data in the input data set and the output data set is 0, no memory allocation is performed; and if the life cycle of the data in the input data set and the output data set is not 0, memory is allocated to the data in the input data set and the output data set, and the memory block information allocated to the data in the input data set and the output data set is determined.

[0072] Optionally, allocating memory to data in the input data set and the output data set based on the life cycle, and determining the memory block information allocated to the data in the input data set and the output data set, also includes: extracting required data from the data using a data retrieval mode based on attribute information of the data in the input data set and the output data set, and determining valid data; and allocating memory to the valid data based on the life cycle, and determining the memory block information allocated to the data in the input data set and the output data set.

[0073] Therefore, according to this embodiment, by mining the usage and life cycle of the array (input data and output data), the memory bank space utilization is maximized, the work efficiency of the entire CGRA is improved, and the time spent on accessing data is reduced. The life cycle of each data is further obtained by studying the relationship between the data involved in different subgraphs. Based on this life cycle, after each subgraph is finished running, the data at the end of the life cycle is recycled, achieving the technical effect of maximizing the utilization of the memory space, and by reasonably recycling the memory space, the working performance of the reconstruction processor is greatly improved, avoiding the problem of long time consumption caused by external storage of data. This solves the technical problem that when the existing reconstruction processor processes data in the prior art, due to conflicts caused by simultaneous access to the bank and no timely recycling, the external access of data causes the access time to be too long.

[0074] The serial numbers of the above embodiments of the present invention are only for description and do not represent the advantages or disadvantages of the embodiments.

[0075] In the above embodiments of the present invention, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0076] In the several embodiments provided by the present invention, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only schematic, for example, the division of the units is only a logical function division, and there may be other division methods in actual implementation, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point, the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0077] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0078] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0079] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, RandomAccess Memory), mobile hard disk, magnetic disk or optical disk and other media that can store program codes.

[0080] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A memory allocation and recovery method for a reconfigurable processor, characterized in that: include: Parse the data in the input data set and the output data set to determine the life cycle of each input data and each output data; According to the life cycle, memory is allocated to the data in the input data set and the output data set, and memory block information to which the data in the input data set and the output data set are allocated is determined; as well as According to the life cycle of the input data set and the output data set and the memory block information, the memory blocks allocated to the data in the input data set and the output data set of the subgraphs in the subgraph set are calculated one by one for recycling, wherein the subgraph set is a set of all subgraphs of the point graph; Parse the data in the input data set and determine the operations of the life cycle of each input data, including: Traversing the input data subsets of the subgraphs in the subgraph set one by one, and parsing the input data in the input data subsets to obtain attribute information of the input data, wherein the attribute information includes an operation label, an array name of the operation, an array length of the operation, a starting position of the array of the operation, a step size of the operation data, and subgraph information used by the operation data, wherein the subgraph information used by the operation data is used to indicate the life cycle of the operation data; Determining first subgraph information corresponding to the input data in the input data set according to the attribute information; and Determining the life cycle of the input data in the input data set according to first subgraph information corresponding to the input data in the input data set; Parse the data in the output data set and determine the operations of the life cycle of each output data, including: Traversing the output data subsets and input data subsets of the subgraphs in the subgraph set one by one, and parsing the input data and output data in the output data subset and the input data subset to obtain attribute information of the output data, wherein the attribute information includes an operation label, an array name of the operation, an array length of the operation, a starting position of the array of the operation, a step size of the operation data, and subgraph information used by the operation data, wherein the subgraph information used by the operation data is used to indicate the life cycle of the operation data; Determining, according to the attribute information, second subgraph information corresponding to the input data in the output data set; and The life cycle of the output data in the output data set is determined according to the second subgraph information corresponding to the output data in the output data set.

2. The method according to claim 1, characterized in that The operation of performing memory allocation on the data in the input data set and the output data set according to the life cycle and determining the memory block information allocated to the data in the input data set and the output data set includes: Determine whether the life cycle of the data of the input data set and the output data set is 0, and if the life cycle of the data of the input data set and the output data set is 0, do not perform memory allocation; and When the life cycle of the data in the input data set and the output data set is not 0, memory is allocated to the data in the input data set and the output data set, and memory block information allocated to the data in the input data set and the output data set is determined.

3. The method according to claim 1, characterized in that The operation of performing memory allocation for the data in the input data set and the output data set according to the life cycle and determining the memory block information allocated to the data in the input data set and the output data set further includes: According to the attribute information of the data of the input data set and the output data set, using the data acquisition mode to extract the required data from the data to determine the valid data; and According to the life cycle, memory is allocated to the valid data, and memory block information of the data allocation in the input data set and the output data set is determined.

4. A storage medium, characterized in that: The storage medium includes a stored program, wherein when the program is executed, the processor executes the method according to any one of claims 1 to 3.

5. A memory allocation and recovery device for a reconfigurable processor, characterized in that: include: A first determination module is used to parse the data in the input data set and the output data set to determine the life cycle of each input data and each output data; A second determining module is used to perform memory allocation on the data in the input data set and the output data set according to the life cycle, and determine memory block information allocated to the data in the input data set and the output data set; as well as A recycling module, used to calculate the memory blocks allocated to the data in the input data set and the output data set of the subgraphs in the subgraph set one by one for recycling according to the life cycle of the input data set and the output data set and the memory block information, wherein the subgraph set is the set of all subgraphs of the point graph; The first determination module includes: A first determination submodule is used to traverse the input data subsets of the subgraphs in the subgraph set one by one, and parse the input data in the input data subsets to determine the attribute information of the input data, wherein the attribute information includes an operation label, an array name of the operation, an array length of the operation, a starting position of the array of the operation, a step size of the operation data, and subgraph information used by the operation data, wherein the subgraph information used by the operation data is used to indicate the life cycle of the operation data; A second determining submodule is configured to determine first subgraph information corresponding to the input data in the input data set according to the attribute information; and A third determination submodule, configured to determine the life cycle of the input data in the input data set according to the first subgraph information corresponding to the input data in the input data set; The first determination module includes: a fourth determination submodule, configured to traverse the output data subsets and input data subsets of the subgraphs in the subgraph set one by one, and parse the input data and output data in the output data subset and the input data subset to determine the attribute information of the output data, wherein the attribute information includes an operation label, an array name of the operation, an array length of the operation, a starting position of the array of the operation, a step size of the operation data, and subgraph information used by the operation data, wherein the subgraph information used by the operation data is used to indicate the life cycle of the operation data; a fifth determining submodule, configured to determine, according to the attribute information, second subgraph information corresponding to the input data in the output data set; and The sixth determination submodule is used to determine the life cycle of the output data in the output data set according to the second subgraph information corresponding to the output data in the output data set.

6. A memory allocation and recovery device for a reconfigurable processor, characterized in that: include: processor; as well as A memory, connected to the processor, configured to provide the processor with instructions for processing the following processing steps: Parse the data in the input data set and the output data set to determine the life cycle of each input data and each output data; According to the life cycle, memory is allocated to the data in the input data set and the output data set, and memory block information to which the data in the input data set and the output data set are allocated is determined; as well as According to the life cycle of the input data set and the output data set and the memory block information, the memory blocks allocated to the data in the input data set and the output data set of the subgraphs in the subgraph set are calculated one by one for recycling, wherein the subgraph set is a set of all subgraphs of the point graph; Parse the data in the input data set and determine the operations of the life cycle of each input data, including: Traversing the input data subsets of the subgraphs in the subgraph set one by one, and parsing the input data in the input data subsets to obtain attribute information of the input data, wherein the attribute information includes an operation label, an array name of the operation, an array length of the operation, a starting position of the array of the operation, a step size of the operation data, and subgraph information used by the operation data, wherein the subgraph information used by the operation data is used to indicate the life cycle of the operation data; Determining first subgraph information corresponding to the input data in the input data set according to the attribute information; and Determining the life cycle of the input data in the input data set according to the first subgraph information corresponding to the input data in the input data set; Parse the data in the output data set and determine the operations of the life cycle of each output data, including: Traversing the output data subsets and input data subsets of the subgraphs in the subgraph set one by one, and parsing the input data and output data in the output data subset and the input data subset to obtain attribute information of the output data, wherein the attribute information includes an operation label, an array name of the operation, an array length of the operation, a starting position of the array of the operation, a step size of the operation data, and subgraph information used by the operation data, wherein the subgraph information used by the operation data is used to indicate the life cycle of the operation data; Determining, according to the attribute information, second subgraph information corresponding to the input data in the output data set; and The life cycle of the output data in the output data set is determined according to the second subgraph information corresponding to the output data in the output data set.

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