Display panel and driving method thereof, and display device

Abstract

The present application provides a display panel and a driving method thereof, and a display device, which relate to the field of display technology. Each first gate driving unit and each second gate driving unit in the display panel are electrically connected to a first circuit control terminal and a second circuit control terminal in N adjacent rows of pixel driving circuits, and each third gate driving unit is electrically connected to a scan signal terminal in one row of pixel driving circuits; N≥2 and is a positive integer; the driving method of the display panel comprises: within a frame scanning time, in the N adjacent rows of pixel driving circuits, a first time period is included between the end point at which the scan signal terminal of the N-th row of pixel driving circuits receives the scan drive signal transmitted by the third gate driving unit and the end point at which the second circuit control terminal of the N-th row of pixel driving circuits receives the drive signal transmitted by the second gate driving unit; the first time period is used for all charges of the second node in the N-th row of pixel driving circuits to leak to the first node in the N-th row of pixel driving circuits.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and more specifically, to a display panel and a driving method thereof, and a display device. Background Art

[0002] Nowadays, with the development of information society, the requirements for displays that display information are getting higher and higher. Therefore, users have an increasing demand for flat panel displays that are small in size, light in weight, and have good display effects.

[0003] As personal devices become more popular, portable and / or wearable devices are being actively developed. In order to apply display devices to portable and / or wearable devices, the device needs to have the characteristics of low power consumption; however, using the technology developed so far, the display with excellent low power consumption performance is limited. For example, in the prior art, when the display product is displayed at a low frequency, and in order to ensure that the border of the display product is small enough, part of the gate drive circuit is often designed as a one-drive-multiple design, such as a one-drive-two design; however, when the display product adopts a one-drive-multiple design, the problem of interlaced bright and dark lines is prone to occur, affecting the user experience. Therefore, it is urgent to provide a method that can improve the problem of bright and dark lines on the screen of the display device. Summary of the invention

[0004] In view of this, the present invention provides a display panel and a driving method thereof, and a display device, so as to solve the problem of bright and dark lines appearing on the screen of the display device in the prior art.

[0005] In a first aspect, the present application provides a method for driving a display panel, wherein the display panel comprises a display area and a non-display area surrounding the display area;

[0006] The display panel comprises a first gate driving circuit, a second gate driving circuit and a third gate driving circuit located in the non-display area, the first gate driving circuit comprises a plurality of first gate driving units connected in cascade, the second gate driving circuit comprises a plurality of second gate driving units connected in cascade, and the third gate driving circuit comprises a plurality of third gate driving units connected in cascade;

[0007] It also includes a plurality of pixel driving circuits located in the display area, the pixel driving circuits including:

[0008] A first switch module, wherein a first end of the first switch module is electrically connected to a first node,

[0009] The second end of the first switch module is electrically connected to the first reference voltage end, and the control end of the first switch module is electrically connected to the first circuit control end;

[0010] A data writing module, wherein a first end of the data writing module is electrically connected to the data signal end, a second end of the data writing module is electrically connected to the second node, and a control end of the data writing module is electrically connected to the scan signal end;

[0011] a second switch module, wherein a first end of the second switch module is electrically connected to the first node, a second end of the second switch module is electrically connected to a third node, and a control end of the second switch module is electrically connected to a second circuit control end;

[0012] Each of the first gate driving units is electrically connected to the first circuit control terminal of the pixel driving circuits in N adjacent rows, each of the second gate driving units is electrically connected to the second circuit control terminal of the pixel driving circuits in N adjacent rows, and each of the third gate driving units is electrically connected to the scanning signal terminal of the pixel driving circuit in one row; wherein N≥2, and N is a positive integer;

[0013] The driving method of the display panel includes:

[0014] Within a frame scanning time, in the N adjacent rows of pixel driving circuits, a first time period is included between an end point at which the scanning signal end of the pixel driving circuit in the Nth row receives the scanning driving signal transmitted by the third gate driving unit and an end point at which the second circuit control end of the pixel driving circuit in the Nth row receives the driving signal transmitted by the second gate driving unit; the first time period is used for all charges of the second node in the pixel driving circuit in the Nth row to leak to the first node in the pixel driving circuit in the Nth row.

[0015] In a second aspect, the present application provides a display panel, the display panel comprising a display area and a non-display area surrounding the display area;

[0016] The display panel comprises a first gate driving circuit, a second gate driving circuit and a third gate driving circuit located in the non-display area, the first gate driving circuit comprises a plurality of first gate driving units connected in cascade, the second gate driving circuit comprises a plurality of second gate driving units connected in cascade, and the third gate driving circuit comprises a plurality of third gate driving units connected in cascade;

[0017] It also includes a plurality of pixel driving circuits located in the display area, the pixel driving circuits including:

[0018] A first switch module, wherein a first end of the first switch module is electrically connected to a first node,

[0019] The second end of the first switch module is electrically connected to the first reference voltage end, and the control end of the first switch module is electrically connected to the first circuit control end;

[0020] A data writing module, wherein a first end of the data writing module is electrically connected to the data signal end, a second end of the data writing module is electrically connected to the second node, and a control end of the data writing module is electrically connected to the scan signal end;

[0021] a second switch module, wherein a first end of the second switch module is electrically connected to the first node, a second end of the second switch module is electrically connected to a third node, and a control end of the second switch module is electrically connected to a second circuit control end;

[0022] Among them, each of the first gate driving units is electrically connected to the first circuit control end in the adjacent N rows of pixel driving circuits, each of the second gate driving units is electrically connected to the second circuit control end in the adjacent N rows of pixel driving circuits, and each of the third gate driving units is electrically connected to the scanning signal end in 1 row of the pixel driving circuits; wherein N≥2, and N is a positive integer.

[0023] In a third aspect, the present application provides a display device, comprising the display panel.

[0024] Compared with the prior art, the display panel and its driving method and display device provided by the present invention achieve at least the following beneficial effects:

[0025] The present application provides a display panel and a driving method thereof, and a display device. The first gate driving circuit and the second gate driving circuit in the display panel are both designed as one-drive N-row pixel driving circuits, and the third gate driving circuit is designed as one-drive one-row pixel driving circuit. By setting in the driving method of the display panel that in a frame scanning time, in the adjacent N-row pixel driving circuits, a first time period is included between an end point at which a scanning signal end of the N-row pixel driving circuit receives a scanning driving signal transmitted by a third gate driving unit and an end point at which a second circuit control end of the N-row pixel driving circuit receives a driving signal transmitted by a second gate driving unit; the first time period is used for all charges of the second node in the N-row pixel driving circuit to leak to the first node in the N-row pixel driving circuit, and the first node therein is electrically connected to a driving transistor in the pixel driving circuit, so that the potentials of the first nodes of the pixel driving circuits in the 1st to Nth rows are the same, thereby avoiding the bright and dark line problem caused by different potentials of the first nodes of the pixel driving circuits of each row, thereby improving the display effect of the display panel.

[0026] Of course, any product implementing the present invention does not necessarily need to achieve all of the technical effects described above at the same time.

[0027] Further features and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments of the present invention with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0029] Figure 1 Shown is a schematic diagram of a display panel in the prior art;

[0030] Figure 2 Shown is a schematic diagram of a display panel provided in an embodiment of the present application;

[0031] Figure 3 FIG. 1 is a schematic diagram of a pixel driving circuit provided in an embodiment of the present application;

[0032] Figure 4 Another schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0033] Figure 5 FIG. 1 is a driving timing diagram of a display panel driving method provided in an embodiment of the present application;

[0034] Figure 6 Another schematic diagram of a pixel driving circuit provided in an embodiment of the present application is shown;

[0035] Figure 7 FIG. 2 is another driving timing diagram of a driving method for a display panel provided in an embodiment of the present application;

[0036] Figure 8 Another schematic diagram of a pixel driving circuit provided in an embodiment of the present application is shown;

[0037] Fig. 9 Shown is a schematic diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present invention unless otherwise specifically stated.

[0039] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

[0040] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0041] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0042] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0043] In the prior art, when display products are displayed at low frequencies, and in order to ensure that the borders of display products are small enough, some gate drive circuits are often designed as one-drive-multiple, such as one-drive-two design; however, when display products adopt one-drive-multiple design, the problem of interlaced bright and dark lines is prone to occur, affecting the user experience. Therefore, it is urgent to provide a method that can improve the problem of bright and dark lines on the screen of a display device.

[0044] For example, Figure 1 The figure shows a schematic diagram of a display panel in the prior art. Figure 1 In the prior art, when the pixel driving circuit adopts a one-drive-two design, after SP1 is turned on to write data, SP2 is turned on to write data in the next row, and then S2 is turned off. This results in a waiting time of one row after the N1 node in the SP1 row pixel circuit completes Vth compensation. During this time, S2 is in the on state. Since the N2 node potential is data at the previous moment, the N1 node potential is less than and close to (data-|Vth|); since the N2 node has parasitic capacitance, the N2 node potential will continue to leak to the N1 node, so that the potential of the N1 node is further increased. However, S2 is turned off soon after the SP2 row pixel circuit writes data, and the N2 node potential in the SP2 row pixel circuit does not leak to the N1 node for a long time, resulting in the N1 node potential in the SP2 row pixel circuit being lower than the N1 node potential in the SP1 row pixel circuit. Therefore, when the display panel displays the picture, the SP1 row is dark and the SP2 row is bright, that is, there is a problem of interlaced bright and dark lines. Especially for wearable products, where one line lasts for 30 to 50 us, leakage current will be more obvious, making the bright and dark lines on the display more obvious.

[0045] In view of this, the present invention provides a display panel and a driving method thereof, and a display device, so as to solve the problem of bright and dark lines appearing on the screen of the display device in the prior art.

[0046] Figure 2 FIG. 1 is a schematic diagram of a display panel provided in an embodiment of the present application. Figure 3 FIG. 1 is a schematic diagram of a pixel driving circuit provided in an embodiment of the present application. Figure 4 FIG. 1 is another schematic diagram of a display panel provided in an embodiment of the present application. Figure 5FIG. 1 is a driving timing diagram of a display panel driving method provided in an embodiment of the present application; please refer to FIG. Figure 2-Figure 5 , the present application provides a method for driving a display panel, wherein the display panel 100 includes a display area 20 and a non-display area 10 surrounding the display area 20;

[0047] The display panel 100 includes a first gate driving circuit 110, a second gate driving circuit 120 and a third gate driving circuit 130 located in a non-display area 10, wherein the first gate driving circuit 110 includes a plurality of first gate driving units 11 connected in cascade, the second gate driving circuit 120 includes a plurality of second gate driving units 12 connected in cascade, and the third gate driving circuit 130 includes a plurality of third gate driving units 13 connected in cascade;

[0048] It also includes a plurality of pixel driving circuits 21 located in the display area 20, such as Figure 3 As shown, the pixel driving circuit 21 includes:

[0049] A first switch module 30, wherein a first end of the first switch module 30 is electrically connected to a first node N1, a second end of the first switch module 30 is electrically connected to a first reference voltage end Vref1, and a control end of the first switch module 30 is electrically connected to a first circuit control end S1N1;

[0050] A data writing module 40, wherein a first end of the data writing module 40 is electrically connected to the data signal end Data, a second end of the data writing module 40 is electrically connected to the second node N2, and a control end of the data writing module 40 is electrically connected to the scan signal end SP1 / SP2;

[0051] A second switch module 30, wherein a first end of the second switch module 30 is electrically connected to the first node N1, a second end of the second switch module 30 is electrically connected to the third node N3, and a control end of the second switch module 30 is electrically connected to the second circuit control end S2N1;

[0052] Each first gate driving unit 11 is electrically connected to the first circuit control terminal S1N1 of the adjacent N rows of pixel driving circuits 21, each second gate driving unit 12 is electrically connected to the second circuit control terminal S2N1 of the adjacent N rows of pixel driving circuits 21, and each third gate driving unit 13 is electrically connected to the scan signal terminal SP1 / SP2 of one row of pixel driving circuits 21;

[0053] Wherein, N ≥ 2, and N is a positive integer;

[0054] The driving method of the display panel 100 includes:

[0055] Within a frame scanning time, in the N adjacent rows of pixel driving circuits 21, a first time period (B) is included between the end point at which the scanning signal terminal SP1 / SP2 of the N-th row pixel driving circuit 21 receives the scanning driving signal transmitted by the third gate driving unit 13 and the end point at which the second circuit control terminal S2N1 of the N-th row pixel driving circuit 21 receives the driving signal transmitted by the second gate driving unit 12; the first time period (B) is used for all charges of the second node N2 in the N-th row pixel driving circuit 21 to leak to the first node N1 in the N-th row pixel driving circuit 21.

[0056] Please continue to refer to Figure 2-Figure 5 Specifically, the driving method of the display panel 100 provided in the present application is for Figure 2 , Figure 4 The display panel 100 shown in the figure includes a display area 20 and a non-display area 10, and the non-display area 10 is arranged around the display area 20; wherein, the first gate driving circuit 110, the second gate driving circuit 120 and the third gate driving circuit 130 arranged in the non-display area 10 are included, and the first gate driving circuit 110, the second gate driving circuit 120 and the third gate driving circuit 130 are all used to transmit corresponding driving signals to each row of pixel driving circuits 21 arranged in the display area 20. Specifically, each gate driving circuit includes a plurality of cascade-connected gate driving units, that is, the first gate driving circuit 110 includes a plurality of cascade-connected first gate driving units 11, the second gate driving circuit 120 includes a plurality of cascade-connected second gate driving units 12, and the third gate driving circuit 130 includes a plurality of cascade-connected third gate driving units 13; such an arrangement enables the driving signal to be transmitted downward one level at a time between the gate driving units, so as to realize the scanning drive of the pixel driving circuits 21 one row at a time.

[0057] Please refer to Figure 3Each pixel driving circuit 21 includes a first switch module 30, a data writing module 40, and a second switch module 30, wherein the first switch module 30 includes a fourth transistor M4, a first end of the fourth transistor M4 is electrically connected to the first node N1 in the pixel driving circuit 21, a second end is electrically connected to the first reference voltage end Vref1, and a control end is electrically connected to the first circuit control end S1N1; the first circuit control end S1N1 is used to control the opening or closing of the first switch module 30 (fourth transistor M4), when the first switch module 30 is in the opening state, the electrical signal received by the first reference voltage end Vref1 can be transmitted to the first node N1 through the first switch module 30. The data writing module 40 includes a second transistor M2, a first end of the second transistor M2 is electrically connected to the data signal end Data, a second end is electrically connected to the second node N2 in the pixel driving circuit 21, and a control end is electrically connected to the scanning signal end SP1 / SP2; the scanning signal end SP1 / SP2 is used to transmit an electrical signal to the data writing module 40, so as to control the opening or closing of the data writing module 40. When the data writing module 40 is in the opening state, the electrical signal received by the data signal end Data can be transmitted to the first node N1 through the first switch module 30. The second switch module 30 includes a fifth transistor M5, a first end of the fifth transistor M5 is also electrically connected to the first node N1 in the pixel driving circuit 21, a second end is electrically connected to the third node N3 in the pixel driving circuit 21, and a control end is electrically connected to the second circuit control end S2N1; wherein the second circuit control end S2N1 is used to control the opening or closing of the second switch module, and when the second switch module 30 is in the opening state, the potential of the third node N3 is also transmitted to the first node N1.

[0058] In which, the present application sets each first gate driving unit 11 in the display panel 100 to be electrically connected to the first circuit control terminal S1N1 in the adjacent multi-row pixel driving circuit 21, so as to transmit an electrical signal to the first circuit control terminal S1N1 in the multi-row pixel driving circuit 21 through one first gate driving unit 11; and sets each second gate driving unit 12 in the display panel 100 to be electrically connected to the adjacent multi-row pixel driving circuit 21 correspondingly electrically connected to each first gate driving unit 11, specifically, the second gate driving unit 12 is electrically connected to the second circuit control terminal S2N1 in the multi-row pixel driving circuit 21, so as to transmit an electrical signal to the second circuit control terminal S2N1 in the multi-row pixel driving circuit 21 through one second gate driving unit 12; and sets each third gate driving unit 13 in the display panel 100 to be electrically connected to the scanning signal terminal SP1 / SP2 in the corresponding 1-row pixel driving circuit 21, so as to transmit an electrical signal to the scanning signal terminal SP1 / SP2 in each row of pixel driving circuit 21 row by row through the third gate driving unit 13.

[0059] like Figure 2 As shown, the present application provides an optional embodiment, in which the first gate driving unit 11 and the second gate driving unit 12 are both electrically connected to two rows of pixel driving circuits 21, that is, the case of N=2, and the third gate driving unit 13 is still arranged with a row of pixel driving circuits 21. Based on this, the present application provides a driving method for a display panel 100, in which, in two adjacent rows of pixel driving circuits 21 within a frame scanning time, the scanning signal terminal SP1 / SP2 in the second row of pixel driving circuits 21 in the two rows of pixel driving circuits 21 is arranged to include a first time period (B) between the end point of receiving the scanning driving signal transmitted by the third gate driving unit 13 and the end point of receiving the driving signal transmitted by the second gate driving unit 12 by the second circuit control terminal S2N1 in the second row of pixel driving circuits 21, and the first time period (B) is arranged for the second row of pixel driving circuits 21 in the two rows of pixel driving circuits 21. The charges of the second node N2 can all leak to the first node N1 in the second row of pixel driving circuits 21, so that the potential of the first node N1 in the first row of pixel driving circuits 21 in the two rows of pixel driving circuits 21 is the same as the potential of the first node N1 in the second row of pixel driving circuits 21 in the two rows of pixel driving circuits 21, thereby avoiding the situation where the potentials finally transmitted to the light-emitting elements in the pixel driving circuits 21 are different, and making the potentials transmitted to the corresponding light-emitting elements by the two adjacent rows of pixel driving circuits 21 the same, thereby driving the light-emitting elements to have the same brightness, avoiding the occurrence of bright and dark lines, and improving the display effect of the display panel 100.

[0060] That is, the present application adjusts the driving timing so that S2N1 will not be turned off until a period of time (first time period B) has passed after the second row of pixel driving circuits 21 in the two rows of pixel driving circuits 21 has written data, and can make all the charges of the second node N2 leak to the first node N1 within the first time period (B), so that the potential of the first node N1 in the second row of pixel driving circuits 21 can be increased like the potential of the first node N1 in the first row of pixel driving circuits 21, thereby avoiding the problem of bright and dark lines between alternate rows and making the picture display of the display panel 100 more uniform.

[0061] In addition, if Figure 4As shown, the present application provides an optional embodiment, that is, the first gate driving unit 11 and the second gate driving unit 12 are both electrically connected to three rows of pixel driving circuits 21, that is, N=3, and the third gate driving unit 13 is still set with one row of pixel driving circuits 21. Based on this, the present application provides a driving method of a display panel 100, that is, in one frame scanning time, in the three adjacent rows of pixel driving circuits 21, the scanning signal terminal SP1 / SP2 in the third row of pixel driving circuits 21 in the three rows of pixel driving circuits 21 is set to include a first time period (B) between the end point of receiving the scanning driving signal transmitted by the third gate driving unit 13 and the end point of receiving the driving signal transmitted by the second gate driving unit 12 by the second circuit control terminal S2N1 in the third row of pixel driving circuits 21, and the first time period (B) is set for the charge of the second node N2 in the third row of pixel driving circuits 21 in the three rows of pixel driving circuits 21 to be able to drain Flows to the first node N1 in the third row of pixel driving circuits 21, so that the potential of the first node N1 in the first row of pixel driving circuits 21 among the three rows of pixel driving circuits 21, the potential of the first node N1 in the second row of pixel driving circuits 21, and the potential of the first node N1 in the third row of pixel driving circuits 21 among the three rows of pixel driving circuits 21 are the same, avoiding the situation where the potentials finally transmitted to the light-emitting elements in the pixel driving circuits 21 are different, so that the potentials transmitted to the corresponding light-emitting elements by the three adjacent rows of pixel driving circuits 21 are the same, thereby driving the light-emitting elements to have the same brightness, avoiding the occurrence of bright and dark lines, and improving the display effect of the display panel 100.

[0062] It should be added that when the first gate driving unit 11 and the second gate driving unit 12 are both electrically connected to the three adjacent rows of pixel driving circuits 21, there is a risk that the charge of the second node N2 in the third row of pixel driving circuits 21 cannot be completely leaked to the first node N1. Therefore, the first time period (B) is increased so that the charge of the second node N2 in the third row of pixel driving circuits 21 can all leak to the first node N1 in the third row of pixel driving circuits 21. The technical effect that the potential of the first node N1 in the third row of pixel driving circuits 21 can be increased as well as the potential of the first node N1 in the first row of pixel driving circuits 21 and the second row of pixel driving circuits 21 can be increased, thereby avoiding the problem of bright and dark lines and making the picture display of the display panel 100 more uniform.

[0063] It should be noted that N=2 and N=3 listed in the above examples of the present application are only optional embodiments of the present application. The present application does not specifically limit the value range of N. As long as a first time period (B) of the Nth row in the Nth row of adjacently arranged pixel driving circuits 21 in which the first gate driving unit 11 and the second gate driving unit 12 are electrically connected is added in the timing, the charges of the second node N2 in the Nth row of pixel driving circuits 21 can all be leaked to the first node N1 in the Nth row of pixel driving circuits 21, and the technical effect of increasing the potential of the first node N1 in the Nth row of pixel driving circuits 21 can be achieved, as well as the potential of the first node N1 in the 1st to N-1th row of pixel driving circuits 21, thereby avoiding the problem of bright and dark lines and making the picture display of the display panel 100 more uniform.

[0064] It should be supplemented that the "scanning signal terminal SP1" refers to the scanning signal terminal in the pixel driving circuit of the first row in two adjacent rows of pixel driving circuits 21, and the "scanning signal terminal SP2" refers to the scanning signal terminal in the pixel driving circuit of the second row in two adjacent rows of pixel driving circuits 21.

[0065] Please continue to refer to Figure 2-Figure 5 Optionally, within one frame scanning time, a second time period is included between the end point at which the scanning signal terminal SP1 / SP2 of the pixel driving circuit 21 of the first row receives the scanning driving signal transmitted by the third gate driving unit 13 and the end point at which the scanning signal terminal SP1 / SP2 of the pixel driving circuit 21 of the Nth row receives the scanning driving signal transmitted by the third gate driving unit 13; the duration of the second time period is A, and the duration of the first time period is B;

[0066] Among them, A<B.

[0067] Specifically, take the example that each of the first gate driving circuit 110 and the second gate driving circuit 120 is electrically connected to two adjacent rows of pixel driving circuits 21; the end point at which the scanning signal terminal SP1 / SP2 of the first row of pixel driving circuits 21 receives the scanning driving signal transmitted by the third gate driving unit 13 and the end point at which the scanning signal terminal SP1 / SP2 of the second row of pixel driving circuits 21 receives the scanning driving signal transmitted by the third gate driving unit 13 include a second time period (A), where the duration of the second time period is A and the duration of the aforementioned first time period is B for illustration; the present application provides an optional setting method, in which the duration A of the second time period is set to be less than the duration B of the first time period.

[0068] Among them, the duration B of the first time period is the time when the charge of the second node N2 in the pixel driving circuit 21 for the second row can be completely leaked to the first node N1; the sum of the duration B of the first time period and the duration A of the second time period is the time when the charge of the second node N2 in the pixel driving circuit 21 for the first row can be completely leaked to the first node N1. It should be added that the charge of the second node N2 in the pixel driving circuit 21 for the first row can be completely leaked to the first node N1 without using the entire duration A+B.

[0069] The present application sets the duration B of the first time period to be longer, so as to ensure that the charge of the second node N2 is completely leaked to the first node N1 within the first time period B, so that the potential of the first node N1 in the second row pixel driving circuit 21 can be increased like the potential of the first node N1 in the first row pixel driving circuit 21, thereby avoiding the problem of interlaced bright and dark lines, and making the picture display of the display panel 100 more uniform.

[0070] Please continue to refer to Figure 2-Figure 5 Optionally, the pixel driving circuit 21 further includes:

[0071] a driving transistor M3, wherein a gate of the driving transistor M3 is electrically connected to the first node N1, a first electrode of the driving transistor M3 is electrically connected to the second node N2, and a second electrode of the driving transistor M3 is electrically connected to a third node N3;

[0072] The duration of the first time period is B, B = Q / Iv;

[0073] Among them, Q=|Vth|*C1, Q is the amount of charge stored in the second node N2 relative to the potential of the first node N1, Vth is the threshold voltage of the driving transistor M3, C1 is the parasitic capacitance of the second node N2; Iv is the current passing through the driving transistor M3 when the threshold voltage compensation of the driving transistor M3 is completed.

[0074] Specifically, the pixel driving circuit 21 provided in the present application includes a driving transistor M3, which is configured such that its gate is electrically connected to the first node N1, the first electrode is electrically connected to the second node N2, and the second electrode is electrically connected to the third node N3; the electric signal transmitted from the first node N1 to the gate terminal of the driving transistor M3 is used to control the on and off of the driving transistor M3, and when the driving transistor M3 is in the on state, the electric signal at the second node N2 can be transmitted to the third node N3 side. Among them, the voltage of the first reference voltage terminal Vref1 can transmit the first reference voltage to the control terminal of the driving transistor M3 through the first switch module 30 when the first switch module 30 is in the on state, and the electric signal transmitted from the first reference voltage terminal Vref1 to the control terminal of the driving transistor M3 can be used to reset the control terminal of the driving transistor M3 to prevent the voltage at the control terminal of the driving transistor M3 from affecting the display of the next frame when the previous frame is displayed.

[0075] The present application provides a method for calculating the duration B of the first time period (the time required for all the charges at the second node N2 to leak to the first node N1) in a driving method, B=Q / Iv=|Vth|*C1 / Iv. The duration B of the first time period is calculated in this way, so that the time length for the charges at the second node N2 in the pixel driving circuit 21 of the Nth row to completely leak to the first node N1 can be adjusted in the driving method, so that the potential of the first node N1 in the pixel driving circuit 21 of the Nth row can be increased as well as the potential of the first node N1 in the pixel driving circuit 21 of the 1st to N-1th rows, thereby avoiding the problem of bright and dark lines when the display panel 100 displays the picture, and making the picture display of the display panel 100 more uniform.

[0076] An embodiment is provided here, in which the parasitic capacitance of the second node N2 is generally 3 to 5fF, and the time from SP1 closing to SP2 closing is A, which is the time of one line. For a watch, the duration of A is usually 30 to 50us. When SP1 is closed, N1≤data-|Vth|, and the difference with N2≥|Vth|, taking the minimum value |Vth|. The TFT current when Vth compensation is completed is about Iv=0.1nA. The time required for all the charges of N2 to flow to N1 is B, and the amount of charge stored in N2 relative to the potential of N1 is Q=|Vth|*C2; B=Q / Iv=|Vth|*C2 / Iv=(3~5f)*|Vth| / 0.1n=(30~50)*|Vth|(us); |Vth| is usually -2~-3.5V, so the minimum value of B should be greater than 60~165us.

[0077] Please refer to Figure 5 Optionally, the first time period (B) and the second time period (A) are within the time when the second switch module 30 is in the on state.

[0078] Specifically, please combine Figure 2-Figure 4 Reference Figure 5 In the pixel driving circuit 21, the first end of the second switch module 30 is electrically connected to the first node N1, the second end of the second switch module 30 is electrically connected to the third node N3, and the control end of the second switch module 30 is electrically connected to the second circuit control end S2N1; in the driving method, the second circuit control end S2N1 controls the second switch module 30 to be turned on for a relatively long time, and the first time period B and the second time period A are set. Both of these time periods are located within the time period when the second switch module 30 is turned on, so that the potential at the second node N2 in each row of the pixel driving circuit 21 can leak to the first node N1 during the first time period (B) and the second time period (A), and complete leakage is achieved, so that the potential of the first node N1 in the pixel driving circuit 21 of the Nth row can also be improved like the potential of the first node N1 in the pixel driving circuit 21 of the 1st to N-1th rows, thereby avoiding the problem of bright and dark lines when the display panel 100 displays the picture, and making the picture display of the display panel 100 more uniform.

[0079] Figure 6 FIG. 2 is another schematic diagram of a pixel driving circuit provided in an embodiment of the present application. Figure 7 FIG. 1 is another driving timing diagram of the driving method of the display panel provided in the embodiment of the present application. Please refer to FIG. Figure 2 , Figure 4-Figure 7 Optionally, the pixel driving circuit 21 further includes a bias adjustment module 60, a first end of the bias adjustment module 60 is electrically connected to the first pulse signal end DVH, a second end of the bias adjustment module 60 is electrically connected to the second node N2, and a control end of the bias adjustment module 60 is electrically connected to the fourth circuit control end S3;

[0080] The drive methods include:

[0081] In one frame scanning time, the bias adjustment module 60 is turned on twice.

[0082] Specifically, the present application provides a setting method of a pixel driving circuit 21, wherein the pixel driving circuit 21 includes a bias adjustment module 60, wherein the bias adjustment module 60 includes an eighth transistor M8, wherein the first end of the eighth transistor M8 is electrically connected to the first pulse signal end DVH, and the second end is electrically connected to the second node N2, wherein the control end of the eighth transistor M8 is electrically connected to the fourth circuit control end S3, and during the operation of the pixel driving circuit 21, the bias adjustment module 60 is controlled to be turned on twice within a frame scanning time (1frame); that is, the fourth circuit control end S3 is used to control the bias adjustment module 60 (eighth transistor M8) to be turned on twice within a frame scanning time. When the bias adjustment module 60 is in the turned-on state, the bias adjustment signal is transmitted to the second node N2 to control the charge of the second node N2 to be lower than the potential of the third node N3, so as to adjust the bias state of the driving transistor M3. This is used to improve the threshold drift problem of the driving transistor M3 due to the hysteresis effect, and can be applied to the display panel 100 to improve the influence of the driving transistor M3 on the display effect due to the hysteresis effect.

[0083] Please continue to refer to Figure 2 , Figure 4-Figure 7 Optionally, within one frame scanning time, the bias adjustment module 60 is turned on for the first time before the first switch module 30 is turned on, and the bias adjustment module 60 is turned on for the second time after the second switch module 30 is turned off.

[0084] Specifically, within one frame scanning time, the bias adjustment module 60 is turned on twice, wherein the first time period when the bias adjustment module 60 is turned on is all before the first switch module 30 is turned on, and the second time period when the bias adjustment module 60 is turned on is all after the second switch module 30 is turned off; that is, correspondingly, the first bias adjustment stage is set before the gate reset stage and the data writing stage, and the potential of the first node N1 is negative in the first bias adjustment stage, and the voltage difference between the first node N1 and the third node N3 is large in this stage; the second bias adjustment stage is set after the data writing stage, and the potential of the first node N1 is the written data voltage in the second bias adjustment stage, and the voltage difference between the first node N1 and the third node N3 is relatively small. Although the voltage difference between the first node N1 and the third node N3 is different in the first bias adjustment stage and the second bias adjustment stage, the bias adjustment module 60 provided in the present application can be used to transmit the bias adjustment signal to the second node N2 to control the charge of the second node N2 to be lower than the potential of the third node N3, so as to adjust the bias state of the driving transistor M3; to improve the threshold drift problem of the driving transistor M3 caused by the hysteresis effect, and to be applied in the display panel 100 to improve the influence of the driving transistor M3 on the display effect due to the hysteresis effect.

[0085] Please refer to Figure 2-Figure 4 Based on the same inventive concept, the present application also provides a display panel 100, the display panel 100 includes a display area 20 and a non-display area 10 surrounding the display area 20;

[0086] The display panel 100 includes a first gate driving circuit 110, a second gate driving circuit 120 and a third gate driving circuit 130 located in a non-display area 10, wherein the first gate driving circuit 110 includes a plurality of first gate driving units 11 connected in cascade, the second gate driving circuit 120 includes a plurality of second gate driving units 12 connected in cascade, and the third gate driving circuit 130 includes a plurality of third gate driving units 13 connected in cascade;

[0087] The display device further includes a plurality of pixel driving circuits 21 located in the display area 20. The pixel driving circuits 21 include:

[0088] A first switch module 30, wherein a first end of the first switch module 30 is electrically connected to a first node N1, a second end of the first switch module 30 is electrically connected to a first reference voltage end Vref1, and a control end of the first switch module 30 is electrically connected to a first circuit control end S1N1;

[0089] A data writing module 40, wherein a first end of the data writing module 40 is electrically connected to the data signal end Data, a second end of the data writing module 40 is electrically connected to the second node N2, and a control end of the data writing module 40 is electrically connected to the scan signal end SP1 / SP2;

[0090] A second switch module 30, wherein a first end of the second switch module 30 is electrically connected to the first node N1, a second end of the second switch module 30 is electrically connected to the third node N3, and a control end of the second switch module 30 is electrically connected to the second circuit control end S2N1;

[0091] Among them, each first gate driving unit 11 is electrically connected to the first circuit control terminal S1N1 in the adjacent N rows of pixel driving circuits 21, each second gate driving unit 12 is electrically connected to the second circuit control terminal S2N1 in the adjacent N rows of pixel driving circuits 21, and each third gate driving unit 13 is electrically connected to the scanning signal terminal SP1 / SP2 in 1 row of pixel driving circuits 21; wherein N≥2, and N is a positive integer.

[0092] Specifically, the display panel 100 provided in the present application includes a display area 20 and a non-display area 10, and the non-display area 10 is arranged around the display area 20; wherein, the display panel 100 includes a first gate driving circuit 110, a second gate driving circuit 120 and a third gate driving circuit 130 arranged in the non-display area 10, and the first gate driving circuit 110, the second gate driving circuit 120 and the third gate driving circuit 130 are all used to transmit corresponding driving signals to each row of pixel driving circuits 21 arranged in the display area 20. Specifically, each gate driving circuit includes a plurality of cascade-connected gate driving units, that is, the first gate driving circuit 110 includes a plurality of cascade-connected first gate driving units 11, the second gate driving circuit 120 includes a plurality of cascade-connected second gate driving units 12, and the third gate driving circuit 130 includes a plurality of cascade-connected third gate driving units 13; such an arrangement enables the driving signal to be transmitted downward one level at a time between the gate driving units, so as to realize the scanning drive of the pixel driving circuits 21 one row at a time.

[0093] Each pixel driving circuit 21 includes a first switch module 30, a data writing module 40, and a second switch module 30, wherein the first end of the first switch module 30 is electrically connected to the first node N1 in the pixel driving circuit 21, the second end is electrically connected to the first reference voltage end Vref1, and the control end is electrically connected to the first circuit control end S1N1; the first circuit control end S1N1 is used to control the opening or closing of the first switch module 30, when the first switch module 30 is in the opening state, the electric signal received by the first reference voltage end Vref1 can be transmitted to the first node N1 through the first switch module 30. The first end of the data writing module 40 is electrically connected to the data signal end Data, the second end is electrically connected to the second node N2 in the pixel driving circuit 21, and the control end is electrically connected to the scanning signal end SP1 / SP2; the scanning signal end SP1 / SP2 is used to transmit an electric signal to the data writing module 40 to control the opening or closing of the data writing module 40, when the data writing module 40 is in the opening state, the electric signal received by the data signal end Data can be transmitted to the first node N1 through the first switch module 30. The first end of the second switch module 30 is also electrically connected to the first node N1 in the pixel driving circuit 21, the second end is electrically connected to the third node N3 in the pixel driving circuit 21, and the control end is electrically connected to the second circuit control end S2N1; wherein, the second circuit control end S2N1 is used to regulate the opening or closing of the second switch module, and when the second switch module 30 is in the on state, the potential of the third node N3 will also be transmitted to the first node N1.

[0094] In which, the present application sets each first gate driving unit 11 in the display panel 100 to be electrically connected to the first circuit control terminal S1N1 in the adjacent multi-row pixel driving circuit 21, so as to transmit an electrical signal to the first circuit control terminal S1N1 in the multi-row pixel driving circuit 21 through one first gate driving unit 11; and sets each second gate driving unit 12 in the display panel 100 to be electrically connected to the adjacent multi-row pixel driving circuit 21 correspondingly electrically connected to each first gate driving unit 11, specifically, the second gate driving unit 12 is electrically connected to the second circuit control terminal S2N1 in the multi-row pixel driving circuit 21, so as to transmit an electrical signal to the second circuit control terminal S2N1 in the multi-row pixel driving circuit 21 through one second gate driving unit 12; and sets each third gate driving unit 13 in the display panel 100 to be electrically connected to the scanning signal terminal SP1 / SP2 in the corresponding 1-row pixel driving circuit 21, so as to transmit an electrical signal to the scanning signal terminal SP1 / SP2 in each row of pixel driving circuit 21 row by row through the third gate driving unit 13.

[0095] The present application provides an optional embodiment in which the first gate driving unit 11 and the second gate driving unit 12 are both electrically connected to two rows of pixel driving circuits 21, that is, N=2, and the third gate driving unit 13 is still configured with one row of pixel driving circuits 21.

[0096] In addition, the present application also provides an optional embodiment in which the first gate driving unit 11 and the second gate driving unit 12 are both electrically connected to three rows of pixel driving circuits 21, that is, N=3, and the third gate driving unit 13 is still set with one row of pixel driving circuits 21.

[0097] It should be noted that the N=2 and N=3 cited above in the present application are merely optional embodiments of the present application, and the present application does not make any specific limitation on the value range of N.

[0098] Please continue to refer to Figure 2-Figure 4 Optionally, the pixel driving circuit 21 further includes:

[0099] The driving transistor M3 has a gate electrically connected to the first node N1 , a first electrode electrically connected to the second node N2 , and a second electrode electrically connected to the third node N3 .

[0100] Specifically, the pixel driving circuit 21 provided in the present application includes a driving transistor M3, which is configured such that its gate is electrically connected to the first node N1, the first electrode is electrically connected to the second node N2, and the second electrode is electrically connected to the third node N3; the electric signal transmitted from the first node N1 to the gate terminal of the driving transistor M3 is used to control the on and off of the driving transistor M3, and when the driving transistor M3 is in the on state, the electric signal at the second node N2 can be transmitted to the third node N3 side. Among them, the voltage of the first reference voltage terminal Vref1 can transmit the first reference voltage to the control terminal of the driving transistor M3 through the first switch module 30 when the first switch module 30 is in the on state, and the electric signal transmitted from the first reference voltage terminal Vref1 to the control terminal of the driving transistor M3 can be used to reset the control terminal of the driving transistor M3 to prevent the voltage at the control terminal of the driving transistor M3 from affecting the display of the next frame when the previous frame is displayed.

[0101] Please refer to Figure 2 , Figure 4 and Figure 6 Optionally, the pixel driving circuit 21 also includes a bias adjustment module 60, a first end of the bias adjustment module 60 is electrically connected to the first pulse signal terminal DVH, a second end of the bias adjustment module 60 is electrically connected to the second node N2, and a control end of the bias adjustment module 60 is electrically connected to the fourth circuit control terminal S3.

[0102] Specifically, the present application provides a setting method of a pixel driving circuit 21, wherein the pixel driving circuit 21 includes a bias adjustment module 60, wherein a first end of the bias adjustment module 60 is electrically connected to a first pulse signal end DVH, a second end is electrically connected to a second node N2, and a control end of the bias adjustment module 60 is electrically connected to a fourth circuit control end S3. When the bias adjustment module 60 is in an on state, it can transmit a bias adjustment signal to the second node N2 to control the charge of the second node N2 to be lower than the potential of the third node N3, so as to adjust the bias state of the driving transistor M3, so as to improve the threshold drift problem of the driving transistor M3 due to the hysteresis effect, and can be applied in the display panel 100 to improve the influence of the driving transistor M3 on the display effect due to the hysteresis effect.

[0103] Figure 8 FIG. 1 is another schematic diagram of a pixel driving circuit provided in an embodiment of the present application. Figure 2 and Figure 8 Optionally, the pixel driving circuit 21 further includes a reset module 70,

[0104] A first end of the reset module 70 is electrically connected to the second reference voltage end Vref2 , a second end of the reset module 70 is electrically connected to the fourth node, and a control end of the reset module 70 is electrically connected to the fourth circuit control end S3 .

[0105] Specifically, in the pixel driving circuit 21 provided in the present application, the reset module 70 includes a seventh transistor M7, a first end of the seventh transistor M7 is electrically connected to the second reference voltage end Vref2, a second end is electrically connected to the fourth node, and a control end of the seventh transistor M7 is electrically connected to the fourth circuit control end S3. The fourth circuit control end S3 is used to transmit an electrical signal to the control end of the reset module 70 to adjust the reset module 70 to be in an on state or a off state. When the reset module 70 is in an on state, the second reference voltage received by the second reference voltage end Vref2 can be transmitted to the fourth node through the reset module 70, thereby being used to reset the light-emitting element.

[0106] Please refer to Figure 2 and Figure 8 Optionally, the pixel driving circuit 21 further includes:

[0107] A first power signal terminal PVDD and a second power signal terminal PVEE;

[0108] A light emitting element D1, wherein an anode of the light emitting element D1 is electrically connected to a fourth node N4, and a cathode of the light emitting element D1 is electrically connected to a second power signal terminal PVEE;

[0109] The light emitting control module 80, the light emitting control module 80, the driving transistor M3 and the light emitting element D1 are connected in series between the first power signal terminal PVDD and the second power signal terminal PVEE;

[0110] The storage module C1 has a first terminal electrically connected to the first power signal terminal PVDD, and a second terminal electrically connected to the first node N1.

[0111] Specifically, since the anode of the light-emitting element D1 is electrically connected to the fourth node N4, when the reset module 70 is in the on state, the second reference voltage received by the second reference voltage terminal Vref2 can be transmitted to the fourth node N4 through the reset module 70, thereby being used to reset the anode of the light-emitting element D1 to prevent the light-emitting element D1 from lighting up secretly, thereby avoiding affecting the display effect when applied.

[0112] The pixel driving circuit 21 also includes a light emitting control module 80. The light emitting control module 80, the driving transistor M3 and the light emitting element D1 are connected in series between the first power signal terminal PVDD and the second power signal terminal PVEE to control whether the driving current flows through the light emitting element D1.

[0113] The pixel driving circuit 21 also includes a storage module C1, a first end of the storage module C1 is electrically connected to the first power signal end PVDD, and a second end is electrically connected to the first node N1. The storage module C1 is used to maintain the potential of the first node N1 during the light-emitting stage to ensure that the first node N1 continuously provides a valid level signal to the control end of the driving transistor M3 during the light-emitting stage to control the conduction between the first end and the second end of the driving transistor M3.

[0114] Please continue to refer to Figure 2 and Figure 8 , Optionally, the light control module 80 includes a first light control module 801 and a second light control module 802;

[0115] A first end of the first light emitting control module 801 is electrically connected to the first power signal end PVDD, a second end of the first light emitting control module 801 is electrically connected to the second node N2, and a control end of the first light emitting control module 801 is electrically connected to the light emitting control signal end Emit;

[0116] A first end of the second light emitting control module 802 is electrically connected to a third node N3 , a second end of the second light emitting control module 802 is electrically connected to a fourth node N4 , and a control end of the second light emitting control module 802 is electrically connected to a light emitting control signal end Emit.

[0117] Specifically, in the pixel driving circuit 21 provided in the present application, the light-emitting control module 80 may simultaneously include a first light-emitting control module 801 and a second light-emitting control module 802, wherein the first light-emitting control module 801 includes a first transistor M1, a first end of the first transistor M1 is configured to be electrically connected to the first power signal terminal PVDD, a second end is electrically connected to the second node N2, and a control end of the first transistor M1 is electrically connected to the light-emitting control signal terminal Emit; the second light-emitting control module 802 includes a sixth transistor M6, a first end of the sixth transistor M6 is electrically connected to the third node N3, a second end is electrically connected to the fourth node N4, and a control end of the sixth transistor M6 is electrically connected to the light-emitting control signal terminal Emit.

[0118] When the pixel driving circuit 21 operates in the light-emitting stage, the first light-emitting control module 801 and the second light-emitting control module 802 cooperate to provide a driving current to the light-emitting element D1, wherein the first light-emitting control module 801, under the control of the signal of the light-emitting control signal terminal Emit, provides the signal of the first power supply signal terminal PVDD to the second node N2; the driving transistor M3, under the control of the gate (control terminal) voltage thereof, provides the voltage signal of the second node N2 to the third node N3; the second light-emitting control module 802, under the control of the signal of the light-emitting control signal terminal Emit, provides the voltage signal of the third node N3 to the electrode (anode) of the light-emitting element D1, so as to realize the driving current flowing through the light-emitting element D1 and control the light-emitting element D1 to emit light.

[0119] It should also be added that the control ends of the first light-emitting control module 801 and the second light-emitting control module 802 provided in the present application are electrically connected to the same light-emitting control signal end Emit, which is equivalent to the multiplexing of the light-emitting control signal end Emit, which can save the setting of the modules in the pixel driving circuit 21 and simplify the circuit structure.

[0120] The present application does not limit the control ends of the first light-emitting control module 801 and the second light-emitting control module 802 to be electrically connected to the same light-emitting control signal end Emit. It is also possible to select that the control end of the first light-emitting control module 801 is electrically connected to a first light-emitting control signal end Emit, and the control end of the second light-emitting control module 802 is electrically connected to a second light-emitting control signal end Emit, so as to realize separate control of the first light-emitting control module 801 and the second light-emitting control module 802, which is conducive to realizing the multiplexing of the first light-emitting control module 801 or the second light-emitting control module 802 in other working stages.

[0121] Fig. 9 FIG. 1 is a schematic diagram of a display device provided in an embodiment of the present application. Figure 2-Figure 8 Reference Fig. 9 Based on the same inventive concept, the present application also provides a display device 200, which includes a display panel 100, and the display panel 100 is any display panel 100 provided in the present application.

[0122] It should be noted that the embodiment of the display device 200 provided in the embodiment of the present application can refer to the embodiment of the display panel 100 described above, and will not be repeated. The display device 200 provided in the present application can be: a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a navigator, or any other product or component with a display function.

[0123] It can be seen from the above embodiments that the display panel and the driving method thereof, and the display device provided by the present invention achieve at least the following beneficial effects:

[0124] The present application provides a display panel and a driving method thereof, and a display device. The first gate driving circuit and the second gate driving circuit in the display panel are both designed as one-drive N-row pixel driving circuits, and the third gate driving circuit is designed as one-drive one-row pixel driving circuit. By setting in the driving method of the display panel that in a frame scanning time, in the adjacent N-row pixel driving circuits, a first time period is included between an end point at which a scanning signal end of the N-row pixel driving circuit receives a scanning driving signal transmitted by a third gate driving unit and an end point at which a second circuit control end of the N-row pixel driving circuit receives a driving signal transmitted by a second gate driving unit; the first time period is used for all charges of the second node in the N-row pixel driving circuit to leak to the first node in the N-row pixel driving circuit, and the first node therein is electrically connected to a driving transistor in the pixel driving circuit, so that the potentials of the first nodes of the pixel driving circuits in the 1st to Nth rows are the same, thereby avoiding the bright and dark line problem caused by different potentials of the first nodes of the pixel driving circuits of each row, thereby improving the display effect of the display panel.

[0125] Although some specific embodiments of the present invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that the above embodiments may be modified without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A method for driving a display panel, characterized in that: The display panel includes a display area and a non-display area surrounding the display area; The display panel comprises a first gate driving circuit, a second gate driving circuit and a third gate driving circuit located in the non-display area, the first gate driving circuit comprises a plurality of first gate driving units connected in cascade, the second gate driving circuit comprises a plurality of second gate driving units connected in cascade, and the third gate driving circuit comprises a plurality of third gate driving units connected in cascade; It also includes a plurality of pixel driving circuits located in the display area, the pixel driving circuits including: A first switch module, wherein a first end of the first switch module is electrically connected to a first node, a second end of the first switch module is electrically connected to a first reference voltage end, and a control end of the first switch module is electrically connected to a first circuit control end; A data writing module, wherein a first end of the data writing module is electrically connected to the data signal end, a second end of the data writing module is electrically connected to the second node, and a control end of the data writing module is electrically connected to the scan signal end; a second switch module, wherein a first end of the second switch module is electrically connected to the first node, a second end of the second switch module is electrically connected to a third node, and a control end of the second switch module is electrically connected to a second circuit control end; Each of the first gate driving units is electrically connected to the first circuit control terminal of the pixel driving circuits in N adjacent rows, each of the second gate driving units is electrically connected to the second circuit control terminal of the pixel driving circuits in N adjacent rows, and each of the third gate driving units is electrically connected to the scanning signal terminal of the pixel driving circuit in one row; wherein N≥2, and N is a positive integer; The driving method of the display panel includes: Within a frame scanning time, in the N adjacent rows of pixel driving circuits, a first time period is included between an end point at which the scanning signal end of the pixel driving circuit in the Nth row receives the scanning driving signal transmitted by the third gate driving unit and an end point at which the second circuit control end of the pixel driving circuit in the Nth row receives the driving signal transmitted by the second gate driving unit; the first time period is used for all charges of the second node in the pixel driving circuit in the Nth row to leak to the first node in the pixel driving circuit in the Nth row.

2. The method for driving a display panel according to claim 1, wherein: In a frame scanning time, a second time period is included between an end point at which the scanning signal end of the pixel driving circuit in the first row receives the scanning driving signal transmitted by the third gate driving unit and an end point at which the scanning signal end of the pixel driving circuit in the Nth row receives the scanning driving signal transmitted by the third gate driving unit; the duration of the second time period is A, and the duration of the first time period is B; Among them, A<B.

3. The method for driving a display panel according to claim 1, wherein: The pixel driving circuit further includes: a driving transistor, wherein a gate of the driving transistor is electrically connected to the first node, a first electrode of the driving transistor is electrically connected to the second node, and a second electrode of the driving transistor is electrically connected to the third node; The duration of the first time period is B, B=Q / Iv; Where, Q=|Vth| C1, Q is the amount of charge stored in the second node relative to the potential of the first node, Vth is the threshold voltage of the driving transistor, C1 is the parasitic capacitance of the second node; Iv is the current passing through the driving transistor when the threshold voltage of the driving transistor is compensated.

4. The method for driving a display panel according to claim 2, wherein: The first time period and the second time period are within the time when the second switch module is in the on state.

5. The method for driving a display panel according to claim 1, wherein: The pixel driving circuit further includes a bias adjustment module, a first end of the bias adjustment module is electrically connected to the first pulse signal end, a second end of the bias adjustment module is electrically connected to the second node, and a control end of the bias adjustment module is electrically connected to the fourth circuit control end; The driving method comprises: The bias adjustment module is turned on twice within one frame scanning time.

6. The method for driving a display panel according to claim 5, characterized in that: In one frame scanning time, the bias adjustment module is turned on for the first time before the first switch module is turned on, and the bias adjustment module is turned on for the second time after the second switch module is turned off.

7. A display panel driven by the display panel driving method according to any one of claims 1 to 6, characterized in that: The display panel includes a display area and a non-display area surrounding the display area; The display panel comprises a first gate driving circuit, a second gate driving circuit and a third gate driving circuit located in the non-display area, the first gate driving circuit comprises a plurality of first gate driving units connected in cascade, the second gate driving circuit comprises a plurality of second gate driving units connected in cascade, and the third gate driving circuit comprises a plurality of third gate driving units connected in cascade; It also includes a plurality of pixel driving circuits located in the display area, the pixel driving circuits including: A first switch module, wherein a first end of the first switch module is electrically connected to a first node, a second end of the first switch module is electrically connected to a first reference voltage end, and a control end of the first switch module is electrically connected to a first circuit control end; A data writing module, wherein a first end of the data writing module is electrically connected to the data signal end, a second end of the data writing module is electrically connected to the second node, and a control end of the data writing module is electrically connected to the scan signal end; a second switch module, wherein a first end of the second switch module is electrically connected to the first node, a second end of the second switch module is electrically connected to a third node, and a control end of the second switch module is electrically connected to a second circuit control end; Each of the first gate driving units is electrically connected to the first circuit control terminal of the pixel driving circuits in N adjacent rows, each of the second gate driving units is electrically connected to the second circuit control terminal of the pixel driving circuits in N adjacent rows, and each of the third gate driving units is electrically connected to the scanning signal terminal of the pixel driving circuit in one row; wherein N≥2, and N is a positive integer; Within a frame scanning time, in the N adjacent rows of pixel driving circuits, a first time period is included between an end point at which the scanning signal end of the pixel driving circuit in the Nth row receives the scanning driving signal transmitted by the third gate driving unit and an end point at which the second circuit control end of the pixel driving circuit in the Nth row receives the driving signal transmitted by the second gate driving unit; the first time period is used for all charges of the second node in the pixel driving circuit in the Nth row to leak to the first node in the pixel driving circuit in the Nth row.

8. The display panel according to claim 7, characterized in that: The pixel driving circuit further includes: A driving transistor, wherein a gate of the driving transistor is electrically connected to the first node, a first electrode of the driving transistor is electrically connected to the second node, and a second electrode of the driving transistor is electrically connected to the third node.

9. The display panel according to claim 7, characterized in that: The pixel driving circuit also includes a bias adjustment module, a first end of the bias adjustment module is electrically connected to the first pulse signal end, a second end of the bias adjustment module is electrically connected to the second node, and a control end of the bias adjustment module is electrically connected to the fourth circuit control end.

10. The display panel according to claim 9, characterized in that: The pixel driving circuit further includes a reset module. The first end of the reset module is electrically connected to the second reference voltage end, the second end of the reset module is electrically connected to the fourth node, and the control end of the reset module is electrically connected to the fourth circuit control end.

11. The display panel according to claim 8, characterized in that: The pixel driving circuit further includes: a first power signal terminal and a second power signal terminal; a light emitting element, wherein an anode of the light emitting element is electrically connected to the fourth node, and a cathode of the light emitting element is electrically connected to the second power signal terminal; A light emitting control module, wherein the light emitting control module, the driving transistor and the light emitting element are connected in series between the first power signal terminal and the second power signal terminal; A storage module, wherein a first end of the storage module is electrically connected to the first power signal end, and a second end of the storage module is electrically connected to the first node.

12. The display panel according to claim 11, characterized in that: The light emitting control module comprises a first light emitting control module and a second light emitting control module; A first end of the first light emitting control module is electrically connected to the first power signal end, a second end of the first light emitting control module is electrically connected to a second node, and a control end of the first light emitting control module is electrically connected to a light emitting control signal end; The first end of the second light emitting control module is electrically connected to the third node, the second end of the second light emitting control module is electrically connected to the fourth node, and the control end of the second light emitting control module is electrically connected to the light emitting control signal end.

13. A display device, characterized in that: Comprising a display panel as described in any one of claims 7-12.

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