Ternary Content Addressable Memory and Two-Port Static Random Access Memory

Abstract

The present invention discloses a three-state content addressable memory and a dual-port static random access memory, which includes a memory cell and two transistors. The memory cell includes a first active region, a second active region, a third active region and a fourth active region extending along a first direction, and a first gate line, a second gate line, a third gate line and a fourth gate line extending along a second direction. The first gate line spans the third active region and the fourth active region, the second gate line spans the fourth active region, the third gate line spans the first active region, and the fourth gate line spans the first active region and the second active region. The transistor is electrically connected to the memory cell, wherein the transistor and the memory cell are arranged along the first direction.

Description

Technical Field

[0001] The present invention relates to a ternary content addressable memory (TCAM) and a two-port static random access memory (SRAM), and in particular to a TCAM and a two-port SRAM using 8 transistors as a unit structure. Background Art

[0002] In a conventional memory array structure, a six-transistor static-random access memory (6T-SRAM) cell is commonly used as a bit cell structure. As memory performance improves, two transistors are further included in the memory bit cell structure. However, the arrangement of these two transistors causes the originally relatively symmetrical layout structure to lose symmetry, resulting in different transistor characteristics in the memory bit cell structure, which in turn affects the performance of the memory. For example, in a conventional memory bit cell structure, these two transistors are arranged on one side of the 6T-SRAM along the extension direction of the gate line. In order to prevent the pull-down (PD) transistor and the pass-gate (PG) transistor from being affected by these two transistors, the width of the shallow trench isolation (STI) between these two transistors and the pull-down transistor is greater than the width of the STI on the side of the 6T-SRAM relative to the two transistors. Due to the different diffusion length (LOD) effects (also called STI stress effects), the two pull-down transistors adjacent to the STI on both sides of the 6T-SRAM will have different transistor characteristics, and the two pass-gate transistors adjacent to the STI on both sides will also have different transistor characteristics, such as different threshold voltages, resulting in poor memory read operations and bit error rate (BER). Summary of the invention

[0003] According to one embodiment of the present invention, a TCAM is provided, which includes a memory cell and two search transistors. The memory cell includes a first active region, a second active region, a third active region, a fourth active region, a first gate line, a second gate line, a third gate line and a fourth gate line. The first active region, the second active region, the third active region and the fourth active region extend along a first direction and are arranged in sequence along a second direction. The first gate line spans the third active region and the fourth active region and extends along the second direction, and the second gate line spans the fourth active region and extends along the second direction. The third gate line spans the first active region and extends along the second direction. The fourth gate line spans the first active region and the second active region and extends along the second direction. The search transistor is electrically connected to the memory cell, wherein the search transistor and the memory cell are arranged along the first direction.

[0004] According to one embodiment of the present invention, a two-port SRAM is provided, which includes a memory cell and two read transistors. The memory cell includes a first active region, a second active region, a third active region, a fourth active region, a first gate line, a second gate line, a third gate line and a fourth gate line. The first active region, the second active region, the third active region and the fourth active region extend along a first direction and are arranged in sequence along a second direction. The first gate line spans the third active region and the fourth active region and extends along the second direction, and the second gate line spans the fourth active region and extends along the second direction. The third gate line spans the first active region and extends along the second direction. The fourth gate line spans the first active region and the second active region and extends along the second direction. The read transistor is electrically connected to the memory cell, wherein the read transistor and the memory cell are arranged along the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 A circuit diagram of a TCAM according to an embodiment of the present invention;

[0006] Figure 2 A schematic top view of the layout structure of a single basic unit according to an embodiment of the present invention;

[0007] Figure 3 A schematic top view of an active region, a gate line, a first contact layer and a first metal layer of a TCAM according to an embodiment of the present invention;

[0008] Figure 4 A schematic top view of an active region, a gate line, a second contact layer and a second metal layer of a TCAM according to an embodiment of the present invention;

[0009] Figure 5 A schematic top view of an active region, a gate line, a third contact layer and a third metal layer of a TCAM according to an embodiment of the present invention;

[0010] Figure 6A circuit diagram of a two-port SRAM according to an embodiment of the present invention;

[0011] Figure 7 A schematic top view of an active region, a gate line, a first contact layer and a first metal layer of a two-port SRAM according to an embodiment of the present invention;

[0012] Figure 8 A schematic top view of an active region, a gate line, a second contact layer and a second metal layer of a two-port SRAM according to an embodiment of the present invention;

[0013] Fig. 9 The diagram is a top view of an active region, a gate line, a third contact layer and a third metal layer of a two-port SRAM according to an embodiment of the present invention.

[0014] Main component symbols

[0015] 1 TCAM

[0016] 10 TCAM bit cell

[0017] 10A First TCAM bit cell

[0018] 10B Second TCAM bit cell

[0019] 10C Third TCAM bit cell

[0020] 11 Repeating Structure

[0021] 12 Basic Units

[0022] 14, 22 Storage Units

[0023] 16 Search transistor group

[0024] 16a First search transistor

[0025] 16b Second search transistor

[0026] 18 Insulation layer

[0027] 18a First insulation block

[0028] 18b Second insulation block

[0029] 2 Two-port SRAM

[0030] 20 SRAM cells

[0031] 20A First SRAM cell

[0032] 20B Second SRAM cell

[0033] 20C and the third SRAM cell

[0034] 24 Read transistor group

[0035] AR1 First active area

[0036] AR2 Second active area

[0037] AR3 Third Active Zone

[0038] AR4 Fourth Active Area

[0039] BL1, BL2, wBL, wBLB, rBL bit lines

[0040] C1~C44 Contact plug

[0041] CL cable

[0042] CL1, CL2 center line

[0043] D1 First direction

[0044] D2 Second direction

[0045] DGL1, DGL2 virtual gate lines

[0046] E1~E20 Electrode

[0047] GL1 First gate line

[0048] GL2 Second gate line

[0049] GL3 The third gate line

[0050] GL4 Fourth gate line

[0051] GL5 Fifth gate line

[0052] GL6 Sixth gate line

[0053] IN1 First Inverter

[0054] IN2 Second Inverter

[0055] ML Match Line

[0056] N1 First End

[0057] N2 Second terminal

[0058] PD1 First pull-down transistor

[0059] PD2 Second pull-down transistor

[0060] PG1 First pass gate transistor

[0061] PG2 Second pass gate transistor

[0062] PL1 First voltage supply line

[0063] PL2 Second voltage source line

[0064] PU1 First pull-up transistor

[0065] PU2 Second pull-up transistor

[0066] PW, PW2 Second voltage source

[0067] PW1 First voltage source

[0068] rPD First read transistor

[0069] rPG Second read transistor

[0070] SL1, SL2 search lines

[0071] VD Looking down direction

[0072] W1, W2 Width

[0073] WL1, WL2, wWL, rWL character lines DETAILED DESCRIPTION

[0074] In order to enable those skilled in the art to further understand the present invention, the following examples of the present invention are listed below, and the accompanying drawings are used to explain in detail the components and intended effects of the present invention. It should be noted that the following drawings are for illustration only, and the dimensions and proportions between components may be different from the actual ones, and are not limited thereto.

[0075] Please refer to Figure 1 , which depicts a circuit diagram of a ternary content addressable memory (TCAM) according to an embodiment of the present invention. Figure 1 As shown, TCAM 1 may include a plurality of TCAM bit cells 10, a plurality of bit lines BL1, BL2, a plurality of word lines WL1, WL2, a plurality of search lines SL1, SL2 and a match line ML, and each TCAM bit cell 10 may be electrically connected to a corresponding bit line BL1, BL2, word line WL1, WL2, search line SL1, SL2 and match line ML. For clarity, Figure 1Two adjacent TCAM bit cells 10 and corresponding bit lines BL1, BL2, word lines WL1, WL2, search lines SL1, SL2 and match lines ML are shown, but the present invention is not limited thereto. Since each TCAM bit cell 10 may have the same electrical connection method, a single TCAM bit cell 10 is used as an example for description below, but the present invention is not limited thereto.

[0076] exist Figure 1 In the embodiment, each TCAM bit cell 10 may include two basic cells 12, and each basic cell 12 may include a memory cell 14 and a search transistor group 16, wherein each memory cell 14 may include a first inverter IN1, a second inverter IN2, a first pass-gate transistor PG1, and a second pass-gate transistor PG2. In each memory cell 14, the first inverter IN1 and the second inverter IN2 may have a first end N1 and a second end N2, for example, an input end and an output end, respectively, the first end N1 of the first inverter IN1 may be electrically connected to the drain / source of the first pass-gate transistor PG1 and the second end N2 of the second inverter IN2, and the first end N1 of the second inverter IN2 may be electrically connected to the drain / source of the second pass-gate transistor PG2 and the second end N2 of the first inverter IN1. Although Figure 1 Not shown, the first inverter IN1 and the second inverter IN2 may include a pull-up (PU) transistor and a pull-down (PD) transistor, wherein in each inverter, the gates of the pull-up transistor and the pull-down transistor are electrically connected to each other and serve as the second terminal N2, the drain / source of the pull-up transistor and the pull-down transistor are electrically connected to each other and serve as the first terminal N1, the source / drain of the pull-up transistor and the source / drain of the pull-down transistor are electrically connected to the first voltage source and the second voltage source PW, respectively, and the voltage provided by the first voltage source may be greater than the voltage provided by the second voltage source PW. In other words, the memory cell 14 may include, for example, a 6T-SRAM cell.

[0077] like Figure 1 As shown, in the same TCAM bit cell 10, the source / drain of the first pass-gate transistor PG1 of the basic cell 12 can be electrically connected to the corresponding same bit line BL1, the source / drain of the second pass-gate transistor PG2 can be electrically connected to the corresponding same bit line BL2, and the gates of the first pass-gate transistor PG1 and the second pass-gate transistor PG2 of one basic cell 12 and the gates of the first pass-gate transistor PG1 and the second pass-gate transistor PG2 of another basic cell 12 are electrically connected to two different word lines WL1 and WL2, respectively.

[0078] like Figure 1As shown, each search transistor group 16 may include a first search transistor 16a and a second search transistor 16b, wherein the gate, drain / source, and source / drain of the first search transistor 16a may be electrically connected to the second terminal N2 of the first inverter IN1, the second voltage source PW, and the drain / source of the second search transistor 16b, respectively, and the source / drain of the second search transistor 16b may be electrically connected to the corresponding match line ML. In the same TCAM bit cell 10, the gates of the second search transistors 16b of different basic cells 12 may be electrically connected to two different search lines SL1 and SL2, respectively.

[0079] Please refer to Figure 2 , which depicts a top view schematic diagram of the layout structure of a single basic unit according to an embodiment of the present invention. Figure 2 As shown, the memory cell 14 of the basic unit 12 may include a first active region AR1, a second active region AR2, a third active region AR3, a fourth active region AR4, a first gate line GL1, a second gate line GL2, a third gate line GL3, and a fourth gate line GL4. The first active region AR1, the second active region AR2, the third active region AR3, and the fourth active region AR4 may extend along a first direction D1, and the first active region AR1, the second active region AR2, the third active region AR3, and the fourth active region AR4 may be arranged in sequence along a second direction D2. The first active region AR1 and the fourth active region AR4 may be mirror-symmetrical with the first direction D1 as the axis of symmetry, and the second active region AR2 and the third active region AR3 are symmetrical to each other with the center of the memory cell 14 as the center of symmetry. The first active region AR1, the second active region AR2, the third active region AR3, and the fourth active region AR4 may be, for example, surrounded by an insulating layer 18 and may be electrically isolated by the insulating layer 18. The insulating layer 18 may, for example, include shallow trench isolation (STI).

[0080] For example, the first active region AR1, the second active region AR2, the third active region AR3 and the fourth active region AR4 may respectively include a long fin structure extending continuously and protruding from the semiconductor substrate or a doped region in the semiconductor substrate. When the first active region AR1, the second active region AR2, the third active region AR3 and the fourth active region AR4 include a fin structure, the transistor formed by the first, second, third and fourth active regions AR1, AR2, AR3 and AR4 may be a Fin Field-Effect Transistor (FINFET), but is not limited thereto. In some embodiments, depending on the type of transistor formed, the fin structure may, for example, include a semiconductor substrate material doped with N-type dopants or P-type dopants. For example, the semiconductor substrate material may include silicon, germanium, IV-IV compound semiconductors such as silicon carbide or silicon germanium, or III-V semiconductors such as GaAs, GaP, GaN, InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP, or a combination of the above materials. In the present embodiment, the first active region AR1 and the fourth active region AR4 may have a first conductivity type, and the second active region AR2 and the third active region AR3 may have a second conductivity type different from the first conductivity type. For example, the first conductivity type and the second conductivity type may be p-type and n-type, respectively, but are not limited thereto.

[0081] like Figure 2As shown, the first gate line GL1, the second gate line GL2, the third gate line GL3 and the fourth gate line GL4 can extend along the second direction D2. When viewed from the top view direction VD, the first gate line GL1 can cross the third active area AR3 and the fourth active area AR4, so that the first gate line GL1 crossing the fourth active area AR4 can form the gate of the first pull-down transistor PD1 of the first inverter IN1, and the source / drain and drain / source of the first pull-down transistor PD1 of the first inverter IN1 are respectively arranged in the fourth active area AR4 on both sides of the first gate line GL1. The first gate line GL1 crossing the third active area AR3 can form the gate of the first pull-up transistor PU1 of the first inverter IN1, and the source / drain and drain / source of the first pull-up transistor PU1 are respectively arranged in the third active area AR3 on both sides of the first gate line GL1. From the top-view direction VD, the second gate line GL2 may cross the fourth active region AR4, so that the second gate line GL2 crossing the fourth active region AR4 may form the gate of the first pass-gate transistor PG1, and the source / drain and drain / source of the first pass-gate transistor PG1 are respectively arranged in the fourth active region AR4 on both sides of the second gate line GL2. In the present embodiment, the drain / source of the first pass-gate transistor PG1 and the drain / source of the first pull-down transistor PD1 of the first inverter IN1 may be formed by the same doping region arranged in the fourth active region AR4, but is not limited thereto. From the top-view direction VD, the third gate line GL3 may cross the first active region AR1, so that the third gate line GL3 crossing the first active region AR1 may form the gate of the second pass-gate transistor PG2, and the source / drain and drain / source of the second pass-gate transistor PG2 are respectively arranged in the first active region AR1 on both sides of the third gate line GL3. When viewed from the top-down direction VD, the fourth gate line GL4 may cross the first active region AR1 and the second active region AR2, so that the fourth gate line GL4 crossing the first active region AR1 may form the gate of the second pull-down transistor PD2 of the second inverter IN2, and the source / drain and drain / source of the second pull-down transistor PD2 of the second inverter IN2 are respectively arranged in the first active region AR1 on both sides of the fourth gate line GL4. The fourth gate line GL4 crossing the second active region AR2 may form the gate of the second pull-up transistor PU2 of the second inverter IN2, and the source / drain and drain / source of the second pull-up transistor PU2 are respectively arranged in the second active region AR2 on both sides of the fourth gate line GL4. In the present embodiment, the drain / source of the second pass-gate transistor PG2 and the drain / source of the first pull-down transistor PD1 of the second inverter IN1 may be formed by the same doping region arranged in the first active region AR1, but is not limited thereto.For example, the first pull-up transistor PU1 and the second pull-up transistor PU2 may be p-type field effect transistors (pFET), such as PMOSFET, and the first pull-down transistor PD1, the second pull-down transistor PD2, the first pass-gate transistor PG1 and the second pass-gate transistor PG2 may be n-type field effect transistors (nFET), such as nMOSFET.

[0082] like Figure 2 As shown, the third gate line GL3 and the fourth gate line GL4 can be symmetrical to the second gate line GL2 and the first gate line GL1 respectively with the center of the storage unit 14 as the symmetry center, so that the layout structure of the first pull-up transistor PU1 and the first pull-down transistor PD1 of the first inverter IN1 can be symmetrical to the layout structure of the second pull-up transistor PU2 and the second pull-down transistor PD2 of the second inverter IN2 with the center of the storage unit 14 as the symmetry center, and the layout structure of the first pass-gate transistor PG1 can be symmetrical to the layout structure of the second pass-gate transistor PG2 with the center of the storage unit 14 as the symmetry center. In some embodiments, the first gate line GL1 and the fourth gate line GL4 can have the same length in the second direction D2.

[0083] exist Figure 2 In the embodiment of the present invention, the first search transistor 16a of the basic unit 12 may further include a fifth gate line GL5, and when viewed from the top view direction VD, the fifth gate line GL5 may extend along the second direction D2 and cross the fourth active region AR4, so that the fifth gate line GL5 crossing the fourth active region AR4 may serve as the gate of the first search transistor 16a, and the source / drain and drain / source of the first search transistor 16a are respectively arranged in the fourth active region AR4 on both sides of the fifth gate line GL5. The fifth gate line GL5 may be arranged adjacent to the first gate line GL1, and the source / drain of the first search transistor 16a and the source / drain of the first pull-down transistor PD1 of the first inverter IN1 may be formed by the same doping region arranged in the fourth active region AR4, so that the two may be electrically connected to each other, but is not limited thereto.

[0084] like Figure 2 As shown, the fifth gate line GL5 can be electrically connected to the first gate line GL1. In the present embodiment, the TCAM 1 can further include a connection line CL, which is connected between the first gate line GL1 and the fifth gate line GL5 and is used to electrically connect the first gate line GL1 to the fifth gate line GL5. For example, the connection line CL can be connected to the first gate line GL1 and the fifth gate line GL5 to form an integrated C-shaped gate structure, but is not limited thereto. In some embodiments, the first gate line GL1 and the fifth gate line GL5 can be mirror-symmetrical with the second direction D2 as the symmetry axis.

[0085] exist Figure 2In the embodiment of the present invention, the second search transistor 16b of the basic unit 12 may include a sixth gate line GL6, wherein the fifth gate line GL5 may be disposed between the sixth gate line GL6 and the first gate line GL1. When viewed from the top view direction VD, the sixth gate line GL6 may extend along the second direction D2 and cross the fourth active region AR4, so that the sixth gate line GL6 crossing the fourth active region AR4 may serve as the gate of the second search transistor 16b, and the source / drain and drain / source of the second search transistor 16b are respectively disposed in the fourth active region AR4 on both sides of the sixth gate line GL6. The drain / source of the first search transistor 16a and the source / drain of the second search transistor 16b may be disposed in the same fourth active region AR4, for example, may be formed by the same doping region. In other words, in this embodiment, the source / drain and drain / source of the first search transistor 16a, the second search transistor 16b, the first pull-down transistor PD1 of the first inverter IN1, and the first pass-gate transistor PG1 can be arranged in the same fourth active region AR4, so the first search transistor 16a and the second search transistor 16b can be arranged with the memory cell 14 in the extension direction of the active region (e.g., the first direction D1). Figure 2 In the embodiment, the sixth gate line GL6 may be symmetrical to the fifth gate line GL5 with the second direction D2 as the axis of symmetry, or the lengths of the sixth gate line GL6 and the fifth gate line GL5 in the second direction D2 may be the same, but not limited thereto. In some embodiments, the sixth gate line GL6 and the fifth gate line GL5 may be asymmetrical with respect to the second direction D2.

[0086] It is worth mentioning that, since the memory cell 14 and the search transistor group 16 in the same basic unit 12 can be arranged in the extension direction of the active region (e.g., the second direction D2), the width of the insulating layer 18 on the side of the fourth active region AR4 of the memory cell 14 relative to the third active region AR3 in the second direction D2 can be designed to be the same as the width of the insulating layer 18 on the side of the first active region AR1 relative to the second active region AR2 in the second direction D2 without considering the search transistor group 16. Thus, the difference in the diffusion length (length of diffusion, LOD) effect (also known as the STI stress effect) to which the first pull-down transistor PD1 and the second pull-down transistor PD1 are subjected can be reduced, thereby improving the consistency of the transistor characteristics of the first pull-down transistor PD1 and the second pull-down transistor PD1. Similarly, the difference in the transistor characteristics of the first pass-gate transistor PU1 and the second pass-gate transistor PU2 can be reduced, and the consistency of the two can be improved.

[0087] In some embodiments, Figure 2As shown, the basic unit 12 may optionally include two dummy gate lines DGL1 and DGL2, which are arranged in the first direction D1 and extend along the second direction D2 and cross the first active area AR1. It is worth noting that the dummy gate line DGL1 can be arranged on the same straight line extending along the second direction D2 with the fifth gate line GL5, and the dummy gate line DGL2 can be arranged on the same straight line extending along the second direction D2 with the sixth gate line GL6. By setting the dummy gate lines DGL1 and DGL2, the quality of forming the gate lines can be improved in the patterning process of forming the gate lines.

[0088] In the present invention, the gate line and the connection line CL refer to a structure in which a gate insulating layer and a gate conductive layer are stacked in sequence, and for example, a spacer may be provided on the sidewalls of the gate conductive layer and the gate insulating layer. The gate line and the connection line CL may include a suitable conductive material, such as polysilicon, metal silicide or a suitable metal material, and the metal material may include aluminum or tungsten, for example. When the gate line and the connection line CL are metal gate lines, the gate line and the connection line CL may also include a high-k material and a work function metal, and the work function metal may include titanium nitride (TiN) for forming a pFET, or titanium aluminide (TiAl) for forming an nFET, but is not limited thereto.

[0089] exist Figure 2 In the embodiment of FIG. 1 , the basic unit 12 may further include a first contact layer and a first metal layer, which are sequentially disposed on the gate line and the active region. To clearly illustrate the layout structure of the basic unit 12, Figure 2 The insulating layer disposed between the first metal layer and the gate line and the active region and used to electrically isolate the first metal layer from the non-corresponding gate line and the active region is omitted, but the present invention is not limited thereto. Specifically, the first contact layer may include contact plugs C1 to C14 disposed in the insulating layer, and the first metal layer may include electrodes E1 to E12 disposed on the insulating layer. The contact plug C1 may be disposed on the third gate line GL3, and the electrode E1 may be disposed on the contact plug C1 to electrically connect the third gate line GL3 to the corresponding word line (such as Figure 1 In the top view direction VD, the electrode E1 may, for example, cross the third gate line GL3 and the dummy gate line DGL1, but is not limited thereto. The contact plugs C2 to C4 may be disposed on the source / drain and drain / source of the second pull-down transistor PD2 and the source / drain of the second pass-gate transistor PG2, respectively. The electrode E2 may be disposed on the contact plug C2 to electrically connect the source / drain of the second pull-down transistor PD2 to a second voltage source (such as Figure 1The electrode E3 may be disposed on the contact plug C3 and the contact plug C6 to electrically connect the drain / source of the second pull-down transistor PD2 and the second pull-up transistor PU2. The electrode E4 is disposed on the contact plug C4 to electrically connect the source / drain of the second pass-gate transistor PG2 to the corresponding bit line (e.g., Figure 1 2 ). The contact plugs C5 and C6 may be respectively disposed on the source / drain and the drain / source of the second pull-up transistor PU2. The electrode E5 is disposed on the contact plug C5 to electrically connect the source / drain of the second pull-up transistor PU2 to the first voltage source. The electrode E6 may be disposed on the contact plug C8 to electrically connect the source / drain of the first pull-up transistor PU1 to the first voltage source. The contact plugs C7 and C8 may be respectively disposed on the drain / source and the source / drain of the first pull-up transistor PU1. The electrode E7 may be disposed on the contact plug C7 and the contact plug C10 to electrically connect the first pull-down transistor PD1 to the drain / source of the first pull-up transistor PU1. The contact plugs C9-C11 may be respectively disposed on the source / drain of the first pass-gate transistor PG1 and the drain / source and the source / drain of the second pull-down transistor PD2. The electrode E8 may be disposed on the contact plug C9 to electrically connect the source / drain of the first pass-gate transistor PG1 to the corresponding bit line (eg, Figure 1 The electrode E9 may be disposed on the contact plug C11 to electrically connect the source / drain of the first pull-down transistor PD1 to the second voltage source. The contact plug C12 may be disposed on the second gate line GL2, the contact plug C13 may be disposed on the sixth gate line GL6, and the contact plug C14 may be disposed on the drain / source of the second search transistor 16b. The electrode E10 may be disposed on the contact plug C12 to electrically connect the second gate line GL2 to the corresponding word line (e.g., Figure 1 The electrode E11 may be disposed on the contact plug C13 to electrically connect the gate of the second search transistor 16b to the corresponding search line (eg, Figure 1 The electrode E12 may be disposed on the contact plug C14 to electrically connect the drain / source of the second search transistor 16b to the corresponding matching line (eg, Figure 1 The first contact layer may include a suitable conductive material, such as tungsten or copper. The first metal layer may include a suitable conductive material, such as aluminum, copper or tungsten, but the present invention is not limited thereto.

[0090] Please refer to further Figure 3 , which depicts a top view of the active region, gate line, first contact layer and first metal layer of a TCAM according to an embodiment of the present invention. In order to clearly illustrate the structure of each TCAM bit unit 10, Figure 3 The basic unit 12 on the upper side of the TCAM bit cell 10B can be connected to Figure 2 The basic units 12 shown are the same, so the symbols of the corresponding transistors and gate lines are omitted, but the present invention is not limited thereto. Figure 3 As shown, in a single TCAM bit cell 10, the structures of the two basic cells 12 can be mirror-symmetric with the extension direction of the gate line (e.g., the second direction D2) as the symmetry axis. For example, the structures of the two basic cells 12 can be located between the two sixth gate lines GL6 of the two basic cells 12 and the center line CL1 equidistant from the two sixth gate lines GL6 can be the symmetry axis. The structures of the two TCAM bit cells 10 adjacent to each other and arranged in the second direction D2 can be mirror-symmetric with the extension direction of the active region (e.g., the first direction D1) as the symmetry axis. Therefore, the structure of each basic cell 12 can be Figure 2 For example, the structure of the two TCAM bit cells 10 can be located between the two first active regions AR1 or the two fourth active regions AR4 of the two TCAM bit cells 10 and the center line CL2 equidistant from the two first active regions AR1 or the two fourth active regions AR4 is the symmetry axis. In some embodiments, Figure 3 As shown, two adjacent TCAM bit cells 10 arranged in the second direction D2 may form a repeating structure 11, and the TCAM 1 may include a plurality of repeating structures 11, wherein the repeating structures 11 may have the same structure and be arranged in an array in the same configuration direction. In some embodiments, the structure of two adjacent TCAM bit cells 10 arranged in the first direction D1 may be mirror-symmetric with the second direction D2 as the symmetry axis, but is not limited thereto.

[0091] exist Figure 3In the embodiment of the present invention, in the same TCAM bit cell 10, the memory cells 14 are arranged along the first direction D1, and the first search transistor 16a and the second search transistor 16b of the search transistor group 16 can be arranged between the two memory cells 14, so that the search transistor group 16 does not need to be arranged between the adjacent memory cells 14 arranged in the second direction D2, so that the insulating layer 18 located on both sides of the memory cells 14 can have the same width in the second direction D2. Specifically, the insulating layer 18 may include a first insulating block 18a and a second insulating block 18b, wherein the first insulating block 18a is arranged on a side of the first active region AR1 relative to the second active region AR2, and the second insulating block 18b is arranged on a side of the fourth active region AR4 relative to the third active region AR3, and the width W1 of the first insulating block 18a in the second direction D2 is substantially equal to the width W2 of the second insulating block 18b in the second direction D2. Further, the TCAM 1 may include a first TCAM bit cell 10A, a second TCAM bit cell 10B, and a third TCAM bit cell 10C, which are sequentially arranged in the second direction D2. The adjacent first TCAM bit cell 10A and the second TCAM bit cell 10B may be mirror-symmetric with the extension direction of the active region (e.g., the first direction D1) as the symmetry axis, and the adjacent second TCAM bit cell 10B and the third TCAM bit cell 10C may be mirror-symmetric with the first direction D1 as the symmetry axis, so the spacing between the first active regions AR1 in the first TCAM bit cell 10A and the second TCAM bit cell 10B may be defined as the width W1 of the first insulating block 18a in the second direction D2, and the spacing between the fourth active regions AR4 in the second TCAM bit cell 10B and the third TCAM bit cell 10C may be defined as the width W2 of the second insulating block 18b in the second direction D2. Since the width W1 and the width W2 can be substantially the same, the difference in transistor characteristics between the first pull-down transistor PD1 and the second pull-down transistor PD1 and the difference in transistor characteristics between the first pass-gate transistor PU1 and the second pass-gate transistor PU2 can be reduced, thereby improving the read operation and bit error rate of TCAM1. In the same TCAM bit cell 10 of some embodiments, the storage unit 14 can be disposed between the two search transistor groups 16, but is not limited thereto. In some embodiments, the first active regions AR1 of the two basic cells 12 can be connected to each other to form a single active region, and the fourth active regions AR4 can also be connected to each other to form a single active region.

[0092] Please refer to Figure 4 and Figure 5 , and also refer to Figure 2 and Figure 3 . Figure 4 A schematic top view of an active region, a gate line, a second contact layer and a second metal layer of a TCAM according to an embodiment of the present invention is shown. Figure 5 A schematic top view of the active region, gate line, third contact layer and third metal layer of a TCAM according to an embodiment of the present invention is shown. To clearly illustrate the layout structure of the second contact layer and the second metal layer and the layout structure of the third contact layer and the third metal layer, Figure 4 Only the active region, gate line, second contact layer and second metal layer are shown. Figure 5 Only the active region, the gate line, the third contact layer and the third metal layer are shown. Figure 4 and Figure 5 The active region and gate line in Figure 3 The active region and gate line shown, and Figure 4 and Figure 5 Symbols corresponding to transistors and gate lines are omitted, but the present invention is not limited thereto. An insulating layer may be disposed between the second metal layer and the first metal layer and between the third metal layer and the second metal layer, but the present invention is not limited thereto. Figure 4 As shown, the TCAM 1 may further include a second contact layer and a second metal layer, which are sequentially arranged at Figure 3 The second contact layer may include contact plugs C15-C24, and the second metal layer may include bit lines BL1, BL2, first voltage supply line PL1, search lines SL1, SL2 and electrodes E13-E17, respectively extending along the first direction D1. In this embodiment, the bit line BL2, the first voltage supply line PL1, the search line SL1, the search line SL2 and the bit line BL1 corresponding to the same TCAM bit cell 10 may be arranged in sequence in the second direction D2, but the present invention is not limited thereto. The second contact layer may include a suitable conductive material, such as tungsten or copper. The second metal layer may include a suitable conductive material, such as aluminum, copper or tungsten, but the present invention is not limited thereto.

[0093] like Figure 3 and Figure 4As shown, in the present embodiment, the contact plug C15 may be disposed on the electrode E2, and the electrode E13 may be disposed on the contact plug C15, thereby electrically connecting the source / drain of the second pull-down transistor PD2. The contact plug C16 may be disposed on the electrode E1, and the electrode E14 may be disposed on the contact plug C16, thereby electrically connecting the third gate line GL3 (i.e., the gate of the second pass-gate transistor PG2). The contact plug C17 may be disposed on the electrode E4, and the bit line BL2 may be disposed on the contact plug C17, so that the bit line BL2 may be electrically connected to the source / drain of the second pass-gate transistor PG2. The contact plug C18 may be disposed on the electrode E5, the contact plug C19 may be disposed on the electrode E6, and the first voltage supply line PL1 may be disposed on the contact plugs C18 and C19, so that the source / drain of the second pull-up transistor PU2 and the first pull-up transistor PU1 may be electrically connected to the first voltage source through the first voltage supply line PL1. The contact plug C20 may be disposed on the electrode E11, and the search line SL1 may be disposed on the contact plug C20, so that the search line SL1 may be electrically connected to the sixth gate line GL6 (i.e., the gate of the second search transistor 16b). The contact plug C25 may be disposed on the electrode E11 of another basic unit 12, and the search line SL2 may be disposed on the contact plug C25, so that the search line SL2 may be electrically connected to the gate of the second search transistor 16b of another basic unit 12. The contact plug C21 is disposed on the electrode E8, and the bit line BL1 is disposed on the contact plug C21, so that the bit line BL1 may be electrically connected to the source / drain of the first pass-gate transistor PG1. The contact plug C22 is disposed on the electrode E10, and the electrode E15 is disposed on the contact plug C22, so that the second gate line GL2 (i.e., the gate of the first pass-gate transistor PG1) may be electrically connected. Contact plug C23 is disposed on electrode E9, and electrode E16 is disposed on contact plug C23, thereby electrically connecting the source / drain of first pull-down transistor PD1. Contact plug C24 is disposed on electrode E12, and electrode E17 is disposed on contact plug C24, thereby electrically connecting the drain / source of second search transistor 16b.

[0094] like Figure 5 As shown, the TCAM 1 may further include a third contact layer and a third metal layer, which are sequentially arranged at Figure 4The second metal layer shown. The third contact layer may include contact plugs C26-C30, and the third metal layer may include a second voltage supply line PL2, word lines WL1, WL2 and a matching line ML, wherein the second voltage supply line PL2, word lines WL1, WL2 and matching line ML extend along the second direction D2 respectively, and cross the first active area AR1 and the fourth active area AR4 in the top-view direction VD. In this embodiment, the second voltage supply line PL2, word line WL1, second voltage supply line PL2, matching line ML, second voltage supply line PL2, word line WL2 and second voltage supply line PL2 corresponding to the same TCAM bit cell 10 may be arranged in sequence in the first direction D1, but is not limited thereto. The third contact layer may include a suitable conductive material, such as tungsten or copper. The third metal layer may include a suitable conductive material, such as aluminum, copper or tungsten, but the present invention is not limited thereto.

[0095] like Figure 4 and Figure 5 As shown, in this embodiment, the contact plug C26 is disposed on the electrode E13, and the second voltage supply line PL2 is disposed on the contact plug C26, so that the source / drain of the second pull-down transistor PD2 can be electrically connected to the second voltage source (e.g. Figure 1 The second voltage source PW shown is shown in FIG. 1 . In one of the basic units 12, the contact plug C27 is disposed on the electrode E14, the contact plug C28 is disposed on the electrode E15, and the word line WL1 is disposed on the contact plugs C27 and C28, so that the word line WL1 can be electrically connected to the third gate line GL3 (i.e., the gate of the second pass-gate transistor PG2) and the second gate line GL2 (i.e., the gate of the first pass-gate transistor PG1) through the electrodes E14 and E15 at the same time. In another basic unit 12, the word line WL2 can be disposed on the other contact plugs C27 and C28. The contact plug C29 is disposed on the electrode E16, and the second voltage source line PL2 is disposed on the contact plug C29, so that the source / drain of the first pull-down transistor PD1 can be electrically connected to the second voltage source (e.g., the gate of the second pass-gate transistor PG2) through the second voltage source line PL2 and the electrode E16. Figure 1 A contact plug C30 is disposed on the electrode E17, and a match line ML is disposed on the contact plug C30, so that the match line ML can be electrically connected to the drain / source of the second search transistor 16b through the electrode E17.

[0096] The layout structure of the basic unit of the present invention can be applied to other types of electronic components, and is not limited to the above-mentioned embodiments. The following takes the application of the basic unit to a two-port SRAM as an example, but is not limited to this. In order to facilitate the comparison of different embodiments and simplify the description, the same components will be marked with the same symbols below. The following description will explain the differences between different embodiments in detail, and the same features will not be repeated.

[0097] Please refer to Figure 6 , which depicts a circuit diagram of a two-port SRAM according to an embodiment of the present invention. Figure 6 As shown, the two-port SRAM 2 may include a static-random access memory (SRAM) unit 20. For clarity, Figure 6 Only a single SRAM cell 20 is shown, but the present invention is not limited thereto. Specifically, the SRAM cell 20 may include a memory cell 22 and a read transistor group 24, wherein the memory cell 22 may be similar to or the same as the memory cell 14 of the TCAM, and thus may include a first pull-up transistor PU1, a first pull-down transistor PD1, a second pull-up transistor PU2, a second pull-down transistor PD2, a first pass-gate transistor PG1, and a second pass-gate transistor PG2, and the electrical connection method therebetween may be the same as Figure 1 The storage unit 14 shown is not described in detail here. Figure 6 As shown, the source / drain of the first pull-up transistor PU1 and the second pull-up transistor PU2 may be electrically connected to each other and to the first voltage source PW1, and the source / drain of the first pull-down transistor PD1 and the second pull-down transistor PD2 may be electrically connected to each other and to the second voltage source PW2. The gates of the first pass-gate transistor PG1 and the second pass-gate transistor PG2 may be electrically connected to the same word line wWL, and the source / drain of the first pass-gate transistor PG1 and the source / drain of the second pass-gate transistor PG2 may be electrically connected to the bit line wBL and the bit line wBLB, respectively, wherein the word line wWL may be, for example, a write word line, and the bit line wBL and the bit line wBLB may be, for example, a write bit line, but are not limited thereto. The bit line wBL and the bit line wBLB may, for example, transmit inverted or complementary signals.

[0098] In addition, Figure 6 In the embodiment of the present invention, the read transistor group 24 may include a first read transistor rPD and a second read transistor rPG, wherein the gate, drain / source, and source / drain of the first read transistor rPD may be electrically connected to the drain / source of the second pass-gate transistor PG2, the second voltage source PW2, and the drain / source of the second read transistor rPG, respectively, and the gate and source / drain of the second read transistor rPD may be electrically connected to the corresponding bit line rBL and word line rWL, respectively. The bit line rBL and the word line rWL may be, for example, a read bit line and a read word line, respectively, but are not limited thereto. Figure 6 The connection method of the first read transistor rPD and the second read transistor rPG in the embodiment may be the same as or similar to Figure 1 The connection method of the first search transistor 16a and the second search transistor 16b is shown, so no further details are given here.

[0099] Please refer to Figure 7 to Figure 9 , Figure 7 A schematic top view of an active region, a gate line, a first contact layer and a first metal layer of a two-port SRAM according to an embodiment of the present invention is shown. Figure 8 A schematic top view of an active region, a gate line, a second contact layer and a second metal layer of a two-port SRAM according to an embodiment of the present invention is shown. Fig. 9 A schematic top view of the active region, gate line, third contact layer and third metal layer of a two-port SRAM according to an embodiment of the present invention is shown. To clearly illustrate the layout structure of the first contact layer and the first metal layer, the layout structure of the second contact layer and the second metal layer, and the layout structure of the third contact layer and the third metal layer, Figure 7 Only the active region, gate line, first contact layer and first metal layer are shown. Figure 8 Only the active region, gate line, second contact layer and second metal layer are shown. Fig. 9 Only the active region, gate line, third contact layer and third metal layer are shown, and insulating layers may be disposed between the first metal layer and the active region and gate line, between the second metal layer and the first metal layer, and between the third metal layer and the second metal layer, but the present invention is not limited thereto. Figure 7 The SRAM cell 20 can be connected with Figure 2 The basic units 12 shown are similar, so the symbols of the corresponding transistors are omitted, but the present invention is not limited thereto. Figure 8 and Fig. 9 The active region and gate line in Figure 7 The active region and gate line shown, and Figure 8 and Fig. 9 Symbols corresponding to transistors and gate lines are omitted.

[0100] like Figure 7 As shown, the two-port SRAM 2 may include a plurality of SRAM cells 20, wherein a storage cell 22 of one SRAM cell 20 (eg, SRAM cell 20B) may be connected to Figure 2 The memory cell 14 shown has substantially the same structure. Specifically, the memory cell 22 may include a first active region AR1, a second active region AR2, a third active region AR3, a fourth active region AR4, a first gate line GL1, a second gate line GL2, a third gate line GL3, and a fourth gate line GL4. Since the first active region AR1, the second active region AR2, the third active region AR3, the fourth active region AR4, the first gate line GL1, the second gate line GL2, the third gate line GL3, and the fourth gate line GL4 may form Figure 6 The first pull-up transistor PU1, the first pull-down transistor PD1, the second pull-up transistor PU2, the second pull-down transistor PD2, the first pass-gate transistor PG1, and the second pass-gate transistor PG2 are shown and may be the same as Figure 2The embodiments shown are therefore not described in detail here.

[0101] In addition, if Figure 7 As shown, the read transistor set 24 of the SRAM cell 20 may be substantially similar or identical to Figure 2 The search transistor group 16 is shown, and thus the read transistor group 24 may include a fifth gate line GL5 and a sixth gate line GL6, each crossing the fourth active region AR4 to form a Figure 6 The first read transistor rPD and the second read transistor rPG are shown. The drain / source of the first read transistor and the source / drain of the second read transistor can be arranged in the same fourth active region AR4, for example, they can be formed by the same doping region, so the source / drain and drain / source of the first read transistor, the second read transistor, the first pull-down transistor and the first pass-gate transistor can be arranged in the same fourth active region AR4, so that the first read transistor and the second read transistor can be arranged with the memory cell 22 along the extension direction (first direction D1) of the active region.

[0102] The fifth gate line GL5 of this embodiment can be connected to Figure 2 The fifth gate line GL5 has substantially the same structure and can be electrically connected to the first gate line GL1. The SRAM unit 20 may further include a connecting line CL connected between the first gate line GL1 and the fifth gate line GL5. For example, the connecting line CL may be connected to the first gate line GL1 and the fifth gate line GL5 to form an integrated C-shaped gate structure, but is not limited thereto. In some embodiments, the first gate line GL1 and the fifth gate line GL5 may be mirror-symmetrical with the second direction D2 as the axis of symmetry. Figure 7 In the embodiment of the present invention, the read transistor group 24 and Figure 2 The difference of the search transistor group 16 is that the sixth gate line GL6 may be asymmetric to the fifth gate line GL5. Specifically, the length of the sixth gate line GL6 in the second direction D2 of the present embodiment may be smaller than the length of the fifth gate line GL5 in the second direction D2.

[0103] In some embodiments, Figure 7 As shown, the SRAM cell 20 may optionally further include two dummy gate lines DGL1 and DGL2 arranged in the first direction D1. Figure 2 The dummy gate lines DGL1 and DGL2 shown have the same function, and thus will not be described in detail herein.

[0104] like Figure 7As shown, the dual-port SRAM 2 may include a plurality of SRAM cells 20, and the structures of the SRAM cells 20 that are adjacent and arranged in the first direction D1 may be mirror-symmetrical with the extension direction of the gate line (e.g., the second direction D2) as the axis of symmetry. For example, the structures of two adjacent SRAM cells 20 may be located between two adjacent fourth gate lines GL4 and the center line CL1 that is equidistant from the two fourth gate lines GL4 is the axis of symmetry. The structures of the two SRAM cells 20 that are adjacent and arranged in the second direction D2 may be mirror-symmetrical with the extension direction of the active region (e.g., the first direction D1) as the axis of symmetry, so that the structure of each SRAM cell 20 may be obtained, which will not be described in detail here. For example, the structures of the two adjacent SRAM cells 20 that are adjacent and arranged in the second direction D2 may be located between two adjacent first active regions AR1 or two adjacent fourth active regions AR4 and the center line CL2 that is equidistant from the two adjacent first active regions AR1 or two adjacent fourth active regions AR4 is the axis of symmetry.

[0105] exist Figure 7In the embodiment, in the SRAM cells 20 adjacent and arranged in the first direction D1, the memory cell 22 can be disposed between the two read transistor groups 24, so that the read transistor group 24 does not need to be disposed between the memory cells 22 adjacent and arranged in the second direction D2, so that the insulating layer 18 located on both sides of the memory cell 2 can have the same width in the second direction D2. Specifically, the insulating layer 18 may include a first insulating block 18a and a second insulating block 18b, wherein the first insulating block 18a is disposed on a side of the first active region AR1 relative to the second active region AR2, the second insulating block 18b is disposed on a side of the fourth active region AR4 relative to the third active region AR3, and the width W1 of the first insulating block 18a in the second direction D2 is substantially equal to the width W2 of the second insulating block 18b in the second direction D. In other words, the two-port SRAM 2 may include a first SRAM cell 20A, a second SRAM cell 20B, and a third SRAM cell 20C, which are arranged in sequence in the second direction D2. The spacing between the first active area AR1 in the first SRAM cell 20A and the second SRAM cell 20B can be defined as the width W1 of the first insulating block 18a in the second direction D2, and the spacing between the fourth active area AR4 in the second SRAM cell 20B and the third SRAM cell 20C can be defined as the width W2 of the second insulating block 18b in the second direction D2. Since the width W1 and the width W2 can be designed to be substantially the same without considering the read transistor group 24, the difference in transistor characteristics between the first pull-down transistor and the second pull-down transistor and the difference in transistor characteristics between the first pass-gate transistor PU1 and the second pass-gate transistor PU2 can be reduced, thereby improving the read operation and bit error rate of TCAM 1. In some embodiments, the read transistor group 24 can be disposed between the two storage cells 22, but is not limited thereto. In some embodiments, as Figure 7 As shown, four adjacent SRAM cells 20 (eg, SRAM cells 20B, 20C, 20D, 20E) arranged in a matrix may form a repeating structure 11, and the dual-port SRAM 2 may include a plurality of repeating structures 11, wherein the repeating structures 11 may have the same structure and be arranged in an array in the same configuration direction.

[0106] like Figure 7 As shown, the dual-port SRAM 2 of this embodiment may include a first contact layer and a first metal layer, which are sequentially disposed on the active region and the gate line. Figure 2The contact plugs of the first contact layer shown in FIG. 1 are similar, and the same contact plugs will not be described again. The difference between the two is that the contact plug C31 disposed on the sixth gate line GL6 in the present embodiment is disposed on the side of the fourth active region AR4 relative to the first active region AR1 in the top view direction VD, but the present invention is not limited thereto. In addition, the first metal layer of the present embodiment may also include electrodes E1 to E12, which are connected to the storage unit 22 and the read transistor group 24 in the same manner as Figure 2 The electrodes E1 to E12 shown are similar and thus will not be described again here.

[0107] Furthermore, if Figure 8 As shown, the dual-port SRAM 2 may further include a second contact layer and a second metal layer, which are sequentially arranged at Figure 7 The second contact layer may include contact plugs C32-C40, and the second metal layer corresponding to the same SRAM cell 20 may include three bit lines wBLB, wBL, rBL, two second voltage supply lines PL2, a first voltage supply line PL1, and electrodes E18-E20, respectively extending along the first direction D1. In the present embodiment, the bit line wBLB, the second voltage supply line PL2, the first voltage supply line PL1, the bit line rBL, the second voltage supply line PL2, and the bit line wBL corresponding to the same SRAM cell 20 may be arranged in sequence along the second direction D2, but are not limited thereto.

[0108] like Figure 7 and Figure 8 As shown, in this embodiment, the contact plug C32 may be disposed on the electrode E1, and the electrode E18 may be disposed on the contact plug C32, thereby electrically connecting the third gate line GL3 (i.e., the gate of the second pass-gate transistor). The contact plug C33 may be disposed on the electrode E4, and the bit line BL2 may be disposed on the contact plug C17, so that the bit line wBLB may be electrically connected to the source / drain of the second pass-gate transistor. The contact plug C34 may be disposed on the electrode E2, and the second voltage supply line PL2 may be disposed on the contact plug C34, so that the source / drain of the second pull-down transistor may be electrically connected to the second voltage source (e.g., Figure 6 The contact plug C35 may be disposed on the electrode E5, the contact plug C36 may be disposed on the electrode E6, and the first voltage supply line PL1 may be disposed on the contact plugs C35 and C36, so that the source / drain of the second pull-up transistor PU2 and the first pull-up transistor PU1 may be electrically connected to the first voltage source (such as Figure 6A contact plug C37 may be disposed on the electrode E12, and a bit line rBL may be disposed on the contact plug C37, so that the bit line rBL is electrically connected to the drain / source of the second read transistor. A contact plug C38 may be disposed on the electrode E9, and a second voltage supply line PL2 is disposed on the contact plug C38, so that the source / drain of the first pull-down transistor may be electrically connected to the second voltage source (such as Figure 6 The second voltage source PW2 shown in FIG. 1 is provided on the electrode E8. The contact plug C39 is provided on the electrode E8, and the bit line wBL is provided on the contact plug C39, so that the bit line wBL can be electrically connected to the source / drain of the first pass-gate transistor. The contact plug C40 can be provided on the electrode E10, and the electrode E19 is provided on the contact plug C40, thereby electrically connecting the second gate line GL2 (i.e., the gate of the first pass-gate transistor PG1). The contact plug C41 can be provided on the electrode E11, and the electrode E20 is provided on the contact plug C41, so that the electrode E20 can be electrically connected to the sixth gate line GL6 (i.e., the gate of the second read transistor).

[0109] like Fig. 9 As shown, the dual-port SRAM 2 may further include a third contact layer and a third metal layer, which are sequentially arranged at Figure 8 The third contact layer may include contact plugs C42-C44, and the third metal layer may include word lines wWL and rWL extending along the second direction D2 and crossing the first active area AR1 and the fourth active area AR4 in the top-view direction VD. The word lines wWL and the word lines rWL corresponding to the same SRAM cell 20 may be arranged in sequence in the first direction D1, but are not limited thereto.

[0110] like Figure 8 and Fig. 9 As shown, the contact plug C42 may be disposed on the electrode E18, the contact plug C43 may be disposed on the electrode E19, and the word line wWL is disposed on the contact plugs C42 and C43, so that the third gate line GL3 (i.e., the gate of the second pass-gate transistor) and the second gate line GL2 (i.e., the gate of the first pass-gate transistor) may be electrically connected to the word line wWL. The contact plug C44 may be disposed on the electrode E20, and the word line rWL is disposed on the contact plug C44, so that the word line rWL may be electrically connected to the sixth gate line GL6 (i.e., the gate of the second read transistor).

[0111] In summary, in the TCAM and two-port SRAM of the present invention, since the memory cell can be arranged with the search transistor group or the read transistor group in the extension direction of the active region, the width of the insulating layer located on the side of the fourth active region of the memory cell relative to the third active region in the extension direction of the gate line can be designed to be the same as the width of the insulating layer on the side of the first active region relative to the second active region in the extension direction of the gate line without considering the search transistor group 16. Thus, the difference in transistor characteristics between the first pull-down transistor and the second pull-down transistor and the difference in transistor characteristics between the first pass-gate transistor PU1 and the second pass-gate transistor PU2 can be reduced, thereby improving the read operation and bit error rate of the TCAM and the two-port SRAM.

[0112] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A ternary content addressable memory, characterized in that: include: Storage unit, comprising: A first active region extending along a first direction; A second active area extending along the first direction; A third active area extending along the first direction; A fourth active region extending along the first direction, wherein the first active region, the second active region, the third active region and the fourth active region are arranged in sequence along the second direction; A first gate line spans across the third active region and the fourth active region and extends along the second direction; A second gate line spans across the fourth active region and extends along the second direction; A third gate line spans across the first active region and extends along the second direction; and a fourth gate line, crossing the first active region and the second active region and extending along the second direction; and Two search transistors are electrically connected to the memory cell, wherein the combination of the two search transistors and the memory cell are arranged along the first direction.

2. The ternary content addressable memory as described in claim 1 further includes a first insulating block and a second insulating block, the first insulating block is arranged on a side of the first active region relative to the second active region, and the second insulating block is arranged on a side of the fourth active region relative to the third active region, wherein the width of the first insulating block in the second direction is equal to the width of the second insulating block in the second direction.

3. The ternary content addressable memory as claimed in claim 1, wherein the source / drain and drain / source of the two search transistors are disposed in the fourth active region. 4 . The ternary content addressable memory as claimed in claim 1 , wherein the first gate line and the fourth gate line have the same length in the second direction.

5. The ternary content addressable memory as claimed in claim 1, further comprising another memory cell, wherein the memory cell and the another memory cell are arranged along the first direction, and the two search transistors are disposed between the memory cell and the another memory cell. 6 . The ternary content addressable memory as claimed in claim 1 , wherein one of the two search transistors comprises a fifth gate line crossing the fourth active region. 7 . The ternary content addressable memory as claimed in claim 6 , wherein the first gate line and the fifth gate line are mirror-symmetrical with respect to the second direction as a symmetry axis. 8 . The ternary content addressable memory as claimed in claim 6 , further comprising a connection line connected between the first gate line and the fifth gate line.

9. The ternary content addressable memory as claimed in claim 1, wherein one of the two search transistors comprises a sixth gate line crossing the fourth active region. 10 . The ternary content addressable memory as claimed in claim 1 , further comprising two dummy gate lines crossing the first active region.

11. A two-port static random access memory, characterized in that: include: Storage unit, comprising: A first active region extending along a first direction; A second active area extending along the first direction; A third active area extending along the first direction; A fourth active region extending along the first direction, wherein the first active region, the second active region, the third active region and the fourth active region are arranged in sequence along the second direction; A first gate line spans across the third active region and the fourth active region and extends along the second direction; A second gate line spans across the fourth active region and extends along the second direction; A third gate line spans across the first active region and extends along the second direction; and a fourth gate line, crossing the first active region and the second active region and extending along the second direction; and Two read transistors are electrically connected to the memory cell, wherein the combination of the two read transistors and the memory cell are arranged along the first direction.

12. The two-port static random access memory as described in claim 11 further includes a first insulating block and a second insulating block, the first insulating block is arranged on a side of the first active region relative to the second active region, and the second insulating block is arranged on a side of the fourth active region relative to the third active region, wherein the width of the first insulating block in the second direction is equal to the width of the second insulating block in the second direction. 13 . The two-port static random access memory as claimed in claim 11 , wherein the source / drain and drain / source of the two read transistors are disposed in the fourth active region. 14 . The two-port static random access memory as claimed in claim 11 , wherein the first gate line and the fourth gate line have the same length in the second direction.

15. The two-port static random access memory as claimed in claim 11, further comprising another memory cell and another two read transistors, wherein the memory cell and the another memory cell are arranged along the first direction, and the memory cell and the another memory cell are disposed between the two read transistors and the other two read transistors. 16 . The two-port static random access memory as claimed in claim 11 , wherein one of the two read transistors comprises a fifth gate line crossing the fourth active region. 17 . The two-port static random access memory as claimed in claim 16 , wherein the first gate line and the fifth gate line are mirror-symmetrical with respect to the second direction as a symmetry axis. 18 . The two-port static random access memory as claimed in claim 16 , further comprising a connecting line connected to the first gate line and the fifth gate line. 19 . The two-port static random access memory as claimed in claim 11 , wherein one of the two read transistors comprises a sixth gate line crossing the fourth active region.

20. The two-port static random access memory as claimed in claim 11, further comprising two dummy gate lines crossing the first active region.

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