Display substrate, manufacturing method thereof, and display device

Abstract

A display substrate, a manufacturing method thereof, and a display device. The display substrate includes a plurality of sub-pixels, and a pixel driving circuit in the sub-pixel includes a driving transistor and a storage capacitor; the display substrate includes a semiconductor layer, a first conductive layer, and a second conductive layer sequentially disposed on a substrate; the semiconductor layer at least includes an active layer of the driving transistor, the first conductive layer at least includes a first electrode plate, the second conductive layer at least includes a second electrode plate and an electrode plate connection line, and the electrode plate connection line connects the second electrode plates in adjacent sub-pixels in a first direction; the active layer of the driving transistor at least includes a channel region, and the channel region has a second-direction effective length in a second direction; there is an overlapping region between the orthographic projection of the electrode plate connection line on the substrate and the orthographic projection of the semiconductor layer on the substrate, and the distance between the overlapping region and the channel region of the driving transistor is greater than or equal to the second-direction effective length.

Description

Technical Field

[0001] This document relates to the field of display technologies, and particularly to a display substrate, a manufacturing method thereof, and a display device. Background Art

[0002] An organic light-emitting diode (OLED) is an active light-emitting display device, which has the advantages of self-luminescence, wide viewing angle, high contrast ratio, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technologies, a flexible display device that uses an OLED as a light-emitting device and is signal-controlled by a thin film transistor (TFT) has become the mainstream product in the current display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this document. This overview is not intended to limit the scope of protection of the claims.

[0004] The present disclosure provides a display substrate. In a plane parallel to the display substrate, the display substrate includes a plurality of sub-pixels, and at least one sub-pixel includes a pixel driving circuit and a light-emitting device connected to the pixel driving circuit. The pixel driving circuit at least includes a driving transistor and a storage capacitor. In a plane perpendicular to the display substrate, the display substrate includes a semiconductor layer, a first conductive layer, and a second conductive layer sequentially disposed on a substrate. The semiconductor layer at least includes an active layer of the driving transistor. The first conductive layer at least includes a first electrode plate of the storage capacitor. The second conductive layer at least includes a second electrode plate of the storage capacitor and an electrode plate connection line. The electrode plate connection line connects the second electrode plates in adjacent sub-pixels in a first direction. The first direction is the direction of the sub-pixel row.

[0005] The active layer of the driving transistor at least includes a channel region. The channel region at least includes a first channel segment extending in the first direction and a second channel segment extending in a second direction. The second direction is the direction of the sub-pixel column. The channel region has an effective length in the second direction, and the effective length in the second direction is the length of the second channel segment in the second direction.

[0006] The orthographic projection of the electrode plate connection line on the substrate and the orthographic projection of the semiconductor layer on the substrate have an overlapping region, and the distance between the overlapping region and the channel region of the driving transistor is greater than or equal to the effective length in the second direction.

[0007] In an exemplary embodiment, the active layer of the driving transistor further includes a first region and a second region respectively connected to the channel region, and the semiconductor layer in the overlapping region includes the second region of the driving transistor.

[0008] In an exemplary embodiment, the channel region of the driving transistor includes a first channel segment, a second channel segment, a third channel segment, a fourth channel segment, and a fifth channel segment; a first end of the first channel segment is connected to the first region, and a second end of the first channel segment extends in a first direction and then is connected to a first end of the second channel segment; a second end of the second channel segment extends in a direction opposite to a second direction and then is connected to a first end of the third channel segment; a second end of the third channel segment extends in the first direction and then is connected to a first end of the fourth channel segment; a second end of the fourth channel segment extends in the second direction and then is connected to a first end of the fifth channel segment; a second end of the fifth channel segment extends in the first direction and then is connected to the second region;

[0009] The distance between the overlapping region and the channel region of the driving transistor is the distance between an edge of the overlapping region adjacent to a second direction side of the fifth channel segment and an edge of the fifth channel segment adjacent to a second direction side of the overlapping region.

[0010] In an exemplary embodiment, the distance between the overlapping region and the channel region of the driving transistor is greater than or equal to 1.5 μm.

[0011] In an exemplary embodiment, the distance between the overlapping region and the channel region of the driving transistor is 1.6 μm to 4.5 μm.

[0012] In an exemplary embodiment, the pixel driving circuit further includes a third conductive layer, the third conductive layer at least includes a first power line, and the first power line is connected to the second electrode plate through a power via; an opening is provided in the middle of the second electrode plate, and the power via is provided between the opening and the overlapping region.

[0013] In an exemplary embodiment, the distance between an edge of the power via adjacent to a first direction side of the opening and an edge of the opening adjacent to a first direction side of the power via is greater than or equal to the distance between an edge of the power via adjacent to a first direction side of the overlapping region and an edge of the overlapping region adjacent to a first direction side of the power via.

[0014] In an exemplary embodiment, the distance between an edge of the power via adjacent to a first direction side of the opening and an edge of the opening adjacent to a first direction side of the power via is greater than or equal to 0.85 μm.

[0015] In an exemplary embodiment, the distance between the edge of the power via adjacent to one side of the opening in the first direction and the edge of the opening adjacent to one side of the power via in the first direction is 1.5 μm to 3.0 μm.

[0016] In an exemplary embodiment, the distance between the edge of the power via adjacent to one side of the overlapping region in the first direction and the edge of the overlapping region adjacent to one side of the power via in the first direction is greater than or equal to 0.6 μm.

[0017] In an exemplary embodiment, the distance between the edge of the power via adjacent to one side of the overlapping region in the first direction and the edge of the overlapping region adjacent to one side of the power via in the first direction is 1.2 μm to 3.0 μm.

[0018] In an exemplary embodiment, the conductivity of the second region of the driving transistor is greater than the conductivity of the channel region of the driving transistor.

[0019] The present disclosure also provides a display device, including the aforementioned display substrate.

[0020] The present disclosure also provides a method for manufacturing a display substrate. In a plane parallel to the display substrate, the display substrate includes a plurality of sub-pixels, and at least one sub-pixel includes a pixel driving circuit and a light-emitting device connected to the pixel driving circuit. The pixel driving circuit at least includes a driving transistor and a storage capacitor. The manufacturing method includes:

[0021] Forming a semiconductor layer, a first conductive layer, and a second conductive layer on a substrate in sequence; the semiconductor layer at least includes an active layer of the driving transistor, the first conductive layer at least includes a first electrode plate of the storage capacitor, the second conductive layer at least includes a second electrode plate of the storage capacitor and an electrode plate connection line, and the electrode plate connection line connects the second electrode plates in adjacent sub-pixels in a first direction; the first direction is the direction of the sub-pixel row.

[0022] The active layer of the driving transistor at least includes a channel region, and the channel region at least includes a first channel segment extending in a first direction and a second channel segment extending in a second direction. The second direction is the direction of the sub-pixel column; the channel region has an effective length in the second direction, and the effective length in the second direction is the length of the second channel segment in the second direction.

[0023] The positive projection of the electrode plate connection line on the substrate and the positive projection of the semiconductor layer on the substrate have an overlapping region, and the distance between the overlapping region and the channel region of the driving transistor is greater than or equal to the effective length in the second direction.

[0024] In an exemplary embodiment, the manufacturing method further includes:

[0025] A third conductive layer is formed. The third conductive layer at least includes a first power line, and the first power line is connected to the second electrode plate through a power via. An opening is provided on the second electrode plate, and the power via is provided between the opening and the overlapping region. The distance between the edge of the power via adjacent to one side of the opening in the first direction and the edge of the opening adjacent to the power via in the first direction is greater than or equal to the distance between the edge of the power via adjacent to one side of the overlapping region in the first direction and the edge of the overlapping region adjacent to the power via in the first direction.

[0026] Other aspects will be apparent after reading and understanding the drawings and the detailed description. Description of the Drawings

[0027] The drawings are used to provide an understanding of the technical solutions of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation to the technical solutions of the present disclosure.

[0028] Figure 1 It is a schematic structural diagram of a display device;

[0029] Figure 2 It is a schematic plan view of a display substrate;

[0030] Figure 3 It is a schematic cross-sectional view of a display substrate;

[0031] Figure 4 It is a schematic equivalent circuit diagram of a pixel driving circuit;

[0032] Figure 5 It is a timing diagram of the operation of a pixel driving circuit;

[0033] Figure 6 It is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0034] Figure 7 It is a schematic diagram after forming a semiconductor layer pattern according to an exemplary embodiment of the present disclosure;

[0035] Figure 8 It is a schematic diagram after forming a first conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0036] Figure 9a It is a schematic diagram after forming a second conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0037] Figure 9b It is Figure 9a an enlarged view of the second electrode plate region in

[0038] Figure 9cis Figure 9b A cross-sectional view taken along the A-A direction in

[0039] Figure 9d is Figure 9b A cross-sectional view taken along the B-B direction in

[0040] Figure 10a A schematic diagram after forming a pattern of the fourth insulating layer in an exemplary embodiment of the present disclosure;

[0041] Figure 10b is Figure 10a An enlarged view of the second electrode plate region in

[0042] Figure 10c is Figure 10b A cross-sectional view taken along the A-A direction in

[0043] Figure 10d is Figure 10b A cross-sectional view taken along the B-B direction in

[0044] Figure 11a A schematic diagram after forming a pattern of the third conductive layer in an exemplary embodiment of the present disclosure;

[0045] Figure 11b is Figure 11a A cross-sectional view taken along the B-B direction in

[0046] Figure 12 A schematic diagram after forming a pattern of the fifth insulating layer in an exemplary embodiment of the present disclosure;

[0047] Figure 13 A schematic diagram after forming a pattern of the fourth conductive layer in an exemplary embodiment of the present disclosure.

[0048] Description of reference numerals:

[0049] 11—First active layer; 12—Second active layer; 13—Third active layer;

[0050] 14—Fourth active layer; 15—Fifth active layer; 16—Sixth active layer;

[0051] 17—Seventh active layer; 18—Channel region; 21—First scan signal line;

[0052] 22—Second scan signal line; 23—Light emission control line; 24—First electrode plate;

[0053] 31—Initial signal line; 32—Second electrode plate; 33—Shielding electrode;

[0054] 34—Opening; 35—Electrode plate connection line; 36—Overlap region;

[0055] 41—the first power supply line; 42—the second pole of the first transistor; 43—the first pole of the seventh transistor;

[0056] 44—the first pole of the fourth transistor; 45—the first pole of the fifth transistor; 46—the second pole of the sixth transistor;

[0057] 51—the data signal line; 52—the anode connection electrode; 61—the first insulating layer;

[0058] 62—the second insulating layer; 63—the third insulating layer; 64—the fourth insulating layer;

[0059] 101—the substrate; 102—the driving circuit layer; 103—the light-emitting device;

[0060] 104—the encapsulation layer; 301—the anode; 302—the pixel definition layer;

[0061] 303—the organic light-emitting layer; 304—the cathode; 401—the first encapsulation layer;

[0062] 402—the second encapsulation layer; 403—the third encapsulation layer. Detailed implementation manners

[0063] In order to make the objectives, technical solutions and advantages of the present disclosure clearer and more understandable, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation manners can be implemented in multiple different forms. It is easy for those of ordinary skill in the art to understand the fact that the manners and contents can be transformed into various forms without departing from the gist and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited only to the contents described in the following implementation manners. Without conflict, the embodiments and the features in the embodiments in the present disclosure can be combined with each other arbitrarily.

[0064] In the drawings, sometimes for clarity, the sizes, thicknesses of layers or regions of the respective components are exaggerated. Therefore, one manner of the present disclosure is not necessarily limited to such dimensions, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and one manner of the present disclosure is not limited to the shapes or values shown in the drawings.

[0065] The ordinal numbers such as "first", "second", "third", etc. in this specification are set to avoid confusion of the components, rather than to limit in terms of quantity.

[0066] In this specification, for convenience, terms indicating orientation or positional relationships such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationships of the constituent elements with reference to the accompanying drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation on the present disclosure. The positional relationships of the constituent elements are appropriately changed according to the directions describing the constituent elements. Therefore, it is not limited to the terms described in the specification and can be appropriately replaced according to the circumstances.

[0067] In this specification, unless otherwise clearly defined and limited, the terms "mounted", "connected", and "coupled" shall be construed broadly. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be a direct connection, an indirect connection through an intermediate member, or a communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0068] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region where current mainly flows.

[0069] In this specification, the first pole can be the drain electrode and the second pole can be the source electrode, or the first pole can be the source electrode and the second pole can be the drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, etc., the functions of the "source electrode" and "drain electrode" sometimes swap with each other. Therefore, in this specification, the "source electrode" and "drain electrode" can swap with each other.

[0070] In this specification, "electrically connected" includes the case where the constituent elements are connected together through an element having a certain electrical effect. There is no particular limitation on the "element having a certain electrical effect" as long as it can transfer electrical signals between the constituent elements that can be connected. Examples of the "element having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0071] In this specification, "parallel" means a state where the angle formed by two straight lines is more than -10° and less than 10°, and thus also includes a state where the angle is more than -5° and less than 5°. Additionally, "perpendicular" means a state where the angle formed by two straight lines is more than 80° and less than 100°, and thus also includes a state where the angle is more than 85° and less than 95°.

[0072] In this specification, "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be changed to "conductive film". Similarly, sometimes "insulating film" can be changed to "insulating layer".

[0073] "About" in the present disclosure means not strictly defining the boundary and allowing values within the range of process and measurement errors.

[0074] Figure 1 It is a schematic structural diagram of a display device. As Figure 1 shown, the OLED display device may include a scan signal driver, a data signal driver, a light emission signal driver, an OLED display substrate, a first power supply unit, a second power supply unit, and an initial power supply unit. In an exemplary embodiment, the OLED display substrate at least includes a plurality of scan signal lines (S1 to S N ), a plurality of data signal lines (D1 to D M ), and a plurality of light emission signal lines (EM1 to EM N ). The scan signal driver is configured to sequentially provide scan signals to the plurality of scan signal lines (S1 to S N ), the data signal driver is configured to provide data signals to the plurality of data signal lines (D1 to D M ), and the light emission signal driver is configured to sequentially provide light emission control signals to the plurality of light emission signal lines (EM1 to EM N ). In an exemplary embodiment, the plurality of scan signal lines and the plurality of light emission signal lines extend along the horizontal direction. The display device includes a plurality of sub-pixels, each sub-pixel includes a pixel driving circuit and a light emitting device, and the pixel driving circuit of one sub-pixel can be connected to one scan signal line, one light emission control line, and one data signal line. The first power supply unit, the second power supply unit, and the initial power supply unit are respectively configured to provide a first power supply voltage, a second power supply voltage, and an initial power supply voltage to the pixel driving circuit through a first power supply line, a second power supply line, and an initial signal line.

[0075] Figure 2 It is a schematic plan view of a display substrate. As Figure 2As shown, the display substrate may include a plurality of pixel units P arranged in a matrix. At least one of the plurality of pixel units P includes a first sub-pixel P1 that emits light of a first color, a second sub-pixel P2 that emits light of a second color, and a third sub-pixel P3 that emits light of a third color. The first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 each include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting devices in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the pixel driving circuits of the respective sub-pixels, and the light-emitting devices are configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuits of the respective sub-pixels.

[0076] In an exemplary embodiment, the pixel unit P may include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel, or may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white (W) sub-pixel. The present disclosure does not limit this here. In an exemplary embodiment, the shape of the sub-pixel in the pixel unit may be rectangular, diamond-shaped, pentagonal, or hexagonal. When the pixel unit includes three sub-pixels, the three sub-pixels may be arranged in a horizontal side-by-side, vertical side-by-side, or triangular (pinzi) manner. When the pixel unit includes four sub-pixels, the four sub-pixels may be arranged in a horizontal side-by-side, vertical side-by-side, or square manner. The present disclosure does not limit this here.

[0077] Figure 3 It is a schematic cross-sectional structure diagram of a display substrate, showing the structures of three sub-pixels of an OLED display substrate. As Figure 3 shown, in a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 102 provided on a substrate 101, a light-emitting device 103 provided on a side of the driving circuit layer 102 away from the substrate 1, and a packaging layer 104 provided on a side of the light-emitting device 103 away from the substrate 1. In some possible implementation manners, the display substrate may include other film layers, such as spacers, etc. The present disclosure does not limit this here.

[0078] In an exemplary embodiment, the driving circuit layer 102 of each sub-pixel may include a plurality of transistors and a storage capacitor that constitute a pixel driving circuit. Figure 3Taking the example that each sub-pixel includes a driving transistor and a storage capacitor, it is schematically illustrated. In some possible implementation manners, the driving circuit layer 102 of each sub-pixel may include: a first insulating layer disposed on a substrate; an active layer disposed on the first insulating layer; a second insulating layer covering the active layer; a gate electrode and a first electrode plate disposed on the second insulating layer; a third insulating layer covering the gate electrode and the first electrode plate; a second electrode plate disposed on the third insulating layer; a fourth insulating layer covering the second electrode plate, through holes are formed in the second insulating layer, the third insulating layer and the fourth insulating layer, and the through holes expose the active layer; a source electrode and a drain electrode disposed on the fourth insulating layer, the source electrode and the drain electrode are respectively connected to the active layer through the through holes; a planarization layer covering the foregoing structure, through holes are formed in the planarization layer, and the through holes expose the drain electrode. The active layer, the gate electrode, the source electrode and the drain electrode form a driving transistor 210, and the first electrode plate and the second electrode plate form a storage capacitor 211.

[0079] In an exemplary embodiment, the light-emitting device 103 may include an anode 301, a pixel defining layer 302, an organic light-emitting layer 303 and a cathode 304. The anode 301 is disposed on the planarization layer and is connected to the drain electrode of the driving transistor 210 through a through hole formed in the planarization layer; the pixel defining layer 302 is disposed on the anode 301 and the planarization layer, a pixel opening is provided on the pixel defining layer 302, and the pixel opening exposes the anode 301; the organic light-emitting layer 303 is at least partially disposed in the pixel opening, and the organic light-emitting layer 303 is connected to the anode 301; the cathode 304 is disposed on the organic light-emitting layer 303, and the cathode 304 is connected to the organic light-emitting layer 303; the organic light-emitting layer 303 emits light of a corresponding color under the drive of the anode 301 and the cathode 304.

[0080] In an exemplary embodiment, the encapsulation layer 104 may include a stacked first encapsulation layer 401, a second encapsulation layer 402 and a third encapsulation layer 403. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of an inorganic material, the second encapsulation layer 402 may be made of an organic material, and the second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403, which can ensure that external moisture cannot enter the light-emitting device 103.

[0081] In an exemplary embodiment, the organic light-emitting layer 303 may at least include a hole injection layer, a hole transport layer, a light-emitting layer and a hole blocking layer stacked on the anode 301. In an exemplary embodiment, the hole injection layers of all sub-pixels are a common layer connected together, the hole transport layers of all sub-pixels are a common layer connected together, the light-emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the hole blocking layers are a common layer connected together.

[0082] In an exemplary embodiment, the pixel driving circuit may have a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure. Figure 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit. As Figure 4 shown, the pixel driving circuit may include seven switching transistors (a first transistor T1 to a seventh transistor T7), one storage capacitor C, and seven signal lines (a data signal line DATA, a first scan signal line S1, a second scan signal line S2, an initial signal line INIT, a first power supply line VDD, a second power supply line VSS, and a light emitting signal line EM).

[0083] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the second scan signal line S2, the first pole of the first transistor T1 is connected to the initial signal line INIT, and the second pole of the first transistor is connected to the second node N2. The gate electrode of the second transistor T2 is connected to the first scan signal line S1, the first pole of the second transistor T2 is connected to the second node N2, and the second pole of the second transistor T2 is connected to the third node N3. The gate electrode of the third transistor T3 is connected to the second node N2, the first pole of the third transistor T3 is connected to the first node N1, and the second pole of the third transistor T3 is connected to the third node N3. The gate electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first pole of the fourth transistor T4 is connected to the data signal line DATA, and the second pole of the fourth transistor T4 is connected to the first node N1. The gate electrode of the fifth transistor T5 is connected to the light emitting signal line EM, the first pole of the fifth transistor T5 is connected to the first power supply line VDD, and the second pole of the fifth transistor T5 is connected to the first node N1. The gate electrode of the sixth transistor T6 is connected to the light emitting signal line EM, the first pole of the sixth transistor T6 is connected to the third node N3, and the second pole of the sixth transistor T6 is connected to the first pole of the light emitting device. The gate electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first pole of the seventh transistor T7 is connected to the initial signal line INIT, and the second pole of the seventh transistor T7 is connected to the first pole of the light emitting device. The first end of the storage capacitor C is connected to the first power supply line VDD, and the second end of the storage capacitor C is connected to the second node N2.

[0084] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be P-type transistors, or may be N-type transistors. Using transistors of the same type in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementation manners, the first transistor T1 to the seventh transistor T7 may include P-type transistors and N-type transistors.

[0085] In an exemplary embodiment, the second pole of the light-emitting device is connected to the second power supply line VSS, the signal of the second power supply line VSS is a low-level signal, and the signal of the first power supply line VDD is a continuously provided high-level signal. The first scan signal line S1 is the scan signal line in the pixel driving circuit of the current display row, and the second scan signal line S2 is the scan signal line in the pixel driving circuit of the previous display row. That is, for the nth display row, the first scan signal line S1 is S(n), and the second scan signal line S2 is S(n - 1). The second scan signal line S2 of the current display row and the first scan signal line S1 in the pixel driving circuit of the previous display row can be the same signal line to reduce the signal lines of the display panel and achieve a narrow border of the display panel.

[0086] In an exemplary embodiment, the first scan signal line S1, the second scan signal line S2, the light-emitting signal line EM, and the initial signal line INIT extend in the horizontal direction, and the second power supply line VSS, the first power supply line VDD, and the data signal line DATA extend in the vertical direction.

[0087] In an exemplary embodiment, the light-emitting device may be an organic light-emitting diode (OLED), including a stacked first pole (anode), an organic light-emitting layer, and a second pole (cathode).

[0088] Figure 5 It is a timing diagram of the operation of a pixel driving circuit. The following Figure 4 illustrates the working process of the exemplary pixel driving circuit to explain the exemplary embodiments of the present disclosure. Figure 4 The pixel driving circuit in the embodiment includes seven transistors (the first transistor T1 to the sixth transistor T7), one storage capacitor C, and seven signal lines (the data signal line DATA, the first scan signal line S1, the second scan signal line S2, the initial signal line INIT, the first power supply line VDD, the second power supply line VSS, and the light-emitting signal line EM). All seven transistors are P-type transistors.

[0089] In an exemplary embodiment, the working process of the pixel driving circuit may include:

[0090] The first stage A1, called the reset stage, the signal of the second scan signal line S2 is a low-level signal, and the signals of the first scan signal line S1 and the light-emitting signal line EM are high-level signals. The signal of the second scan signal line S2 being a low-level signal turns on the first transistor T1, and the signal of the initial signal line INIT is provided to the second node N2 to initialize the storage capacitor C and clear the original data voltage in the storage capacitor. The signals of the first scan signal line S1 and the light-emitting signal line EM being high-level signals turn off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. In this stage, the OLED does not emit light.

[0091] The second stage A2, known as the data writing stage or the threshold compensation stage, has a low-level signal on the first scan signal line S1, high-level signals on the second scan signal line S2 and the emission signal line EM, and the data signal line DATA outputs a data voltage. In this stage, since the second end of the storage capacitor C is at a low level, the third transistor T3 is turned on. The low-level signal on the first scan signal line S1 turns on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The conduction of the second transistor T2 and the fourth transistor T4 causes the data voltage output by the data signal line DATA to be provided to the second node N2 through the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the difference between the data voltage output by the data signal line DATA and the threshold voltage of the third transistor T3 is charged into the storage capacitor C. The voltage at the second end (the second node N2) of the storage capacitor C is Vdata - |Vth|, where Vdata is the data voltage output by the data signal line DATA and Vth is the threshold voltage of the third transistor T3. The conduction of the seventh transistor T7 provides the initial voltage of the initial signal line INIT to the first pole of the OLED to initialize (reset) the first pole of the OLED, clear the pre-stored voltage inside it, complete the initialization, and ensure that the OLED does not emit light. The high-level signal on the second scan signal line S2 turns off the first transistor T1. The high-level signal on the emission signal line EM turns off the fifth transistor T5 and the sixth transistor T6.

[0092] The third stage A3, known as the emission stage, has a low-level signal on the emission signal line EM and high-level signals on the first scan signal line S1 and the second scan signal line S2. The low-level signal on the emission signal line EM turns on the fifth transistor T5 and the sixth transistor T6, and the power supply voltage output by the first power supply line VDD provides a driving voltage to the first pole of the OLED through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6 to drive the OLED to emit light.

[0093] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by the voltage difference between its gate electrode and the first pole. Since the voltage at the second node N2 is Vdata - |Vth|, the driving current of the third transistor T3 is:

[0094] I = K * (Vgs - Vth) 2 = K * [(Vdd - Vdata + |Vth|) - Vth] 2 = K * [(Vdd - Vdata] 2

[0095] Wherein, I is the driving current flowing through the third transistor T3, which is also the driving current for driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data signal line DATA, and Vdd is the power supply voltage output by the first power supply line VDD.

[0096] Figure 6 FIG. 4 is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure, showing the planar structure of a sub-pixel. As Figure 6 shown, in the plane parallel to the display substrate, the sub-pixel of the display substrate is provided with a first scan signal line 21, a second scan signal line 22, a light emission control line 23, an initial signal line 31, a first power supply line 41, a data signal line 51, a pixel driving circuit, and a light emitting device. The pixel driving circuit may include a plurality of transistors, a storage capacitor, a plate connection line 35, and an anode connection electrode 52. The plurality of transistors at least include a driving transistor (third transistor). The third transistor includes an active layer, a gate electrode, a first electrode, and a second electrode. The active layer of the third transistor includes a channel region, a first region, and a second region 13-2. The storage capacitor includes a first plate 24 and a second plate 32.

[0097] In the plane perpendicular to the display substrate, the display substrate may include a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on a substrate. In an exemplary embodiment, the semiconductor layer may include the active layers of a plurality of transistors. The active layer of the third transistor includes a channel region, a first region, and a second region 13-2. The first conductive layer may include a first scan signal line 21, a second scan signal line 22, a light emission control line 23, a first plate 24 of the storage capacitor, and the gate electrodes of a plurality of transistors. The second conductive layer may include an initial signal line 31, a second plate 32 of the storage capacitor, a shielding electrode 33, and a plate connection line 35. The third conductive layer may include a first power supply line 41 and the first and second electrodes of a plurality of transistors. The fourth conductive layer may include a data signal line 51 and an anode connection electrode 52.

[0098] In an exemplary embodiment, the display substrate may further include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer. The first insulating layer is disposed between the substrate and the semiconductor layer. The second insulating layer is disposed between the semiconductor layer and the first conductive layer. The third insulating layer is disposed between the first conductive layer and the second conductive layer. The fourth insulating layer is disposed between the second conductive layer and the third conductive layer. The fifth insulating layer is disposed between the third conductive layer and the fourth conductive layer.

[0099] In an exemplary embodiment, the sub-pixel has a first center line O X and a second center line O Y。The first center line O X is the center line that equally divides sub-pixels in the first direction X, and the first center line O X extends along the second direction Y. The second center line O Y is the center line that equally divides sub-pixels in the second direction Y, and the second center line O Y extends along the first direction X. In an exemplary embodiment, the first direction X may be the direction of sub-pixel rows (horizontal direction), and the second direction Y may be the direction of sub-pixel columns (vertical direction).

[0100] In an exemplary embodiment, along the first direction X, the sub-pixels may be divided into a first horizontal region H1, a second horizontal region H2, and a third horizontal region H3. That is, the first horizontal region H1 is located on one side of the first center line O X , the third horizontal region H3 is located on the other side of the first center line O X , and the second horizontal region H2 is located between the first horizontal region H1 and the third horizontal region H3. In an exemplary embodiment, the first length of the first horizontal region H1 may be greater than or equal to the first length of the second horizontal region H2, and the first length of the third horizontal region H3 may be greater than or equal to the first length of the second horizontal region H2. In the exemplary embodiment of the present disclosure, the first length refers to the dimension in the first direction X.

[0101] In an exemplary embodiment, along the second direction Y, the sub-pixels may be divided into a first vertical region R1, a second vertical region R2, and a third vertical region R3. The second vertical region R2 is located between the first vertical region R1 and the third vertical region R3. In an exemplary embodiment, the second length of the first vertical region R1 may be greater than the second length of the second vertical region R2, and the second length of the second vertical region R2 may be greater than the second length of the third vertical region R3. In the exemplary embodiment of the present disclosure, the second length refers to the dimension in the second direction Y.

[0102] In an exemplary embodiment, the sum of the second length of the second vertical region R2 and the second length of the third vertical region R3 may be equal to the second length of the first vertical region R1. That is, the first vertical region R1 is located on one side of the second center line O Y , the second vertical region R2 is located on the other side of the second center line O Y , and the third vertical region R3 is located on the side of the second vertical region R2 away from the first vertical region R1.

[0103] In an exemplary embodiment, the main body portion of the data signal line 51 extending along the second direction Y is located in the first horizontal region H1, and the main body portion of the first power supply line 41 extending along the second direction Y is located in the third horizontal region H3.

[0104] In an exemplary embodiment, a first scan signal line 21, a second scan signal line 22, and an initial signal line 31 extending along a first direction X are located in a first longitudinal region R1, a first electrode plate 24 and a second electrode plate 32 are located in a second longitudinal region R2, and a light emission control line 23 extending along the first direction X is located in a third longitudinal region R3. In the exemplary embodiment, the first electrode plate 24 and the second electrode plate 32 form a storage capacitor of the pixel driving circuit.

[0105] In an exemplary embodiment, the plurality of transistors of the pixel driving circuit may include a first transistor to a seventh transistor. A gate electrode of the first transistor is connected to the second scan signal line 22, a first pole of the first transistor is connected to the initial signal line 31, and a second pole of the first transistor is respectively connected to a first pole of the second transistor, a gate electrode of the third transistor, and the first electrode plate 24. A gate electrode of the second transistor is connected to the first scan signal line 21, and a second pole of the second transistor is respectively connected to a second pole of the third transistor and a first pole of the sixth transistor. A first pole of the third transistor is respectively connected to a second pole of the fourth transistor and a second pole of the fifth transistor. A gate electrode of the fourth transistor is connected to the first scan signal line 21, and a first pole of the fourth transistor is connected to the data signal line 51. A gate electrode of the fifth transistor is connected to the light emission signal line 23, and a first pole of the fifth transistor is respectively connected to a first power supply line 41 and the second electrode plate 32. A gate electrode of the sixth transistor is connected to the light emission signal line 23, and a second pole of the sixth transistor is respectively connected to a second pole of the seventh transistor T7 and a first pole of the light emitting device. A gate electrode of the seventh transistor is connected to the first scan signal line 21, a first pole of the seventh transistor is connected to the initial signal line 31, and a second pole of the seventh transistor is respectively connected to a second pole of the sixth transistor and a first pole of the light emitting device.

[0106] In an exemplary embodiment, a first via V1 is formed in a third insulating layer and a fourth insulating layer covering the first electrode plate 24, and a second pole 42 of the first transistor is connected to the first electrode plate 24 through the first via V1.

[0107] In an exemplary embodiment, a second via V2 is formed in the fourth insulating layer covering the second electrode plate 32, and the first power supply line 41 is connected to the second electrode plate 32 through the second via V2.

[0108] In an exemplary embodiment, a second region 13-2 of the third active layer is disposed in the semiconductor layer, a first end thereof is connected to a channel region of the third transistor (driving transistor), a second end is connected to an active layer of the second transistor, and a third end is connected to an active layer of the sixth transistor.

[0109] In an exemplary embodiment, the plate connection line 35 is disposed in the second conductive layer. The plate connection line 35 is linear and parallel to the first direction X. The first end of the plate connection line 35 is connected to the second plate 32 of the subpixel, and the second end extends along the first direction X or the opposite direction of the first direction X and is connected to the second plate 32 of the adjacent subpixel.

[0110] In an exemplary embodiment, an opening 34 is provided on the second plate 32. The opening 34 is located in the transverse second region H2, and the orthographic projection of the opening 34 on the substrate includes the orthographic projection of the first via V1 on the substrate.

[0111] As Figure 6 and in combination with Figures 7 to 9d shown, there is an overlapping region 36 between the orthographic projection of the semiconductor layer (the second region 13-2 of the third active layer) on the substrate and the orthographic projection of the plate connection line 35 on the substrate. The distance L2 between the overlapping region 36 and the channel region of the third transistor may be greater than or equal to the effective length in the second direction of the channel region of the third transistor. The third transistor is a driving transistor, and the active layer of the third transistor includes at least a channel region. The channel region includes at least a first channel segment extending along the first direction X and a second channel segment extending along the second direction Y. The effective length in the second direction is the length of the second channel segment in the second direction Y.

[0112] In an exemplary embodiment, the distance L2 may be greater than or equal to 1.5 μm. In some possible implementation manners, the distance L2 may be approximately 1.6 μm to 4.5 μm. In some other possible implementation manners, the distance L2 may be approximately 2.5 μm to 4.5 μm.

[0113] The display substrate provided by the exemplary embodiment of the present disclosure effectively reduces the influence of the overlapping capacitance on the third transistor for transmitting data signals, reduces the load, reduces the power consumption, and improves the display effect by setting the distance between the overlapping region and the channel region of the third transistor.

[0114] In an exemplary embodiment, the distance L3 between the edge of the second via V2 adjacent to the opening 34 and the edge of the opening 34 adjacent to the second via V2 may be greater than or equal to the distance L4 between the edge of the second via V2 adjacent to the overlapping region 36 and the edge of the overlapping region 36 adjacent to the second via V2.

[0115] In an exemplary embodiment, the distance L3 may be greater than or equal to 0.85 μm. In some possible implementation manners, the distance L3 may be approximately 1.5 μm to 3.0 μm. In some other possible implementation manners, the distance L3 may be approximately 2.0 μm to 3.0 μm.

[0116] In an exemplary embodiment, the spacing L4 may be greater than or equal to 0.6 μm. In some possible implementations, the spacing L4 may be approximately 1.2 μm to 3.0 μm. In some other possible implementations, the spacing L4 may be approximately 2.0 μm to 3.0 μm.

[0117] The display substrate provided by the exemplary embodiment of the present disclosure improves the process margin, avoids short circuits, and improves the yield by setting the spacing between the second via hole and the opening and the spacing between the second via hole and the overlapping region.

[0118] The following is an exemplary description through the manufacturing process of the display substrate. The "patterning process" mentioned in the present disclosure, for metal materials, inorganic materials, or transparent conductive materials, includes processes such as coating photoresist, mask exposure, development, etching, and photoresist stripping. For organic materials, it includes processes such as coating organic materials, mask exposure, and development. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition. Coating can be carried out by any one or more of spraying, spin coating, and inkjet printing. Etching can be carried out by any one of dry etching and wet etching. The present disclosure does not make any limitations. A "thin film" refers to a thin film made of a certain material on a substrate by using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire manufacturing process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The statement "A and B are arranged in the same layer" in the present disclosure means that A and B are formed simultaneously through the same patterning process. The "thickness" of a film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiment of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. "The orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0119] In an exemplary embodiment, the manufacturing process of the display substrate may include the following operations.

[0120] (1) Form a semiconductor layer pattern. In the exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film through a patterning process to form a first insulating layer covering the substrate, and a semiconductor layer provided on the first insulating layer, as Figure 7 shown.

[0121] In an exemplary embodiment, the semiconductor layer of each sub-pixel may include a first active layer of a first transistor T1 to a seventh active layer of a seventh transistor T7, and the first active layer of the first transistor T1 to the seventh active layer of the seventh transistor T7 are an integrally connected structure.

[0122] In an exemplary embodiment, the first active layer 11 of the first transistor T1, the second active layer 12 of the second transistor T2, the fourth active layer 14 of the fourth transistor T4, and the seventh active layer 17 of the seventh transistor T7 are disposed in a first longitudinal region R1, the third active layer 13 of the third transistor T3 is disposed in a second longitudinal region R2, and the fifth active layer 15 of the fifth transistor T5 and the sixth active layer 16 of the sixth transistor T6 are disposed in a third longitudinal region R3. The first active layer 11 to the seventh active layer 17 are disposed on one side of the first longitudinal region R1 away from the second longitudinal region R2, and the second active layer 12 and the fourth active layer 14 are disposed on one side of the first longitudinal region R1 adjacent to the second longitudinal region R2.

[0123] In an exemplary embodiment, the first active layer 11 is in an "n" shape, the seventh active layer 17 is in an "L" shape, and the seventh active layer 17 is located on a side of the first active layer 11 away from the first center line O X The second active layer 12 is in a "7" shape and is located in a third transverse region H3. The fourth active layer 14 is in a "1" shape and is located in a first transverse region H1. The third active layer 13 is in a "ji" shape, and the "ji" shape may be mirror-symmetrical with respect to the first center line O X The fifth active layer 15 is in an "L" shape and is located in the first transverse region H1. The sixth active layer 16 is located in the third transverse region H3, and the shape of the sixth active layer 16 may be mirror-symmetrical with respect to the first center line O X with the shape of the fifth active layer 15.

[0124] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first region and the second region. In an exemplary embodiment, the first region 11-1 of the first active layer 11 serves as the first region 17-1 of the seventh active layer 17 at the same time, the second region 11-2 of the first active layer 11 serves as the first region 12-1 of the second active layer 12 at the same time, the first region 13-1 of the third active layer 13 serves as the second region 14-2 of the fourth active layer 14 and the second region 15-2 of the fifth active layer 15 at the same time, the second region 13-2 of the third active layer 13 serves as the second region 12-2 of the second active layer 12 and the first region 16-1 of the sixth active layer 16 at the same time, and the second region 16-2 of the sixth active layer 16 serves as the second region 17-2 of the seventh active layer 17 at the same time.

[0125] In an exemplary embodiment, a third active layer 13 of a third transistor includes a first region 13-1, a second region 13-2, and a channel region 18. The first region 13-1 of the third active layer 13 serves simultaneously as the second region 14-2 of a fourth active layer 14 and the second region 15-2 of a fifth active layer 15, that is, the first region 13-1 of the third active layer 13, the second region 14-2 of the fourth active layer 14, and the second region 15-2 of the fifth active layer 15 are interconnected. The second region 13-2 of the third active layer 13 serves simultaneously as the second region 12-2 of a second active layer 12 and the first region 16-1 of a sixth active layer 16, that is, the second region 13-2 of the third active layer 13, the second region 12-2 of the second active layer 12, and the first region 16-1 of the sixth active layer 16 are interconnected. The channel region 18 of the third active layer 13 is disposed between the first region 13-1 and the second region 13-2, and both ends of the channel region 18 are respectively connected to the first region 13-1 and the second region 13-2.

[0126] In an exemplary embodiment, the channel region 18 includes a first channel segment 18-1, a third channel segment 18-3, and a fifth channel segment 18-5 extending along a first direction X, and a second channel segment 18-2 and a fourth channel segment 18-4 extending along a second direction Y. A first end of the first channel segment 18-1 is connected to the first region 13-1, and a second end extends along the first direction X and then is connected to a first end of the second channel segment 18-2. The first end of the second channel segment 18-2 is connected to the second end of the first channel segment 18-1, and a second end extends along the opposite direction of the second direction Y and then is connected to a first end of the third channel segment 18-3. The first end of the third channel segment 18-3 is connected to the second end of the second channel segment 18-2, and a second end extends along the first direction X and then is connected to a first end of the fourth channel segment 18-4. The first end of the fourth channel segment 18-4 is connected to the second end of the third channel segment 18-3, and a second end extends along the second direction Y and then is connected to a first end of the fifth channel segment 18-5. The first end of the fifth channel segment 18-5 is connected to the second end of the fourth channel segment 18-4, and a second end extends along the first direction X and then is connected to the second region 13-2, forming a channel region 18 in a shape of "ji".

[0127] In an exemplary embodiment, the channel region 18 has a first-direction length M1 in the first direction X. The first-direction length M1 is the distance between a first end of the first channel segment 18-1 and a second end of the fifth channel segment 18-5, that is, the sum of the lengths of the first channel segment 18-1, the third channel segment 18-3, and the fifth channel segment 18-5 extending along the first direction X.

[0128] In an exemplary embodiment, the channel region 18 has a second-direction effective length L1 in the second direction Y. The second-direction effective length L1 is the distance between the first end and the second end of the second channel segment 18-2, that is, the length that the second end of the second channel segment extends along the second direction Y to the first end, or the distance between the first end and the second end of the fourth channel segment 18-4, that is, the length that the first end of the fourth channel segment extends along the second direction Y to the second end.

[0129] A channel refers to the semiconductor layer between the first region and the second region in the active layer of a transistor. The channel width-to-length ratio is the ratio of the channel width to the channel length and is an important parameter in a transistor. When the channel lengths are the same, the larger the channel width, the faster the speed and the greater the power consumption. When the channel widths are the same, the smaller the channel length, the faster the speed and the greater the power consumption. The channel region 18 is arranged in a "ji" shape to increase the channel length. Figure 7 The channel length shown is M1 + 2*L1. The second-direction effective length L1 affects the channel length value and the channel width-to-length ratio.

[0130] In an exemplary embodiment, in the second stage when the pixel driving circuit is operating, the low-level signal output by the first scanning signal line S1 turns on the second transistor, the fourth transistor, and the seventh transistor. At the same time, the first plate of the storage capacitor being at a low level turns on the third transistor. Therefore, the data voltage output by the data signal line passes through the first region 14-1 of the fourth active layer 14, the first region 13-1 of the third active layer 13 (i.e., the second region 14-2 of the fourth active layer 14), the channel region 18 of the third active layer 13, the second region 13-2 of the third active layer 13 (i.e., the second region 12-2 of the second active layer 12), and the first region 12-1 of the second active layer 12, and the difference between the data voltage output by the data signal line and the threshold voltage of the third transistor T3 is charged into the first plate of the storage capacitor. Since there is an overlap between the second region 13-2 of the third active layer 13 and the plate connection line of the subsequently formed storage capacitor, the second region 13-2 of the third active layer 13 transmits the data signal and the plate connection line transmits the power supply signal. Therefore, an overlap capacitor is formed between the second region 13-2 of the third active layer 13 and the plate connection line. Research shows that this overlap capacitor will affect the transmission of the data signal by the third transistor, causing an increase in the load and power consumption of the pixel driving circuit and reducing the display effect.

[0131] (2) Form a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first metal film on a substrate on which the foregoing pattern is formed, patterning the first metal film through a patterning process to form a second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer. The first conductive layer pattern at least includes: a first scan signal line 21, a second scan signal line 22, a light emission control line 23, and a first electrode plate 24 of a storage capacitor, as Figure 8 shown.

[0132] In an exemplary embodiment, the first scan signal line 21, the second scan signal line 22, and the light emission control line 23 extend along a first direction X. The first scan signal line 21 and the second scan signal line 22 are disposed in a first longitudinal region R1. The second scan signal line 22 is located on a side of the first scan signal line 21 away from a second longitudinal region R2. The light emission control line 23 is disposed in a third longitudinal region R3. The first electrode plate 24 of the storage capacitor is disposed in the second longitudinal region R2 and is located between the first scan signal line 21 and the light emission control line 23.

[0133] In an exemplary embodiment, the first electrode plate 24 may be rectangular, chamfers may be provided at corners of the rectangular shape, and there is an overlapping region between a positive projection of the first electrode plate 24 on the substrate and a positive projection of a third active layer of a third transistor T3 on the substrate. In an exemplary embodiment, the first electrode plate 24 simultaneously serves as a gate electrode of the third transistor T3.

[0134] In an exemplary embodiment, the first scan signal line 21 may be set with non-uniform widths, and the width of the first scan signal line 21 is a dimension of the first scan signal line 21 in a second direction Y. The first scan signal line 21 includes a region overlapping with the semiconductor layer and a region not overlapping with the semiconductor layer. The width of the first scan signal line 21 in the region overlapping with the semiconductor layer may be greater than the width of the first scan signal line 21 in the region not overlapping with the semiconductor layer.

[0135] In an exemplary embodiment, the first scan signal line 21 is provided with a gate block 21-1 protruding toward the second scan signal line 22. There is an overlapping region between a positive projection of the gate block 21-1 on the substrate and a positive projection of a second active layer of a second transistor T2 on the substrate to form a double-gate structure.

[0136] In an exemplary embodiment, the second scan signal line 22 may be set to have a non-uniform width, and the width of the second scan signal line 22 is the dimension of the second scan signal line 22 in the second direction Y. The second scan signal line 22 includes a region overlapping with the seventh active layer of the seventh transistor T7 and other regions, and the width of the second scan signal line 22 in the region overlapping with the seventh active layer of the seventh transistor T7 may be greater than the width of the second scan signal line 22 in other regions.

[0137] In an exemplary embodiment, the light emission control line 23 may be set to have a non-uniform width, and the width of the light emission control line 23 is the dimension of the light emission control line 23 in the second direction Y. The light emission control line 23 includes a region overlapping with the semiconductor layer and a region not overlapping with the semiconductor layer, and the width of the light emission control line 23 in the region overlapping with the semiconductor layer may be greater than the width of the light emission control line 23 in the region not overlapping with the semiconductor layer.

[0138] In an exemplary embodiment, the first electrode plate 24 simultaneously serves as the gate electrode of the third transistor T3, and the region of the third active layer of the third transistor T3 overlapping with the first electrode plate 24 serves as the channel region 18 of the third transistor T3. One end of the channel region 18 is connected to the first region 13-1 of the third active layer, and the other end is connected to the second region 13-2 of the third active layer. The region of the first scan signal line 21 overlapping with the fourth active layer of the fourth transistor T4 serves as the gate electrode of the fourth transistor T4, and the region of the first scan signal line 21 and the gate block 21-1 overlapping with the second active layer of the second transistor T2 serves as the gate electrode (dual gate) of the second transistor T2. The region of the second scan signal line 22 overlapping with the first active layer of the first transistor T1 serves as the gate electrode (dual gate) of the first transistor T1. The region of the second scan signal line 22 overlapping with the seventh active layer of the seventh transistor T7 serves as the gate electrode of the seventh transistor T7. The region of the light emission control line 23 overlapping with the fifth active layer of the fifth transistor T5 serves as the gate electrode of the fifth transistor T5. The region of the light emission control line 23 overlapping with the sixth active layer of the sixth transistor T6 serves as the gate electrode of the sixth transistor T6.

[0139] In an exemplary embodiment, after forming the first conductive layer pattern, the semiconductor layer may be conductorized using the first conductive layer as a mask. The semiconductor layer in the region shielded by the first conductive layer forms the channel regions of the first transistor T1 to the seventh transistor T7, and the semiconductor layer in the region not shielded by the first conductive layer is conductorized, that is, the first regions and the second regions of the first active layer to the seventh active layer are all conductorized.

[0140] (3) Form a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second metal film on the substrate on which the foregoing pattern is formed, patterning the second metal film using a patterning process to form a third insulating layer 63 covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer 63. The second conductive layer pattern at least includes: an initial signal line 31, a second electrode plate 32 of a storage capacitor, a shielding electrode 33, and an electrode plate connection line 35, as Figure 9a , Figure 9b , Figure 9c and Figure 9d shown. Figure 9b is Figure 9a an enlarged view of the second electrode plate region in Figure 9c is Figure 9b a cross-sectional view taken along the A-A direction in Figure 9d is Figure 9b a cross-sectional view taken along the B-B direction in

[0141] As Figure 9a shown, in an exemplary embodiment, the initial signal line 31 extends along the first direction X, is disposed in the longitudinal first region R1, and is located on the side of the second scan signal line 22 away from the longitudinal second region R2. The shielding electrode 33 is disposed in the longitudinal first region R1 and is located between the first scan signal line 21 and the second scan signal line 22. The second electrode plate 32 of the storage capacitor is disposed in the longitudinal second region R2 and is located between the first scan signal line 21 and the light emission control line 23.

[0142] In an exemplary embodiment, the initial signal line 31 may be set to have a non-uniform width. The width of the initial signal line 31 is the dimension of the initial signal line 31 in the second direction Y. The initial signal line 31 includes a region overlapping with the semiconductor layer and a region not overlapping with the semiconductor layer. The width of the initial signal line 31 in the region not overlapping with the semiconductor layer may be greater than the width of the initial signal line 31 in the region overlapping with the semiconductor layer.

[0143] In an exemplary embodiment, the shielding electrode 33 is in an "n" shape and is configured to be connected to a first power supply line formed subsequently to improve the working reliability of the pixel driving circuit.

[0144] In an exemplary embodiment, the profile of the second electrode plate 32 may be rectangular, chamfers may be provided at the corners of the rectangular shape, and there is an overlapping area between the orthographic projection of the second electrode plate 32 on the substrate and the orthographic projection of the first electrode plate 24 on the substrate. An opening 34 is provided on the second electrode plate 32. In the first direction X, the opening 34 may be located in the transverse second region H2, and in the second direction Y, the opening 34 may be located in the middle of the longitudinal second region R2. The opening 34 may be rectangular, causing the second electrode plate 32 to form an annular structure. The opening 34 exposes the third insulating layer 63 covering the first electrode plate 24, and the orthographic projection of the first electrode plate 24 on the substrate includes the orthographic projection of the opening 34 on the substrate. In an exemplary embodiment, the opening 34 is configured to accommodate a subsequently formed first via hole, and the first via hole is located within the opening 34 and exposes the first electrode plate 24, enabling the second pole of a subsequently formed first transistor T1 to be connected to the first electrode plate 24.

[0145] In an exemplary embodiment, the electrode plate connection line 35 is provided between the second electrode plates 32 of adjacent sub-pixels. The first end of the electrode plate connection line 35 is connected to the second electrode plate 32 of this sub-pixel, and the second end of the electrode plate connection line 35 extends along the first direction X or the opposite direction of the first direction X and is connected to the second electrode plate 32 of the adjacent sub-pixel, that is, the electrode plate connection line 35 is configured to connect the second electrode plates of adjacent sub-pixels in the first direction X. In an exemplary embodiment, through the electrode plate connection line 35, the second electrode plates in a sub-pixel row form an interconnected integral structure, and the second electrode plates of the integral structure can be reused as power signal lines, ensuring that the second electrode plates in a sub-pixel row have the same potential, which is beneficial to improving the uniformity of the panel, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0146] In an exemplary embodiment, the orthographic projection of the edge of the second electrode plate 32 adjacent to the longitudinal first region R1 on the substrate overlaps with the orthographic projection of the boundary line between the longitudinal first region R1 and the longitudinal second region R2 on the substrate, and the orthographic projection of the edge of the second electrode plate 32 adjacent to the longitudinal third region R3 on the substrate overlaps with the orthographic projection of the boundary line between the longitudinal second region R2 and the longitudinal third region R3 on the substrate, that is, the second length of the second electrode plate 32 is equal to the second length of the longitudinal second region R2, and the second length of the second electrode plate 32 refers to the dimension of the second electrode plate 32 in the second direction Y.

[0147] As Figure 9bAs shown, in an exemplary embodiment, there is an overlapping region 36 between a second region 13-2 of a third active layer extending along a second direction Y and a plate connection line 35 extending along a first direction X. In a second stage of operation of the pixel driving circuit, a low-level signal output by a first scanning signal line 21 turns on a second transistor, a fourth transistor, and a seventh transistor. At the same time, a first plate of a storage capacitor being at a low level turns on a third transistor. Therefore, a data voltage output by a data signal line passes through a fourth active layer, a third active layer, and a second active layer respectively, and a difference between the data voltage output by the data signal line and a threshold voltage of the third transistor T3 is charged into the first plate 24 of the storage capacitor. Since the second region 13-2 of the third active layer forms an overlapping capacitor with the plate connection line 35, a channel region 18 of the third transistor has a fourth channel segment 18-4 extending along the second direction Y. If an edge of the overlapping region 36 close to the fourth channel segment 18-4 and an edge of the fourth channel segment 18-4 close to the overlapping region 36 are disposed opposite to each other, that is, edges of the overlapping region 36 and the fourth channel segment 18-4 are disposed opposite to each other in the first direction X, the overlapping region 36 will affect transmission of a data signal by the fourth channel segment 18-4, increase a load of the third transistor, increase power consumption of the pixel driving circuit, and reduce display quality.

[0148] In an exemplary embodiment, a minimum distance L2 between the overlapping region 36 and the channel region 18 of the third transistor may be greater than or equal to an effective length L1 of the channel region 18 in the second direction.

[0149] The distance L2 may be a distance between an edge of the overlapping region 36 adjacent to a second direction Y side of a fifth channel segment 18-5 and extending along the first direction X and an edge of the fifth channel segment 18-5 adjacent to the second direction Y side of the overlapping region 36 and extending along the first direction X.

[0150] In an exemplary embodiment, the distance L2 may be greater than or equal to 1.5 μm. In some possible implementation manners, the distance L2 may be about 1.6 μm to 4.5 μm. In some other possible implementation manners, the distance L2 may be about 2.5 μm to 4.5 μm.

[0151] In an exemplary embodiment, a width of the plate connection line 35 may be about 2 μm to 4 μm, and a width of the second region 13-2 of the third active layer may be about 1.8 μm to 2.0 μm to reduce an area of the overlapping region 36.

[0152] In an exemplary embodiment of the present disclosure, by setting a minimum distance between the overlapping region and the channel region of the third transistor, there is no region disposed opposite between a channel segment extending along the second direction in the channel region and the overlapping region, an influence of the overlapping capacitor on the driving transistor is reduced, a load of the driving transistor is reduced, power consumption of the pixel driving circuit is reduced, and a display effect is improved.

[0153] As Figure 9c and Figure 9d shown, in a plane perpendicular to the substrate, a first insulating layer 61 is disposed on the substrate 101, a semiconductor layer is disposed on the first insulating layer 61, the semiconductor layer at least includes a second region 13-2 of a third active layer and a channel region 18 of the third active layer, and the channel region 18 of the third active layer at least includes a fourth channel segment 18-4 and a fifth channel segment 18-5. A second insulating layer 62 covers the semiconductor layer, a first conductive layer is disposed on the second insulating layer 62, and the first conductive layer at least includes a first electrode plate 24 of a storage capacitor. A third insulating layer 63 covers the first conductive layer, a second conductive layer is disposed on the third insulating layer 63, and the second conductive layer at least includes a second electrode plate 32 of the storage capacitor and an electrode plate connection line 35.

[0154] In an exemplary embodiment, there is an overlapping region 36 between the second region 13-2 of the third active layer and the electrode plate connection line 35, and the distance L2 between the edge of the overlapping region 36 adjacent to the fifth channel segment 18-5 and the edge of the fifth channel segment 18-5 adjacent to the overlapping region 36 is L21 + L22.

[0155] In an exemplary embodiment, there is an overlapping region between the orthographic projection of the second electrode plate 32 on the substrate and the orthographic projection of the first electrode plate 24 on the substrate. An opening 34 is provided on the second electrode plate 32, and the opening 34 exposes the third insulating layer 63 covering the first electrode plate 24.

[0156] (4) Form a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating thin film on the substrate on which the foregoing patterns are formed, patterning the fourth insulating thin film by a patterning process to form a fourth insulating layer covering the second conductive layer, and a plurality of vias are provided on the fourth insulating layer. The plurality of vias at least include: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, and a ninth via V9, as Figure 10a , Figure 10b , Figure 10c and Figure 10d shown, Figure 10b is Figure 10a an enlarged view of the second electrode plate region in Figure 10c is Figure 10b a cross-sectional view taken along the A-A direction in Figure 10d is Figure 10b a cross-sectional view taken along the B-B direction in

[0157] As Figure 10aAs shown, in an exemplary embodiment, the first via V1 is located within the opening 34 of the second electrode plate 32. The orthographic projection of the first via V1 on the substrate is within the range of the orthographic projection of the opening 34 on the substrate. The fourth insulating layer and the third insulating layer within the first via V1 are etched away to expose the surface of the first electrode plate 24. The first via V1 is configured to connect the second pole of the subsequently formed first transistor T1 to the first electrode plate 24 through this via.

[0158] In an exemplary embodiment, the second via V2 is located between the opening 34 and the second region 13-2 of the third active layer. The orthographic projection of the second via V2 on the substrate is within the range of the orthographic projection of the second electrode plate 32 on the substrate. The fourth insulating layer within the second via V2 is etched away to expose the surface of the second electrode plate 32. The second via V2 is configured to connect the subsequently formed first power supply line VDD to the second electrode plate 32 through this via, and the second via V2 serves as a power supply via.

[0159] In an exemplary embodiment, the third via V3 is located in the longitudinal third region R3. The fourth insulating layer, the third insulating layer, and the second insulating layer within the third via V3 are etched away to expose the surface of the first region of the fifth active layer. The third via V3 is configured to connect the first pole of the subsequently formed fifth transistor T5 to the fifth active layer through this via.

[0160] In an exemplary embodiment, the fourth via V4 is located in the longitudinal third region R3. The fourth insulating layer, the third insulating layer, and the second insulating layer within the fourth via V4 are etched away to expose the surface of the second region of the sixth active layer (which is also the second region of the seventh active layer). The fourth via V4 is configured to connect the second pole of the subsequently formed sixth transistor T6 to the sixth active layer through this via, and to connect the second pole of the subsequently formed seventh transistor T7 to the seventh active layer through this via.

[0161] In an exemplary embodiment, the fifth via V5 is located in the longitudinal first region R1. The fourth insulating layer, the third insulating layer, and the second insulating layer within the fifth via V5 are etched away to expose the surface of the first region of the fourth active layer. The fifth via V5 is configured to connect the first pole of the subsequently formed fourth transistor T4 to the fourth active layer through this via.

[0162] In an exemplary embodiment, the sixth via V6 is located in the longitudinal first region R1. The fourth insulating layer, the third insulating layer, and the second insulating layer within the sixth via V6 are etched away to expose the surface of the second region of the first active layer (which is also the first region of the second active layer). The sixth via V6 is configured to connect the second pole of the subsequently formed first transistor T1 to the first active layer through this via, and to connect the first pole of the subsequently formed second transistor T2 to the second active layer through this via.

[0163] In an exemplary embodiment, a seventh via V7 is located in a first longitudinal region R1. The fourth insulating layer, the third insulating layer, and the second insulating layer within the seventh via V7 are etched away, exposing the surface of the first region of the seventh active layer (which is also the first region of the first active layer). The seventh via V7 is configured to connect the first pole of a subsequently formed seventh transistor T7 to the seventh active layer through this via, and to connect the first pole of a subsequently formed first transistor T1 to the first active layer through this via.

[0164] In an exemplary embodiment, an eighth via V8 is located in a first longitudinal region R1. The fourth insulating layer within the eighth via V8 is etched away, exposing the surface of the shielding electrode 33. The eighth via V8 is configured to connect a subsequently formed first power supply line VDD to the shielding electrode 33 through this via.

[0165] In an exemplary embodiment, a ninth via V9 is located in a first longitudinal region R1. The fourth insulating layer within the ninth via V9 is etched away, exposing the surface of the initial signal line 31. The ninth via V9 is configured to connect the first pole (which is also the first pole of the first transistor T1) of a subsequently formed seventh transistor T7 to the initial signal line 31 through this via.

[0166] As Figure 9b shown, in an exemplary embodiment, the second via V2 is configured to connect a subsequently formed first power supply line VDD to the second electrode plate 32 through this via. Since there is an overlapping region between the opening 34 on the second electrode plate 32 and the first electrode plate 24, if the distance between the second via V2 and the opening 34 is small, the formed second via V2 will expose the first electrode plate 24, which will cause the first power supply line VDD to be connected to the first electrode plate 24, resulting in a short circuit between the first power supply line VDD and the gate electrode of the third transistor T3. Since the second electrode plate 32 is adjacent to the second region 13-2 of the third active layer, if the distance between the second via V2 and the second region 13-2 of the third active layer is small, the formed second via V2 will expose the second region 13-2 of the third active layer, which will cause the first power supply line VDD to be connected to the second region 13-2 of the third active layer, resulting in a short circuit between the first power supply line VDD and the data line DATA.

[0167] In an exemplary embodiment, the distance L3 between the edge of the second via V2 adjacent to the opening 34 and the edge of the opening 34 adjacent to the second via V2 may be greater than or equal to the distance L4 between the edge of the second via V2 adjacent to the second region 13-2 of the third active layer and the edge of the second region 13-2 of the third active layer adjacent to the second via V2.

[0168] In an exemplary embodiment, the spacing L3 between the edge of the second via V2 adjacent to one side of the opening 34 and the edge of the opening 34 adjacent to the second via V2 can be greater than or equal to 0.85 μm. In some possible implementation manners, the spacing L3 can be approximately 1.5 μm to 3.0 μm. In other possible implementation manners, the spacing L3 can be approximately 2.0 μm to 3.0 μm.

[0169] In an exemplary embodiment of the present disclosure, the spacing L4 between the edge of the second via V2 adjacent to the second region 13-2 (overlap region 36) of the third active layer and the edge of the second region 13-2 of the third active layer adjacent to the second via V2 can be greater than or equal to 0.6 μm. In some possible implementation manners, the spacing L4 can be approximately 1.2 μm to 3.0 μm. In other possible implementation manners, the spacing L4 can be approximately 2.0 μm to 3.0 μm.

[0170] In an exemplary embodiment, the spacing L5 between the edge of the second via V2 adjacent to one side of the opening 34 and the edge of the second via V2 adjacent to the second region 13-2 of the third active layer can be approximately 2.0 μm to 2.5 μm.

[0171] In an exemplary embodiment, high-PPI displays have become a design trend product, with finer picture quality displays and higher display quality. Since the pixel area of high-PPI displays is small, it is not conducive to the layout of pixel driving circuits. Therefore, when arranging pixel driving circuits within a limited space, various factors need to be comprehensively considered. Increasing the spacing L2 can reduce the influence of overlapping capacitance on data signal transmission, reduce load and power consumption. Increasing the spacing L3 can avoid short circuits between the first power supply line VDD and the gate electrode of the third transistor T3. Increasing the spacing L4 can avoid short circuits between the first power supply line VDD and the initial signal line INIT, but it is not conducive to the overall layout. Considering comprehensively, the spacing L2 can be set to be greater than the spacing L3. In some possible implementation manners, the difference between the spacing L2 and the spacing L3 can be approximately 0.3 μm to 0.6 μm.

[0172] In an exemplary embodiment of the present disclosure, by setting the spacing L3 between the edge of the second via V2 adjacent to one side of the opening 34 and the edge of the opening 34 adjacent to the second via V2 to be greater than or equal to 0.85 μm, and setting the spacing L4 between the edge of the second via V2 adjacent to the overlap region 36 and the edge of the overlap region 36 adjacent to the second via V2 to be greater than or equal to 0.6 μm, the process margin is improved, short circuits are avoided, and the yield is increased.

[0173] Such as Figure 10c and Figure 10dAs shown, in a plane perpendicular to the substrate, the fourth insulating layer 64 covers the second conductive layer, and a plurality of vias are provided thereon. The plurality of vias at least include a second via V2. The fourth insulating layer 64 within the second via V2 is etched away to expose the surface of the second electrode plate 32. The distance L3 between the edge of the second via V2 adjacent to the opening 34 and the edge of the opening 34 adjacent to the second via V2 can be greater than or equal to the distance L4 between the edge of the second via V2 adjacent to the second region 13-2 of the third active layer and the edge of the second region 13-2 of the third active layer adjacent to the second via V2.

[0174] In an exemplary embodiment, the distance L3 can be greater than or equal to 0.85 μm, and the distance L4 can be greater than or equal to 0.6 μm.

[0175] (5) Form a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third metal thin film on the substrate on which the foregoing pattern is formed, and patterning the third metal thin film by a patterning process to form a third conductive layer disposed on the fourth insulating layer. The third conductive layer at least includes: a first power line 41, a second pole 42 of the first transistor T1, a first pole 43 of the seventh transistor T7, a first pole 44 of the fourth transistor T4, a first pole 45 of the fifth transistor T5, and a second pole 46 of the sixth transistor T6, as Figure 11a and Figure 11b shown, Figure 11b for Figure 11a a cross-sectional view taken along line B-B in

[0176] As Figure 11a and Figure 11b shown, in an exemplary embodiment, the first power line 41 is disposed on the fourth insulating layer 64. On the one hand, the first power line 41 is connected to the shielding electrode 33 through an eighth via V8, and on the other hand, it is connected to the second electrode plate 32 through a second via V2, so that the shielding electrode 33 and the second electrode plate 32 have the same potential as the first power line 41.

[0177] In an exemplary embodiment, the second pole 42 of the first transistor T1 simultaneously serves as the first pole of the second transistor T2. Its first end is connected to the first active layer of the first transistor T1 through a sixth via V6, and its second end is connected to the first electrode plate 24 through a first via V1, so that the first electrode plate 24, the second pole 42 of the first transistor T1, and the first pole of the second transistor T2 have the same potential.

[0178] In an exemplary embodiment, a first pole 43 of a seventh transistor T7 serves as a first pole of a first transistor T1 at the same time. A first end thereof is connected to an initial signal line 31 through a ninth via V9, and a second end thereof is connected to a seventh active layer of the seventh transistor T7 through a seventh via V7, so that the first pole 43 of the seventh transistor T7 and the first pole of the first transistor T1 have the same potential as the initial signal line 31.

[0179] In an exemplary embodiment, a first pole 44 of a fourth transistor T4 is connected to a fourth active layer of the fourth transistor T4 through a fifth via V5. In an exemplary embodiment, the first pole 44 of the fourth transistor T4 is configured to be connected to a data signal line DATA formed subsequently, and thus the fifth via V5 serves as a data writing hole.

[0180] In an exemplary embodiment, a first end of a first pole 45 of a fifth transistor T5 is connected to a first power supply line 41, and a second end thereof is connected to a fifth active layer of the fifth transistor T5 through a third via V3. In an exemplary embodiment, the first pole 45 of the fifth transistor T5 and the first power supply line 41 may be an integral structure.

[0181] In an exemplary embodiment, a second pole 46 of a sixth transistor T6 serves as a second pole of the seventh transistor T7 at the same time. A first end thereof is connected to a sixth active layer of the sixth transistor T6 through a fourth via V4. In an exemplary embodiment, the second pole 46 of the sixth transistor T6 is configured to be connected to a second connection electrode formed subsequently, and the second connection electrode is configured to be connected to an anode formed subsequently.

[0182] In an exemplary embodiment, the first power supply line 41 may be a polyline with a non-uniform width, and the width of the first power supply line 41 is a dimension in a first direction X of the first power supply line 41. In an exemplary embodiment, along a second direction Y, the first power supply line 41 may include a first power supply portion, a second power supply portion, a third power supply portion, and a fourth power supply portion connected in sequence. The width of the first power supply portion may be greater than the width of the second power supply portion, the width of the third power supply portion may be greater than the width of the fourth power supply portion, and the width of the third power supply portion may be greater than the width of the first power supply portion. The first power supply line 41 is arranged as a polyline with a variable width, which can not only facilitate the layout of the pixel structure, but also reduce the parasitic capacitance.

[0183] In an exemplary embodiment, the first power supply unit and the third power supply unit may be parallelograms, and the second power supply unit and the fourth power supply unit may be rectangles, that is, the rectangle is disposed between the two parallelograms. A pair of edges of the first power supply unit extends along the second direction Y, and the other pair of edges extends along a first inclined direction. The first inclined direction and the second direction Y have a first included angle, and the first included angle may be greater than 0 degrees and less than 90 degrees. In an exemplary embodiment, a pair of edges of the third power supply unit extends along the second direction Y, and the other pair of edges extends along a second inclined direction. The second inclined direction and the second direction Y have a second included angle, and the second included angle may be greater than 0 degrees and less than 90 degrees. In an exemplary embodiment, the first included angle may be equal to the second included angle, and the first inclined direction and the second inclined direction are mirror symmetric with respect to the second center line O Y Mirror symmetric.

[0184] (6) Form a fifth insulating layer pattern. In an exemplary embodiment, forming the fifth insulating layer pattern may include: depositing a fifth insulating thin film on the substrate on which the foregoing patterns are formed, patterning the fifth insulating thin film by a patterning process to form a fifth insulating layer covering the third conductive layer, and a plurality of vias are provided on the fifth insulating layer. The plurality of vias at least include: a tenth via V10 and an eleventh via V11, as Figure 12 shown.

[0185] In an exemplary embodiment, the tenth via V10 is located in the first longitudinal region R1, and the fifth insulating layer within the tenth via V10 is etched away to expose the surface of the first pole 44 of the fourth transistor T4. The tenth via V10 is configured to enable a data signal line DATA formed subsequently to be connected to the first pole 44 of the fourth transistor T4 through the via.

[0186] In an exemplary embodiment, the eleventh via V11 is located in the third longitudinal region R3, and the fifth insulating layer within the eleventh via V11 is etched away to expose the surface of the second pole 46 of the sixth transistor T6. The eleventh via V11 is configured to enable a second connection electrode formed subsequently to be connected to the second pole 46 of the sixth transistor T6 through the via.

[0187] (7) Form a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth metal thin film on the substrate on which the foregoing patterns are formed, patterning the fourth metal thin film by a patterning process to form a fourth conductive layer disposed on the fifth insulating layer. The fourth conductive layer at least includes: a data signal line 51 and an anode connection electrode 52, as Figure 13 shown.

[0188] In an exemplary embodiment, the data signal line 51 extends along the second direction Y and is connected to the first pole 44 of the fourth transistor T4 through the tenth via V10. The anode connection electrode 52 is rectangular and is located in the third longitudinal region R3 and is connected to the second pole 46 of the sixth transistor T6 through the eleventh via V11. The anode connection electrode 52 is configured to be connected to the anode formed subsequently.

[0189] In an exemplary embodiment, the subsequent preparation process may include: coating a planarizing film on the substrate on which the foregoing pattern is formed, patterning the planarizing film by a patterning process to form a planarizing layer covering the fourth conductive layer, and a twelfth via is provided on the planarizing layer, and the surface of the anode connection electrode 52 is exposed through the twelfth via. Subsequently, a conductive film is deposited on the substrate on which the foregoing pattern is formed, and the conductive film is patterned by a patterning process to form an anode provided on the planarizing layer. The anode is connected to the anode connection electrode 52 through the twelfth via. Since the anode is connected to the anode connection electrode 52 and the anode connection electrode 52 is connected to the second pole 46 of the sixth transistor T6, the pixel driving circuit can drive the light-emitting device to emit light. Subsequently, a pixel definition film is coated on the anode, and the pixel definition film is patterned by a patterning process to form a pixel definition layer. Each sub-pixel's pixel definition layer is provided with a pixel opening that exposes the anode. Subsequently, an organic light-emitting layer is formed by an evaporation process, and a cathode is formed on the organic light-emitting layer. Subsequently, a packaging layer is formed. The packaging layer may include a stacked first packaging layer, a second packaging layer, and a third packaging layer. The first packaging layer and the third packaging layer may be made of inorganic materials, and the second packaging layer may be made of organic materials. The second packaging layer is disposed between the first packaging layer and the third packaging layer, which can prevent external moisture from entering the light-emitting device.

[0190] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass and quartz. The flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer. The materials of the first flexible material layer and the second flexible material layer may be materials such as polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials of the first inorganic material layer and the second inorganic material layer may be materials such as silicon nitride (SiNx) or silicon oxide (SiOx) for improving the water and oxygen resistance of the substrate. The material of the semiconductor layer may be amorphous silicon (a-si).

[0191] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multi-layer, or a composite layer. The first insulating layer is called a buffer layer and is used to improve the water and oxygen resistance of the substrate. The second insulating layer and the third insulating layer are called gate insulating (GI) layers. The fourth insulating layer is called an interlayer dielectric (ILD) layer, and the fifth insulating layer is called a passivation (PVX) layer. The active layer may be made of amorphous indium gallium zinc oxide material (a-IGZO), zinc oxide nitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, or polythiophene, etc. That is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology, or organic technology. The planarization layer may be made of an organic material, the transparent conductive thin film may be indium tin oxide ITO or indium zinc oxide IZO, and the pixel definition layer may be made of polyimide, acrylic, or polyethylene terephthalate. The cathode may be made of any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or an alloy made of any one or more of the above metals.

[0192] In an exemplary embodiment, the thickness of the first insulating layer is from 3000 angstroms to 5000 angstroms, the thickness of the second insulating layer is from 1000 angstroms to 2000 angstroms, the thickness of the third insulating layer is from 4500 angstroms to 7000 angstroms, the thickness of the fourth insulating layer is from 3000 angstroms to 5000 angstroms, and the thickness of the fifth insulating layer is from 3000 angstroms to 5000 angstroms.

[0193] The structure shown in the present disclosure and its manufacturing process are merely an exemplary illustration. In the exemplary embodiment, the corresponding structure may be changed according to actual needs, and the patterning process may be increased or decreased. The present disclosure does not make specific limitations here.

[0194] As can be seen from the structure and manufacturing process of the display substrate described above, for the display substrate provided by the present disclosure, by setting the distance between the overlapping region and the channel region of the driving transistor, the influence of the overlapping capacitance on the data signal transmission of the driving transistor is effectively reduced, the load of the driving transistor is reduced, the power consumption of the pixel driving circuit is reduced, and the display effect is improved. By setting the distance between the second vias and the opening and the distance between the second vias and the second region of the driving transistor, the process margin is increased, short circuits are avoided, and the yield is improved. The manufacturing process of the present disclosure can be well compatible with the existing manufacturing processes, the process implementation is simple, easy to implement, has high production efficiency, low production cost, and high yield.

[0195] The present disclosure also provides a method for manufacturing a display substrate to manufacture the display substrate provided in the above embodiments. In an exemplary embodiment, in a plane parallel to the display substrate, the display substrate includes a plurality of sub-pixels, and at least one sub-pixel includes a pixel driving circuit and a light-emitting device connected to the pixel driving circuit. The pixel driving circuit at least includes a driving transistor and a storage capacitor. The manufacturing method includes:

[0196] Forming a semiconductor layer, a first conductive layer, and a second conductive layer on a substrate in sequence; the semiconductor layer at least includes an active layer of the driving transistor, the first conductive layer at least includes a first electrode plate of the storage capacitor, the second conductive layer at least includes a second electrode plate of the storage capacitor and an electrode plate connection line, and the electrode plate connection line connects the second electrode plates in adjacent sub-pixels in a first direction; the first direction is the direction of the sub-pixel row;

[0197] The active layer of the driving transistor at least includes a channel region, and the channel region at least includes a first channel segment extending in the first direction and a second channel segment extending in a second direction. The second direction is the direction of the sub-pixel column; the channel region has an effective length in the second direction, and the effective length in the second direction is the length of the second channel segment in the second direction;

[0198] The positive projection of the electrode plate connection line on the substrate and the positive projection of the semiconductor layer on the substrate have an overlapping region, and the distance between the overlapping region and the channel region of the driving transistor is greater than or equal to the effective length in the second direction.

[0199] In an exemplary embodiment, the distance between the overlapping region and the channel region of the driving transistor is greater than or equal to 1.5 μm.

[0200] In an exemplary embodiment, the manufacturing method further includes:

[0201] A third conductive layer is formed. The third conductive layer includes at least a first power line, and the first power line is connected to the second electrode plate through a power via. An opening is provided on the second electrode plate, and the power via is disposed between the opening and the overlapping region. The distance between the edge of the power via adjacent to the opening on the first direction side and the edge of the opening adjacent to the power via on the first direction side is greater than or equal to the distance between the edge of the power via adjacent to the overlapping region on the first direction side and the edge of the overlapping region adjacent to the power via on the first direction side.

[0202] In an exemplary embodiment, the distance between the edge of the power via adjacent to the opening on the first direction side and the edge of the opening adjacent to the power via on the first direction side is greater than or equal to 0.85 μm; the distance between the edge of the power via adjacent to the overlapping region on the first direction side and the edge of the overlapping region adjacent to the power via on the first direction side is greater than or equal to 0.6 μm.

[0203] The display substrate manufactured by the manufacturing method of the display substrate provided by the present disclosure has a similar implementation principle and implementation effect, which will not be elaborated here.

[0204] The present disclosure further provides a display device, and the display device includes the aforementioned display substrate. The display device can be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any product or component with a display function. The embodiments of the present invention are not limited thereto.

[0205] Although the disclosed embodiments are as above, the content described is only an embodiment adopted for facilitating the understanding of the present disclosure and is not intended to limit the present invention. Any person skilled in the art can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed by the present disclosure. However, the scope of patent protection of the present invention shall still be subject to the scope defined by the appended claims.

Claims

1. A display substrate, within a plane parallel to the display substrate, the display substrate includes a plurality of sub-pixels, at least one sub-pixel includes a pixel driving circuit and a light-emitting device connected to the pixel driving circuit, the pixel driving circuit at least includes a driving transistor and a storage capacitor; within a plane perpendicular to the display substrate, the display substrate includes a semiconductor layer, a first conductive layer, and a second conductive layer sequentially disposed on a substrate; the semiconductor layer at least includes an active layer of the driving transistor, the first conductive layer at least includes a first electrode plate of the storage capacitor, the second conductive layer at least includes a second electrode plate of the storage capacitor and an electrode plate connection line, and the electrode plate connection line connects the second electrode plates in adjacent sub-pixels in a first direction; the first direction is the direction of the sub-pixel row; The active layer of the driving transistor includes at least a channel region, and the channel region includes at least a first channel segment extending in a first direction and a second channel segment extending in a second direction, where the second direction is the direction of the sub-pixel column; The channel region has a second-direction effective length in a second direction, and the second-direction effective length is the length of the second channel segment in the second direction; There is an overlapping region between the orthographic projection of the electrode plate connection line on the substrate and the orthographic projection of the semiconductor layer on the substrate, and the distance between the overlapping region and the channel region of the driving transistor is greater than or equal to the second-direction effective length.

2. The display substrate according to claim 1, wherein, The active layer of the driving transistor further includes a first region and a second region respectively connected to the channel region, and the semiconductor layer in the overlapping region includes the second region of the driving transistor.

3. The display substrate according to claim 2, wherein, The channel region of the driving transistor includes a first channel segment, a second channel segment, a third channel segment, a fourth channel segment, and a fifth channel segment; a first end of the first channel segment is connected to the first region, and a second end of the first channel segment extends along the first direction and then is connected to a first end of the second channel segment; a second end of the second channel segment extends along the opposite direction of the second direction and then is connected to a first end of the third channel segment; a second end of the third channel segment extends along the first direction and then is connected to a first end of the fourth channel segment; a second end of the fourth channel segment extends along the second direction and then is connected to a first end of the fifth channel segment; a second end of the fifth channel segment extends along the first direction and then is connected to the second region; The distance between the overlapping region and the channel region of the driving transistor is the distance between an edge of the overlapping region adjacent to the second direction side of the fifth channel segment and an edge of the fifth channel segment adjacent to the second direction side of the overlapping region.

4. The display substrate according to any one of claims 1 to 3, wherein, The distance between the overlapping region and the channel region of the driving transistor is greater than or equal to 1.5 μm.

5. The display substrate according to any one of claims 1 to 3, wherein, The distance between the overlapping region and the channel region of the driving transistor is from 1.6 μm to 4.5 μm.

6. The display substrate according to any one of claims 1 to 3, wherein, The pixel driving circuit further includes a third conductive layer, the third conductive layer at least includes a first power supply line, and the first power supply line is connected to the second electrode plate through a power supply via; an opening is provided in the middle of the second electrode plate, and the power supply via is provided between the opening and the overlapping region.

7. The display substrate according to claim 6, wherein, The distance between the edge of the power via adjacent to one side of the opening in the first direction and the edge of the opening adjacent to the power via in the first direction is greater than or equal to the distance between the edge of the power via adjacent to one side of the overlapping region in the first direction and the edge of the overlapping region adjacent to the power via in the first direction.

8. The display substrate according to claim 7, wherein, The distance between the edge of the power via adjacent to one side of the opening in the first direction and the edge of the opening adjacent to the power via in the first direction is greater than or equal to 0.85 μm.

9. The display substrate according to claim 7, wherein, The distance between the edge of the power via adjacent to one side of the opening in the first direction and the edge of the opening adjacent to the power via in the first direction is 1.5 μm to 3.0 μm.

10. The display substrate according to claim 7, wherein, The distance between the edge of the power via adjacent to one side of the overlapping region in the first direction and the edge of the overlapping region adjacent to the power via in the first direction is greater than or equal to 0.6 μm.

11. The display substrate according to claim 7, wherein, The distance between the edge of the power via adjacent to one side of the overlapping region in the first direction and the edge of the overlapping region adjacent to the power via in the first direction is 1.2 μm to 3.0 μm.

12. The display substrate according to claim 2, wherein, The conductivity of the second region of the driving transistor is greater than the conductivity of the channel region of the driving transistor.

13. A display device, comprising the display substrate according to any one of claims 1 to 12.

14. A method for manufacturing a display substrate, in a plane parallel to the display substrate, the display substrate includes a plurality of sub-pixels, at least one sub-pixel includes a pixel driving circuit and a light-emitting device connected to the pixel driving circuit, and the pixel driving circuit at least includes a driving transistor and a storage capacitor; the manufacturing method includes: Successively forming a semiconductor layer, a first conductive layer, and a second conductive layer on a substrate; The semiconductor layer at least includes the active layer of the driving transistor, the first conductive layer at least includes the first electrode plate of the storage capacitor, the second conductive layer at least includes the second electrode plate of the storage capacitor and the electrode plate connection line, and the electrode plate connection line connects the second electrode plates in adjacent sub-pixels in the first direction; the first direction is the direction of the sub-pixel rows; The active layer of the driving transistor at least includes a channel region, and the channel region at least includes a first channel segment extending in the first direction and a second channel segment extending in the second direction, and the second direction is the direction of the sub-pixel columns; The channel region has an effective length in the second direction, and the effective length in the second direction is the length of the second channel segment in the second direction; The orthographic projection of the electrode plate connection line on the substrate and the orthographic projection of the semiconductor layer on the substrate have an overlapping region, and the distance between the overlapping region and the channel region of the driving transistor is greater than or equal to the effective length in the second direction.

15. According to the method for manufacturing a display substrate according to claim 14, wherein, The manufacturing method further includes: A third conductive layer is formed, and the third conductive layer includes at least a first power supply line, and the first power supply line is connected to the second electrode plate through a power supply via; an opening is provided on the second electrode plate, the power supply via is disposed between the opening and the overlapping region, and a distance between an edge of the power supply via adjacent to one side of the opening in a first direction and an edge of the opening adjacent to one side of the power supply via in the first direction is greater than or equal to a distance between an edge of the power supply via adjacent to one side of the overlapping region in the first direction and an edge of the overlapping region adjacent to one side of the power supply via in the first direction.

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