Display driver circuits, display modules, display screen driving methods and electronic devices

Abstract

The present application provides a display driving circuit, a display module, a driving method for a display screen, and an electronic device, which can improve the display performance of the display screen. The electronic device includes: a display screen, including a first display area and a second display area; a main controller is used to send a first clock signal to the first display driving circuit and the second display driving circuit respectively; the first display driving circuit is used to receive the first clock signal; the first display driving circuit is also used to output a first GOA clock signal to the display screen, wherein the first GOA clock signal is generated based on the first clock signal; the second display driving circuit is used to receive the first clock signal; the second display driving circuit is also used to output a second GOA clock signal to the display screen, wherein the second GOA clock signal is generated based on the first clock signal.

Description

Technical Field

[0001] The present application relates to the field of terminal technology, and in particular to a display driving circuit, a display module, a driving method for a display screen, and an electronic device. Background Art

[0002] With the rapid development of electronic technology, electronic devices such as smart terminals and tablet computers have greatly changed people's lives and working methods. In order to meet the various different needs of users such as entertainment, office, watching videos or browsing the web, the area of ​​the display screen of electronic devices is designed to be larger and larger, and the performance requirements for display driver circuits are also getting higher and higher. Therefore, it may happen that the capacity of a single display driver circuit is not enough to drive the display panel. In this case, multiple display driver circuits can be used to drive the display screen, and this driving structure can be called a multi-display driver circuit system. In a multi-display driver circuit system, clock signal synchronization is required between multiple display driver circuits to ensure that the display screen outputs normal video images.

[0003] In a synchronization method in a multi-display driving circuit system, multiple display driving circuits may include a main display driving circuit and at least one auxiliary display driving circuit. The main display driving circuit sends a clock signal generated internally to the auxiliary display driving circuit, and the auxiliary display driving circuit performs time synchronization based on the received clock signal to achieve synchronization between multiple display driving circuits. However, this synchronization method is only used to synchronize the vertical synchronization signal (vertical synchronization, V-Sync) and horizontal synchronization (horizontal synchronization, H-Sync) signals between multiple display driving circuits. Among them, the vertical synchronization signal is used for synchronization between frames and frames of the scanned image, and the horizontal synchronization signal is used for synchronization between lines and lines (line-to-line) of the scanned image. The clock signal in the row for scanning each row of pixels is generated based on the internal clock signal of each display driving circuit, and no clock synchronization is performed. Since there is an error in the internal clock frequency of different display driving circuits, it will affect the display performance of the display screen. Summary of the invention

[0004] The present application provides a display driving circuit, a display module, a driving method of a display screen and an electronic device, which can improve the display performance of the display screen.

[0005] In a first aspect, an electronic device is provided, comprising: a display screen, comprising a first display area and a second display area; a main controller, comprising a first clock output terminal, the first clock output terminal being used to send a first clock signal to a first display driving circuit and a second display driving circuit respectively; the first display driving circuit comprising a first clock receiving terminal, the first clock receiving terminal being used to receive the first clock signal; the first display driving circuit further comprises a first gate drive array GOA clock signal output terminal, the first GOA clock signal output terminal being used to output a first GOA clock signal to the display screen, the first GOA clock signal being used to control GOA of the first display area to be turned on or off, wherein the first GOA clock signal is generated based on the first clock signal; the second display driving circuit comprising a second clock receiving terminal, the second clock receiving terminal being used to receive the first clock signal; the second display driving circuit further comprises a second GOA clock signal output terminal, the second GOA clock signal output terminal being used to output a second GOA clock signal to the display screen, the second GOA clock signal being used to control GOA of the second display area to be turned on or off, wherein the second GOA clock signal is generated based on the first clock signal.

[0006] In an embodiment of the present application, each of the multiple display driving circuits in the electronic device can receive a first clock signal sent by a main controller, and generate a GOA clock signal based on the first clock signal, so that the GOA clock signals output by the multiple display driving circuits to the display screen are all generated based on the same clock signal, which can reduce the error between the frequencies of the GOA clock signals between different display driving circuits and improve the display performance of the display screen.

[0007] In combination with the first aspect, in a possible implementation, the first display driving circuit also includes a first vertical synchronization signal output terminal, which is used to output a first vertical synchronization signal to the display screen, wherein the first vertical synchronization signal is generated based on the first clock signal, and the first vertical synchronization signal is used to perform frame synchronization of the first display area; the second display driving circuit also includes a second vertical synchronization signal output terminal, which is used to output a second vertical synchronization signal to the display screen, wherein the second vertical synchronization clock signal is generated based on the first clock signal, and the second vertical synchronization signal is used to perform frame synchronization of the second display area, and the first vertical synchronization signal and the second vertical synchronization signal are signals with the same phase.

[0008] In an embodiment of the present application, each of the multiple display driving circuits in the electronic device can receive a first clock signal sent by a main controller, and generate a vertical synchronization signal based on the first clock signal, so that the vertical synchronization signals output by the multiple display driving circuits to the display screen are generated based on the same signal, thereby reducing the frequency error of the vertical synchronization signal between different display driving circuits, and reducing the timing error between the vertical synchronization signal and the GOA clock signal, thereby improving the display performance of the display screen.

[0009] In combination with the first aspect, in a possible implementation, the first display driving circuit also includes a first horizontal synchronization signal output terminal, which is used to output a first horizontal synchronization signal to the display screen, wherein the first horizontal synchronization signal is generated based on the first clock signal, and the first horizontal synchronization signal is used to perform row synchronization of the first display area; the second display driving circuit also includes a second horizontal synchronization signal output terminal, which is used to output a second horizontal synchronization signal to the display screen, wherein the second horizontal synchronization signal is generated based on the first clock signal, and the second horizontal synchronization signal is used to perform row synchronization of the second display area.

[0010] In an embodiment of the present application, each of the multiple display driving circuits in the electronic device receives a first clock signal sent by a main controller, and generates a horizontal synchronization signal based on the first clock signal, so that the horizontal synchronization signals output by the multiple display driving circuits to the display screen are generated based on the same clock signal. Therefore, the frequency error of the horizontal synchronization signal between different display driving circuits can be reduced, and the timing error between the horizontal synchronization signal and the GOA clock signal can be reduced, thereby improving the display performance of the display screen.

[0011] In combination with the first aspect, in a possible implementation, the first display driving circuit also includes a first light-emitting EM signal output terminal, which is used to output a first EM signal to the display screen, and the first EM signal is used to control the pixel circuit in the first display area to emit light or not, wherein the first EM signal is generated based on the first clock signal; and / or, the second display driving circuit also includes a second EM signal output terminal, which is used to output a second EM signal to the display screen, and the second EM signal is used to control the pixel circuit in the second display area to emit light or not, wherein the second EM signal is generated based on the first clock signal.

[0012] In an embodiment of the present application, each of the multiple display driving circuits in the electronic device receives a first clock signal sent by a main controller, and generates an EM signal based on the first clock signal, so that the EM signals output by the multiple display driving circuits to the display screen are generated based on the same clock signal, thereby reducing the frequency error of the EM signal between different display driving circuits, and reducing the timing error between the EM signal and the GOA clock signal, thereby improving the display performance of the display screen.

[0013] In combination with the first aspect, in a possible implementation, the first display driving circuit includes a video processing module, which is used to process the video data input by the main controller to generate a video source signal sent to the display screen, the reference clock of the digital circuit in the video processing module is a third clock signal generated by an internal clock generation module of the first display driving circuit, and the reference clock of the analog circuit in the video processing module is the first clock signal.

[0014] In an embodiment of the present application, the display driving circuit uses the first clock signal sent by the main controller as the reference clock of the analog circuit in the display driving circuit, and uses the internally generated third clock signal as the reference clock of the digital circuit in the display driving circuit, thereby reducing the frequency error between the clock signals of multiple display driving circuits, and reducing problems such as timing convergence and electromagnetic interference.

[0015] In combination with the first aspect, in a possible implementation manner, a first buffer is provided in the video processing module, and the first buffer is provided between a digital circuit and an analog circuit in the video processing module.

[0016] In a second aspect, a display driving circuit is provided, which includes: a first clock receiving end, used to receive a first clock signal sent by a main controller; a first gate drive array GOA clock signal output end, the first GOA clock signal output end is used to output a first GOA clock signal to the display screen, the first GOA clock signal is used to control the GOA of the display screen to turn on or off, wherein the first GOA clock signal is generated based on the first clock signal.

[0017] It should be understood that the display driving circuit of the second aspect and the electronic device of the first aspect are based on the same inventive concept, so the beneficial technical effects that can be achieved by the technical solution of the second aspect can be referred to the description of the first aspect and will not be repeated here.

[0018] In combination with the second aspect, in a possible implementation, the display driving circuit also includes a first vertical synchronization signal output terminal, used to output a first vertical synchronization signal to the display screen, wherein the first vertical synchronization signal is generated based on the first clock signal, and the first vertical synchronization signal is used to perform frame synchronization of the display screen.

[0019] In combination with the second aspect, in a possible implementation, the display driving circuit also includes a first horizontal synchronization signal output terminal, which is used to output a first horizontal synchronization signal to the display screen, wherein the first horizontal synchronization signal is generated based on the first clock signal, and the first horizontal synchronization signal is used to perform row synchronization of the display screen.

[0020] In combination with the second aspect, in a possible implementation, the first display driving circuit also includes a first light-emitting EM signal output terminal, which is used to output a first EM signal to the display screen, and the first EM signal is used to control the pixel circuit of the display screen to emit light or not, wherein the first EM signal is generated based on the first clock signal.

[0021] In combination with the second aspect, in a possible implementation, the display driving circuit includes a video processing module, which is used to process the video data input by the main controller to generate a video source signal sent to the display screen, the reference clock of the digital circuit in the video processing module is the third clock signal generated by the internal clock generation module of the display driving circuit, and the reference clock of the analog circuit in the video processing module is the first clock signal.

[0022] In combination with the second aspect, in a possible implementation manner, a first buffer is provided in the video processing module, and the first buffer is provided between a digital circuit and an analog circuit in the video processing module.

[0023] In a third aspect, a method for driving a display screen is provided, wherein the display screen includes a first display area and a second display area, and the method includes: a main controller sends a first clock signal to a first display driving circuit and a second display driving circuit respectively; the first display driving circuit outputs a first gate drive array GOA clock signal to the display screen, and the first GOA clock signal is used to control the GOA of the first display area to be turned on or off, wherein the first GOA clock signal is generated based on the first clock signal; the second display driving circuit outputs a second GOA clock signal to the display screen, and the second GOA clock signal is used to control the GOA of the second display area to be turned on or off, wherein the second GOA clock signal is generated based on the first clock signal.

[0024] It should be understood that the driving method of the display screen of the third aspect and the electronic device of the first aspect are based on the same inventive concept, so the beneficial technical effects that can be achieved by the technical solution of the third aspect can be referred to the description of the first aspect and will not be repeated here.

[0025] In combination with the third aspect, in a possible implementation manner, the method further includes: the first display driving circuit outputting a first vertical synchronization signal to the display screen, wherein the first vertical synchronization signal is generated based on the first clock signal, and the first vertical synchronization signal is used for frame synchronization of the first display area;

[0026] The second display driving circuit outputs a second vertical synchronization signal to the display screen, wherein the second vertical synchronization clock signal is generated based on the first clock signal, the second vertical synchronization signal is used for frame synchronization of the second display area, and the first vertical synchronization signal and the second vertical synchronization signal are signals with the same phase.

[0027] In combination with the third aspect, in a possible implementation, the first display driving circuit also includes a first horizontal synchronization signal output terminal, which is used to output a first horizontal synchronization signal to the display screen, wherein the first horizontal synchronization signal is generated based on the first clock signal, and the first horizontal synchronization signal is used to perform row synchronization of the first display area; the second display driving circuit also includes a second horizontal synchronization signal output terminal, which is used to output a second horizontal synchronization signal to the display screen, wherein the second horizontal synchronization signal is generated based on the first clock signal, and the second horizontal synchronization signal is used to perform row synchronization of the second display area.

[0028] In combination with the third aspect, in a possible implementation, the first display driving circuit also includes a first light-emitting EM signal output terminal, which is used to output a first EM signal to the display screen, and the first EM signal is used to control the pixel circuit in the first display area to emit light or not, wherein the first EM signal is generated based on the first clock signal; the second display driving circuit also includes a second EM signal output terminal, which is used to output a second EM signal to the display screen, and the second EM signal is used to control the pixel circuit in the second display area to emit light or not, wherein the second EM signal is generated based on the first clock signal.

[0029] In combination with the third aspect, in a possible implementation, the first display driving circuit includes a video processing module, which is used to process the video data input by the main controller to generate a video source signal sent to the display screen, the reference clock of the digital circuit in the video processing module is the third clock signal generated by the internal clock generation module of the first display driving circuit, and the reference clock of the analog circuit in the video processing module is the first clock signal.

[0030] In combination with the third aspect, in a possible implementation manner, a first buffer is provided in the video processing module, and the first buffer is provided between a digital circuit and an analog circuit in the video processing module.

[0031] In a fourth aspect, a display module is provided, comprising: a display screen, comprising a first display area and a second display area; a first display driving circuit, comprising a first clock receiving end, the first clock receiving end being used to receive a first clock signal sent by a main controller; the first display driving circuit also includes a first gate drive array GOA clock signal output end, the first GOA clock signal output end being used to output a first GOA clock signal to the display screen, the first GOA clock signal being used to control the GOA of the first display area to be turned on or off, wherein the first GOA clock signal is generated based on the first clock signal; a second display driving circuit, comprising a second clock receiving end, the second clock receiving end being used to receive the first clock signal; the second display driving circuit also includes a second GOA clock signal output end, the second GOA clock signal output end being used to output a second GOA clock signal to the display screen, the second GOA clock signal being used to control the GOA of the second display area to be turned on or off, wherein the second GOA clock signal is generated based on the first clock signal.

[0032] It should be understood that the display module of the fourth aspect and the electronic device of the first aspect are based on the same inventive concept, so the beneficial technical effects that can be achieved by the technical solution of the fourth aspect can be referred to the description of the first aspect and will not be repeated here.

[0033] In the fourth aspect, in a possible implementation, the first display driving circuit also includes a first vertical synchronization signal output terminal, which is used to output a first vertical synchronization signal to the display screen, wherein the first vertical synchronization signal is generated based on the first clock signal, and the first vertical synchronization signal is used to perform frame synchronization of the first display area; the second display driving circuit also includes a second vertical synchronization signal output terminal, which is used to output a second vertical synchronization signal to the display screen, wherein the second vertical synchronization clock signal is generated based on the first clock signal, and the second vertical synchronization signal is used to perform frame synchronization of the second display area, and the first vertical synchronization signal and the second vertical synchronization signal are signals with the same phase.

[0034] In the fourth aspect, in a possible implementation, the first display driving circuit also includes a first horizontal synchronization signal output terminal, which is used to output a first horizontal synchronization signal to the display screen, wherein the first horizontal synchronization signal is generated based on the first clock signal, and the first horizontal synchronization signal is used to perform row synchronization of the first display area; the second display driving circuit also includes a second horizontal synchronization signal output terminal, which is used to output a second horizontal synchronization signal to the display screen, wherein the second horizontal synchronization signal is generated based on the first clock signal, and the second horizontal synchronization signal is used to perform row synchronization of the second display area.

[0035] In the fourth aspect, in a possible implementation, the first display driving circuit also includes a first light-emitting EM signal output terminal, which is used to output a first EM signal to the display screen, and the first EM signal is used to control the pixel circuit in the first display area to emit light or not, wherein the first EM signal is generated based on the first clock signal; the second display driving circuit also includes a second EM signal output terminal, and the second EM signal output terminal is used to output a second EM signal to the display screen, and the second EM signal is used to control the pixel circuit in the second display area to emit light or not, wherein the second EM signal is generated based on the first clock signal.

[0036] In the fourth aspect, in a possible implementation, the first display driving circuit includes a video processing module, which is used to process the video data input by the main controller to generate a video source signal sent to the display screen, the reference clock of the digital circuit in the video processing module is the third clock signal generated by the internal clock generation module of the first display driving circuit, and the reference clock of the analog circuit in the video processing module is the first clock signal.

[0037] In a fourth aspect, in a possible implementation manner, a first buffer is provided in the video processing module, and the first buffer is provided between a digital circuit and an analog circuit in the video processing module.

[0038] In a fifth aspect, the present application provides a circuit system, comprising a processor. The processor is configured to read and execute a computer program stored in a memory to perform the method in the third aspect or any possible implementation thereof, or to perform the method in the fourth aspect or any possible implementation thereof.

[0039] Optionally, the circuit further includes a memory, and the memory is connected to the processor via a circuit or wire.

[0040] Further optionally, the circuit system also includes a communication interface.

[0041] In a sixth aspect, the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, and when the computer instructions are executed on a computer, the computer executes the method in the third aspect or any possible implementation thereof.

[0042] In a seventh aspect, the present application provides a computer program product, comprising a computer program code, which, when executed on a computer, enables the computer to execute the method in the third aspect or any possible implementation thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 It is a schematic diagram of the structure of an electronic device according to an embodiment of the present application.

[0044] Figure 2 It is a schematic diagram of a flow chart of processing video data by a multi-display driving circuit system according to an embodiment of the present application.

[0045] Figure 3 is a circuit diagram of a pixel circuit according to an embodiment of the present application.

[0046] Figure 4 4 is a circuit diagram of a pixel circuit in a reset phase according to an embodiment of the present application.

[0047] Figure 5 1 is a circuit diagram of a pixel circuit in a data voltage Vdata writing phase according to an embodiment of the present application.

[0048] Figure 6 1 is a circuit diagram of a pixel circuit in a light emitting stage according to an embodiment of the present application.

[0049] Figure 7It is a structural diagram of a gate driver on array (GOA) according to an embodiment of the present application.

[0050] Figure 8 2 is a timing diagram of GOA according to an embodiment of the present application.

[0051] Fig. 9 It is a schematic diagram of the structure of an electronic device according to an embodiment of the present application.

[0052] Fig.10 It is a structural schematic diagram of an electronic device according to another embodiment of the present application.

[0053] Fig.11 : is a schematic diagram of the structure of a display driving circuit according to an embodiment of the present application.

[0054] Fig.12 It is a structural schematic diagram of a digital circuit of a video processing module in a display driving circuit of an embodiment of the present application.

[0055] Fig.13 It is a structural schematic diagram of an analog circuit of a video processing module in a display driving circuit according to an embodiment of the present application.

[0056] Fig.14 It is a structural diagram of a video processing module according to an embodiment of the present application. DETAILED DESCRIPTION

[0057] The technical solution in this application will be described below in conjunction with the accompanying drawings.

[0058] The embodiments of the present application provide a display driving circuit, a driving method of a multi-display driving circuit system, and an electronic device, which can improve the display performance of a display screen, wherein the display driving circuit can be installed in the electronic device.

[0059] The electronic device in the embodiments of the present application may include any electronic device including a display screen, such as a user device, a mobile terminal, a mobile phone, a tablet computer (pad), etc., but the embodiments of the present application are not limited to this.

[0060] The electronic device in the embodiment of the present application includes a multi-display driving system, and the multi-display driving system includes multiple display driving circuits. In the embodiment of the present application, a multi-display driving system including two display driving circuits is used as an example for description, and those skilled in the art can understand that the present application can also be applied to a multi-display driving circuit system including more than two display driving circuits.

[0061] Figure 1 1 is a schematic diagram of the structure of an electronic device according to an embodiment of the present application. The electronic device 100 is a multi-display driving circuit system. Figure 1As shown, the electronic device 100 includes a main controller 110, a first display driving circuit 120, a second display driving circuit 130 and a display screen 140. For ease of description, the following describes Figure 1 Definitions of terms used in this document.

[0062] The main controller 110 is used to output the video data to be processed, the clock synchronization signal, the signaling, etc. to the display driving circuit (120, 130). The main controller may include, but is not limited to, various types of processors such as a system on chip (SOC), an application processor (AP), or a general-purpose processor.

[0063] Display driving circuit (120, 130): used to receive video data sent from the main controller 110, and obtain a video source signal after performing digital and analog processing on the video data. The video source signal is used to output to the display screen 130 to drive the display screen 130 to display an image. In addition, the display driving circuit 120 can also perform emission (EM) control management, gate driver array (GOA) control management and power supply voltage management on the display screen 130, and output emission (EM) signals, emission layer positive voltage (emission layer VDD, ELVDD) signals, emission layer negative voltage (emission layer VSS, ELVSS) signals, GOA clock signals, etc. to the display screen. In the embodiment of the present application, the video source signal may also be referred to as a source signal.

[0064] Optionally, multiple display driver circuits may be connected via an interface to facilitate clock synchronization or interaction. In some examples, the display driver circuit may also be referred to as a display driver integrated circuit (DDIC).

[0065] The display screen 140 is used to receive video source signals from the display driving circuit 120 and the display driving circuit 130 respectively, and display an image. The display screen may include a folding display screen or a non-folding display screen. The display screen 140 may be implemented as a flexible screen or a rigid display screen. The flexible screen may include, for example, an organic light-emitting diode (OLED) display screen and other structures, which are not limited in the embodiments of the present application.

[0066] Figure 2 FIG. 1 is a schematic diagram of a process flow of video data in a multi-display driving circuit system according to an embodiment of the present application. Figure 2As shown, the display screen 140 can be divided into a first display area 11 and a second display area 12, the first display area 11 corresponds to the first display driving circuit 120, and the second display area 12 corresponds to the second display driving circuit 130. Different display driving circuits (120, 130) are used to drive different display areas. Optionally, there may be an interface between the first display driving circuit 120 and the second display driving circuit 130, and clock synchronization or signaling interaction is performed through the interface.

[0067] The main controller 110 can divide the video data into multiple sub-video data according to the multiple display areas, and send the sub-video data to different display driving circuits respectively. After each of the multiple display driving circuits processes the corresponding sub-video data, multiple sub-video source signals are obtained. The multiple display driving circuits can send the multiple sub-video source signals to the display screen respectively to drive different display areas of the display screen to display images.

[0068] In order to facilitate the understanding of the scheme of the present application, the structure and working principle of the pixel circuit and GOA in the display screen of the embodiment of the present application are introduced below in conjunction with the accompanying drawings. It should be noted that the following description is only an example of the pixel circuit and is not intended to limit the scope of protection of the present application. The scheme or its variation obtained by those skilled in the art based on the scheme of the present application without creative work also falls within the scope of protection of the present application.

[0069] The pixel circuit is the smallest circuit unit in the display screen. A pixel circuit is equivalent to a sub-pixel (or sub-pixel) in the display screen, and the display screen includes multiple rows of sub-pixels. Based on the structure of the pixel circuit, the sub-pixels in the display screen are scanned and emitted line by line. Therefore, when displaying a frame of image, after the first row of sub-pixels emits light, it is necessary to keep emitting light until the last row of sub-pixels emits light, so that a frame of image can be displayed. GOA is used to control the opening or closing of each row of GOA in the display screen to control the input of the selection signal for each row of pixel circuits.

[0070] Figure 3 is a circuit diagram of a pixel circuit according to an embodiment of the present application. Figure 3As shown, the pixel circuit 50 may include a capacitor Cst, a light emitting device L, and a plurality of transistors (M1, M2, M3, M4, M5, M6, M7). For the convenience of explanation, the transistor M1 is called a first reset transistor, the transistor M7 is called a second reset transistor, the transistor M4 is called a driving transistor, the transistor M6 is called a first light emitting control transistor, and the transistor M5 is called a second light emitting control transistor. It should be noted that this is only an example of a pixel circuit, and the pixel circuit may also adopt other designs, such as a 2T1C circuit including only 2 transistors and 1 capacitor, a 4T1C circuit including 4 transistors and 1 capacitor, a 5T2C circuit including 5 transistors and 2 capacitors, etc. The designs of these pixel circuits can control the conduction and cutoff of a transistor connected in series with the light emitting device through an EM signal, thereby realizing the control of the light emission of the light emitting device, and the embodiments of the present application are not limited to this.

[0071] It should be noted that the light emitting device L may be an organic light emitting diode (OLED). In this case, the display screen is an OLED display screen. Alternatively, the light emitting device L may be a micro light emitting diode (mirco light emitting diode, mirco LED). In this case, the display screen is a mirco LED display screen. For the convenience of description, the following examples are all taken as examples in which the light emitting device L is an OLED.

[0072] based on Figure 3 The structure of the pixel circuit 50 shown in FIG. 5 includes the following steps: Figure 4-Figure 6 There are three stages shown, the first stage ①, the second stage ② and the third stage ③. Figure 4 , Figure 5 as well as Figure 6 For the convenience of explanation, the transistors that are cut off are distinguished by adding an "×" mark.

[0073] In the first stage①, under the control of the strobe signal GN-1, Figure 4 As shown, the first reset transistor M1 and the second reset transistor M7 are turned on. The initial voltage Vint is transmitted to the gate of the driving transistor M4 through the first reset transistor M1, thereby resetting the gate of the driving transistor M4. In addition, the initial voltage Vint is transmitted to the anode (anode, a) of the OLED through the second reset transistor M7, resetting the anode a of the OLED. At this time, the voltage Va of the anode a of the OLED and the voltage Vg4 of the gate g of the driving transistor M4 are Vint.

[0074] In this way, in the first stage ①, the voltage of the gate g of the driving transistor M4 and the anode a of the OLED can be reset to the initial voltage Vint, thereby preventing the voltage remaining on the gate g of the driving transistor M4 and the anode a of the OLED in the previous image frame from affecting the next image frame. Therefore, the first stage ① can be called a reset stage.

[0075] In the second stage ②, under the control of the strobe signal GN, Figure 5 As shown, transistor M2 and transistor M3 are turned on. When transistor M3 is turned on, the gate g of the driving transistor M4 is coupled to the drain (d for short), and the driving transistor M4 is in a diode-on state. At this time, the data voltage Vdata is written to the source s of the driving transistor M4 through the turned-on transistor M2. Therefore, the second stage ② above can be called the data voltage Vdata writing stage of the pixel circuit.

[0076] In the third stage ③, under the control of the light emitting control signal EM, the second light emitting control transistor M5 and the first light emitting control transistor M6 are turned on, and the current path between the high power supply voltage ELVDD and the low power supply voltage ELVSS is turned on. The driving current I generated by the driving transistor M4 is transmitted to the OLED through the above current path to drive the OLED to emit light.

[0077] Since the OLED emits light in the third stage ③, the third stage ③ can be called the light-emitting stage. From the description of the third stage ③, it can be seen that the EM signal can control the pixel circuit to be in a light-emitting state or a non-light-emitting state.

[0078] Combine the following Figure 7 and Figure 8 The working principle of the GOA circuit in the embodiment of the present application is introduced. Figure 7 Schematic diagram of the structure of GOA according to an embodiment of the present application. Figure 8 4 is a timing diagram of a GOA circuit according to an embodiment of the present application.

[0079] like Figure 7 As shown, GOA includes a GCK clock input terminal and a GCB clock input terminal, which are used to receive a GCK clock signal and a GCB clock signal. Among them, the GCK clock signal and the GCB clock signal are a pair of mutually inverted clock signals. The GCK clock signal and the GCB clock signal can be input to the display screen by the GOA management module in the display driving circuit. GOA also includes a GN-1 signal input terminal, which is used to receive a gating signal of a pixel circuit of the previous row of the display screen. GOA also includes a GN signal output terminal, which is used to output a gating signal of the pixel circuit of the current row corresponding to GOA.

[0080] Figure 8The G1 signal, G2 signal, ..., GN-1 signal, and GN signal in the display screen respectively represent the selection signals of the pixel circuits of the first row to the Nth row in the display screen. That is, the GN signal and the GN-1 signal are equivalent to Figure 3-Figure 6 The strobe signals GN and GN-1 in the display are shown in Figure 1. The STV signal represents the start signal. Under the control of the GCK clock signal and the GCB clock signal, after the STV signal is started, the strobe signals G1 and G2 control the pixel circuits of each row to start refreshing in turn. The GCK controls the strobe signal to refresh the pixel circuits of each row in turn until all display areas in the display screen are scanned.

[0081] In order to enable multiple display areas in a display screen to display images synchronously, clock synchronization is required between multiple display driving circuits in a multi-display driving system. In a clock synchronization scheme, multiple display driving circuits can be divided into a main display driving circuit and at least one auxiliary display driving circuit. The main display driving circuit outputs a clock synchronization signal to the auxiliary display driving circuit, and the auxiliary display driving circuit performs clock synchronization of the internal circuit of the auxiliary display driving circuit according to the clock synchronization signal received from the main display driving circuit. For example, the above-mentioned clock synchronization signal may include a vertical synchronization (vertical synchronization, V-Sync) signal and a horizontal synchronization (horizontal synchronization, H-Sync) signal. The vertical synchronization signal is used to synchronize the frames of the scanned image, and the horizontal synchronization signal is used to synchronize the rows of the scanned image. However, the clock signal in the row for scanning each row of pixels is generated by the internal reference clock of each display driving circuit, and there is an error in the internal clock frequency of different display driving circuits, which will affect the display performance of the display screen. For example, due to differences in the working environment (for example, temperature, humidity, etc.) and the device itself, the internal clock frequencies of different display driving circuits cannot be exactly the same.

[0082] In the prior art, the gate driver on array (GOA) clock signal is generated based on the internal reference clock signal of the display driver circuit, so there is an error in the frequency of the GOA clock signals of different display driver circuits. Among them, the GOA clock signal is used to control the opening or closing of the GOA of the display screen. For the auxiliary display driver circuit, its GOA clock signal and horizontal synchronization signal are generated based on different reference clock signals. During the row scanning time interval, the GOA opening time of the display area driven by the auxiliary display driver circuit will be reduced, resulting in insufficient charging time for the pixel circuit in the row, thereby affecting the performance of the display screen. Among them, as an example, the GOA clock signal may include Figure 7 or Figure 8 The GCK signal and the GCB signal in the example.

[0083] In order to solve the above problems, an embodiment of the present application proposes a driving scheme for a multi-display driving system. In this scheme, each of the multiple display driving circuits receives a first clock signal sent by a main controller, and generates a GOA clock signal based on the first clock signal. Since the GOA clock signals output by the multiple display driving circuits are all generated based on the first clock signal, the frequency error between the GOA clock signals output by the multiple display driving circuits is reduced, so that the GOA clock signals between the multiple display driving circuits can be effectively synchronized, thereby improving the display performance of the display screen.

[0084] Fig. 9 is a schematic diagram of an electronic device according to an embodiment of the present application. Fig. 9 As shown, the electronic device includes a main controller 110, a display driving circuit 120, a display driving circuit 130 and a display screen 140, and the functions of the above modules are described as follows.

[0085] Display screen 140 : includes a first display area 11 and a second display area 12 .

[0086] The main controller 110 includes a first clock output terminal, wherein the first clock output terminal is used to send a first clock signal to the first display driving circuit and the second display driving circuit respectively.

[0087] As an example, the first clock output terminal may be a MIPI TX interface of a main controller, which may output a relatively high-frequency and relatively stable clock frequency, such as a frequency of tens to hundreds of megahertz.

[0088] The first display driving circuit 120: includes a first clock receiving end, and the first clock receiving end is used to receive the first clock signal; the first display driving circuit 120 also includes a first gate drive array GOA clock signal output end, and the first GOA clock signal output end is used to output a first GOA clock signal to the display screen, and the first GOA clock signal is used to control the GOA of the first display area to turn on or off, wherein the first GOA clock signal is generated based on the first clock signal.

[0089] The second display driving circuit 130 includes a second clock receiving end, the second clock receiving end is used to receive the first clock signal; the second display driving circuit 130 also includes a second GOA clock signal output end, the second GOA clock signal output end is used to output a second GOA clock signal to the display screen, the second GOA clock signal is used to control the GOA of the second display area to be turned on or off, wherein the second GOA clock signal is generated based on the first clock signal.

[0090] by Figure 7 or Figure 8 For example, the first GOA clock signal may be a GCK signal corresponding to the first display area, and the second GOA clock signal may be a GCK signal corresponding to the second display area. Alternatively, the first GOA clock signal may be a GCB signal corresponding to the first display area, and the second GOA clock signal may be a GCB signal corresponding to the second display area. The GCK signal and the GCB signal are a pair of mutually inverted clock signals.

[0091] Optionally, the first GOA clock signal and the second GOA clock signal may be signals with the same phase.

[0092] The first GOA clock signal is generated based on the first clock signal, which may mean that the first GOA clock signal uses the first clock signal as a reference clock signal. In one example, the first clock signal may be divided or multiplied to obtain a second clock signal, and the first GOA clock signal may be generated based on the second clock signal. The second GOA clock signal or other clock signals are similar, and will not be described here for brevity.

[0093] In the embodiment of the present application, a plurality of display driving circuits in the electronic device Each display driver circuit can Receive a first clock signal sent by the main controller, and generate based on the first clock signal GOA clock signal, so that multiple displays The display driving circuit outputs GOA The clock signals are generated based on the same clock signal, which can reduce The same display driver circuit GOA The error between the frequencies of the clock signals improves the display performance of the display.

[0094] like Fig.10 As shown, in one example, the first display driving circuit 120 includes a first GCK signal output terminal and a first GCB signal output terminal, which are respectively used to output the first GCK signal and the first GCB signal. The second display driving circuit 130 includes a second GCK signal output terminal and a second GCB signal output terminal. The phases of the first GCK signal and the second GCK signal can be the same. The phases of the first GCB signal and the second GCB signal can be the same. The first GCK signal, the second GCK signal, the first GCB signal, and the second GCB signal are all generated based on the first clock signal. In other words, Fig. 9 The first GOA clock signal output end includes the first GCK signal output end and / or the first GCB signal output end, and the second GOA clock signal output end includes the second GCK signal output end and / or the second GCB signal output end.

[0095] Optionally, each of the plurality of display driving circuits may further generate a vertical synchronization signal (i.e., a V-sync signal) based on the first clock signal sent by the main controller, wherein the vertical synchronization signal is used for synchronization between frames of the scanned image. As an example, the duration of each time frame may be 16.67 ms (milliseconds), i.e., the refresh rate of the display screen is 60 Hz (hertz). Then the frequency of V-sync is 60 Hz.

[0096] Continue to see Fig.10 In one example, the first display driving circuit further includes a first vertical synchronization signal output terminal (or referred to as a first V-sync signal output terminal), and the first vertical synchronization signal output terminal is used to output a first vertical synchronization signal (or referred to as a first V-sync signal). The first vertical synchronization signal is generated based on the first clock signal, and the first vertical synchronization signal is used to perform frame synchronization of the first display area; the second display driving circuit further includes a second vertical synchronization signal output terminal (or referred to as a second V-sync signal output terminal), and the second vertical synchronization signal terminal is used to output a second vertical synchronization signal (or referred to as a second V-sync signal). The second vertical synchronization clock signal is generated based on the first clock signal, and the second vertical synchronization signal is used to perform frame synchronization of the second display area. Optionally, the first vertical synchronization signal and the second vertical synchronization signal are signals with the same phase.

[0097] In an embodiment of the present application, each of the multiple display driving circuits in the electronic device can receive a first clock signal sent by a main controller, and generate a vertical synchronization signal based on the first clock signal, so that the vertical synchronization signals output by the multiple display driving circuits to the display screen are generated based on the same signal, thereby reducing the frequency error of the vertical synchronization signal between different display driving circuits, and reducing the timing error between the vertical synchronization signal and the GOA clock signal, thereby improving the display performance of the display screen.

[0098] Optionally, each of the plurality of display drive circuits may also generate a horizontal synchronization signal based on the first clock signal sent by the main controller, and the horizontal synchronization signal is used for synchronization between rows of the scanned image. As an example, the duration of each time frame may be 16.67 ms (milliseconds), that is, the refresh rate of the display screen is 60 Hz. Then the frequency of V-sync is 60 Hz. Then the frequency of the horizontal synchronization signal is the refresh rate multiplied by the number of rows. For example, if the display screen has 2000 rows of pixels, the frequency of H-sync is 120 kHz (kilohertz).

[0099] Continue to see Fig.10In one example, the first display driving circuit further includes a first horizontal synchronization signal output terminal (or referred to as a first H-sync output terminal), and the first horizontal synchronization signal output terminal is used to output a first horizontal synchronization signal (or referred to as a first H-sync signal). The first horizontal synchronization signal is generated based on the first clock signal, and the first horizontal synchronization signal is used to perform row synchronization of the first display area; the second display driving circuit further includes a second horizontal synchronization signal output terminal (or referred to as a second H-sync output terminal), and the second horizontal synchronization signal output terminal is used to output a second horizontal synchronization signal (or referred to as a second H-sync signal). The second horizontal synchronization signal is generated based on the first clock signal, and the second horizontal synchronization signal is used to perform row synchronization of the second display area, and the first horizontal synchronization signal and the second horizontal synchronization signal are signals with the same phase.

[0100] In an embodiment of the present application, each of the multiple display driving circuits in the electronic device receives a first clock signal sent by a main controller, and generates a horizontal synchronization signal based on the first clock signal, so that the horizontal synchronization signals output by the multiple display driving circuits to the display screen are generated based on the same clock signal. Therefore, the frequency error of the horizontal synchronization signal between different display driving circuits can be reduced, and the timing error between the horizontal synchronization signal and the GOA clock signal can be reduced, thereby improving the display performance of the display screen.

[0101] As an example, the vertical synchronization signal and the horizontal synchronization signal output by the display driving circuit may also adopt the solution in the prior art, that is, the auxiliary display driving circuit generates the vertical synchronization signal and the horizontal synchronization signal based on the clock signal output by the main display driving circuit. In this solution, although there is an error between the vertical synchronization signal (or horizontal synchronization signal) and the GOA clock signal received by different display areas of the display screen, since the GOA clock signals received by different display areas are synchronized, the time error between the vertical synchronization signal (or horizontal synchronization signal) and the GOA clock signal is fixed within the time interval of each frame (or each row), and will not accumulate with the increase of time, so the impact on the display performance of the display screen is limited.

[0102] Continue to see Fig.10In one example, the first display driving circuit further includes a first EM signal output terminal, which is used to output a first EM signal to the display screen, wherein the first EM signal is used to control the pixel circuit in the first display area to emit light or not, wherein the first EM signal is generated based on the first clock signal; the second display driving circuit further includes a second EM signal output terminal, wherein the second EM signal output terminal is used to output a second EM signal to the display screen, wherein the second EM signal is used to control the pixel circuit in the second display area to emit light or not, wherein the second EM signal is generated based on the first clock signal.

[0103] In an embodiment of the present application, each of the multiple display driving circuits in the electronic device receives a first clock signal sent by a main controller, and generates an EM signal based on the first clock signal, so that the EM signals output by the multiple display driving circuits to the display screen are generated based on the same clock signal, thereby reducing the frequency error of the EM signal between different display driving circuits, and reducing the timing error between the EM signal and the GOA clock signal, thereby improving the display performance of the display screen.

[0104] Fig.11 Schematic diagram of the structure of a display driving circuit according to an embodiment of the present application. Fig.11 The display driver circuit in can be applied to Figure 1 , Figure 2 , Fig. 9 or Fig.10 The display driving circuit 120 and / or the display driving circuit 130 in FIG. Fig.10 As shown, the display driving circuit includes but is not limited to the following modules: a video processing module, a clock processing module, an internal clock generation module, a GOA management module and an EM management module. It should be noted that Fig.11 The structure in the figure is only an example and not a limitation. The display driving circuit may include more or fewer functional modules than the above modules. For example, the display driving circuit may also include a power management module, etc. The working principle of each module and the connection relationship between the modules can be expanded and deformed according to the actual application, and the embodiments of the present application are not limited to this.

[0105] The video processing module is used to receive the video data sent by the main controller, and process the video data to generate a video source signal. The video processing module includes a digital circuit part and an analog circuit part, and the video data is processed by the digital circuit and the analog circuit in turn.

[0106] Fig.12 FIG. 1 is a schematic diagram of the structure of a digital circuit of a video processing module of a display driving circuit according to an embodiment of the present application. Fig.12As shown, the digital circuit part may include but is not limited to: frame buffers, decoders, and pixel pipelines. The pixel pipeline includes a plurality of digital modules for pipeline processing of pixel data, such as a digital module for brightness adjustment. Video data may be processed by the frame buffers, decoders, and pixel pipelines in sequence.

[0107] After being processed by the digital circuit part, the video data stream needs to be further processed by the analog circuit part before it can be output to the display screen. Fig.13 FIG. 1 is a schematic diagram of the structure of an analog circuit of a video processing module of a display driving circuit according to an embodiment of the present application. Fig.13 As shown, the analog circuit part includes but is not limited to modules such as shift register, data latch, digital to analog converter (DAC), data output buffer, etc. The video data stream processed by the digital circuit can be processed by the shift register, data latch, DAC, data output buffer, etc. modules in sequence to generate a video source signal.

[0108] Continue to see Fig.11 In one example, the clock processing module receives a first clock signal sent by the main controller, generates a second clock signal based on the first clock signal, and outputs the second clock signal to the GOA management module as a reference clock signal of the GOA management module. The GOA management module generates a GOA clock signal based on the second clock signal, and the GOA clock signal may include the above-mentioned GCK signal and / or GCB signal.

[0109] In one example, the clock processing module may include a clock frequency division circuit. The first clock signal output by the main controller is usually a high-frequency signal, and the display driving circuit needs to perform frequency division processing on the first clock signal to obtain a low-frequency second clock signal, and then use the second clock signal as a reference clock signal inside the display driving circuit.

[0110] Continue to see Fig.11 In one example, the display driving circuit may further include an EM management module, and the EM management module may generate an EM signal based on the second clock signal, and the EM signal is used to control the pixel circuit in the display screen to emit light or not.

[0111] In a possible solution, the display driving circuit can use the first clock signal as the main reference clock signal inside the display driving circuit. For example, the first clock signal can be used as the clock signal of the digital circuit part and the module circuit part in the video processing module. However, since each clock signal in the display driving circuit is generated based on the same clock signal, this will result in the frequency range of the clock signal inside the display driving circuit being inflexible and adjustable, thus causing problems such as timing convergence and electromagnetic interference (EMI) for the display driving circuit.

[0112] In order to avoid the above problems, in the embodiment of the present application, the display driving circuit can use the third clock signal generated by the internal clock generating module as the reference clock signal of the digital circuit part of the display driving circuit. The first clock signal can be used as the reference clock signal of the analog circuit part of the display driving circuit, the EM management module and / or the GOA management module.

[0113] Continue to see Fig.11 In one example, the internal clock generation module is used to generate a third clock signal, and the third clock signal can be used as a reference clock signal for the digital circuit part of the video processing module, such as the digital modules in the frame buffer, decoder and pixel pipeline. The third clock signal is a clock signal generated inside the display driving circuit. In one example, the internal clock generation module includes an oscillator (OSC).

[0114] Continue to see Fig.11 In one example, the first clock signal can be used as a reference clock signal for the analog circuit part of the video processing module. As an example, the first clock signal can be divided by the clock processing module to obtain a second clock signal, and the second clock signal can be used as a reference signal for the analog circuit part of the video processing module. For example, the second clock signal can be used to control a shift register and an analog circuit module after the shift register.

[0115] like Fig.11 As shown, since the reference clock signal of the digital circuit and the reference clock of the back-end analog circuit are decoupled, in order to compensate for the timing error that may be generated between different reference clocks, a first buffer can be added between the digital circuit part and the analog circuit part. The first buffer can be used to compensate for the delay caused by the different reference clock signals between the digital circuit part and the analog circuit part. The first buffer receives the second clock signal and the third clock signal, and buffers the input video data according to the above clock signals to compensate for the timing error. Fig.14FIG. 1 is a schematic diagram of a video processing module in a display driving circuit according to an embodiment of the present application. Fig.14 As shown, as an example, the buffer can be arranged between the pixel pipeline module of the digital circuit part and the shift register of the analog circuit part.

[0116] It should be noted that in Fig.11 In the embodiment, the second clock signal may be processed once or multiple times by frequency division, frequency multiplication or other types of processing before being input into each module in the video processing module. The embodiment of the present application takes the second clock signal as an example for explanation. Alternatively, in some examples, the display driving circuit does not need to perform frequency division, frequency multiplication or other processing on the first clock signal, and can directly input the first clock signal into each module as a reference clock signal. In other words, Fig.11 The clock processing module in the figure is only used as an example. The first clock signal may not be processed before being input into each module, or may be processed by multiple frequency division or frequency multiplication. Fig.11 In the embodiment, the second clock signal may represent one or more clock signals, that is, the second clock signal input to each module may be the same signal with the same frequency, or may be multiple signals with different frequencies, and the second clock signal is only used as an exemplary description of a clock signal generated based on the first clock signal. Similarly, the third clock signal is only used as an exemplary description of a clock signal generated based on the internal clock signal of the display driving circuit.

[0117] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0118] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0119] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0120] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0121] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0122] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage media include: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memories (ROM), random access memories (RAM), magnetic disks or optical disks.

[0123] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. An electronic device, characterized in that: include: A display screen, comprising a first display area and a second display area; A main controller, comprising a first clock output terminal, wherein the first clock output terminal is used to send a first clock signal to the first display driving circuit and the second display driving circuit respectively; The first display driving circuit comprises a first clock receiving end, wherein the first clock receiving end is used to receive the first clock signal; The second display driving circuit comprises a second clock receiving end, wherein the second clock receiving end is used to receive the first clock signal; The first display driving circuit further includes a first GOA clock signal output terminal, the first GOA clock signal output terminal is used to output a first GOA clock signal to the first display area, and the first GOA clock signal is generated based on the first clock signal; The second display driving circuit also includes a second GOA clock signal output terminal, which is used to output a second GOA clock signal to the second display area, and the second GOA clock signal is generated based on the first clock signal.

2. The electronic device according to claim 1, wherein: The first display driving circuit further comprises a first vertical synchronization signal output terminal, which is used to output a first vertical synchronization signal, wherein the first vertical synchronization signal is used to perform frame synchronization of the first display area; The second display driving circuit further includes a second vertical synchronization signal output terminal, configured to output a second vertical synchronization signal; The second vertical synchronization signal is used for frame synchronization of the second display area, and the first vertical synchronization signal and the second vertical synchronization signal are signals with the same phase.

3. The electronic device according to claim 1 or 2, characterized in that: The first display driving circuit further comprises a first horizontal synchronization signal output terminal, which is used to output a first horizontal synchronization signal, wherein the first horizontal synchronization signal is used to perform row synchronization of the first display area; The second display driving circuit further includes a second horizontal synchronization signal output terminal for outputting a second horizontal synchronization signal, wherein the second horizontal synchronization signal is used for performing row synchronization of the second display area.

4. The electronic device according to claim 1 or 2, characterized in that: The first display driving circuit further comprises a first light emitting EM signal output terminal, which is used to output a first EM signal, wherein the first EM signal is used to control the pixel circuits in the first display area to emit light or not emit light; The second display driving circuit further includes a second EM signal output terminal for outputting a second EM signal, wherein the second EM signal is used to control the pixel circuits in the second display area to emit light or not emit light.

5. The electronic device according to claim 1 or 2, characterized in that: The first display driving circuit includes a video processing module, which is used to process the video data input by the main controller to generate a video source signal sent to the display screen. The reference clock of the digital circuit in the video processing module is the third clock signal generated by the internal clock generating module of the first display driving circuit, and the reference clock of the analog circuit in the video processing module is the first clock signal.

6. The electronic device according to claim 5, characterized in that: The video processing module is provided with a first buffer, and the first buffer is provided between the digital circuit and the analog circuit in the video processing module.

7. A display driving circuit, characterized in that: The display driving circuit comprises: a first display driving circuit and a second display driving circuit; The first display driving circuit comprises a first clock receiving end, and the first clock receiving end is used to receive a first clock signal; The first display driving circuit further includes a first GOA clock signal output terminal, the first GOA clock signal output terminal is used to output a first GOA clock signal, and the first GOA clock signal is generated based on the first clock signal; The second display driving circuit comprises a second clock receiving end, and the second clock receiving end is used to receive the first clock signal; The second display driving circuit further includes a second GOA clock signal output terminal, where the second GOA clock signal output terminal is used to output a second GOA clock signal, where the second GOA clock signal is generated based on the first clock signal.

8. The display driving circuit according to claim 7, characterized in that: The display driving circuit also includes a first vertical synchronization signal output terminal for outputting a first vertical synchronization signal.

9. The display driving circuit according to claim 7 or 8, characterized in that: The display driving circuit also includes a first horizontal synchronization signal output terminal for outputting a first horizontal synchronization signal.

10. The display driving circuit according to claim 7 or 8, characterized in that: The first display driving circuit further includes a first luminous EM signal output terminal for outputting a first EM signal.

11. The display driving circuit according to claim 7 or 8, characterized in that: The display driving circuit includes a video processing module, which is used to process the video data input by the main controller to generate a video source signal. The reference clock of the digital circuit in the video processing module is the third clock signal generated by the internal clock generating module of the display driving circuit, and the reference clock of the analog circuit in the video processing module is the first clock signal.

12. The display driving circuit according to claim 11, characterized in that: The video processing module is provided with a first buffer, and the first buffer is provided between the digital circuit and the analog circuit in the video processing module.

13. A method for driving a display screen, characterized in that: The display screen includes a first display area and a second display area, and the method includes: The first display driving circuit and the second display driving circuit receive a first clock signal respectively; The first display driving circuit outputs a first GOA clock signal to the first display area, wherein the first GOA clock signal is generated based on the first clock signal; The second display driving circuit outputs a second GOA clock signal to the second display area, where the second GOA clock signal is generated based on the first clock signal.

14. The method according to claim 13, characterized in that The method further includes: the first display driving circuit outputting a first vertical synchronization signal, the first vertical synchronization signal being used for frame synchronization of the first display area; The second display driving circuit outputs a second vertical synchronization signal, where the second vertical synchronization signal is used for frame synchronization of the second display area; The first vertical synchronization signal and the second vertical synchronization signal are signals with the same phase.

15. The method according to claim 13 or 14, characterized in that The first display driving circuit further comprises a first horizontal synchronization signal output terminal, which is used to output a first horizontal synchronization signal, wherein the first horizontal synchronization signal is used to perform row synchronization of the first display area; The second display driving circuit further includes a second horizontal synchronization signal output terminal for outputting a second horizontal synchronization signal, wherein the second horizontal synchronization signal is used for performing row synchronization of the second display area.

16. The method according to claim 13 or 14, characterized in that The first display driving circuit further comprises a first light emitting EM signal output terminal, which is used to output a first EM signal, wherein the first EM signal is used to control the pixel circuits in the first display area to emit light or not emit light; The second display driving circuit further includes a second EM signal output terminal for outputting a second EM signal, wherein the second EM signal is used to control the pixel circuits in the second display area to emit light or not emit light.

17. The method according to claim 13 or 14, characterized in that The first display driving circuit includes a video processing module, which is used to process video data input by a main controller to generate a video source signal sent to the display screen. The reference clock of the digital circuit in the video processing module is a third clock signal generated by an internal clock generating module of the first display driving circuit, and the reference clock of the analog circuit in the video processing module is the first clock signal.

18. The method according to claim 17, characterized in that The video processing module is provided with a first buffer, and the first buffer is provided between the digital circuit and the analog circuit in the video processing module.

19. A display module, characterized in that: include: A display screen, comprising a first display area and a second display area; A first display driving circuit comprises a first clock receiving end, wherein the first clock receiving end is used to receive a first clock signal; The first display driving circuit further includes a first GOA clock signal output terminal, the first GOA clock signal output terminal is used to output a first GOA clock signal to the first display area, and the first GOA clock signal is generated based on the first clock signal; A second display driving circuit comprises a second clock receiving end, wherein the second clock receiving end is used to receive the first clock signal; The second display driving circuit also includes a second GOA clock signal output terminal, which is used to output a second GOA clock signal to the second display area, and the second GOA clock signal is generated based on the first clock signal.

20. The display module according to claim 19, wherein: The first display driving circuit further comprises a first vertical synchronization signal output terminal, which is used to output a first vertical synchronization signal, wherein the first vertical synchronization signal is used to perform frame synchronization of the first display area; The second display driving circuit further comprises a second vertical synchronization signal output terminal, which is used to output a second vertical synchronization signal, and the second vertical synchronization signal is used to perform frame synchronization of the second display area; The first vertical synchronization signal and the second vertical synchronization signal are signals with the same phase.

21. The display module according to claim 19 or 20, characterized in that: The first display driving circuit further comprises a first horizontal synchronization signal output terminal, which is used to output a first horizontal synchronization signal, wherein the first horizontal synchronization signal is used to perform row synchronization of the first display area; The second display driving circuit further includes a second horizontal synchronization signal output terminal for outputting a second horizontal synchronization signal, wherein the second horizontal synchronization signal is used for performing row synchronization of the second display area.

22. The display module according to claim 19 or 20, characterized in that: The first display driving circuit further comprises a first light emitting EM signal output terminal, which is used to output a first EM signal, wherein the first EM signal is used to control the pixel circuits in the first display area to emit light or not emit light; The second display driving circuit further includes a second EM signal output terminal, wherein the second EM signal output terminal is used to output a second EM signal, and the second EM signal is used to control the pixel circuits in the second display area to emit light or not emit light.

23. The display module according to claim 19 or 20, characterized in that: The first display driving circuit includes a video processing module, which is used to process video data input by a main controller to generate a video source signal sent to the display screen. The reference clock of the digital circuit in the video processing module is a third clock signal generated by an internal clock generating module of the first display driving circuit, and the reference clock of the analog circuit in the video processing module is the first clock signal.

24. The display module according to claim 23, wherein: The video processing module is provided with a first buffer, and the first buffer is provided between the digital circuit and the analog circuit in the video processing module.

Images