Centralized error correction circuit

Abstract

This application relates to centralized error correction circuitry. An apparatus can include non-volatile memory disposed on a first die and volatile memory disposed on a second die (different from the first die). The apparatus can also include an interface controller disposed on a third die (different from the first die and the second die). The interface controller can be coupled with the non-volatile memory and the volatile memory, and can include error correction circuitry configured to operate on one or more codewords received from the volatile memory.

Description

[0001] Cross-references to related applications

[0002] This patent application claims priority to U.S. Provisional Patent Application No. 63 / 140,096, entitled “Centralized Error Correction Circuit,” filed January 21, 2021, which is assigned to the assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to centralized error correction circuits. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into different states. For example, a binary memory cell can be programmed to support one of two states, typically indicated by logic 1 or logic 0. In some instances, a single memory cell can support more than two states and can store any of those states. To access the stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write to or program the states in the memory device.

[0005] Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), auto-select memory, and chalcogenide memory technology. Memory cells can be volatile or non-volatile. For example, non-volatile FeRAM can maintain its stored logic state for a long time even without an external power supply. Volatile DRAM devices, on the other hand, may lose their stored state when disconnected from an external power source. Summary of the Invention

[0006] An apparatus is described. The apparatus may include: a non-volatile memory disposed on a first die; a volatile memory disposed on a second die and configured to serve as a cache for the non-volatile memory, the volatile memory including a plurality of memory banks; and an interface controller disposed on a third die and coupled to the non-volatile memory and the volatile memory, the interface controller including error correction code (ECC) circuitry coupled to the volatile memory and configured to operate on one or more codewords received from the volatile memory.

[0007] A method is described. The method can be performed by a memory device and may include: receiving a codeword from a bank of volatile memory disposed on a first die, the volatile memory serving as a cache for non-volatile memory; performing an error detection operation on the codeword from the bank of memory using ECC circuitry included in an interface controller disposed on a second die and coupled to both the non-volatile memory and the volatile memory; and transmitting data bits of the codeword from the interface controller to a host device, at least in part based on the performance of the error detection operation.

[0008] An apparatus is described. The apparatus may include: a non-volatile memory disposed on a first die, the non-volatile memory including a plurality of memory banks; a volatile memory disposed on a second die and configured to serve as a cache for the non-volatile memory; and an interface controller disposed on a third die and coupled to the non-volatile memory and the volatile memory, the interface controller including ECC circuitry coupled to the non-volatile memory and configured to operate on one or more codewords received from the non-volatile memory.

[0009] A method is described. The method is executable by a device and may include: receiving a codeword from a bank of non-volatile memory disposed on a first die; performing an error detection operation on the codeword from the bank of memory using ECC circuitry included in an interface controller disposed on a second die, the interface controller being coupled to the non-volatile memory and volatile memory serving as a cache for the non-volatile memory; and transmitting data bits of the codeword from the interface controller to a host device, at least in part based on the performance of the error detection operation. Attached Figure Description

[0010] Figure 1 Examples of systems that support centralized error correction circuits, as illustrated in the examples disclosed herein.

[0011] Figure 2This section describes an example of a memory subsystem that supports centralized error correction circuitry, based on examples disclosed herein.

[0012] Figure 3 Examples of devices that support centralized error correction circuits, as described in the examples disclosed herein.

[0013] Figure 4 This document describes an example of a processing flow that supports a centralized error correction circuit, as illustrated in the examples disclosed herein.

[0014] Figure 5 This document describes an example of a processing flow that supports a centralized error correction circuit, as illustrated in the examples disclosed herein.

[0015] Figure 6 This document describes an example of a processing flow that supports a centralized error correction circuit, as illustrated in the examples disclosed herein.

[0016] Figure 7 A block diagram of an interface controller supporting centralized error correction circuitry, based on examples disclosed herein, is shown.

[0017] Figure 8 and 9 The flowchart illustrates one or more methods for supporting centralized error correction circuits, based on examples disclosed herein. Detailed Implementation

[0018] For example, electronic devices may include non-volatile memory (e.g., main memory for storing information and other operations) and volatile memory (e.g., secondary memory), which can be used as a cache for the non-volatile memory. This configuration allows the device to benefit from the advantages of non-volatile memory (e.g., non-volatile and persistent storage, high storage capacity, low power consumption) while maintaining compatibility with the host device via the volatile memory. The volatile memory may be disposed on a memory die and may contain multiple memory banks. To improve reliability, each memory bank of the volatile memory may be coupled to a corresponding error correction code (ECC) circuit on the memory die, which detects and corrects errors in the data read from the memory bank. However, including ECC circuitry on the memory die reduces the memory die area available for other components such as memory cells, thereby reducing the capacity of the volatile memory.

[0019] According to the techniques described herein, the capacity of volatile memory can be increased and other advantages can be achieved by including ECC circuitry for volatile memory on the die (e.g., substrate) of a memory controller coupled to volatile memory. This configuration may be referred to herein as a centralized ECC circuit. The centralized ECC circuitry can be configured to operate on codewords from some or all banks of the volatile memory, and can be relatively faster than other ECC circuitry (e.g., ECC circuitry disposed on the memory die) due to the more efficient and effective processes associated with manufacturing the memory controller. In some instances, a second centralized ECC circuitry can also be used for the non-volatile memory of the device to increase the capacity (or reduce the physical size) of the non-volatile memory (e.g., relative to non-volatile memory containing one or more on-die ECC circuitry), and other benefits exist.

[0020] First, as referenced Figures 1 to 2 The features of this disclosure are described in the context of the systems and subsystems described herein. (See references...) Figure 3 The described apparatus and as referenced Figures 4 to 6 The features of this disclosure are described in the context of the described processing flow. (See references...) Figures 7 to 8 The device diagrams and flowcharts relating to the centralized ECC circuit described herein are used to further illustrate and describe these and other features of this disclosure, and reference is made to the device diagrams and flowcharts described herein.

[0021] Figure 1 This document describes an example of a system 100 supporting centralized error correction circuitry, as disclosed herein. System 100 may be included in an electronic device, such as a computer or telephone. System 100 may include a host device 105 and a memory subsystem 110. Host device 105 may be a processor or system-on-a-chip (SoC) that interfaces with interface controller 115 and other components of the electronic device containing system 100. Memory subsystem 110 may store and provide access to electronic information (e.g., digital information, data) for host device 105. Memory subsystem 110 may include interface controller 115, volatile memory 120, and non-volatile memory 125. In some instances, interface controller 115, volatile memory 120, and non-volatile memory 125 may be included in the same physical package, such as package 130. However, interface controller 115, volatile memory 120, and non-volatile memory 125 may be disposed on different corresponding dies (e.g., silicon dies).

[0022] Devices in system 100 can be coupled via various wires (e.g., traces, printed circuit board (PCB) wiring, redistribution layer (RDL) wiring), which enables the transmission of information (e.g., commands, addresses, data) between devices. Wires can form channels, data buses, command buses, address buses, etc.

[0023] Memory subsystem 110 may be configured to provide the benefits of non-volatile memory 125 while maintaining compatibility with host device 105 that supports protocols for different types of memory, such as volatile memory 120, and other instances. For example, non-volatile memory 125 may provide benefits (e.g., relative to volatile memory 120) such as non-volatility, higher capacity, or lower power consumption. However, host device 105 may be incompatible with or inefficiently configured with various aspects of non-volatile memory 125. For example, host device 105 may support voltages, access latency, protocols, page sizes, etc., that are incompatible with non-volatile memory 125. To compensate for the incompatibility between host device 105 and non-volatile memory 125, memory subsystem 110 may be configured with volatile memory 120 that is compatible with host device 105 and acts as a cache for non-volatile memory 125. Therefore, host device 105 can use the protocols supported by volatile memory 120 while also benefiting from the advantages of non-volatile memory 125.

[0024] In some instances, system 100 may be contained in, or coupled to, a computing device, electronic device, mobile computing device, or wireless device. The device may be a portable electronic device. For example, the device may be a computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, etc. In some instances, the device may be configured for bidirectional wireless communication via a base station or access point. In some instances, the device associated with system 100 may be capable of machine-type communication (MTC), machine-to-machine (M2M) communication, or device-to-device (D2D) communication. In some instances, the device associated with system 100 may be referred to as user equipment (UE), station (STA), mobile terminal, etc.

[0025] Host device 105 may be configured to interface with memory subsystem 110 using a first protocol (e.g., Low Power Double Data Rate (LPDDR)) supported by interface controller 115. Therefore, in some instances, host device 105 may interface directly with interface controller 115 and indirectly with non-volatile memory 125 and volatile memory 120. In alternative instances, host device 105 may interface directly with non-volatile memory 125 and volatile memory 120. Host device 105 may also interface with other components of the electronic device comprising system 100. Host device 105 may be or include a SoC, a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or another programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof. In some instances, host device 105 may be referred to as a host.

[0026] Interface controller 115 can be configured (e.g., based on or in response to one or more commands or requests issued by host device 105) to interface with volatile memory 120 and non-volatile memory 125 on behalf of host device 105. For example, interface controller 115 can facilitate the retrieval and storage of data in volatile memory 120 and non-volatile memory 125 on behalf of host device 105. Therefore, interface controller 115 can facilitate data transfer between various sub-components, such as data transfer between at least some of host device 105, volatile memory 120, or non-volatile memory 125. Interface controller 115 can interface with host device 105 and volatile memory 120 using a first protocol and with non-volatile memory 125 using a second protocol supported by non-volatile memory 125.

[0027] Non-volatile memory 125 may be configured to store digital information (e.g., data) for electronic devices including system 100. Therefore, non-volatile memory 125 may include one or more memory cell arrays and a local memory controller configured to operate the memory cell arrays. In some instances, the memory cells may be or include FeRAM cells (e.g., non-volatile memory 125 may be FeRAM). Non-volatile memory 125 may be configured to interface with interface controller 115 using a second protocol different from the first protocol used between interface controller 115 and host device 105. In some instances, non-volatile memory 125 may have a longer latency for access operations compared to volatile memory 120. For example, retrieving data from non-volatile memory 125 may take longer than retrieving data from volatile memory 120. Similarly, writing data to non-volatile memory 125 may take longer than writing data to volatile memory 120. In some instances, non-volatile memory 125 may have a smaller page size than volatile memory 120, as described herein.

[0028] Volatile memory 120 may be configured to serve as a cache for one or more components, such as non-volatile memory 125. For example, volatile memory 120 may store information (e.g., data) for electronic devices containing system 100. Therefore, volatile memory 120 may include one or more memory cell arrays and a local memory controller configured to operate the memory cell arrays. In some instances, the memory cells may be or include DRAM cells (e.g., the volatile memory may be DRAM). Non-volatile memory 125 may be configured to interface with interface controller 115 using a first protocol used between interface controller 115 and host device 105.

[0029] In some instances, volatile memory 120 may have shorter latency for access operations compared to non-volatile memory 125. For example, retrieving data from volatile memory 120 may take less time than retrieving data from non-volatile memory 125. Similarly, writing data to volatile memory 120 may take less time than writing data to non-volatile memory 125. In some instances, volatile memory 120 may have a larger page size than non-volatile memory 125. For example, the page size of volatile memory 120 may be 2 kilobytes (2kB) and the page size of non-volatile memory 125 may be 64 bytes (64B) or 128 bytes (128B).

[0030] While non-volatile memory 125 may be a higher-density memory compared to volatile memory 120, accessing non-volatile memory 125 may take longer than accessing volatile memory 120 (e.g., due to different architectures and protocols, and other reasons). Therefore, using volatile memory 120 as a cache can reduce latency in system 100. As an example, by retrieving data from volatile memory 120 instead of from non-volatile memory 125, access requests for data from host device 105 can be satisfied relatively quickly. To facilitate the operation of volatile memory 120 as a cache, interface controller 115 may include multiple buffers 135. Buffers 135 may be disposed on the same die as interface controller 115 and may be configured to temporarily store data for transfer between volatile memory 120, non-volatile memory 125, or host device 105 (or any combination thereof) during one or more access operations (e.g., store and retrieve operations).

[0031] Access operations may also be referred to as access procedures or access routines and may involve one or more sub-operations performed by one or more components of the memory subsystem 110. Examples of access operations may include: a storage operation in which data provided by the host device 105 is stored (e.g., written to) volatile memory 120 or non-volatile memory 125 (or both); and a retrieval operation in which data requested by the host device 105 is obtained (e.g., read) from volatile memory 120 or non-volatile memory 125 and returned to the host device 105.

[0032] To store data in memory subsystem 110, host device 105 can initiate a storage operation (or “stored procedure”) by transmitting a storage command (also referred to as a storage request, write command, or write request) to interface controller 115. The storage command can target a set of non-volatile memory cells in non-volatile memory 125. In some instances, the set of memory cells may also be referred to as part of the memory. Host device 105 can also provide data to be written to said set of non-volatile memory cells to interface controller 115. Interface controller 115 can temporarily store the data in buffer 135-a. After storing the data in buffer 135-a, interface controller 115 can transfer the data from buffer 135-a to volatile memory 120 or non-volatile memory 125, or both. In write-through mode, interface controller 115 can transfer data to both volatile memory 120 and non-volatile memory 125. In write-back mode, the interface controller 115 may transfer data only to the volatile memory 120 (wherein data is transferred to the non-volatile memory 125 during a later eviction process).

[0033] In any mode, interface controller 115 may identify a suitable set of one or more volatile memory cells in volatile memory 120 for storing data associated with a store command. To this end, interface controller 115 may implement a set-associative mapping, wherein one or more non-volatile memory cells in each set (e.g., block) of non-volatile memory 125 may be mapped to multiple sets of volatile memory cells in volatile memory 120. For example, interface controller 115 may implement an n-way associative mapping, which allows data from a set of non-volatile memory cells to be stored in one of n sets of volatile memory cells in volatile memory 120. Therefore, interface controller 115 can manage volatile memory 120 as a cache for non-volatile memory 125 by referencing n sets of volatile memory cells associated with a set of target non-volatile memory cells. As used herein, unless otherwise described or mentioned, a “set” of objects may refer to one or more of the objects. Although the reference group associative mapping has been described, the interface controller 115 can manage the volatile memory 120 as a cache by implementing one or more other types of mappings, such as direct mapping or associative mapping, and other instances.

[0034] After determining which n sets of volatile memory cells are associated with the target set of non-volatile memory cells, the interface controller 115 can store data in one or more of the n sets of volatile memory cells. Therefore, by retrieving data from the lower latency volatile memory 120 instead of the higher latency non-volatile memory 125, subsequent retrieval commands for data from the host device 105 can be efficiently satisfied. The interface controller 115 can determine which of the n sets of volatile memory 120 stores data based on or in response to determining one or more parameters (e.g., data validity, age, or modification status) associated with the data stored in the n sets of volatile memory 120. Therefore, the host device 105's storage commands can be satisfied fully (e.g., in write-back mode) or partially (e.g., in write-through mode) by storing data in the volatile memory 120. In order to track data stored in volatile memory 120, interface controller 115 may store tag addresses for one or more sets of volatile memory cells (e.g., for each set of volatile memory cells), the tag addresses indicating non-volatile memory cells with data stored in a given set of volatile memory cells.

[0035] To retrieve data from memory subsystem 110, host device 105 can initiate a retrieval operation (also referred to as a retrieval process) by transmitting a retrieval command (also referred to as a retrieval request, read command, or read request) to interface controller 115. The retrieval command can target one or more non-volatile memory cells in non-volatile memory 125. Upon receiving the retrieval command, interface controller 115 can examine the requested data in volatile memory 120. For example, interface controller 115 can examine the requested data in n sets of volatile memory cells associated with the target set of non-volatile memory cells. If one of the n sets of volatile memory cells stores the requested data (e.g., stores data for the target set of non-volatile memory cells), then interface controller 115 can transfer the data from volatile memory 120 to buffer 135-a (e.g., in response to determining whether one of the n sets of volatile memory cells stores the requested data, such as...). Figure 4 and 5 (as described in the document), so that the data can be transmitted to the host device 105.

[0036] Generally, the term "hit" can be used to refer to a scenario where volatile memory 120 stores data targeted by host device 105. If one or more sets of n volatile memory cells do not store the requested data (e.g., n sets of volatile memory cells store data for a set of non-volatile memory cells other than the target set of non-volatile memory cells), then interface controller 115 may transfer the requested data from non-volatile memory 125 to buffer 135-a (e.g., in response to determining whether the n sets of volatile memory cells do not store the requested data, as referenced). Figure 4 and 5 As described, this allows the data to be transmitted to the host device 105. Generally, the term "miss" can be used to refer to a situation where the volatile memory 120 does not store the data targeted by the host device 105.

[0037] More specifically, a write hit refers to a scenario where data in volatile memory 120 is associated with a non-volatile memory address targeted by a write command from the host device (e.g., matching data stored at said non-volatile memory address); while a write miss refers to a scenario where no data associated with the non-volatile memory address exists in volatile memory 120.

[0038] In a miss scenario, after transferring the requested data to buffer 135-a, interface controller 115 may transfer the requested data from buffer 135-a to volatile memory 120, so that subsequent read requests for the data can be satisfied through volatile memory 120 instead of non-volatile memory 125. For example, interface controller 115 may store data in one of n sets of volatile memory cells associated with the target set of non-volatile memory cells. However, the n sets of volatile memory cells may already store data for other sets of non-volatile memory cells. Therefore, to preserve this other data, interface controller 115 may transfer the other data to buffer 135-b, so that the other data can be transferred to non-volatile memory 125 for storage. This process may be referred to as "eviction," and the data transferred from volatile memory 120 to buffer 135-b may be referred to as "victimized" data. In some cases, interface controller 115 may transfer a subset of the victimized data from buffer 135-b to non-volatile memory 125. For example, interface controller 115 may transmit one or more subsets of victim data that have changed since the data was initially stored in non-volatile memory 125. Data that is inconsistent between volatile memory 120 and non-volatile memory 125 (e.g., due to updates in one memory while not in the other) may be referred to as “modified” or “dirty” data in some cases. In some instances (e.g., if the interface controller is operating in a mode such as write-back mode), dirty data may be data that exists in volatile memory 120 but not in non-volatile memory 125.

[0039] System 100 may include any number of non-transitory computer-readable media supporting one or more centralized error correction circuits. For example, host device 105, interface controller 115, volatile memory 120, or non-volatile memory 125 may include or otherwise access one or more non-transitory computer-readable media storing instructions (e.g., firmware) to perform functions attributed herein to host device 105, interface controller 115, volatile memory 120, or non-volatile memory 125. For example, such instructions, when executed by host device 105 (e.g., by a host device controller), by interface controller 115, by volatile memory 120 (e.g., by a local controller), or by non-volatile memory 125 (e.g., by a local controller), may cause host device 105, interface controller 115, volatile memory 120, or non-volatile memory 125 to perform the associated functions as described herein.

[0040] As mentioned, volatile memory 120 may comprise multiple banks, which reduces overhead (e.g., for managing stored information in volatile memory) compared to using a single bank, and offers other advantages. All banks of volatile memory 120 may be housed on a single memory die along with control components such as a controller and supporting circuitry. To improve reliability, at least some banks of volatile memory 120 (if not every bank) may have associated ECC circuitry also housed on the memory die. The ECC circuitry associated with a bank may be configured to operate on data from (or for) said bank. However, for various reasons, such as manufacturing limitations associated with the memory die, the ECC circuitry for a bank may not be able to correct data as quickly as readable data (e.g., error correction latency may be longer than read latency). This latency difference may render single-die ECC circuitry unusable for volatile memory 120, as it could become a bottleneck for outgoing data, causing gaps in data transmission on the outgoing data bus. However, as described above, adding additional ECC circuitry to the memory die to allow parallel ECC operations reduces the area of ​​the memory die available for memory cells. Furthermore, using per-bank ECC circuitry on the memory die can increase power consumption and latency, and has other drawbacks.

[0041] According to the techniques described herein, by using ECC circuitry on the die of interface controller 115 (“controller die”) for volatile memory 120, the capacity of volatile memory 120 can be increased relative to other configurations, and power consumption and latency can be reduced. Since the processes associated with the controller die are faster than those on the memory die, the ECC circuitry on the controller die may be faster than other ECC circuitry (e.g., error correction latency may be shorter than data read latency), which allows centralized ECC circuitry to be used for some or all of the banks of volatile memory 120. Therefore, system capacity, power consumption, and latency can be improved. Although described with reference to volatile memory 120, the centralized ECC circuitry techniques described herein can also be used for non-volatile memory 125 (e.g., by using ECC circuitry on the die of interface controller 115 (“controller die”) for non-volatile memory 125) for similar reasons and with similar advantages.

[0042] ECC circuitry may also be referred to herein as ECC logic, ECC circuitry system, ECC component, or other suitable terms. Centralized ECC circuitry may also be referred to as “off-die” die ECC circuitry, where the term “off-die” is relative to a memory die (e.g., may include a die of volatile memory 120 or non-volatile memory 125 or both).

[0043] Figure 2 This describes an example of a memory subsystem 200 supporting centralized error correction circuitry, as disclosed herein. The memory subsystem 200 may be a reference. Figure 1 An example of the described memory subsystem 110. Therefore, the memory subsystem 200 can be compared with, as referenced... Figure 1 The host device interaction is described. The memory subsystem 200 may include an interface controller 202, volatile memory 204, and non-volatile memory 206, which may be as described in reference... Figure 1 Examples of the described interface controller 115, volatile memory 120, and non-volatile memory 125. Therefore, the interface controller 202 may represent, as referenced... Figure 1 The described host device interfaces with volatile memory 204 and non-volatile memory 206. For example, the interface controller 202 may use volatile memory 204 as a cache for non-volatile memory 206. Using volatile memory 204 as a cache allows the subsystem to provide the benefits of non-volatile memory 206 (e.g., non-volatile, high-density storage) while maintaining compatibility with host devices that support protocols different from those of non-volatile memory 206.

[0044] exist Figure 2 In this diagram, dashed lines between components represent data flows or data transmission paths, while solid lines between components represent command flows or command transmission paths. In some cases, the memory subsystem 200 is one of several similar or identical subsystems that may be included in an electronic device. In some instances, each subsystem may be referred to as a slice and may be associated with a corresponding channel of the host device.

[0045] Non-volatile memory 206 may be configured to be used as main memory for a host device (e.g., memory for long-term data storage). In some cases, non-volatile memory 206 may comprise one or more arrays of FeRAM cells. Each FeRAM cell may include a select element and a ferroelectric capacitor and can be accessed by applying appropriate voltages to one or more access lines, such as word lines, board lines, and digital lines. In some instances, a subset of FeRAM cells coupled to an active word line may be sensed, for example, in parallel or simultaneously, without needing to sense all FeRAM cells coupled to an active word line. Therefore, the page size for the FeRAM array may differ from (e.g., be smaller than) the DRAM page size. In the context of a memory device, a page may refer to a row of memory cells (e.g., a group of memory cells with a common row address), and the page size may refer to the number of memory cells or column addresses in a row, or the number of column addresses accessed during an access operation. Alternatively, the page size may refer to the size of data handled by various interfaces, or the amount of data that a row can store. In some cases, different memory device types may have different page sizes. For example, the page size of DRAM (e.g., 2kB) may be a superset of the page size of non-volatile memory (e.g., FeRAM) (e.g., 64B).

[0046] The smaller page size of FeRAM arrays offers various efficiency benefits because a single FeRAM cell may require more power to read or write compared to a single DRAM cell. For example, a smaller page size for FeRAM arrays promotes efficient energy use because a smaller number of FeRAM cells can be activated with minimal associated changes in information. In some instances, depending on the nature of the data and commands used for FeRAM operations, the page size for the FeRAM cell array can, for example, change dynamically (e.g., during operation of the FeRAM cell array).

[0047] While a single FeRAM cell may require more power to read or write compared to a single DRAM cell, a FeRAM cell can maintain its stored logic state for a long period without an external power supply because the ferroelectric material in the FeRAM cell can maintain a non-zero polarization in the absence of an electric field. Therefore, including an FeRAM array in non-volatile memory 206 can provide power and efficiency benefits relative to volatile memory cells (e.g., DRAM cells in volatile memory 204) because it reduces or eliminates the need to perform refresh operations.

[0048] Volatile memory 204 may be configured to serve as a cache for non-volatile memory 206. In some cases, volatile memory 204 may comprise one or more arrays of DRAM cells. Each DRAM cell may include a capacitor containing dielectric material for storing charges representing programmable states. The memory cells of volatile memory 204 may be logically grouped or arranged into one or more memory banks (as referred to herein as “banks”). For example, volatile memory 204 may comprise sixteen banks. The memory cells of a bank may be arranged in a grid or an array of intersecting columns and rows, and each memory cell may be accessed or refreshed by applying an appropriate voltage to the digital lines (e.g., column lines) and word lines (e.g., row lines) for the memory cell. A row of a bank may be referred to as a page, and the page size may refer to the number of columns or memory cells in the row (and therefore, the amount of data that the row can store). As mentioned, the page size of volatile memory 204 may be different from (e.g., larger than) the page size of non-volatile memory 206.

[0049] Interface controller 202 may include various circuitry for interfacing (e.g., communicating) with other devices, such as host devices, volatile memory 204, and non-volatile memory 206. For example, interface controller 202 may include a data (DA) bus interface 208, a command and address (C / A) bus interface 210, a data bus interface 212, a C / A bus interface 214, a data bus interface 216, and a C / A bus interface 264. The data bus interfaces may support the use of one or more communication protocols to convey information. For example, data bus interface 208, C / A bus interface 210, data bus interface 216, and C / A bus interface 264 may support information conveyed using a first protocol (e.g., LPDDR signaling), while data bus interface 212 and C / A bus interface 214 may support information conveyed using a second protocol. Therefore, the various bus interfaces coupled to interface controller 202 may support different data volumes or data rates.

[0050] Data bus interface 208 may be coupled to data bus 260, transaction bus 222, and buffer circuitry 224. Data bus interface 208 may be configured to transmit and receive data via data bus 260 and control information (e.g., acknowledgment / negative acknowledgment) or metadata via transaction bus 222. Data bus interface 208 may also be configured to transfer data between data bus 260 and buffer circuitry 224. Data bus 260 and transaction bus 222 may be coupled to interface controller 202 and host device, thereby establishing a conductive path between interface controller 202 and host device. In some instances, the pin of transaction bus 222 may be referred to as a Data Mask Inversion (DMI) pin. Although shown as having one data bus 260 and one transaction bus 222, any number of data buses 260 and any number of transaction buses 222 coupled to one or more data bus interfaces 208 may exist.

[0051] C / A bus interface 210 can be coupled to C / A bus 226 and decoder 228. C / A bus interface 210 can be configured to transmit and receive commands and addresses via C / A bus 226. Commands and addresses received via C / A bus 226 can be associated with data received or transmitted via data bus 260. C / A bus interface 210 can also be configured to transmit commands and addresses to decoder 228, such that decoder 228 can decode commands and forward the decoded commands and associated addresses to command circuitry 230.

[0052] Data bus interface 212 can be coupled to data bus 232 and memory interface circuitry 234. Data bus interface 212 can be configured to transmit and receive data via data bus 232, which can be coupled to non-volatile memory 206. Data bus interface 212 can also be configured to transfer data between data bus 232 and memory interface circuitry 234. C / A bus interface 214 can be coupled to C / A bus 236 and memory interface circuitry 234. C / A bus interface 214 can be configured to receive commands and addresses from memory interface circuitry 234 and forward commands and addresses to non-volatile memory 206 via C / A bus 236 (e.g., to a local controller of non-volatile memory 206). Commands and addresses transmitted via C / A bus 236 can be associated with data received or transmitted via data bus 232. The data bus 232 and the C / A bus 236 can be coupled to the interface controller 202 and the non-volatile memory 206, thereby establishing a conductive path between the interface controller 202 and the non-volatile memory 206.

[0053] Data bus interface 216 may be coupled to data bus 238 (e.g., data bus 238-a, data bus 238-b) and memory interface circuitry 240. Data bus interface 216 may be configured to transmit and receive data via data bus 238, which may be coupled to volatile memory 204. Data bus interface 216 may also be configured to transfer data between data bus 238 and memory interface circuitry 240. C / A bus interface 264 may be coupled to C / A bus 242 and memory interface circuitry 240. C / A bus interface 264 may be configured to receive commands and addresses from memory interface circuitry 240 and forward commands and addresses to volatile memory 204 (e.g., to a local controller of volatile memory 204) via C / A bus 242. Commands and addresses transmitted via C / A bus 242 may be associated with data received or transmitted via data bus 238. The data bus 238 and the C / A bus 242 can be coupled to the interface controller 202 and the volatile memory 204, thereby establishing a conductive path between the interface controller 202 and the volatile memory 204.

[0054] In addition to the bus and bus interface for communicating with the coupled device, the interface controller 202 may also include circuitry for using non-volatile memory 206 as main memory and volatile memory 204 as cache. For example, the interface controller 202 may include command circuitry 230, buffer circuitry 224, cache management circuitry 244, one or more engines 246, and one or more schedulers 248.

[0055] Command circuitry system 230 may be coupled to buffer circuitry system 224, decoder 228, cache management circuitry system 244, scheduler 248, and other components. Command circuitry system 230 may be configured to receive command and address information from decoder 228 and store the command and address information in queue 250. Command circuitry system 230 may include logic 262 that processes command information (e.g., from a host device) and stores information from other components (e.g., cache management circuitry system 244, buffer circuitry system 224) and uses the information to generate one or more commands for scheduler 248. Command circuitry system 230 may also be configured to transmit address information (e.g., address bits) to cache management circuitry system 244. In some instances, logic 262 may be circuitry configured to function as a finite state machine (FSM).

[0056] Buffer circuitry system 224 may be coupled to data bus interface 208, command circuitry system 230, memory interface circuitry system 234, and memory interface circuitry system 234. Buffer circuitry system 224 may include one or more sets of buffer circuitry for at least some (if not every) banks of volatile memory 204. Buffer circuitry system 224 may also include components for accessing the buffer circuitry (e.g., a memory controller). In one example, volatile memory 204 may include sixteen banks and buffer circuitry system 224 may include sixteen sets of buffer circuitry. Each set of buffer circuitry may be configured to store data from or for (or from and for) a corresponding bank of volatile memory 204. As an example, the set of buffer circuitry for bank 0 (BK0) may be configured to store data from or for (or from and for) a first bank of volatile memory 204, and the set of buffer circuitry for bank 15 (BK15) may be configured to store data from or for (or from and for) a sixteenth bank of volatile memory 204.

[0057] Each set of buffer circuits in buffer circuit system 224 may include a pair of buffers. The pair of buffers may include: one buffer (e.g., an Open Page Data (OPD) buffer) configured to store data targeted by an access command (e.g., a write command or read command) from the host device; and another buffer (e.g., a Victim Page Data (VPD) buffer) configured to store data for an eviction process triggered by the access command. For example, the buffer circuit set for BK0 may include buffers 218 and 220, which may be instances of buffers 135-a and 135-b, respectively. Buffer 218 may be configured to store BK0 data targeted by an access command from the host device. And buffer 220 may be configured to store data transferred from BK0 as part of an eviction process triggered by an access command. Each buffer in the buffer circuit set may be configured with a size (e.g., storage capacity) corresponding to the page size of volatile memory 204. For example, if the page size of volatile memory 204 is 2kB, then the size of each buffer can be 2kB. Therefore, in some instances, the size of the buffer can be equivalent to the page size of volatile memory 204.

[0058] Cache management circuitry system 244 may be coupled to command circuitry system 230, engine 246, scheduler 248, and other components. Cache management circuitry system 244 may include cache management circuitry groups for one or more banks of volatile memory (e.g., each bank of memory). As an example, cache management circuitry system 244 may include sixteen cache management circuitry groups for BK0 through BK15. Each cache management circuitry group may include two memory arrays configured to store storage information for volatile memory 204. As an example, the cache management circuitry group for BK0 may include memory array 252 (e.g., a cache DRAM tag array (CDT-TA)) and memory array 254 (e.g., a CDRAM active (CDT-V) array), configured to store storage information for BK0. In some instances, the memory array may also be referred to as an array or buffer. In some cases, the memory array may be or contain volatile memory cells, such as static RAM (SRAM) cells.

[0059] Storage information (or “metadata”) may include content information, validity information, or dirty information (or any combination thereof) associated with volatile memory 204, and other instances. Content information (which may also be referred to as tag information or address information) indicates which data is stored in a set of volatile memory cells. For example, the content information (e.g., tag address) of a row in volatile memory 204 may indicate which set of one or more non-volatile memory cells currently has data stored in that row. As mentioned, validity information may indicate whether the data stored in a set of volatile memory cells is actual data (e.g., data with an expected order or form) or placeholder data (e.g., random or dummy data without an expected or important order). Dirty information may indicate whether the data stored in one or more volatile memory cells of volatile memory 204 is different from the corresponding data stored in one or more non-volatile memory cells of non-volatile memory 206. For example, dirty information may indicate whether the data stored in a set of volatile memory cells has been updated relative to the data stored in non-volatile memory 206.

[0060] Memory array 252 may include memory cells storing storage information (e.g., tag information, validity information, dirty information) for associated memory banks (e.g., BK0) of volatile memory 204. The storage information may be stored on a row-by-row basis (e.g., each row of an associated non-volatile memory bank may contain corresponding storage information). Interface controller 202 can examine requested data in volatile memory 204 by referring to the storage information in memory array 252. For example, interface controller 202 may receive a retrieval command from a host device for data in a set of non-volatile memory cells in non-volatile memory 206. Interface controller 202 may refer to the storage information in memory array 252 using a set of one or more address bits (e.g., a set of row address bits) targeted by the access request. For example, using set-associative mapping, interface controller 202 may refer to the content information in memory array 252 to determine which set of volatile memory cells (if present) stores the requested data.

[0061] In addition to storing content information for the volatile memory cells, memory array 252 may also store validity information indicating whether data in a set of volatile memory cells is actual data (also referred to as valid data) or random data (also referred to as invalid data). For example, volatile memory cells in volatile memory 204 may initially store random data and continue to do so until data is written to the volatile memory cells from a host device or non-volatile memory 206. To track which data is valid, memory array 252 may be configured to set a bit for each set (e.g., row) of volatile memory cells when actual data is stored in the set of volatile memory cells. This bit may be referred to as a validity bit or validity flag. Like the content information, the validity information stored in memory array 252 may be stored on a row-by-row basis. Thus, in some instances, each validity bit may indicate the validity of data stored in the associated row.

[0062] In some instances, memory array 252 may store dirty information indicating whether a set (e.g., rows) of volatile memory cells contains any dirty data. Similar to validity information, the dirty information stored in memory array 252 may be stored on a row-by-row basis.

[0063] Memory array 254 may be similar to memory array 252 and may also include memory cells storing storage information for banks (e.g., BK0) of volatile memory 204 associated with memory array 252. For example, memory array 254 may store validity information and dirt information for banks of volatile memory 204. However, the storage information stored in memory array 254 may be stored on a sub-block basis rather than on a row-by-row basis. For example, validity information stored in memory cells of memory array 254 may indicate the validity of data for a subset of volatile memory cells in a row of volatile memory 204.

[0064] As an example, validity information in memory array 254 can indicate the validity of each subset of data (e.g., 32B or 64B) stored in a row of BK0 in volatile memory 204. Similarly, dirty information stored in memory cells of memory array 254 can indicate which subset of volatile memory cells in a row of volatile memory 204 stores dirty data. For example, dirty information in memory array 254 can indicate the dirty state of each subset of data (e.g., 32B or 64B) stored in a row of BK0 in volatile memory 204. Storing storage information (e.g., tag information, validity information) in memory array 252 on a row-by-row basis allows interface controller 202 to determine whether data in volatile memory 204 has a hit or a miss. Storing storage information (e.g., validity information, dirty information) in memory array 254 on a sub-block basis allows interface controller 202 to determine which subsets of data are returned to the host device (e.g., during a retrieval process) and which subsets of data are retained in non-volatile memory 206 (e.g., during an eviction process).

[0065] Each cache management circuitry may also include a corresponding pair of registers, which are coupled to command circuitry 230, engine 246, memory interface circuitry 234, memory interface circuitry 240, and the memory array for the cache management circuitry, as well as other components. For example, a cache management circuitry may include a first register (e.g., register 256, which may be an Open Page Tag (OPT) register) configured to receive storage information (e.g., tag information, validity information, or dirty information, other information, or any combination of bits) from memory array 252 or scheduler 248-b, or both. The cache management circuitry may also include a second register (e.g., register 258, which may be a Victim Page Tag (VPT) register) configured to receive storage information (e.g., validity information and / or dirty information, or both) from memory array 254 and scheduler 248-a, or both. Information in registers 256 and 258 can be passed to command circuitry 230 and engine 246 to enable decisions to be made by these components. For example, the command circuitry 230 may issue a command to read non-volatile memory 206 or volatile memory 204 based on or in response to stored information in register 256 and / or register 258 or both.

[0066] Engine 246-a can be coupled to registers 256 and 258 and scheduler 248. Engine 246-a can be configured to receive stored information from various components and issue commands to scheduler 248 based on the stored information. For example, if interface controller 202 is in a first mode, such as write-through mode, then engine 246-a can issue commands to scheduler 248-b, and in response, scheduler 248-b initiates or facilitates data transfer from buffer 218 to both volatile memory 204 and non-volatile memory 206. Alternatively, if interface controller 202 is in a second mode, such as write-back mode, then engine 246-a can issue commands to scheduler 248-b, and in response, scheduler 248-b can initiate or facilitate data transfer from buffer 218 to volatile memory 204. In the case of a write-back operation, the data stored in volatile memory 204 can eventually be transferred to non-volatile memory 206 during a subsequent eviction process.

[0067] Engine 246-b may be coupled to register 258 and scheduler 248-a. Engine 246-b may be configured to receive stored information from register 258 and issue commands to scheduler 248-a based on the stored information. For example, engine 246-b may issue commands to scheduler 248-a to initiate or facilitate the transfer of dirty data from buffer 220 to non-volatile memory 206 (e.g., as part of an eviction process). If buffer 220 holds a set of data (e.g., victim data) transferred from volatile memory 204, engine 246-b may indicate which one or more subsets (e.g., which 64Bs) of said set of data in buffer 220 should be transferred to non-volatile memory 206.

[0068] Scheduler 248-a can be coupled to various components of interface controller 202 and can facilitate access to non-volatile memory 206 by issuing commands to memory interface circuitry 234. Commands issued by scheduler 248-a can be based on or in response to commands from command circuitry 230, engine 246-a, engine 246-b, or a combination of these components. Similarly, scheduler 248-b can be coupled to various components of interface controller 202 and can facilitate access to volatile memory 204 by issuing commands to memory interface circuitry 240. Commands issued by scheduler 248-b can be based on or in response to commands from command circuitry 230 or engine 246-a, or both.

[0069] The memory interface circuitry 234 can communicate with the non-volatile memory 206 via one or more of the data bus interface 212 and the C / A bus interface 214. For example, the memory interface circuitry 234 can prompt the C / A bus interface 214 to relay commands issued by the memory interface circuitry 234 to a local controller in the non-volatile memory 206 via the C / A bus 236. Furthermore, the memory interface circuitry 234 can transfer data to or receive data from the non-volatile memory 206 via the data bus 232. In some instances, commands issued by the memory interface circuitry 234 may be supported by the non-volatile memory 206 instead of the volatile memory 204 (e.g., commands issued by the memory interface circuitry 234 may differ from commands issued by the memory interface circuitry 240).

[0070] Memory interface circuitry 240 can communicate with volatile memory 204 via one or more of data bus interface 216 and C / A bus interface 264. For example, memory interface circuitry 240 can prompt C / A bus interface 264 to forward commands issued by memory interface circuitry 240 to the local controller of volatile memory 204 via C / A bus 242. Furthermore, memory interface circuitry 240 can transmit data to or receive data from volatile memory 204 via one or more data buses 238. In some instances, commands issued by memory interface circuitry 240 may be supported by volatile memory 204 instead of non-volatile memory 206 (e.g., commands issued by memory interface circuitry 240 may differ from commands issued by memory interface circuitry 234).

[0071] In summary, the components of the interface controller 202 can use the non-volatile memory 206 as main memory and the volatile memory 204 as cache. This operation can be prompted by one or more access commands (e.g., read / retrieve command / request and write / store command / request) received from the host device.

[0072] In some instances, interface controller 202 may receive a store command from a host device. The store command may be received via C / A bus 226 and transmitted to command circuitry 230 via one or more of C / A bus interface 210 and decoder 228. The store command may include or be accompanied by address bits targeting a memory address of non-volatile memory 206. Data to be stored may be received via data bus 260 and transmitted to buffer 218 via data bus interface 208. In write-through mode, interface controller 202 may transmit data to both non-volatile memory 206 and volatile memory 204. In write-back mode, interface controller 202 may transmit data only to volatile memory 204.

[0073] In either mode, the interface controller 202 may first check whether the volatile memory 204 has memory cells available for storing data. To do this, the command circuitry system 230 may refer to the memory array 252 (e.g., using a set of memory address bits) to determine whether one or more of the n groups (e.g., rows) of volatile memory cells associated with the memory address are empty (e.g., storing random or invalid data). For example, the command circuitry system 230 may determine whether one or more of the n groups (e.g., rows) of volatile memory cells are available based on tag information and validity information stored in the memory array 252. In some cases, a group of volatile memory cells in the volatile memory 204 may be referred to as a line, cache line, or row.

[0074] If one of the n sets of associated volatile memory cells is available to store information, then the interface controller 202 can transfer data from buffer 218 to volatile memory 204 for storage in said set of volatile memory cells. However, if the array of associated volatile memory cells is not empty, then the interface controller 202 can initiate an eviction process to free up space for data in volatile memory 204. The eviction process may involve transferring compromised data from one of the n sets of associated volatile memory cells to buffer 220. Dirty information for the compromised data can be transferred from memory array 254 to register 258 to identify a dirty subset of the compromised data. After the compromised data is stored in buffer 220, new data can be transferred from buffer 218 to volatile memory 204 and compromised data can be transferred from buffer 220 to non-volatile memory 206. In some cases, a dirty subset of the old data is transferred to non-volatile memory 206 and a clean subset (e.g., an unmodified subset) is discarded. Engine 246-b can identify a dirty subset based on or in response to dirty information transferred from memory array 254 to register 258 during the eviction process.

[0075] In another example, interface controller 202 may receive a retrieval command from a host device. The retrieval command may be received via C / A bus 226 and transmitted to command circuitry 230 via one or more of C / A bus interface 210 and decoder 228. The retrieval command may contain address bits targeting a memory address of non-volatile memory 206. Before attempting to access the target memory address of non-volatile memory 206, interface controller 202 may check whether volatile memory 204 stores data. To do this, command circuitry 230 may refer to memory array 252 (e.g., using a set of memory address bits) to determine whether one or more of the n groups (e.g., rows) of volatile memory cells associated with the memory address store the requested data. If the requested data is stored in volatile memory 204, then interface controller 202 may transmit the requested data to buffer 218 for transmission to the host device via data bus 260.

[0076] If the requested data is not stored in volatile memory 204, interface controller 202 may retrieve the data from non-volatile memory 206 and transfer the data to buffer 218 for transmission to the host device via data bus 260. Alternatively, interface controller 202 may transfer the requested data from buffer 218 to volatile memory 204, allowing data access with lower latency during subsequent retrieval operations. However, before transferring the requested data, interface controller 202 may first determine whether one or more of the n sets of associated volatile memory cells are available to store the requested data. Interface controller 202 may determine the availability of the n sets of associated volatile memory cells by communicating with the associated cache management circuitry. If a set of associated volatile memory cells is available, then interface controller 202 may transfer the data in buffer 218 to volatile memory 204 without performing an eviction process. Otherwise, interface controller 202 may transfer the data from buffer 218 to volatile memory 204 after performing an eviction process.

[0077] The memory subsystem 200 can be implemented in one or more configurations, including a single-chip version and a multi-chip version. The multi-chip version may include one or more components of the memory subsystem 200, including interface controller 202, volatile memory 204, and non-volatile memory 206 (and other components or combinations thereof), on a separate chip from the chip containing one or more other components of the memory subsystem 200. For example, in a multi-chip version, the corresponding separate chip may contain each of interface controller 202, volatile memory 204, and non-volatile memory 206. In contrast, the single-chip version may include interface controller 202, volatile memory 204, and non-volatile memory 206 on a single chip.

[0078] As mentioned, volatile memory 204 may comprise multiple banks (e.g., to keep the overhead of storing information manageable), and each bank may have associated ECC circuitry to compensate for slow ECC operations (e.g., due to slow processes associated with the memory die of volatile memory 204). Similarly, non-volatile memory 206 may comprise multiple banks, and each bank may have associated ECC circuitry. However, including per-bank ECC circuitry on the memory dies for volatile memory 204 and non-volatile memory 206 reduces the capacity of volatile memory 204 and non-volatile memory 206. According to the techniques described herein, the capacity of volatile memory 204 and non-volatile memory 206 can be increased (or the physical size of volatile memory 204 and non-volatile memory 206 can be reduced) by using first ECC logic for volatile memory 204 on interface controller 202 and second ECC logic for non-volatile memory 206 on interface controller 202, as an example.

[0079] While a corresponding centralized ECC circuitry for volatile memory 204 and non-volatile memory 206 has been described, a single centralized ECC circuitry is also alternatively considered. A single centralized ECC circuitry may serve one or both of volatile memory 204 and non-volatile memory 206. If a single centralized ECC circuitry serves volatile memory 204, then non-volatile memory 206 may have per-bank ECC circuitry on its memory die. If a single centralized ECC circuitry serves non-volatile memory 206, then volatile memory 204 may have per-bank ECC circuitry on its memory die.

[0080] Figure 3 This describes an example of a device 300 supporting a centralized error correction circuit, as disclosed herein. Device 300 may be as described in the references... Figure 1 The memory subsystem 110 described or as referenced Figure 2 An example of the described memory subsystem 200. The device may include an interface controller 302, volatile memory 305, and non-volatile memory 310, which may be coupled to each other via one or more transmission lines or buses, or both. As described herein, the device 300 may use centralized ECC circuitry 315 for volatile memory 305, non-volatile memory 310, or both.

[0081] Although contained in the same physical package, the interface controller 302, volatile memory 305, and non-volatile memory 310 may be housed on two or more different dies. For example, the interface controller 302 may be housed on a first die 320-a, the volatile memory on a second die 320-b, and the non-volatile memory 310 on a third die 320-c. The first die 320-a may be manufactured using advanced techniques that are not supported (or incompatible with) other dies and make the processes associated with the interface controller 302 faster. Therefore, ECC circuitry housed on the first die 320-a (e.g., ECC circuitry 315-a included in the interface controller 302) may be faster than ECC circuitry housed on memory dies (e.g., the second die 320-b or the third die 320-c). Although shown as being housed on different dies, in some instances, the volatile memory 305 and non-volatile memory 310 may be housed on the same die.

[0082] Volatile memory 305 may include multiple memory banks, denoted as memory banks 0 to 7, as well as supporting controllers and circuitry, such as I / O circuitry. Volatile memory 305 may offload error correction operations to centralized ECC circuitry on the first die 320-a, such as ECC circuitry 315-a, instead of using per-bank ECC circuitry on the second die 320-b for error correction. Although eight memory banks are shown, other numbers of memory banks are considered for volatile memory 305.

[0083] The non-volatile memory 310 may include multiple memory banks, denoted as memory banks 0 to 7. Instead of using eight ECC circuits on the third die 320-c for error correction operations on the memory banks (e.g., one ECC circuit per memory bank), the non-volatile memory 310 may offload its error correction operations to a centralized ECC circuit on the first die 320-a, such as ECC circuit 315-b. Although eight memory banks are shown, other numbers of memory banks are considered for the non-volatile memory 310.

[0084] At a high level, ECC circuit 315-a can perform encoding and decoding operations on volatile memory 305. For example, ECC circuit 315-a can encode data bits from a host device to generate codewords for storage in the memory bank of volatile memory 305. After ECC circuit 315-a generates the codewords, interface controller 302 can transmit the codewords to volatile memory 305, for example, for storage. If the host device requests data to be stored in volatile memory 305, ECC circuit 315-a can receive the codewords containing the data from volatile memory 305 and decode the codewords to detect any errors. After ECC circuit 315-a corrects any detected errors in the data, interface controller 302 can transmit the data to the host device.

[0085] Therefore, ECC circuit 315-a allows interface controller 302 to detect and correct errors (e.g., one-bit errors, two-bit errors) in data stored in volatile memory 305. Specifically, ECC circuit 315-a can encode (e.g., generate) codewords for storage in volatile memory 305 and decode codewords from volatile memory 305. For example, ECC circuit 315-a can use encoder 325 to generate parity bits, which, when combined with data bits, form codewords that can be used by memory subsystem 110 to detect errors in the codewords. Parity bits can be generated by applying error correction codes to data bits (which may involve transmitting data bits via logic circuitry consisting of, for example, a series of XOR logic gates). After ECC circuit 315-a generates codewords, interface controller 302 can transmit the codewords to volatile memory 305 for storage in the appropriate memory bank. Encoded codewords can be transmitted from interface controller 302 to volatile memory 305, for example, via I / O circuit 335-b.

[0086] If the host device requests data bits stored in volatile memory 305, volatile memory 305 can read a codeword containing the data bits and transmit the codeword to interface controller 302. Therefore, an uncorrected codeword can be transmitted to interface controller 302, for example, via I / O circuitry 335-b. ECC circuitry 315-a can use decoder 330 to decode the codeword by performing a series of logical operations to detect any errors in the codeword. If decoder 330 detects one or more errors in the data bits of the codeword, decoder 330 (or additional circuitry in ECC circuitry 315-a, or a combination of both) can correct the errors before transmitting the data bits to the host device. Therefore, ECC circuitry 315-a can detect and correct errors in the data from volatile memory 305 before returning data to the host device.

[0087] In some instances, ECC circuit 315-a may additionally or alternatively serve non-volatile memory 310. For example, ECC circuit 315-a may encode data for non-volatile memory 310 and decode data from non-volatile memory 310 (similar to how ECC circuit 315-a may encode data for volatile memory 305 and decode data from volatile memory 305). However, if different error correction codes are used for volatile memory 305 and non-volatile memory 310, or for other reasons, using the same centralized ECC circuit for both memories may be relatively more complex. Therefore, alternatively, non-volatile memory 310 may be served by ECC circuit 315-b. For example, ECC circuit 315-b may encode data for non-volatile memory 310 and decode data from non-volatile memory 310. Therefore, ECC circuit 315-b may operate similarly to ECC circuit 315-a and may include an encoder for encoding and a decoder for decoding. Encoding and decoding may generally be referred to as ECC operation. The encoder may also be referred to as encoder circuit, encoder circuit system, encoder logic, or other suitable terms. The decoder may also be referred to as decoder circuit, decoder circuit system, decoder logic, or other suitable terms.

[0088] Therefore, the error correction operations of volatile memory 305 and non-volatile memory 310 can be offloaded to the ECC circuit 315 on the first die 320-a, which, compared to other configurations, increases the space available for memory cells on the second die 320-b, the third die 320-c, or both, as well as other advantages.

[0089] Figure 4 This describes an example of a processing flow 400 that supports a centralized error correction circuit, as disclosed herein. Processing flow 400 can be derived from, as referenced... Figure 1 The described memory subsystem 110 or interface controller 115, as referenced Figure 2 The described memory subsystem 200 or interface controller 202, or as referenced Figure 3 The described device 300 or interface controller 302, or any combination thereof, may be implemented. However, other types of devices may implement the processing flow 400. The processing flow 400 may describe the operation of a device that uses one or more centralized ECC circuits for ECC operations of volatile and non-volatile memory.

[0090] For ease of reference, the reference apparatus describes processing flow 400. For example, aspects of processing flow 400 may be implemented by means including an interface controller, volatile memory, and non-volatile memory disposed on two or more different dies. Alternatively, aspects of processing flow 400 may be implemented as instructions stored in memory (e.g., firmware stored in volatile memory 120 or non-volatile memory 125, or both). For example, if the instructions are executed by the controller, then the controller may perform the operation of processing flow 400.

[0091] At 405, the first codeword may be received, for example, from volatile memory. For instance, interface controller 302 may receive the first codeword from volatile memory 305 via I / O circuitry 335-b. The first codeword may be read from a memory cell in any of memory banks B0 to B7 and may contain data bits and a parity bit generated based on the data bits. The data bits may be data bits requested by the host device or data bits involved in the evictment procedure, and other instances.

[0092] At 410, an error detection operation can be performed on the first codeword. For example, ECC circuit 315-a can decode the first codeword via decoder 330 to detect any errors in the first codeword. At 415, an error correction operation can be performed. For example, ECC circuit 315-a can correct one or more errors detected in the first codeword via decoder 330 or other circuitry. Error correction may refer to the bits of the codeword with the inverted error. In some instances, ECC circuit 315-a can be configured to correct errors in the data bits of the codeword but not errors in the parity bits (e.g., because data bits can be returned to the host device, while parity bits cannot). If no error is detected at 410, ECC circuit 315-a can skip the error correction operation at 415.

[0093] At 420, the data bits of the first codeword can be transmitted to, for example, a host device. For instance, the interface controller 302 can transmit the data bits of the first codeword to the host device. Alternatively, the data bits can be transmitted to non-volatile memory 310 (e.g., as part of an evictation procedure to free up some space in volatile memory 305).

[0094] At 425, a second codeword may be received, for example, from non-volatile memory. For instance, interface controller 302 may receive the second codeword from non-volatile memory 310 via I / O circuitry 335-c. The second codeword may be read from a memory cell in any of the banks B0 to B7 of non-volatile memory 310 and may include data bits and a parity bit generated based on the data bits. The data bits may be data bits requested by the host device or data bits involved in a padding procedure (e.g., a procedure that occurs in the event of a read miss, where data from non-volatile memory 310 is stored in volatile memory 305).

[0095] At 430, error detection can be performed on the second codeword. For example, ECC circuit 315-b can decode the second codeword via a decoder to detect any errors in the second codeword. At 435, error correction can be performed. For example, ECC circuit 315-b can correct one or more errors detected in the second codeword via a decoder or other circuitry. In some instances, ECC circuit 315-b can be configured to correct errors in the data bits of the codeword but not errors in the parity bits (e.g., because data bits can be returned to the host device, while parity bits cannot). If no error is detected at 430, ECC circuit 315-b can skip the error correction operation at 435.

[0096] At 440, the data bits of the second codeword can be transmitted to, for example, a host device. For instance, the interface controller 302 can transmit the data bits of the second codeword to the host device. Alternatively, the data bits can be transmitted to volatile memory 305 (e.g., as part of a filling process).

[0097] Therefore, the device can use one or more centralized ECC circuits for ECC operations on both volatile and non-volatile memory. For example, the device can use a first centralized ECC circuit for ECC operations on volatile memory and a second centralized ECC circuit for ECC operations on non-volatile memory. In another example, the device can use a single centralized ECC circuit for ECC operations on both volatile and non-volatile memory. In yet another example, the device can use a centralized ECC circuit for ECC operations on one of the memories and can use one or more on-die ECC circuits for ECC operations on other memories. It should be understood that an ECC operation performed on a first codeword from volatile memory can be performed at the same time (e.g., in parallel or simultaneously) or at different times with an ECC operation performed on a second codeword from non-volatile memory.

[0098] Alternative instances of the foregoing may be implemented, in which some operations may be performed in a different order than described, in parallel, or not at all. In some cases, operations may include additional features not mentioned below, or additional operations may be added. Furthermore, certain operations may be performed multiple times, or certain combinations of repeatable or cyclical operations may be performed.

[0099] Figure 5 This describes an example of a processing flow 500 that supports a centralized error correction circuit, as disclosed herein. Processing flow 500 can be derived from, as referenced... Figure 1 The described memory subsystem 110 or interface controller 115, as referenced Figure 2 The described memory subsystem 200 or interface controller 202, or as referenced Figure 3 The described apparatus 300 or interface controller 302, or any combination thereof, may be implemented. However, other types of apparatus may implement the processing flow 500. The processing flow 500 may describe the operation of an apparatus that uses centralized ECC circuitry for ECC operations of multiple banks of volatile memory. Although described with reference to volatile memory 305, the operation of the processing flow 500 may be implemented in a similar manner for non-volatile memory 310.

[0100] For ease of reference, the reference apparatus describes processing flow 500. For example, aspects of processing flow 500 may be implemented by a device comprising an interface controller and volatile memory disposed on different dies. Alternatively, aspects of processing flow 500 may be implemented as instructions stored in memory (e.g., firmware stored in volatile memory 120 or non-volatile memory 125, or both). For example, if the instructions are executed by the controller, then the controller may perform the operation of processing flow 500.

[0101] At 505, a first codeword may be received, for example, from a first bank of volatile memory. For instance, interface controller 302 may receive the first codeword from bank B0 of volatile memory 305 via I / O circuitry 335-b. The first codeword may include a first set of data bits and a parity bit generated based on the first set of data bits. The first set of data bits may be data bits requested by the host device or data bits involved in the evictment procedure, or both.

[0102] At 510, a second codeword may be received, for example, from a second bank of volatile memory. For instance, interface controller 302 may receive the second codeword from bank B1 of volatile memory 305 via I / O circuitry 335-b. The second codeword may include a second set of data bits and a parity bit generated based on the second set of data bits. The second set of data bits may be data bits requested by the host device or data bits involved in the evictment procedure, or both.

[0103] At 515, an ECC operation can be performed on the first codeword. For example, ECC circuit 315-a can perform an error detection procedure on the first codeword (e.g., decoder 330 can decode the first codeword), and if one or more errors are detected, then an error correction procedure is performed on the first codeword. At 520, an ECC operation can be performed on the second codeword. For example, ECC circuit 315-a can perform an error detection procedure on the second codeword (e.g., decoder 330 can decode the second codeword), and if one or more errors are detected, then an error correction procedure is performed on the second codeword. In some instances, the ECC operations at 515 or 520 can be performed in parallel (e.g., in parallel with at least partial overlap, or simultaneously with alignment) or serially.

[0104] At 525, a first set of data bits from the first codeword can be transmitted. For example, interface controller 302 can transmit the first set of data bits to a host device, non-volatile memory 310 (e.g., as part of an evictation procedure), or both. At 530, a second set of data bits from the second codeword can be transmitted. For example, interface controller 302 can transmit the second set of data bits to a host device, non-volatile memory 310 (e.g., as part of an evictation procedure), or both.

[0105] Therefore, the device can use centralized ECC circuitry for ECC operations of multiple banks of volatile memory.

[0106] Alternative instances of the foregoing may be implemented, in which some operations may be performed in a different order than described, in parallel, or not at all. In some cases, operations may include additional features not mentioned below, or additional operations may be added. Furthermore, certain operations may be performed multiple times, or certain combinations of repeatable or cyclical operations may be performed.

[0107] Figure 6 This describes an example of a processing flow 600 that supports a centralized error correction circuit, as disclosed herein. Processing flow 600 can be derived from, as referenced... Figure 1 The described memory subsystem 110 or interface controller 115, as referenced Figure 2 The described memory subsystem 200 or interface controller 202, or as referenced Figure 3 The described device 300 or interface controller 302, or any combination thereof, may be implemented. However, other types of devices may implement the processing flow 600. The processing flow 600 may illustrate the operation of a device that uses centralized ECC circuitry to perform a read-modify-write (RMW) operation on codewords from volatile memory.

[0108] For ease of reference, a processing flow 600 is described in the reference apparatus. For example, aspects of processing flow 600 may be implemented by a device comprising an interface controller and volatile memory disposed on different dies. Alternatively, aspects of processing flow 600 may be implemented as instructions stored in memory (e.g., firmware stored in volatile memory 120 or non-volatile memory 125, or both). For example, when executed by the controller, the instructions may cause the controller to perform the operations of processing flow 600.

[0109] At 605, commands such as partial write commands can be received. For example, interface controller 302 can receive partial write commands from a host device. A partial write command can be targeted at a memory address (e.g., associated with a memory address). A partial write command can be a write command associated with a set of data in volatile memory 305 that is insufficient in size (e.g., too small to access), and volatile memory 305 can have a threshold size for access. For example, if volatile memory 305 has a threshold size of 64B, then a partial write command can be associated with 32B of data.

[0110] At 610, a codeword can be received. For example, interface controller 302 can receive a codeword associated with a memory address targeted by a partial write command. In response to a request sent by interface controller 302 to volatile memory 305, a codeword can be received from volatile memory 305 (e.g., after reading a codeword from volatile memory 305).

[0111] At 615, ECC operation can be performed on the codeword. For example, ECC circuit 315-a can perform an error detection procedure on the codeword (e.g., decoder 330 can decode the first codeword), and if one or more errors are detected, then an error correction procedure is performed on the codeword.

[0112] At 620, data bits from the codeword can be modified (e.g., by rewriting the data bits with new values ​​based on the data associated with a partial write command). For example, if the codeword contains a set of data bits, then the interface controller 302 can modify a subset of those data bits (e.g., 32B in 64B) to reflect the data bits associated with the partial write command.

[0113] At 625, the set of data bits (including a modified subset of data bits) can be encoded to form a codeword, the codeword comprising data bits and a parity bit generated based on the set of data bits. Therefore, a new codeword can be generated or "encoded". At 630, the new codeword can be communicated to volatile memory 305 for storage. Thus, the device can perform read-modify-write operations on the codeword to satisfy partial write commands.

[0114] Alternative instances of the foregoing may be implemented, in which some operations may be performed in a different order than described, in parallel, or not at all. In some cases, operations may include additional features not mentioned below, or additional operations may be added. Furthermore, certain operations may be performed multiple times, or certain combinations of repeatable or cyclical operations may be performed.

[0115] Figure 7 A block diagram 700 illustrates an interface controller 720 supporting centralized error correction circuitry, according to an example disclosed herein. The interface controller 720 may be as described in the references... Figures 1 to 6 Examples of aspects of the described interface controller. Interface controller 720 or its various components may be examples of means for performing various aspects of the centralized error correction circuitry described herein. For example, interface controller 720 may include volatile memory (VM) receiving circuitry 725, VM ECC circuitry 730, host transmission circuitry 735, non-volatile memory (NVM) receiving circuitry 740, NVM ECC circuitry 745, VM transmission circuitry 750, host receiving circuitry 755, NVM transmission circuitry 760, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0116] Receiver circuitry 725 may be or includes a data bus, data bus interface, logic, circuitry, processor, controller, or other components capable of performing the functions described herein. VM ECC circuitry 730 may be or includes a combination of logic, circuitry, controller, registers, latches, buffers, or other components capable of performing the functions described herein. Host transmission circuitry 735 may be or includes a data bus, data bus interface, logic, circuitry, processor, controller, or other components capable of performing the functions described herein. NVM receiver circuitry 740 may be or includes a data bus, data bus interface, logic, circuitry, processor, controller, or other components capable of performing the functions described herein. NVM ECC circuitry 745 may be or includes a combination of logic, circuitry, controller, registers, latches, buffers, or other components capable of performing the functions described herein. VM transmission circuitry 750 may be or includes a data bus, data bus interface, logic, circuitry, processor, controller, or other components capable of performing the functions described herein. Host receiver circuitry 755 may be or includes a data bus, data bus interface, logic, circuitry, processor, controller, or other components capable of performing the functions described herein. The NVM transmission circuit 760 may be or include a data bus, a data bus interface, logic, a circuit system, a processor, a controller, or other components capable of performing the functions described herein.

[0117] VM receiving circuitry 725 may be configured or otherwise supported for means of receiving codewords from a bank of volatile memory disposed on a first die, the volatile memory serving as a cache for non-volatile memory. VM ECC circuitry 730 may be configured or otherwise supported for performing error detection operations on codewords from a bank of memory using ECC circuitry included in an interface controller disposed on a second die and coupled to both the non-volatile and volatile memory. Host transmission circuitry 735 may be configured or otherwise supported for means of transmitting data bits of codewords from the interface controller to a host device, at least in part based on the performance of error detection operations.

[0118] In some instances, the VM ECC circuitry 730 may be configured or otherwise supported as means for detecting errors in a codeword, at least in part, based on performing an error detection operation. In some instances, the VM ECC circuitry 730 may be configured or otherwise supported as means for correcting errors using ECC circuitry before the data bits of the codeword are transmitted to the host device.

[0119] In some instances, the VM ECC circuit 730 may be configured or otherwise support means for receiving a second codeword from a second bank of volatile memory. In some instances, the VM ECC circuit 730 may be configured or otherwise support means for performing error detection operations on the second codeword from the second bank using ECC circuitry included in the interface controller.

[0120] In some instances, the codeword comprises a set of data bits including data bits, and the VM ECC circuitry 730 may be configured or otherwise supported for means by which the interface controller modifies a subset of the data bits after performing an error detection operation. In some instances, the codeword comprises a set of data bits including data bits, and the VM ECC circuitry 730 may be configured or otherwise supported for means by which the interface controller encodes the set of data bits after updating the subset of data bits to generate an updated codeword. In some instances, the codeword comprises a set of data bits including data bits, and the VM transmission circuitry 750 may be configured or otherwise supported for means by which the updated codeword is transmitted from the interface controller to volatile memory for storage.

[0121] In some instances, the host receiving circuitry 755 may be configured or otherwise supported for means of receiving a set of data from a host device at the interface controller. In some instances, the VM ECC circuitry 730 may be configured or otherwise supported for means of encoding a second codeword using ECC circuitry, at least in part, based on said set of data. In some instances, the VM transmission circuitry 750 may be configured or otherwise supported for means of transmitting the second codeword from the interface controller to volatile memory.

[0122] In some instances, the NVM receiver circuit 740 may be configured or otherwise supported as means for receiving a second codeword from a bank of non-volatile memory. In some instances, the NVM ECC circuit 745 may be configured or otherwise supported as means for performing error detection operations on the second codeword using a second ECC circuit included in the interface controller.

[0123] The NVM receiving circuit 740 may be configured or otherwise supported for means of receiving codewords from a bank of non-volatile memory disposed on a first die. The NVM ECC circuit 745 may be configured or otherwise supported for performing error detection operations on codewords from a bank of memory using ECC circuitry included in an interface controller disposed on a second die, the interface controller being coupled to the non-volatile memory and volatile memory serving as a cache for the non-volatile memory. In some instances, the host transmission circuit 735 may be configured or otherwise supported for means of transmitting data bits of a codeword from the interface controller to a host device, at least in part based on the performance of error detection operations.

[0124] In some instances, the VM ECC circuitry 745 may be configured or otherwise supported as means for detecting errors in a codeword, at least in part, based on performing an error detection operation. In some instances, the VM ECC circuitry 745 may be configured or otherwise supported as means for correcting errors using ECC circuitry before the data bits of the codeword are passed to the host device.

[0125] In some instances, the NVM receiver circuit 740 may be configured or otherwise supported as means for receiving a second codeword from a second bank of non-volatile memory. In some instances, the VM ECC circuit 745 may be configured or otherwise supported as means for performing error detection operations on the second codeword from the second bank using ECC circuitry included in the interface controller.

[0126] In some instances, the host receiving circuitry 755 may be configured or otherwise supported for means of receiving a set of data from a host device at the interface controller. In some instances, the NVM ECC circuitry 745 may be configured or otherwise supported for means of encoding a second codeword using ECC circuitry, at least in part, based on said set of data. In some instances, the VM transmission circuitry 760 may be configured or otherwise supported for means of transmitting the second codeword from the interface controller to non-volatile memory.

[0127] In some instances, the VM receiving circuit 725 may be configured or otherwise supported as means for receiving a second codeword from a bank of volatile memory. In some instances, the VM ECC circuit 730 may be configured or otherwise supported as means for performing error detection operations on the second codeword using a second ECC circuit included in the interface controller.

[0128] Figure 8 The flowchart illustrates a method 800 for supporting centralized error correction circuitry, as disclosed herein. Operation of method 800 may be implemented by an interface controller or its components as described herein. For example, operation of method 800 may be implemented by, as referenced... Figures 1 to 7 The described interface controller performs the function. In some instances, the interface controller may execute a set of instructions to control the functional elements of the device to perform the described function. Alternatively, the interface controller may use dedicated hardware to perform aspects of the described function.

[0129] At 805, the method may include receiving a codeword from a bank of volatile memory disposed on a first die, the volatile memory serving as a cache for non-volatile memory. Operation of 805 may be performed according to examples disclosed herein. In some instances, aspects of operation of 805 may be as described in references... Figure 7 The VM receiver circuit 725 described is implemented.

[0130] At 810, the method may include performing an error detection operation on a codeword from a memory bank using ECC circuitry included in an interface controller, the interface controller being disposed on a second die and coupled to both non-volatile and volatile memory. Operation of 810 may be performed according to examples disclosed herein. In some instances, aspects of operation of 810 may be as described in references... Figure 7 The VM ECC circuit 730 described is executed.

[0131] At 815, the method may include transmitting data bits of a codeword from the interface controller to the host device, at least in part based on performing an error detection operation. The operation of 815 may be performed according to examples disclosed herein. In some instances, aspects of the operation of 815 may be as described in the references... Figure 7 The described host transmission circuit 735 is executed.

[0132] In some instances, the device as described herein may perform one or more methods, such as method 800. The device may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following operations: receiving a codeword from a bank of volatile memory disposed on a first die, the volatile memory serving as a cache for non-volatile memory; performing an error detection operation on the codeword from the bank of memory using ECC circuitry included in an interface controller disposed on a second die and coupled to both the non-volatile and volatile memory; and transmitting data bits of the codeword from the interface controller to a host device, at least in part based on the performance of the error detection operation.

[0133] Method 800 and some examples of the devices described herein may further include operations, features, circuit systems, logic, means, or instructions for performing: detecting errors in a codeword at least in part based on performing an error detection operation; and correcting errors using ECC circuitry before transmitting the data bits of the codeword to the host device.

[0134] Method 800 and some examples of the devices described herein may further include operations, features, circuit systems, logic, means, or instructions for performing the following: receiving a second codeword from a second bank of volatile memory; and performing an error detection operation on the second codeword from the second bank using ECC circuitry included in an interface controller.

[0135] In some instances of method 800 and the apparatus described herein, the codeword comprises a set of data bits including data bits, and the method, apparatus, and non-transitory computer-readable medium may further comprise operations, features, circuitry, logic, means, or instructions for performing the following: modifying a subset of the data bits of the set of data bits by an interface controller after an executable error detection operation; encoding the set of data bits by the interface controller after updating the subset of data bits to generate an updated codeword; and transmitting the updated codeword from the interface controller to volatile memory for storage.

[0136] Method 800 and some examples of the devices described herein may further include operations, features, circuit systems, logic, means, or instructions for performing the following: receiving a set of data from a host device at an interface controller; encoding a second codeword using ECC circuitry based at least in part on the set of data; and transmitting the second codeword from the interface controller to volatile memory.

[0137] Method 800 and some examples of the devices described herein may further include operations, features, circuit systems, logic, means, or instructions for performing the following: receiving a second codeword from a bank of non-volatile memory; and performing an error detection operation on the second codeword using a second ECC circuit included in an interface controller.

[0138] Figure 9 The flowchart illustrates a method 900 for supporting centralized error correction circuitry, as disclosed herein. Operation of method 900 may be implemented by an interface controller or its components as described herein. For example, operation of method 900 may be implemented by, as referenced... Figures 1 to 7 The described interface controller performs the function. In some instances, the interface controller may execute a set of instructions to control the functional elements of the device to perform the described function. Alternatively, the interface controller may use dedicated hardware to perform aspects of the described function.

[0139] At 905, the method may include receiving a codeword from a bank of non-volatile memory disposed on the first die. Operation of 905 may be performed according to examples disclosed herein. In some instances, aspects of operation of 905 may be as described in references... Figure 7 The described NVM receiver circuit 740 is implemented.

[0140] At 910, the method may include performing an error detection operation on a codeword from a memory bank using ECC circuitry included in an interface controller disposed on a second die, the interface controller being coupled to a non-volatile memory and a volatile memory serving as a cache for the non-volatile memory. The operation of 910 may be performed according to examples disclosed herein. In some examples, aspects of the operation of 910 may be as described in references... Figure 7 The described NVM ECC circuit 745 is implemented.

[0141] At 915, the method may include transmitting data bits of a codeword from the interface controller to the host device, at least in part based on performing an error detection operation. The operation of 915 may be performed according to examples disclosed herein. In some instances, aspects of the operation of 915 may be as described in the references... Figure 7 The described host transmission circuit 735 is executed.

[0142] In some instances, the device as described herein may perform one or more methods, such as method 900. The device may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following operations: receiving a codeword from a bank of non-volatile memory disposed on a first die; performing an error detection operation on the codeword from the bank of memory using ECC circuitry included in an interface controller disposed on a second die, the interface controller being coupled to the non-volatile memory and volatile memory serving as a cache for the non-volatile memory; and transmitting data bits of the codeword from the interface controller to a host device, at least in part based on the performance of the error detection operation.

[0143] Method 900 and some examples of the devices described herein may further include operations, features, circuit systems, logic, means, or instructions for performing: detecting errors in a codeword at least in part based on performing an error detection operation; and correcting errors using ECC circuitry before transmitting the data bits of the codeword to the host device.

[0144] Method 900 and some examples of the devices described herein may further include operations, features, circuit systems, logic, means, or instructions for performing the following: receiving a second codeword from a second bank of non-volatile memory; and performing an error detection operation on the second codeword from the second bank using ECC circuitry included in an interface controller.

[0145] Method 900 and some examples of the devices described herein may further include operations, features, circuit systems, logic, means, or instructions for performing the following: receiving a set of data from a host device at an interface controller; encoding a second codeword using ECC circuitry based at least in part on the set of data; and transmitting the second codeword from the interface controller to a non-volatile memory.

[0146] Method 900 and some examples of the devices described herein may further include operations, features, circuit systems, logic, means, or instructions for performing the following: receiving a second codeword from a bank of volatile memory; and performing an error detection operation on the second codeword using a second ECC circuit included in an interface controller.

[0147] It should be noted that the methods described herein describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods described may be combined.

[0148] An apparatus is described. The apparatus may include: a non-volatile memory disposed on a first die; a volatile memory disposed on a second die and configured to serve as a cache for the non-volatile memory, the volatile memory comprising a plurality of memory banks; and an interface controller disposed on a third die and coupled to the non-volatile memory and the volatile memory, the interface controller including ECC circuitry coupled to the volatile memory and configured to operate on one or more codewords received from the volatile memory.

[0149] In some instances of the device, the ECC circuitry includes an encoder circuit configured to encode codewords for storage in volatile memory and a decoder circuit configured to decode codewords received from volatile memory.

[0150] In some instances of the device, the volatile memory includes I / O circuitry configured to transmit uncorrected codewords to and receive codewords from an interface controller.

[0151] In some instances, the device may include a second ECC circuitry included in an interface controller, the second ECC circuitry being coupled to and configured to operate on codewords received from the non-volatile memory.

[0152] In some instances of the device, the second ECC circuit includes an encoder circuit configured to encode codewords for storage in non-volatile memory and a decoder circuit configured to decode codewords received from non-volatile memory.

[0153] In some instances of the device, the non-volatile memory includes I / O circuitry configured to transmit uncorrected codewords to and receive codewords from an interface controller.

[0154] In some instances of the device, the first die, the second die, and the third die may be contained in the same package.

[0155] Another device is described. The device may include: a non-volatile memory disposed on a first die, the non-volatile memory comprising a plurality of memory banks; a volatile memory disposed on a second die and configured to serve as a cache for the non-volatile memory; and an interface controller disposed on a third die and coupled to the non-volatile memory and the volatile memory, the interface controller including ECC circuitry coupled to the non-volatile memory and configured to operate on one or more codewords received from the non-volatile memory.

[0156] In some instances of the device, the ECC circuitry includes an encoder circuit configured to encode codewords for storage in a non-volatile memory and a decoder circuit configured to decode codewords received from the non-volatile memory.

[0157] In some instances of the device, the volatile memory includes I / O circuitry configured to transmit uncorrected codewords to and receive codewords from an interface controller.

[0158] In some instances, the device may include a second ECC circuitry included in an interface controller, the second ECC circuitry being coupled to the volatile memory and configured to operate on codewords received from the volatile memory.

[0159] In some instances of the device, the second ECC circuit includes an encoder circuit configured to encode codewords for storage in volatile memory and a decoder circuit configured to decode codewords received from volatile memory.

[0160] In some instances of the device, the volatile memory includes I / O circuitry configured to transmit uncorrected codewords to and receive codewords from an interface controller.

[0161] In some instances of the device, the first die, the second die, and the third die may be contained in the same package.

[0162] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods can be combined.

[0163] When used to describe conditional actions or processes, the terms "if," "when," "based on," "at least partially based on," and "in response to" are interchangeable.

[0164] The information and signals described herein can be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, those skilled in the art will understand that the signal may represent a signal bus, wherein the bus may have multiple bit widths.

[0165] A protocol can define one or more communication procedures and one or more communication parameters supported for use by a device or component. For example, a protocol can define various operations, timing and frequency for those operations, the meaning of various commands or signals or both, one or more addressing schemes for one or more memories, the type of communication reserved for pins, the size of data processed at various components of an interface, the data rates supported by various components of an interface, or the bandwidth supported by various components of an interface, and other parameters and metrics, or any combination thereof. The use of shared protocols enables interaction between devices because each device can operate in a way that another device expects, recognizes, and understands. For example, two devices supporting the same protocol can interact according to the policies, procedures, and parameters defined by the protocol, while two devices supporting different protocols may be incompatible.

[0166] To illustrate, two devices supporting different protocols may be incompatible because the protocols define different addressing schemes (e.g., different numbers of address bits). As another illustration, two devices supporting different protocols may be incompatible because the protocols define different transmission procedures for responding to a single command (e.g., the burst length or number of bytes allowed in response to the command may differ). Simply translating a command into an action should not be interpreted as the use of two different protocols. In fact, protocols can be considered different if the corresponding procedures or parameters defined by the two protocols change. For example, if a device supports different addressing schemes or different transmission procedures for responding to commands, then the device can be said to support two different protocols.

[0167] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" refer to the relationship between components that enables the flow of signals between them. Components are considered electronically connected (or electrically contacting, connected, or coupled) to each other if any conductive path exists between them that enables the flow of signals between them at any given time. At any given time, the conductive path between components that are electronically connected (or electrically contacting, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, the signal flow between connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0168] The term "coupling" refers to a condition that moves from an open-circuit relationship between components to a closed-circuit relationship, in which a signal is currently unable to travel between components via a conductive path, and in which a signal can travel between components via a conductive path. When a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components via conductive paths that were previously not permitted.

[0169] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. If there is an open circuit between components, then the components are separated from each other. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. When a controller isolates two components, it performs the following change: preventing signals from flowing between the components using previously permitted conductive paths.

[0170] The devices containing memory arrays discussed herein can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by using doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0171] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material, such as a metal. The source and drain may be conductive and may include heavily doped semiconductor regions, such as degenerate semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., most charge carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., most charge carriers are holes), then the FET may be called a p-type FET. The channel may be end-capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, makes the channel conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "turned on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "turned off" or "deactivated."

[0172] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior to" other instances. The detailed description includes specific details that provide an understanding of the described techniques. However, embodiments may be implemented without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0173] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a dash followed by a second reference numeral to differentiate them. If only the first reference numeral is used in the specification, the description applies to any similar component that has the same first reference numeral but is independent of the second reference numeral.

[0174] The information and signals described herein can be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof.

[0175] The various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware component or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0176] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distributed implementations such that portions of the functions are implemented in different physical locations. And, as used herein, the word "or" used in the list of items included in the claims (e.g., a list of items beginning with phrases such as "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). And, as used herein, the phrase "based on" should not be construed as referring to a set of closing conditions. For example, without departing from the scope of this disclosure, an exemplary step described as “based on condition A” may be based on both condition A and condition B. In other words, as used herein, the phrase “based on” should also be interpreted as the phrase “at least partially based on”.

[0177] Computer-readable media includes both non-transitory computer storage media and communication media, with communication media encompassing any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, optical fiber, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then such coaxial cable, optical fiber, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. The combinations described above also fall within the scope of computer-readable media.

[0178] The description herein is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory device comprising: Non-volatile memory, which is disposed on the first die; A volatile memory disposed on a second die and configured to serve as a cache for the non-volatile memory, the volatile memory comprising a plurality of memory banks; as well as An interface controller, disposed on a third die and coupled to the non-volatile memory and the volatile memory, and configured to determine that first data requested by the host system does not exist in the volatile memory, the interface controller includes error correction code (ECC) circuitry coupled to the non-volatile memory and the volatile memory and configured to, at least in part, determine based on the absence of the first data in the volatile memory: A first error detection operation is performed on a first codeword received from the non-volatile memory, the first codeword including the first data transferred from the non-volatile memory to the volatile memory, and A second error detection operation is performed on a second codeword received from the volatile memory, the second codeword including second data transferred from the volatile memory to the non-volatile memory.

2. The memory device of claim 1, wherein the ECC circuit comprises: An encoder circuit configured to encode codewords for storage in the volatile memory and the non-volatile memory; as well as A decoder circuit is used to decode codewords received from the volatile memory and the non-volatile memory.

3. The memory device of claim 1, wherein the volatile memory comprises: Input / output (I / O) circuitry configured to transmit uncorrected codewords to and receive codewords from the interface controller.

4. The memory device of claim 1, wherein the non-volatile memory comprises: Input / output (I / O) circuitry configured to transmit uncorrected codewords to and receive codewords from the interface controller.

5. The memory device of claim 1, wherein the first die, the second die, and the third die are contained in the same package.

6. A method performed by an apparatus, comprising: The host system determines that the first data requested does not exist in the volatile memory used as a cache for non-volatile memory, which is disposed on the first die; In response to determining that the first data does not exist in the volatile memory: At the interface controller located on the second die, a first codeword is received from the non-volatile memory, the first codeword including the first data transferred from the non-volatile memory to the volatile memory; At the interface controller, a second codeword is received from the volatile memory, the second codeword including second data transferred from the volatile memory to the non-volatile memory; At the error correction code (ECC) circuit included in the interface controller, a first error detection operation is performed on the first codeword, the first codeword including the first data transferred from the non-volatile memory to the volatile memory; At the ECC circuit, a second error detection operation is performed on the second codeword, the second codeword including the second data transferred from the volatile memory to the non-volatile memory; as well as The interface controller transmits the first data of the first codeword to the volatile memory at least in part based on the execution of the first error detection operation, and transmits the second data of the second codeword to the non-volatile memory at least in part based on the execution of the second error detection operation.

7. The method of claim 6, further comprising: Errors in the first codeword are detected at least in part based on the execution of the first error detection operation; as well as The error is corrected using the ECC circuit before the first data of the first codeword is transmitted to the volatile memory.

8. The method of claim 6, further comprising: Receive the third codeword from the volatile memory; as well as The ECC circuitry included in the interface controller is used to perform a third error detection operation on the third codeword from the volatile memory.

9. The method of claim 6, further comprising: After performing the error detection operation, the interface controller modifies one or more sets of data bits of the first data; The first data is encoded by the interface controller after the set of one or more data bits is updated to generate the updated first codeword; as well as The updated first codeword is transmitted from the interface controller to the volatile memory for storage.

10. The method of claim 6, further comprising: A set of data is received from the host device at the interface controller; The fourth codeword is encoded using the ECC circuit, at least in part, based on the set of data. as well as The fourth codeword is transmitted from the interface controller to the volatile memory.

11. A memory device comprising: Non-volatile memory, wherein the non-volatile memory comprises multiple memory banks; A volatile memory configured to serve as a cache for the non-volatile memory; as well as An interface controller, coupled to the non-volatile memory and the volatile memory, and configured to determine that first data requested by the host system does not exist in the volatile memory, the interface controller comprising: A first error correction code (ECC) decoder, coupled to the non-volatile memory and configured to perform a first error detection operation on a first codeword received from the non-volatile memory, at least partially based on the fact that the first data does not exist in the volatile memory, the first codeword comprising the first data transferred from the non-volatile memory to the volatile memory, and... A second ECC decoder, coupled to the volatile memory and configured to perform a second error detection operation on a second codeword received from the volatile memory, based at least in part on the fact that the first data does not exist in the volatile memory, the second codeword comprising second data transferred from the volatile memory to the non-volatile memory.

12. The memory device of claim 11, wherein the interface controller further comprises: An encoder circuit configured to encode codewords for storage in the non-volatile memory.

13. The memory device of claim 11, wherein the volatile memory comprises: Input / output (I / O) circuitry configured to transmit uncorrected codewords to and receive codewords from the interface controller.

14. The memory device of claim 11, wherein the interface controller further comprises: An encoder circuit configured to encode codewords for storage in the volatile memory.

15. The memory device of claim 11, wherein the volatile memory comprises: Input / output (I / O) circuitry configured to transmit uncorrected codewords to and receive codewords from the interface controller.

16. A method performed by a device, comprising: It is determined that the first data requested by the host system does not exist in the volatile memory used as a cache for non-volatile memory; In response to determining that the first data does not exist in the volatile memory: At the interface controller, a first codeword is received from the non-volatile memory, the first codeword including the first data transferred from the non-volatile memory to the volatile memory; At the interface controller, a second codeword is received from the volatile memory, the second codeword including second data transferred from the volatile memory to the non-volatile memory; At a first ECC decoder included in the interface controller, a first error detection operation is performed on the first codeword, the first codeword including the first data transferred from the non-volatile memory to the volatile memory; At the second ECC decoder included in the interface controller, a second error detection operation is performed on the second codeword, the second codeword including the second data transferred from the volatile memory to the non-volatile memory; as well as The interface controller transmits the first data of the first codeword to the volatile memory at least in part based on the execution of the first error detection operation, and transmits the second data of the second codeword to the non-volatile memory at least in part based on the execution of the second error detection operation.

17. The method of claim 16, further comprising: Errors in the first codeword are detected at least in part based on the execution of the first error detection operation; as well as The error is corrected using the first ECC decoder before the first data of the first codeword is transmitted to the volatile memory.

18. The method of claim 16, further comprising: Receive the third codeword from the non-volatile memory; as well as A third error detection operation is performed on the third codeword from the non-volatile memory using the first ECC decoder included in the interface controller.

19. The method of claim 16, further comprising: A set of data is received from the host device at the interface controller; The fourth codeword is encoded using an ECC encoder, at least in part, based on the aforementioned set of data; as well as The fourth codeword is transmitted from the interface controller to the non-volatile memory.

Images