Display panel, display device, and manufacturing method of display panel

Abstract

Embodiments of the present application disclose a display panel, a display device, and a manufacturing method of the display panel. The display panel includes a substrate, a thin film transistor layer, a passivation layer, and a first planarization layer disposed in sequence. A plurality of recessed regions are formed on a side of the passivation layer facing away from the substrate. At least a part of the first planarization layer is located in the recessed regions, and a maximum value of a height of the first planarization layer relative to the substrate is less than or equal to a maximum value of a height of the passivation layer relative to the substrate. By providing the first planarization layer in the recessed regions of the passivation layer and making the maximum height of the first planarization layer less than or equal to the maximum height of the passivation layer, the present application can reduce the step difference generated in the recessed regions on the passivation layer, improve the flatness of the surface of the passivation layer, contribute to the manufacturing of subsequent film layers, and improve the structural uniformity of the subsequent film layers.

Description

Technical Field

[0001] The present application relates to the field of displays, and particularly to a display panel, a display device, and a method for manufacturing a display panel. Background Art

[0002] With the development of display technology, inkjet printing technology has gradually gained popularity. Among them, after the ink is printed onto the pixel region, it is fluid, and the flatness of the pixel region substrate is an important factor affecting whether the ink can be evenly and well spread, that is, the smaller the maximum step difference of the pixel region substrate, the better. During the manufacturing process of a display panel, after the array substrate is manufactured, a non-flat surface with different heights is formed. Currently, a planarization layer is often formed on the surface of the array substrate to planarize the surface of the array substrate, and the planarization effect is improved by increasing the thickness of the planarization layer. However, the planarization effect of the planarization layer is limited. When the surface step difference of the array substrate is large, even if the thickness of the planarization layer is increased, the flatness of the surface of the array substrate cannot be effectively improved, resulting in a poor display effect of the display panel. Summary of the Invention

[0003] Embodiments of the present application provide a display panel, a display device, and a method for manufacturing a display panel, which can solve the problem of poor planarization effect of the planarization layer in the existing display panel.

[0004] Embodiments of the present application provide a display panel, including:

[0005] A substrate;

[0006] A thin film transistor layer disposed on the substrate;

[0007] A passivation layer disposed on the thin film transistor layer, and a plurality of recessed regions are formed on a side of the passivation layer facing away from the substrate;

[0008] A first planarization layer disposed on the passivation layer, and at least a part of the first planarization layer is located in the recessed regions; the maximum value of the height of the first planarization layer relative to the substrate is less than or equal to the maximum value of the height of the passivation layer relative to the substrate.

[0009] Optionally, in some embodiments of the present application, the thin film transistor layer includes an active layer, a gate insulating layer, a gate layer, and a source-drain layer; any two of the active layer, the gate layer, and the source-drain layer overlap and form a plurality of overlapping regions, and protrusions are formed at positions corresponding to the overlapping regions on a side of the passivation layer facing away from the substrate, and the recessed regions are formed between adjacent two of the protrusions.

[0010] Optionally, in some embodiments of the present application, the gate layer and the source-drain layer are overlapped to form a first overlapping region, and a first protrusion is formed at a position corresponding to the first overlapping region on a side of the passivation layer facing away from the substrate; the active layer and the source-drain layer are overlapped to form a second overlapping region, and a second protrusion is formed at a position corresponding to the second overlapping region on a side of the passivation layer facing away from the substrate; the active layer and the gate layer are overlapped to form a third overlapping region, and a third protrusion is formed at a position corresponding to the third overlapping region on a side of the passivation layer facing away from the substrate.

[0011] Optionally, in some embodiments of the present application, the display panel further includes a light-shielding layer and a buffer layer sequentially disposed on the substrate, the thin-film transistor layer is disposed on the buffer layer, and the light-shielding layer, the gate layer, and the source-drain layer are overlapped to form the first overlapping region; the light-shielding layer, the active layer, and the source-drain layer are overlapped to form the second overlapping region; the light-shielding layer, the active layer, and the gate layer are overlapped to form the third overlapping region.

[0012] Optionally, in some embodiments of the present application, a maximum value of a height of the first planarization layer relative to the substrate is less than or equal to a height of the first protrusion relative to the substrate.

[0013] Optionally, in some embodiments of the present application, a maximum value of a height of the first planarization layer relative to the substrate is less than or equal to a height of the second protrusion relative to the substrate; or,

[0014] The first planarization layer is disposed on a side of the second protrusion facing away from the substrate.

[0015] Optionally, in some embodiments of the present application, a maximum value of a height of the first planarization layer relative to the substrate is less than or equal to a height of the third protrusion relative to the substrate; or,

[0016] The first planarization layer is disposed on a side of the third protrusion facing away from the substrate.

[0017] Optionally, in some embodiments of the present application, a thickness of the first planarization layer is greater than or equal to 0.2 micrometers and less than or equal to 2.5 micrometers.

[0018] Optionally, in some embodiments of the present application, a material of the first planarization layer includes a positive organic photoresist, a negative organic photoresist, or an inorganic material.

[0019] Optionally, in some embodiments of the present application, the display panel includes a second planarization layer, and the second planarization layer is located on the first planarization layer and the passivation layer.

[0020] Optionally, in some embodiments of the present application, the thickness of the second planarization layer is greater than or equal to 1.5 micrometers and less than or equal to 6 micrometers.

[0021] Optionally, in some embodiments of the present application, the display panel further includes:

[0022] An anode layer, disposed on the first planarization layer, and the anode layer is electrically connected to the thin film transistor layer;

[0023] A pixel definition layer, disposed on the anode layer, and a pixel opening is formed on the pixel definition layer, and the pixel opening exposes a part of the anode layer;

[0024] A light-emitting layer, disposed on the anode layer, and the light-emitting layer is located within the pixel opening.

[0025] Correspondingly, an embodiment of the present application further provides a display device, and the display device includes the display panel described in any one of the above.

[0026] Correspondingly, an embodiment of the present application further provides a method for manufacturing a display panel, and the method includes:

[0027] Providing a substrate;

[0028] Forming a thin film transistor layer on the substrate;

[0029] Forming a passivation layer on the thin film transistor layer, and a plurality of recessed areas are formed on a side of the passivation layer facing away from the substrate;

[0030] Forming a first planarization layer on the passivation layer, such that the first planarization layer is at least partially located within the plurality of recessed areas, and a maximum value of a height of the first planarization layer relative to the substrate is less than or equal to a maximum value of a height of the passivation layer relative to the substrate.

[0031] Optionally, in some embodiments of the present application, the method further includes:

[0032] Forming a second planarization layer on the first planarization layer and the passivation layer;

[0033] Forming an anode layer on the second planarization layer, such that the anode layer is electrically connected to the thin film transistor layer;

[0034] Forming a pixel definition layer on the anode layer, and forming a pixel opening on the pixel definition layer, such that the pixel opening exposes a part of the anode layer;

[0035] Print a light-emitting layer on the anode layer so that the light-emitting layer is located within the pixel opening.

[0036] In the embodiment of the present application, the display panel includes a substrate substrate, a thin-film transistor layer, a passivation layer, and a first planarization layer arranged in sequence. A plurality of recessed areas are formed on the side of the passivation layer facing away from the substrate substrate. At least a part of the first planarization layer is located within the recessed areas, and the maximum value of the height of the first planarization layer relative to the substrate substrate is less than or equal to the maximum value of the height of the passivation layer relative to the substrate substrate. By arranging the first planarization layer within the recessed areas of the passivation layer and making the maximum height of the first planarization layer less than or equal to the maximum height of the passivation layer, the present application can reduce the step difference generated in the recessed areas on the passivation layer, improve the flatness of the surface of the passivation layer, contribute to the fabrication of subsequent film layers, and improve the structural uniformity of the subsequent film layers. Description of the Drawings

[0037] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0038] Figure 1 is a schematic structural diagram of a display panel provided by an embodiment of the present application;

[0039] Figure 2 is a schematic structural diagram of another display panel provided by an embodiment of the present application;

[0040] Figure 3 is a schematic structural diagram of another display panel provided by an embodiment of the present application

[0041] Figure 4 is a schematic structural diagram of a display device provided by an embodiment of the present application;

[0042] Figure 5 is a flowchart of a method for manufacturing a display panel provided by an embodiment of the present application;

[0043] Figure 6 is provided by an embodiment of the present application Figure 5 is a schematic structural diagram of step S300

[0044] Figure 7 is provided by an embodiment of the present application Figure 5 is a schematic structural diagram of step S400;

[0045] Figure 8 is another provided by an embodiment of the present application Figure 5Schematic structural diagram of step S400 in

[0046] Description of reference numerals:

[0047]

[0048] Detailed implementation manners

[0049] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative efforts belong to the scope of protection of the present application. In addition, it should be understood that the specific implementation manners described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the orientation words such as "upper" and "lower" generally refer to the upper and lower in the actual use or working state of the device, specifically the drawing direction in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0050] The embodiments of the present application provide a display panel, a display device, and a manufacturing method of the display panel, which will be described in detail below. It should be noted that the description order of the following embodiments does not limit the preferred order of the embodiments.

[0051] As Figure 1 and Figure 2 shown, the display panel 100 includes a substrate 110. The substrate 110 serves as a support structure of the display panel 100 and is used to support other film layer structures in the display panel 100 to ensure the structural stability of the display panel 100. Among them, the substrate 110 can be a glass substrate or other material types, and no special limitation is made here.

[0052] The display panel 100 includes a thin film transistor layer 140. The thin film transistor layer 140 is disposed on the substrate 110. The thin film transistor layer 140 serves as a control switch function layer of the display panel 100 and is used to control other functional structure layers of the display panel 100 to regulate the display mode of the display panel 100.

[0053] As Figure 6 shown, the display panel 100 includes a passivation layer 150. The passivation layer 150 is disposed on the thin film transistor layer 140 and is used to insulate the thin film transistor layer 140 to prevent interference between the thin film transistor layer 140 and subsequent film layers. Among them, a plurality of recessed areas 151 are formed on the side of the passivation layer 150 facing away from the substrate 110, that is, the surface of the passivation layer 150 is an uneven surface with a step difference.

[0054] It should be noted that the thin film transistor layer 140 includes a metal layer and an insulating layer. When forming the metal layer, the metal layer will be patterned to form a target pattern, that is, a protrusion will be formed at the position where the patterned metal layer is located. For the entire thin film transistor layer 140, the region composed only of the insulating layer stacked is the region where the height of the surface of the thin film transistor layer 140 relative to the substrate 110 is smaller. On the contrary, the more metal layers are stacked, the higher the height of the corresponding region surface of the thin film transistor layer 140 relative to the substrate 110, so that protrusions with different heights are formed on the surface of the thin film transistor layer 140. When forming the passivation layer 150 on the thin film transistor layer 140, the surface shape of the passivation layer 150 is directly related to the surface shape of the thin film transistor layer 140. Therefore, protrusions will be formed in the corresponding regions on the surface of the passivation layer 150, and a recessed region 151 will be formed between adjacent protrusions.

[0055] As Figure 7 and Figure 8 shown, the display panel 100 includes a first planarization layer 160. The first planarization layer 160 is disposed on the passivation layer 150, and at least a part of the first planarization layer 160 is located in the recessed region 151 on the passivation layer 150. By disposing the first planarization layer 160 in the recessed region 151 of the passivation layer 150, the step difference generated in the recessed region 151 on the passivation layer 150 can be reduced, the flatness of the surface of the passivation layer 150 can be improved, which is helpful for the fabrication of subsequent film layers and improves the structural uniformity of subsequent film layers.

[0056] Wherein, the maximum value of the height of the first planarization layer 160 relative to the substrate 110 is less than or equal to the maximum value of the height of the passivation layer 150 relative to the substrate 110, that is, the highest point on the side of the first planarization layer 160 facing away from the substrate 110 is lower than the highest point on the side of the passivation layer 150 facing away from the substrate 110, or the highest point on the side of the first planarization layer 160 facing away from the substrate 110 is flush with the highest point on the side of the passivation layer 150 facing away from the substrate 110. This structural design enables reducing the surface step difference of the passivation layer 150 while avoiding generating a new step difference between the first planarization layer 160 and the passivation layer 150, and at the same time can save the use of the first planarization layer 160 and reduce the production cost.

[0057] In the embodiment of the present application, the display panel 100 includes a substrate substrate 110, a thin film transistor layer 140, a passivation layer 150, and a first planarization layer 160 arranged in sequence. A plurality of recessed regions 151 are formed on a side of the passivation layer 150 facing away from the substrate substrate 110. At least a part of the first planarization layer 160 is located in the recessed regions 151. The maximum value of the height of the first planarization layer 160 relative to the substrate substrate 110 is less than or equal to the maximum value of the height of the passivation layer 150 relative to the substrate substrate 110. By arranging the first planarization layer 160 in the recessed regions 151 of the passivation layer 150 and making the maximum height of the first planarization layer 160 less than or equal to the maximum height of the passivation layer 150, the present application can reduce the step difference generated in the recessed regions 151 on the passivation layer 150, improve the flatness of the surface of the passivation layer 150, facilitate the fabrication of subsequent film layers, and improve the structural uniformity of subsequent film layers.

[0058] As Figure 3 , Figures 6 to 8 shown, the thin film transistor layer 140 includes an active layer 141, a gate layer 143, and a source-drain layer 145. When fabricating the thin film transistor layer 140, corresponding film layers are patterned to form structures such as thin film transistors or metal traces. For example, after patterning, the gate layer 143 can form a gate 1431, a scan line 1432, etc., and after patterning, the source-drain layer 145 can form source-drains 1451, data lines 1452, etc.

[0059] Among them, any two of the active layer 141, the gate layer 143, and the source-drain layer 145 are overlapped and arranged to form a plurality of overlapping regions. Protrusions are formed at positions corresponding to the overlapping regions on a side of the passivation layer 150 facing away from the substrate substrate 110, and recessed regions 151 of the passivation layer 150 are formed between adjacent protrusions. By adjusting the overlapping manner of the active layer 141, the gate layer 143, and the source-drain layer 145, the formation positions of the protrusion structures on the passivation layer 150 will also change accordingly, thereby realizing the adjustment of the specific structure of the first planarization layer 160.

[0060] It should be noted that when the thin film transistor in the thin film transistor layer 140 is a top-gate structure, the active layer 141, the gate layer 143, and the source-drain layer 145 are stacked in a direction away from the substrate substrate 110; when the thin film transistor in the thin film transistor layer 140 is a bottom-gate structure, the gate layer 143, the active layer 141, and the source-drain layer 145 are stacked in a direction away from the substrate substrate 110.

[0061] As Figure 3As shown, the gate layer 143 and the source / drain layer 145 are overlapped to form a first overlapping region 146, and a first protrusion 152 is formed at a position corresponding to the first overlapping region 146 on the side of the passivation layer 150 facing away from the substrate 110, that is, the first protrusion 152 corresponds to the region in the thin-film transistor layer 140 where the overlapping metal layers are the most. For example, after the gate layer 143 is patterned, a scan line 1432 is formed, and after the source / drain layer 145 is patterned, a data line 1452 is formed, and the first protrusion 152 corresponds to the region where the scan line 1432 and the data line 1452 are overlapped.

[0062] In some embodiments, as Figure 3 and Figure 7 shown, the active layer 141 and the source / drain layer 145 are overlapped to form a second overlapping region 147, and a second protrusion 153 is formed at a position corresponding to the second overlapping region 147 on the side of the passivation layer 150 facing away from the substrate 110. When the active layer 141 is formed, the active layer 141 is patterned to form a semiconductor region; after the source / drain layer 145 is patterned, source / drains 1451 are formed, and the source / drains 1451 are electrically connected to and overlapped with the active layer 141 to form the second overlapping region 147.

[0063] In other embodiments, as Figure 7 and Figure 8 shown, the active layer 141 and the gate layer 143 are overlapped to form a third overlapping region 148, and a third protrusion 154 is formed at a position corresponding to the third overlapping region 148 on the side of the passivation layer 150 facing away from the substrate 110. After the gate layer 143 is patterned, a gate 1431 is formed, and the gate 1431 is correspondingly arranged with the patterned active layer 141 to form a conductive channel on the active layer 141, and the gate 1431 is overlapped with the active layer 141 to form the third overlapping region 148.

[0064] Optionally, as Figure 7 and Figure 8 shown, when the thin-film transistor layer 140 in the display panel 100 is a top-gate structure, the display panel 100 further includes a light-shielding layer 120 and a buffer layer 130 sequentially arranged on the substrate 110. The light-shielding layer 120 is used to shield the active layer in the thin-film transistor layer 140 to prevent direct light irradiation from affecting the stability of the thin-film transistor layer 140; the buffer layer 130 is used to separate the light-shielding layer 120 from the thin-film transistor layer 140 to prevent mutual interference between the thin-film transistor layer 140 and the light-shielding layer 120 from affecting the normal operation of the thin-film transistor layer 140.

[0065] When forming the light-shielding layer 120, it is necessary to pattern the light-shielding layer 120 to form a target pattern. After patterning, the light-shielding layer 120 also overlaps with relevant film layers in the thin-film transistor layer 140. That is, the first overlapping region 146, the second overlapping region 147, and the third overlapping region 148 in the above embodiments also include the light-shielding layer 120 after patterning, making the step differences generated by the corresponding first protrusion 152, second protrusion 153, and third protrusion 154 larger.

[0066] Among them, the thin-film transistor layer 140 is disposed on the buffer layer 130. The thin-film transistor layer 140 includes an active layer 141, a gate insulating layer 142, a gate layer 143, an interlayer dielectric layer 144, and a source-drain layer 145, which are sequentially disposed in a direction away from the buffer layer 130. The light-shielding layer 120, the gate layer 143, and the source-drain layer 145 overlap and form a first overlapping region 146. That is, the first protrusion 152 corresponding to the first overlapping region 146 on the passivation layer 150 is formed by the overlapping of three metal layers.

[0067] It should be noted that when patterning the gate insulating layer 142 and the gate layer 143, the gate layer 143 is first patterned, and then the gate insulating layer 142 is patterned using the patterned gate layer 143 as a mask. Therefore, the gate insulating layer 142 is disposed under the patterned gate layer 143. That is, the first overlapping region 146 also includes the gate insulating layer 142. Compared with the step difference generated by the overlapping of three metal layers, the influence of the gate insulating layer 142 on the step difference is relatively small.

[0068] Optionally, when forming the thin-film transistor layer 140, after patterning the gate layer 143, the gate 1431 and the scan line 1432 can be formed. After patterning the source-drain layer 145, the source-drain 1451 and the data line 1452 can be formed. The light-shielding layer 120, the scan line 1432, and the data line 1452 overlap and form a first overlapping region 146. A first protrusion 152 is formed at a position corresponding to the first overlapping region 146 on the side of the passivation layer 150 facing away from the substrate 110. That is, the first protrusion 152 is mainly formed by the step difference generated by the superposition of three metal layers, namely the light-shielding layer 120, the scan line 1432, and the data line 1452.

[0069] Among them, the scan line 1432 can also be formed in the patterned light-shielding layer 120. That is, the first overlapping region 146 refers to the overlapping region formed after patterning the three metal layers, namely the light-shielding layer 120, the gate layer 143, and the source-drain layer 145, but the specific position of their overlap is not limited. That is, the first protrusion 152 is formed in the region corresponding to the overlapping of the three metal layers on the passivation layer 150.

[0070] It should be noted that the surface step difference of the thin film transistor layer 140 in the embodiments of the present application mainly comes from the overlapping arrangement of the light shielding layer 120 and the metal layer in the thin film transistor layer 140. The metal layer in the thin film transistor layer 140 includes a gate layer 143 and a source-drain layer 145. That is, the maximum surface step difference of the thin film transistor layer 140 comes from the overlapping arrangement of the three metal layers. That is to say, the height of the first protrusion 152 relative to the substrate 110 is the maximum value of the height of the passivation layer 150 relative to the substrate 110.

[0071] Among them, the maximum value of the height of the first planarization layer 160 relative to the substrate 110 is less than or equal to the height of the first protrusion 152 relative to the substrate 110, that is, the maximum value of the height of the first planarization layer 160 relative to the substrate 110 is less than or equal to the maximum value of the height of the passivation layer 150 relative to the substrate 110. By providing the first planarization layer 160 and making the maximum value of the height of the first planarization layer 160 relative to the substrate 110 less than or equal to the height of the first protrusion 152 relative to the substrate 110, the flatness of the surface of the passivation layer 150 can be improved, which is helpful for the fabrication of subsequent film layers and improves the structural uniformity of the subsequent film layers. At the same time, it can also prevent the first planarization layer 160 from being higher than the first protrusion 152 to generate a new step difference, save the use of the first planarization layer 160, and reduce the production cost.

[0072] Optionally, as Figure 7 and 8 shown, the light shielding layer 120, the active layer 141, and the source-drain layer 145 are overlapped to form a second overlapping region 147. Among them, the source-drain layer 145 includes a source-drain 1451, and the source-drain 1451 is electrically connected to the active layer 141 and overlapped, that is, the light shielding layer 120, the active layer 141, and the source-drain 1451 are overlapped to form a second overlapping region 147. A second protrusion 153 is formed at a position corresponding to the second overlapping region 147 on the side of the passivation layer 150 facing away from the substrate 110. That is, the second protrusion 153 is mainly formed by the step difference generated by the superposition of two metal layers, namely the light shielding layer 120 and the source-drain 1451, and one active layer 141. Compared with the metal layer, the influence of the active layer 141 on the generation of the step difference is small. Therefore, the height of the second protrusion 153 relative to the substrate 110 is less than the height of the first protrusion 152 relative to the substrate 110.

[0073] It should be noted that the patterned source-drain layer 145 can also form a first capacitor line (not shown in the figure), and the patterned light shielding layer 120 can form a second capacitor line (not shown in the figure). The first capacitor line and the second capacitor line are overlapped to form a corresponding second overlapping region 147. That is, a second protrusion 153 is formed at the position on the passivation layer 150 corresponding to the overlapping region of the two metal layers of the light shielding layer 120 and the source-drain layer 145, and the specific overlapping position is not limited.

[0074] In some embodiments, the maximum value of the height of the first planarization layer 160 relative to the substrate 110 is less than or equal to the height of the second protrusion 153 relative to the substrate 110, that is, the first planarization layer 160 is only located in the recessed area 151 of the passivation layer 150. Setting the maximum value of the height of the first planarization layer 160 relative to the substrate 110 to be less than or equal to the height of the second protrusion 153 relative to the substrate 110 can not only reduce the step difference generated by the second protrusion 153, but also avoid generating a new step difference due to the first planarization layer 160 being higher than the second protrusion 153, saving the use of the first planarization layer 160 and reducing the production cost.

[0075] In other embodiments, when the surface step difference of the passivation layer 150 is large, a first planarization layer 160 is provided on the side of the second protrusion 153 facing away from the substrate 110, that is, in addition to being located in the recessed area 151 of the passivation layer 150, the first planarization layer 160 can also be provided on the protrusion of the passivation layer 150. However, at this time, the maximum value of the height of the first planarization layer 160 relative to the substrate 110 is still less than the maximum value of the height of the passivation layer 150 relative to the substrate 110, avoiding generating a new step difference due to the first planarization layer 160 being too high. By providing the first planarization layer 160 on the side of the second protrusion 153 facing away from the substrate 110, the step difference of the recessed area 151 on the surface of the passivation layer 150 can be further reduced, improving the flatness of the surface of the passivation layer 150, which is helpful for the fabrication of subsequent film layers and improves the structural uniformity of subsequent film layers.

[0076] Optionally, as Figure 7 and Figure 8 shown, the light-shielding layer 120, the active layer 141, and the gate layer 143 are overlapped and form a third overlapping region 148. Among them, the gate layer 143 includes a gate 1431, and a gate insulating layer 142 is further provided between the gate 1431 and the active layer 141, that is, the light-shielding layer 120, the active layer 141, the gate insulating layer 142, and the gate 1431 are overlapped and form a third overlapping region 148. A third protrusion 154 is formed at a position corresponding to the third overlapping region 148 on the side of the passivation layer 150 facing away from the substrate 110. Compared with the metal layer, the influence of the active layer 141 and the gate insulating layer 142 on the step difference is relatively small, that is, the third protrusion 154 is mainly formed by the step difference generated by the superposition of two metal layers, namely the light-shielding layer 120 and the gate layer 143. Among them, the height of the third protrusion 154 relative to the substrate 110 is less than the height of the first protrusion 152 relative to the substrate 110.

[0077] In some embodiments, the maximum value of the height of the first planarization layer 160 relative to the substrate 110 is less than or equal to the height of the third protrusion 154 relative to the substrate 110. That is, the first planarization layer 160 is only located in the recessed area 151 of the passivation layer 150. Setting the maximum value of the height of the first planarization layer 160 relative to the substrate 110 to be less than or equal to the height of the third protrusion 154 relative to the substrate 110 can not only reduce the step difference generated by the third protrusion 154, but also avoid generating a new step difference due to the first planarization layer 160 being higher than the third protrusion 154, save the use of the first planarization layer 160, and reduce the production cost.

[0078] In some other embodiments, when the surface step difference of the passivation layer 150 is large, a first planarization layer 160 is provided on the side of the third protrusion 154 facing away from the substrate 110. That is, in addition to being located in the recessed area 151 of the passivation layer 150, the first planarization layer 160 can also be provided on the protrusions of the passivation layer 150. However, at this time, the maximum value of the height of the first planarization layer 160 relative to the substrate 110 is still less than the maximum value of the height of the passivation layer 150 relative to the substrate 110, so as to avoid generating a new step difference due to the first planarization layer 160 being too high. By providing the first planarization layer 160 on the side of the third protrusion 154 facing away from the substrate 110, the step difference in the recessed area 151 on the surface of the passivation layer 150 can be further reduced, the flatness of the surface of the passivation layer 150 can be improved, which is helpful for the fabrication of subsequent film layers and improves the structural uniformity of subsequent film layers.

[0079] In addition, the heights of the second protrusion 153 and the third protrusion 154 relative to the substrate 110 can be the same or different, and their relative height relationship is directly related to the thickness relationship between the light-shielding layer 120, the gate layer 143, and the source-drain layer 145. By adjusting the thicknesses of the light-shielding layer 120, the gate layer 143, and the source-drain layer 145, the height relationship between the second protrusion 153 and the third protrusion 154 can be adjusted, so as to realize the design adjustment of the thickness of the first planarization layer 160.

[0080] It should be noted that the active layer 141 and the gate insulating layer 142 provided between the light-shielding layer 120 and the gate layer 143 may also cause step differences. However, the film thicknesses of the active layer 141 and the gate insulating layer 142 are small, and the step differences generated by the active layer 141 and the gate insulating layer 142 can be ignored compared with the step difference generated by the superposition of the light-shielding layer 120 and the gate layer 143.

[0081] Optionally, the thickness of the first planarization layer 160 is greater than or equal to 0.2 micrometers and less than or equal to 2.5 micrometers. If the thickness of the first planarization layer 160 is too small, the planarization effect of the step difference generated by the first planarization layer 160 on the concave region 151 of the surface of the passivation layer 150 will be poor, which is not conducive to the fabrication of subsequent film layers; if the thickness of the first planarization layer 160 is too large, it may cause a new step difference between the first planarization layer 160 and the surface of the passivation layer 150, which is not only not conducive to the fabrication of subsequent film layers, but also leads to an overuse of the first planarization layer 160, thereby increasing the production cost.

[0082] In the actual fabrication process, the thickness of the first planarization layer 160 can be set to 0.2 micrometers, 0.5 micrometers, 1.0 micrometers, 1.5 micrometers, 2 micrometers, or 2.5 micrometers, which can not only ensure the effective planarization of the step difference generated by the first planarization layer 160 on the concave region 151 of the surface of the passivation layer 150, but also avoid the generation of a new step difference due to the too large thickness of the first planarization layer 160. Among them, the specific value of the thickness of the first planarization layer 160 can be adjusted accordingly according to the actual situation, and no special limitation is made here.

[0083] Optionally, the material of the first planarization layer 160 includes positive organic photoresist, negative organic photoresist, or inorganic material. When the material of the first planarization layer 160 is positive organic photoresist or negative organic photoresist, the first planarization layer 160 can flow from a higher position to a lower position during the coating process to reduce the height difference of the first planarization layer 160 itself. At the same time, the first planarization layer 160 at the corresponding position is removed by exposure and development, such as the first planarization layer 160 on the surface of the first protrusion 152 of the passivation layer 150, so that the maximum value of the height of the first planarization layer 160 relative to the substrate 110 is less than or equal to the maximum value of the height of the passivation layer 150 relative to the substrate 110.

[0084] When the material of the first planarization layer 160 is inorganic material, the first planarization layer 160 is formed on the passivation layer 150 by deposition. Similarly, after the deposition of the first planarization layer 160 is completed, at least the first planarization layer 160 on the surface of the first protrusion 152 of the passivation layer 150 needs to be etched off so that the maximum value of the height of the first planarization layer 160 relative to the substrate 110 is less than or equal to the maximum value of the height of the passivation layer 150 relative to the substrate 110.

[0085] Optionally, such as Figure 1 and Figure 2As shown, the display panel 100 includes a second planarization layer 170, and the second planarization layer 170 is located on the first planarization layer 160 and the passivation layer 150. After the first planarization layer 160 is disposed on the passivation layer 150, the first planarization layer 160 effectively alleviates the step difference of the concave region 151 on the passivation layer 150. However, when the maximum value of the height of the first planarization layer 160 relative to the substrate 110 is less than the maximum value of the height of the passivation layer 150 relative to the substrate 110, there is still a remaining step difference on the surface of the passivation layer 150. By disposing the second planarization layer 170 on the first planarization layer 160 and the passivation layer 150, the remaining step difference on the surface of the passivation layer 150 can be further planarized to further improve the flatness of the surface of the passivation layer 150, which is helpful for the fabrication of subsequent film layers and improves the structural uniformity of subsequent film layers.

[0086] Among them, the thickness of the second planarization layer 170 is greater than or equal to 1.5 microns and less than or equal to 6 microns. If the thickness of the second planarization layer 170 is too small, the second planarization layer 170 will not be able to effectively planarize the remaining step difference on the surface of the passivation layer 150, which is not conducive to the fabrication of subsequent film layers. If the thickness of the second planarization layer 170 is too large, it will result in too large an opening depth during the subsequent opening design process, thereby causing a risk of breakage during the fabrication of subsequent film layers.

[0087] During the actual fabrication process, the thickness of the second planarization layer 170 can be set to 1.5 microns, 2 microns, 3 microns, 4 microns, 5 microns or 6 microns, etc., which can not only ensure that the second planarization layer 170 plays an effective planarization role, but also avoid the breakage of subsequent film layers at the opening due to too large a thickness of the second planarization layer 170, thereby ensuring the stability of subsequent film layers. Among them, the specific value of the thickness of the second planarization layer 170 can be adjusted accordingly according to the actual situation, and no special limitation is made here.

[0088] It should be noted that the materials of the second planarization layer 170 and the first planarization layer 160 can be the same or different, and no limitation is made here, as long as the second planarization layer 170 can effectively improve the remaining step difference on the surface of the passivation layer 150. Among them, when the materials of the second planarization layer 170 and the first planarization layer 160 are the same, the connection strength between the second planarization layer 170 and the first planarization layer 160 can also be improved, thereby improving the structural stability of the display panel 100.

[0089] Optionally, the display panel 100 further includes an anode layer 180. The anode layer 180 is disposed on the first planarization layer 160 and is electrically connected to the thin film transistor layer 140. Among them, the anode layer 180 includes an anode, the thin film transistor layer 140 includes thin film transistors, and the thin film transistors include source electrodes and drain electrodes. The anode is electrically connected to the source electrode or the drain electrode. During the operation of the display panel 100, the conduction and disconnection of the signals on the corresponding anode can be controlled by the conduction and disconnection of the thin film transistors.

[0090] The display panel 100 includes a pixel definition layer 190. The pixel definition layer 190 is disposed on the anode layer 180. A pixel opening 191 is formed in the pixel definition layer 190. The pixel opening 191 is used to define the position of the light-emitting pixel, and a part of the anode layer 180 is exposed through the pixel opening 191 to facilitate the fabrication of subsequent film layers on the anode layer 180.

[0091] The display panel 100 includes a light-emitting layer 200. The light-emitting layer 200 is disposed on the anode layer 180 and is located within the pixel opening 191, that is, the light-emitting layer 200 is disposed on the exposed anode layer 180 to be connected to the anode layer 180. By controlling the conduction and disconnection of the signals on the anode layer 180, the light-emitting mode of the light-emitting layer 200 can be regulated, thereby realizing the regulation of the display mode of the display panel 100.

[0092] Among them, the display effect of the display panel 100 is related to the thickness uniformity of the light-emitting layer 200. The thickness uniformity of the light-emitting layer 200 is related to the flatness of the surface of the anode layer 180, and the flatness of the anode layer 180 is directly related to the flatness of the surface of the passivation layer 150. Therefore, by providing the first planarization layer 160 and the second planarization layer 170 on the passivation layer 150, the flatness of the surface of the passivation layer 150 can be effectively improved, thereby improving the flatness of the surface of the anode layer 180, further improving the thickness uniformity of the light-emitting layer 200, and enhancing the display effect of the display panel 100.

[0093] The display panel 100 further includes a cathode layer and a packaging layer. The cathode layer is disposed on the pixel definition layer 190 and the light-emitting layer 200 and is connected to the light-emitting layer 200. By jointly controlling the input signals on the anode layer 180 and the cathode layer, the light-emitting mode of the light-emitting layer 200 can be regulated, thereby realizing the regulation of the display mode of the display panel 100.

[0094] The packaging layer is disposed on the cathode layer and fills the pixel opening 191 to encapsulate and protect the internal structures of the light-emitting layer 200 and the thin film transistor layer 140, preventing moisture or oxygen in the external environment from eroding the internal structures of the display panel 100, thereby ensuring the normal use of the display panel 100.

[0095] Secondly, an embodiment of the present application further provides a display device, which includes a display panel. For the specific structure of the display panel, please refer to the above embodiments. Since this display device adopts all the technical solutions of the above embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, and will not be elaborated here one by one.

[0096] As Figure 4 shown, the display device 10 includes a display panel 100, a control circuit 300 and a housing 400. Among them, the housing 400 is connected to the display panel 100 to support and fix the display panel 100. The control circuit 300 is disposed in the housing 400, and the control circuit 300 is electrically connected to the display panel 100 to control the display panel 100 to display images.

[0097] Among them, the display panel 100 can be fixed to the housing 400 to form an integral body with the housing 400. The display panel 100 and the housing 400 form a sealed space for accommodating the control circuit 300. The control circuit 300 can be the main board of the display device 10. At the same time, one or more functional components such as a battery, an antenna structure, a microphone, a speaker, a headphone jack, a universal serial bus interface, a camera, a distance sensor, an ambient light sensor, and a processor can also be integrated on the control circuit 300, so that the display device 10 can adapt to various application fields.

[0098] It should be noted that the display device 10 is not limited to the above content, and it may further include other components, such as a camera, an antenna structure, a fingerprint unlocking module, etc., to expand its scope of use, which is not limited here.

[0099] The display device 10 in the embodiment of the present application has a very wide range of applications, including televisions, computers, mobile phones, flexible displays and lighting such as foldable and rollable display screens, as well as wearable devices such as smart bracelets and smart watches, all of which are within the scope of the application fields of the display device 10 in the embodiment of the present application.

[0100] Finally, an embodiment of the present application further provides a method for manufacturing a display panel, which can be used to manufacture the display panel in the above embodiments. As Figure 5 shown, the method for manufacturing a display panel mainly includes the following steps:

[0101] S100. Provide a substrate 110.

[0102] When manufacturing the display panel 100, a substrate 110 needs to be provided first, and the substrate 110 is cleaned to remove stains on the surface of the substrate 110, facilitating the subsequent fabrication of film layers. The substrate 110 serves as the support structure of the display panel 100, used to support other film layer structures in the display panel 100 to ensure the structural stability of the display panel 100. Among them, the substrate 110 can be a glass substrate or other material types, and no special restrictions are made here.

[0103] S200. Form a thin film transistor layer 140 on the substrate 110.

[0104] After preparing the substrate 110, a thin film transistor layer 140 is formed on the substrate 110. The thin film transistor layer 140 serves as the control switch functional layer of the display panel 100, used to control other functional structure layers of the display panel 100 to regulate the display mode of the display panel 100.

[0105] Among them, the thin film transistor layer 140 includes an active layer 141, a gate layer 143, and a source-drain layer 145. When manufacturing the thin film transistor layer 140, corresponding film layers are patterned to form structures such as thin film transistors or metal traces. For example, after patterning, the gate layer 143 can form a gate 1431, a scan line 1432, etc., and after patterning, the source-drain layer 145 can form source-drains 1451, data lines 1452, etc.

[0106] It should be noted that when the thin film transistor in the thin film transistor layer 140 is a top-gate structure, the active layer 141, the gate layer 143, and the source-drain layer 145 are stacked in a direction away from the substrate 110; when the thin film transistor in the thin film transistor layer 140 is a bottom-gate structure, the gate layer 143, the active layer 141, and the source-drain layer 145 are stacked in a direction away from the substrate 110.

[0107] When the thin film transistor in the thin film transistor layer 140 is a top-gate structure, between forming the thin film transistor layer 140 on the substrate 110, a light-shielding layer 120 and a buffer layer 130 can be formed on the substrate 110 in sequence. The light-shielding layer 120 is used to shield structures such as the active layer 141 in the thin film transistor layer 140 from light, avoiding direct light irradiation from affecting the structural stability of the thin film transistor layer 140; the buffer layer 130 is used to separate the light-shielding layer 120 from the thin film transistor layer 140, avoiding interference between the thin film transistor layer 140 and the light-shielding layer 120 and affecting the normal operation of the thin film transistor layer 140.

[0108] S300. Form a passivation layer 150 on the thin film transistor layer 140, and a plurality of recessed regions 151 are formed on the side of the passivation layer 150 facing away from the substrate 110.

[0109] As shown Figure 6 After the thin film transistor layer 140 is fabricated, a passivation layer 150 is formed on the thin film transistor layer 140 to insulate the thin film transistor layer 140 and prevent interference between the thin film transistor layer 140 and subsequent film layers. A plurality of recessed regions 151 are formed on a side of the passivation layer 150 facing away from the substrate 110, and a raised structure is correspondingly formed between adjacent recessed regions 151. That is, the surface of the passivation layer 150 is an uneven surface with a step difference.

[0110] It should be noted that the thin film transistor layer 140 includes a metal layer and an insulating layer. When the metal layer is formed, the metal layer is patterned to form a target pattern, that is, a raised portion is formed at the position of the patterned metal layer. For the entire thin film transistor layer 140, the region composed only of the insulating layer stacked is the region where the height of the surface of the thin film transistor layer 140 relative to the substrate 110 is smaller. On the contrary, the more metal layers are stacked, the higher the height of the corresponding region of the thin film transistor layer 140 surface relative to the substrate 110, thereby forming raised portions with different heights on the surface of the thin film transistor layer 140. When the passivation layer 150 is formed on the thin film transistor layer 140, the surface shape of the passivation layer 150 is directly related to the surface shape of the thin film transistor layer 140. Therefore, raised portions are formed in corresponding regions on the surface of the passivation layer 150, and recessed regions 151 are formed between adjacent raised portions.

[0111] In some embodiments, when the thin film transistor layer 140 is formed, the light-shielding layer 120, the gate layer 143, and the source-drain layer 145 are overlapped and arranged to form a first overlapping region 146. For example, after the gate layer 143 is patterned, the gate 1431 and the scanning line 1432 can be formed. After the source-drain layer 145 is patterned, the source-drain 1451 and the data line 1452 can be formed. The light-shielding layer 120, the scanning line 1432, and the data line 1452 are overlapped and arranged to form a first overlapping region 146. A first raised portion 152 is formed at a position of the passivation layer 150 facing away from the substrate 110 corresponding to the first overlapping region 146. That is, the first raised portion 152 is mainly formed by the step difference generated by the stacking of three metal layers, namely the light-shielding layer 120, the scanning line 1432, and the data line 1452.

[0112] Among them, the scanning line 1432 can also be formed in the patterned light-shielding layer 120. That is, the first overlapping region 146 refers to the overlapping region formed after the three metal layers, namely the light-shielding layer 120, the gate layer 143, and the source-drain layer 145, are patterned. However, the specific position of the overlap is not limited. That is, the first raised portion 152 is formed in the region of the passivation layer 150 corresponding to the overlapping arrangement of the three metal layers.

[0113] It should be noted that a gate insulating layer 142 is further provided between the gate layer 143 and the active layer 141. When patterning the gate insulating layer 142 and the gate layer 143, the gate layer 143 is first patterned, and then the gate insulating layer 142 is patterned using the patterned gate layer 143 as a mask. Therefore, a gate insulating layer 142 is provided below the patterned gate layer 143, that is, the first overlapping region 146 further includes the gate insulating layer 142. Compared with the step difference generated by the overlapping arrangement of the three metal layers, the influence of the gate insulating layer 142 on the step difference is relatively small.

[0114] In some other embodiments, the light-shielding layer 120, the active layer 141, and the source-drain layer 145 are overlapped to form a second overlapping region 147. The source-drain layer 145 includes a source-drain 1451, and the source-drain 1451 is electrically connected to the active layer and overlapped, that is, the light-shielding layer 120, the active layer 141, and the source-drain 1451 are overlapped to form the second overlapping region 147. A second protrusion 153 is formed at a position corresponding to the second overlapping region 147 on the side of the passivation layer 150 away from the substrate 110. That is, the second protrusion 153 is mainly formed by the step difference generated by the superposition of two metal layers, namely the light-shielding layer 120 and the source-drain 1451, and one active layer 141. Compared with the metal layer, the influence of the active layer 141 on the step difference is relatively small. Therefore, the height of the second protrusion 153 relative to the substrate 110 is less than the height of the first protrusion 152 relative to the substrate 110.

[0115] It should be noted that the patterned source-drain layer 145 can also form a first capacitor line (not shown in the figure), and the patterned light-shielding layer 120 can form a second capacitor line (not shown in the figure). The first capacitor line and the second capacitor line are overlapped to form a corresponding second overlapping region 147, that is, second protrusions 153 are formed at positions on the passivation layer 150 corresponding to the overlapping region of the two metal layers, namely the light-shielding layer 120 and the source-drain layer 145, and the specific overlapping position is not limited.

[0116] In some other embodiments, the light-shielding layer 120, the active layer 141, and the gate layer 143 are overlapped to form a third overlapping region 148. The gate layer 143 includes a gate 1431, and a gate insulating layer 142 is further disposed between the gate 1431 and the active layer 141, that is, the light-shielding layer 120, the active layer 141, the gate insulating layer 142, and the gate 1431 are overlapped to form the third overlapping region 148. A third protrusion 154 is formed at a position corresponding to the third overlapping region 148 on a side of the passivation layer 150 facing away from the substrate 110. Compared with the metal layer, the influence of the active layer 141 and the gate insulating layer 142 on the step difference is relatively small, that is, the third protrusion 154 is mainly formed by the step difference generated by the superposition of the two metal layers of the light-shielding layer 120 and the gate layer 143. The height of the third protrusion 154 relative to the substrate 110 is less than the height of the first protrusion 152 relative to the substrate 110.

[0117] It should be noted that the heights of the second protrusion 153 and the third protrusion 154 relative to the substrate 110 can be the same or different, and the relative relationship of their heights is directly related to the thickness relationship among the light-shielding layer 120, the gate layer 143, and the source-drain layer 145. By adjusting the thicknesses of the light-shielding layer 120, the gate layer 143, and the source-drain layer 145, the height relationship between the second protrusion 153 and the third protrusion 154 can be adjusted.

[0118] S400. A first planarization layer 160 is formed on the passivation layer 150, so that the first planarization layer 160 is at least partially located in the plurality of recessed regions 151, and the maximum value of the height of the first planarization layer 160 relative to the substrate 110 is less than or equal to the maximum value of the height of the passivation layer 150 relative to the substrate 110.

[0119] As Figure 7 and Figure 8 shown, after the passivation layer 150 is fabricated, the first planarization layer 160 is formed on the passivation layer 150, so that the first planarization layer 160 is at least partially located in the plurality of recessed regions 151. By disposing the first planarization layer 160 in the recessed regions 151 of the passivation layer 150, the step difference generated by the recessed regions 151 on the passivation layer 150 can be reduced, the flatness of the surface of the passivation layer 150 can be improved, which is helpful for the fabrication of subsequent film layers and improves the structural uniformity of the subsequent film layers.

[0120] Among them, the maximum value of the height of the first planarization layer 160 relative to the substrate 110 is less than or equal to the maximum value of the height of the passivation layer 150 relative to the substrate 110, that is, the highest point of the surface of the first planarization layer 160 facing away from the substrate 110 is lower than the highest point of the surface of the passivation layer 150 facing away from the substrate 110, or the highest point of the surface of the first planarization layer 160 facing away from the substrate 110 is flush with the highest point of the surface of the passivation layer 150 facing away from the substrate 110. This structural design can reduce the surface step difference of the passivation layer 150 while avoiding the generation of a new step difference between the first planarization layer 160 and the passivation layer 150, and can also save the use of the first planarization layer 160 and reduce the production cost.

[0121] It should be noted that the generation of the surface step difference of the thin film transistor layer 140 in the embodiment of the present application mainly comes from the overlapping arrangement of the light shielding layer 120 and the metal layer in the thin film transistor layer 140, and the metal layer in the thin film transistor layer 140 includes a gate layer 143 and a source-drain layer 145, that is, the maximum surface step difference of the thin film transistor layer 140 comes from the overlapping arrangement of the three metal layers. That is to say, the height of the first protrusion 152 relative to the substrate 110 is the maximum value of the height of the passivation layer 150 relative to the substrate 110.

[0122] When forming the first planarization layer 160, the first planarization layer 160 can be entirely disposed in the recessed area 151 on the passivation layer 150, that is, the surfaces of the first protrusion 152, the second protrusion 153, and the third protrusion 154 on the passivation layer 150 are not provided with the first planarization layer 160. At this time, the maximum value of the height of the first planarization layer 160 relative to the substrate 110 is less than or equal to the height of the first protrusion 152 relative to the substrate 110, or the maximum value of the height of the first planarization layer 160 relative to the substrate 110 is less than or equal to the height of the second protrusion 153 relative to the substrate 110, or the maximum value of the height of the first planarization layer 160 relative to the substrate 110 is less than or equal to the height of the third protrusion 154 relative to the substrate 110.

[0123] Among them, the specific height of the first planarization layer 160 can be adjusted and designed according to the height relationship of each protrusion structure. This structural design can reduce the surface step difference of the passivation layer 150 by the first planarization layer 160 while avoiding the generation of a new step difference between the first planarization layer 160 and the protrusion structure.

[0124] In some embodiments, the first planarization layer 160 can be disposed on the surfaces of some of the protruding structures in addition to the recessed regions 151 of the passivation layer 150. For example, when the passivation layer 150 includes a first protrusion 152, a second protrusion 153, and a third protrusion 154 at the same time, the first planarization layer 160 can be disposed on the surfaces of the second protrusion 153 and the third protrusion 154 at the same time, only exposing the surface of the first protrusion 152 at the highest point.

[0125] That is to say, when forming the first planarization layer 160 on the passivation layer 150, according to the distribution of the protruding structures on the passivation layer 150, only the surface of the protruding structure that is the highest relative to the substrate 110 on the passivation layer 150 is exposed. Such a structural design can minimize the step difference on the surface of the passivation layer 150, improve the flatness of the surface of the passivation layer 150, contribute to the fabrication of subsequent film layers, and improve the structural uniformity of the subsequent film layers.

[0126] Among them, the material of the first planarization layer 160 includes positive photoresist, negative photoresist, or inorganic material. When the material of the first planarization layer 160 is positive photoresist or negative photoresist, the first planarization layer 160 can be applied by coating. During the coating process, the first planarization layer 160 can flow from a higher position to a lower position to reduce the height difference of the first planarization layer 160 itself; then, the first planarization layer 160 at the corresponding position is removed by exposure and development, such as the first planarization layer 160 on the surface of the first protrusion 152 of the passivation layer 150, so that the maximum value of the height of the first planarization layer 160 relative to the substrate 110 is less than or equal to the maximum value of the height of the passivation layer 150 relative to the substrate 110.

[0127] When the material of the first planarization layer 160 is an inorganic material, the first planarization layer 160 is formed on the passivation layer 150 by deposition. Similarly, after the deposition of the first planarization layer 160 is completed, at least the first planarization layer 160 on the surface of the first protrusion 152 of the passivation layer 150 needs to be etched off so that the maximum value of the height of the first planarization layer 160 relative to the substrate 110 is less than or equal to the maximum value of the height of the passivation layer 150 relative to the substrate 110.

[0128] Optionally, the manufacturing method of the display panel 100 in the embodiments of the present application further includes the following content:

[0129] Such as Figure 1 and Figure 2As shown, a second planarization layer 170 is formed on the first planarization layer 160 and the passivation layer 150; an anode layer 180 is formed on the second planarization layer 170, and the anode layer 180 is electrically connected to the thin film transistor layer 140; a pixel definition layer 190 is formed on the anode layer 180, and a pixel opening 191 is formed on the pixel definition layer 190, so that the pixel opening 191 exposes a part of the anode layer 180; a light-emitting layer 200 is printed on the anode layer 180, and the light-emitting layer 200 is located within the pixel opening 191.

[0130] After the first planarization layer 160 is disposed on the passivation layer 150, the first planarization layer 160 effectively alleviates the step difference of the concave region 151 on the passivation layer 150. However, when the maximum value of the height of the first planarization layer 160 relative to the substrate 110 is less than the maximum value of the height of the passivation layer 150 relative to the substrate 110, there is still a remaining step difference on the surface of the passivation layer 150. By disposing the second planarization layer 170 on the first planarization layer 160 and the passivation layer 150, the remaining step difference on the surface of the passivation layer 150 can be further planarized to further improve the flatness of the surface of the passivation layer 150, which is helpful for the fabrication of subsequent film layers and improves the structural uniformity of subsequent film layers.

[0131] Specifically, the anode layer 180 includes an anode, the thin film transistor layer 140 includes thin film transistors, the thin film transistors include source electrodes and drain electrodes, and the anode is electrically connected to the source electrode or the drain electrode. During the operation of the display panel 100, the conduction and disconnection of the signals on the corresponding anode can be controlled by the conduction and disconnection of the thin film transistors. The pixel opening 191 on the pixel definition layer 190 is used to define the position of the light-emitting pixels, and the pixel opening 191 exposes a part of the anode layer 180. The light-emitting layer 200 is disposed on the exposed anode layer 180 to be connected to the anode layer 180. The light-emitting mode of the light-emitting layer 200 can be regulated by the conduction and disconnection of the signals on the anode layer 180, thereby realizing the regulation of the display mode of the display panel 100.

[0132] Among them, the display effect of the display panel 100 is related to the thickness uniformity of the light-emitting layer 200. The thickness uniformity of the light-emitting layer 200 is related to the flatness of the surface of the anode layer 180, and the flatness of the anode layer 180 is directly related to the flatness of the surface of the passivation layer 150. Therefore, by disposing the first planarization layer 160 and the second planarization layer 170 on the passivation layer 150, the flatness of the surface of the passivation layer 150 can be effectively improved, thereby improving the flatness of the surface of the anode layer 180, further improving the thickness uniformity of the light-emitting layer 200, and improving the display effect of the display panel 100.

[0133] The manufacturing method of the display panel 100 further includes sequentially forming a cathode layer and a packaging layer on the pixel definition layer 190, and the cathode layer is connected to the light-emitting layer 200. By jointly controlling the input signals on the anode layer 180 and the cathode layer, the light-emitting mode of the light-emitting layer 200 can be regulated, thereby realizing the regulation of the display mode of the display panel 100. The packaging layer is disposed on the cathode layer and fills the pixel opening 191 to package and protect the internal structures of the light-emitting layer 200 and the thin-film transistor layer 140, preventing moisture or oxygen in the external environment from eroding the internal structures of the display panel 100, thereby ensuring the normal use of the display panel 100.

[0134] The above has introduced in detail a display panel, a display device, and a manufacturing method of a display panel provided by an embodiment of the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application; at the same time, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A display panel, characterized in that, Comprising: A substrate; A thin film transistor layer disposed on the substrate; A passivation layer disposed on the thin film transistor layer. On a side of the passivation layer facing away from the substrate, a first protrusion and a second protrusion are formed. A height of the first protrusion relative to the substrate is greater than a height of the second protrusion relative to the substrate. A recessed area is formed between the first protrusion and the second protrusion; A first planarization layer disposed on the passivation layer. The first planarization layer is at least partially located within the recessed area and on a side of the second protrusion facing away from the substrate. A maximum value of a height of the first planarization layer relative to the substrate is less than or equal to a maximum value of a height of the first protrusion relative to the substrate.

2. The display panel according to claim 1, wherein The thin film transistor layer includes an active layer, a gate layer, and a source-drain layer. The gate layer and the source-drain layer are overlapped to form a first overlapping area. The first protrusion is formed at a position corresponding to the first overlapping area on a side of the passivation layer facing away from the substrate. The active layer and the source-drain layer are overlapped to form a second overlapping area. The second protrusion is formed at a position corresponding to the second overlapping area on a side of the passivation layer facing away from the substrate. The active layer and the gate layer are overlapped to form a third overlapping area. The third protrusion is formed at a position corresponding to the third overlapping area on a side of the passivation layer facing away from the substrate.

3. The display panel according to claim 2, wherein The display panel further includes a light-shielding layer and a buffer layer sequentially disposed on the substrate. The thin film transistor layer is disposed on the buffer layer. The light-shielding layer, the gate layer, and the source-drain layer are overlapped to form the first overlapping area. The light-shielding layer, the active layer, and the source-drain layer are overlapped to form the second overlapping area. The light-shielding layer, the active layer, and the gate layer are overlapped to form the third overlapping area.

4. The display panel according to claim 2, characterized in that, The first planarization layer is disposed on a side of the third protrusion facing away from the substrate.

5. The display panel according to any one of claims 1 to 4, characterized in that, A thickness of the first planarization layer is greater than or equal to 0.2 micrometers and less than or equal to 2.5 micrometers.

6. The display panel according to any one of claims 1 to 4, characterized in that, A material of the first planarization layer includes a positive organic photoresist, a negative organic photoresist, or an inorganic material.

7. The display panel according to any one of claims 1 to 4, characterized in that, The display panel includes a second planarization layer. The second planarization layer is located on the first planarization layer and the passivation layer.

8. The display panel according to claim 7, wherein, A thickness of the second planarization layer is greater than or equal to 1.5 micrometers and less than or equal to 6 micrometers.

9. The display panel according to claim 1, wherein The display panel further includes: An anode layer disposed on the first planarization layer. The anode layer is electrically connected to the thin film transistor layer; A pixel definition layer disposed on the anode layer. A pixel opening is formed in the pixel definition layer. The pixel opening exposes a part of the anode layer; A light-emitting layer disposed on the anode layer. The light-emitting layer is located within the pixel opening.

10. A display device, characterized in that, The display device includes the display panel according to any one of claims 1 to 9.

11. A method for manufacturing a display panel, characterized in that The method includes: Providing a substrate; Forming a thin film transistor layer on the substrate; A passivation layer is formed on the thin film transistor layer. On a side of the passivation layer facing away from the substrate, a first protrusion and a second protrusion are formed. A height of the first protrusion relative to the substrate is greater than a height of the second protrusion relative to the substrate. A recessed area is formed between the first protrusion and the second protrusion. A first planarization layer is formed on the passivation layer such that the first planarization layer is at least partially located within the plurality of recessed areas and on a side of the second protrusion facing away from the substrate. A maximum value of a height of the first planarization layer relative to the substrate is less than or equal to a maximum value of a height of the first protrusion relative to the substrate.

12. The manufacturing method of the display panel according to claim 11, wherein The method further includes: forming a second planarization layer on the first planarization layer and the passivation layer; forming an anode layer on the second planarization layer such that the anode layer is electrically connected to the thin film transistor layer; forming a pixel definition layer on the anode layer and forming a pixel opening in the pixel definition layer such that the pixel opening exposes a part of the anode layer; printing a layer of a light emitting layer on the anode layer such that the light emitting layer is located within the pixel opening.

Images