Display device and method for manufacturing the same

Abstract

A display device and a method for manufacturing a display device are provided. The display device according to an embodiment includes: a substrate; a conductive line disposed on the substrate; a first capacitor electrode disposed on the conductive line and connected to the conductive line; a passivation layer disposed on the first capacitor electrode; a first electrode disposed on the passivation layer and at least partially overlapping the first capacitor electrode; a second electrode spaced apart from the first electrode and formed in the same layer as the first electrode; and a light-emitting element disposed between the first electrode and the second electrode.

Description

Technical Field

[0001] The present invention relates to a display device and a manufacturing method thereof. Background Art

[0002] A display device can display an image by using a light-emitting element such as a light-emitting diode as a light source of a pixel. The light-emitting diode has relatively good durability even under harsh environmental conditions and has excellent performance in terms of lifespan and brightness.

[0003] Research has been conducted on manufacturing a light-emitting diode using a material having a highly reliable inorganic crystal structure, disposing it in a display panel of a display device, and using it as a pixel light source. As part of the research, development of a display device that manufactures a light-emitting diode of a micron scale or a nanoscale and uses it as a light source for each pixel is underway. Summary of the Invention

[0004]

Technical Problem

[0005] A display device using such a light-emitting diode as a light-emitting element may include a plurality of alignment lines, and the light-emitting element can be aligned between the alignment lines by applying a predetermined voltage to the alignment lines. When a noise component voltage is included in the voltage applied to the alignment lines, a problem may occur in which the light-emitting element is misaligned or unevenly aligned between the alignment lines.

[0006] Therefore, the problem to be solved by the present invention is to provide a display device and a manufacturing method thereof that can improve manufacturing efficiency while easily aligning a light-emitting element between alignment lines.

[0007] The object of the present invention is not limited to the above-mentioned object, and other technical objects not mentioned can be clearly understood by those of ordinary skill in the art using the following description.

[0008]

Technical Solution

[0009] An embodiment of the present invention provides a display device, including: a substrate; a conductive wire disposed on the substrate; a first capacitor electrode disposed on the conductive wire and connected to the conductive wire; a passivation layer disposed on the first capacitor electrode; a first electrode disposed on the passivation layer and at least partially overlapping the first capacitor electrode; a second electrode spaced apart from the first electrode and formed in the same layer as the first electrode; and a light-emitting element disposed between the first electrode and the second electrode.

[0010] The passivation layer may include an insulating material, and the first capacitor electrode, the passivation layer, and the first electrode may form a first capacitor.

[0011] The display device may further include a transistor disposed between the substrate and the light-emitting element and electrically connected to the light-emitting element. The transistor may include: a semiconductor pattern disposed on the substrate; a gate electrode disposed on the semiconductor pattern; and a first transistor electrode and a second transistor electrode disposed on the gate electrode and connected to the semiconductor pattern, and the conductive wire may be disposed on the same layer as the gate electrode.

[0012] The first electrode may be connected to the first power line, and the first electrode may receive a first driving voltage through the first power line.

[0013] The first transistor electrode may be connected to the second electrode, the second transistor electrode may be connected to the second power line, and may receive a second driving voltage greater than the first driving voltage through the second power line.

[0014] The first capacitor electrode may be disposed on the same layer as the second power line.

[0015] At least a part of the second power line may overlap with the second electrode, a passivation layer may be disposed between the second power line and the second electrode, and the second power line, the passivation layer, and the second electrode may form a second capacitor.

[0016] The first capacitor electrode may be disposed on the same layer as the first transistor electrode.

[0017] The conductive wire may extend along a first direction in a plan view, and the first power line may extend along a second direction intersecting the first direction in the plan view.

[0018] The display device may further include a first connection electrode connecting the first electrode and the first power line and extending along the first direction. The first electrode may extend along the second direction, at least a part of the first connection electrode may overlap with the first capacitor electrode, and the first electrode, the first connection electrode, and the first power line may be integrally formed.

[0019] The display device may further include a third electrode disposed on the same layer as the second electrode. In the plan view, the first electrode may be disposed between the second electrode and the third electrode, and the light-emitting element may also be disposed between the first electrode and the third electrode.

[0020] The display device may further include a second connection electrode connecting the second electrode and the third electrode and extending along the first direction. The second electrode, the third electrode, and the second connection electrode may be integrally formed.

[0021] The display device may further include: a third electrode that contacts the first electrode and the first end portion of the light-emitting element; and a fourth electrode that contacts the second electrode and the second end portion of the light-emitting element.

[0022] The display device may further include an insulating layer disposed on the first electrode and the second electrode. The insulating layer may include a first opening exposing at least a part of the first electrode and a second opening exposing at least a part of the second electrode. The third electrode may contact the first electrode through the first opening, and the fourth electrode may contact the second electrode through the second opening.

[0023] The display device may further include a fixing layer disposed on the insulating layer and the light-emitting element. The fixing layer may contact at least a part of the outer peripheral surface of each of the light-emitting elements and may expose the first end portion and the second end portion of each of the light-emitting elements.

[0024] The display device may further include: a first bank disposed between the first electrode and the passivation layer and overlapping the first electrode; and a second bank disposed between the second electrode and the passivation layer and overlapping the second electrode.

[0025] Another embodiment provides a display device, which includes: a substrate; a conductive line disposed on the substrate; a first capacitor electrode disposed on the conductive line and connected to the conductive line; a second capacitor electrode disposed on the conductive line and spaced apart from the first capacitor electrode; a passivation layer disposed on the first capacitor electrode and the second capacitor electrode; a first electrode disposed on the passivation layer and at least partially overlapping the first capacitor electrode; a second electrode spaced apart from the first electrode, formed in the same layer as the first electrode, and at least partially overlapping the second capacitor electrode; and a light-emitting element disposed between the first electrode and the second electrode.

[0026] The passivation layer may include an insulating material. The first capacitor electrode, the passivation layer, and the first electrode may form a first capacitor, and the second capacitor electrode, the passivation layer, and the second electrode may form a second capacitor.

[0027] The first capacitor electrode and the second capacitor electrode may be disposed in the same layer.

[0028] The display device may further include a transistor disposed between the substrate and the light-emitting element and electrically connected to the light-emitting element. The transistor may include: a semiconductor pattern disposed on the substrate; a gate electrode disposed on the semiconductor pattern; and a first transistor electrode and a second transistor electrode disposed on the gate electrode to be connected to the semiconductor pattern. The first transistor electrode may be connected to the second electrode, the second transistor electrode may be connected to the second capacitor electrode, and the conductive line may be disposed in the same layer as the gate electrode.

[0029] The conductive line may extend in a first direction in a plan view, and the second capacitor electrode may extend in a second direction intersecting the first direction in the plan view.

[0030] The display device may further include: a third electrode disposed on the same layer as the second electrode; and a second connection electrode connecting the second electrode and the third electrode and extending along a first direction, wherein, in a plan view, the first electrode may be disposed between the second electrode and the third electrode, and a light-emitting element may be further disposed between the first electrode and the third electrode.

[0031] The display device may further include: a third capacitor electrode disposed on the same layer as the second capacitor electrode; and a third connection electrode connecting the second capacitor electrode and the third capacitor electrode and extending along a first direction, wherein at least a part of the third capacitor electrode may overlap with the third electrode, at least a part of the third connection electrode may overlap with the second connection electrode, and the first capacitor electrode, the second capacitor electrode, the third capacitor electrode, and the third connection electrode may be formed on the same layer.

[0032] Another embodiment of the present invention provides a method of manufacturing a display device, the manufacturing method including: forming a bypass power line on a substrate, forming a first capacitor electrode connected to the bypass power line on an upper portion of the bypass power line, forming a first electrode at least partially overlapping with the first capacitor electrode and a second electrode spaced apart from the first electrode on an upper portion of the first capacitor electrode, and supplying a first voltage to the bypass power line, supplying a second voltage to the first electrode, and supplying a third voltage to the second electrode to align a light-emitting element between the first electrode and the second electrode, wherein the first voltage, the second voltage, and the third voltage may be different voltages.

[0033] The first voltage and the second voltage may be DC voltages, and the third voltage may be an AC voltage.

[0034] In the step of aligning the light-emitting element, the first capacitor electrode and the first electrode may form a first capacitor, and the first capacitor may bypass an AC voltage component in the voltage supplied to the first electrode to the bypass power line.

[0035] The step of forming the first capacitor electrode may further include forming a second capacitor electrode spaced apart from the first capacitor electrode, and at least a part of the second capacitor electrode may overlap with the second electrode.

[0036] In the step of aligning the light-emitting element, the second capacitor electrode and the second electrode may form a second capacitor, and the second electrode may receive the third voltage from the second capacitor electrode through the second capacitor.

[0037] The first voltage may be a value between a positive peak voltage and a negative peak voltage of the third voltage, and the second voltage may be a ground voltage.

[0038] Details of other embodiments are included in the detailed description and the drawings.

[0039]

Advantageous Effects

[0040] According to the display device and manufacturing method thereof according to an embodiment of the present invention, it is possible to remove the noise component voltage (e.g., AC voltage component) of the ground voltage applied to the first electrode by forming a first capacitor electrode under the first electrode to which a first voltage (which is a ground voltage for aligning the light-emitting element) is applied. Therefore, the alignment characteristics of the light-emitting element can be improved.

[0041] In addition, according to the display device and manufacturing method thereof according to an embodiment of the present invention, it is possible to remove the noise component voltage (e.g., DC voltage component) of the AC voltage applied to the second electrode by forming a second capacitor electrode under the second electrode to which a second voltage (which is an AC voltage for aligning the light-emitting element) is applied. Therefore, the alignment characteristics of the light-emitting element can be improved.

[0042] In addition, according to an embodiment of the present invention, since the noise component voltage of the voltage applied to the alignment electrode is removed, a uniform electric field is formed between the alignment lines, so that the light-emitting elements can be uniformly aligned in each pixel. Therefore, the display quality and manufacturing efficiency of the display device can be improved.

[0043] The effects of the embodiments of the present invention are not limited to those shown above, and more various effects are included in this specification. Description of the Drawings

[0044] Figure 1a and Figure 1b A perspective view of a light-emitting element according to an embodiment is shown.

[0045] Figure 2 A top plan view of a display device according to an embodiment is shown.

[0046] Figures 3a to 3c Circuit diagrams of pixels according to embodiments are shown respectively.

[0047] Figure 4 A circuit diagram of a pixel according to another embodiment is shown.

[0048] Figure 5 A top plan view of a pixel according to an embodiment is shown.

[0049] Figure 6 It shows along Figure 5 A cross-sectional view taken along line A-A'.

[0050] Figures 7 to 11 Cross-sectional views of pixels according to various embodiments are shown, and a cross-sectional view taken along line A-A' is shown. Figure 5 A cross-sectional view taken along line A-A'.

[0051] Figure 12 A plan view of a pixel according to another embodiment is shown.

[0052] Figures 13 to 16 A plan view for explaining a method of manufacturing a display device according to an embodiment is shown.

[0053] Figure 17 A circuit diagram for explaining a noise removal method of a voltage supplied to a display device according to an embodiment when aligning light emitting elements is shown.

[0054] Figure 18 A waveform diagram of the voltage actually supplied to each electrode of a display device according to an embodiment when aligning light emitting elements is shown.

[0055] Figure 19 A plan view of a pixel according to another embodiment is shown.

[0056] Figure 20 It shows along Figure 19 a cross-sectional view taken along line B - B'.

[0057] Figure 21 A cross-sectional view of a pixel according to another embodiment is shown, and a cross-sectional view taken along line B - B' is shown. Figure 19 a cross-sectional view taken along line B - B'.

[0058] Figure 22 A plan view of a pixel according to another embodiment is shown.

[0059] Figures 23 to 26 A plan view for explaining a method of manufacturing a display device according to another embodiment is shown.

[0060] Figure 27 A circuit diagram for explaining a noise removal method of a voltage supplied to a display device according to another embodiment when aligning light emitting elements is shown. Detailed Description of the Embodiments

[0061] Advantages and features of the present invention and methods for implementing the present invention can be more easily understood by referring to the following detailed description of preferred embodiments and the accompanying drawings. However, the present invention is not limited to the embodiments described below and can be implemented in many different forms. The following embodiments are provided to make the disclosure of the present invention complete and to allow those skilled in the art to clearly understand the scope of the present invention. The present invention is defined only by the scope of the appended claims.

[0062] It will be understood that when an element or layer is referred to as being "on" another element or layer, the element or layer can be directly on the other element or layer, or intervening elements or layers may also be present. Throughout the specification, the same reference numerals denote the same constituent elements. The shapes, dimensions, ratios, angles, quantities, etc. disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited to the embodiments shown.

[0063] Although terms such as "first", "second", etc. are used to describe various constituent elements, these constituent elements are not limited by these terms. These terms are only used to distinguish one constituent element from another. Thus, within the technical spirit of the present invention, the first constituent element described below may be the second constituent element. Unless the context clearly indicates otherwise, the singular form is intended to include the plural form.

[0064] Each of the features of the various embodiments of the present invention can be partially or completely combined or combined with each other, and can be variously interlocked and driven technically in a manner fully understandable to those skilled in the art. Each embodiment can be feasible independently of each other, and can be feasible together in a mutual relationship.

[0065] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same or similar reference numerals are used for the same constituent elements in the drawings.

[0066] Figure 1a and Figure 1b A perspective view of a light-emitting element according to an embodiment is shown.

[0067] Referring to Figure 1a and Figure 1b , a light-emitting element LD according to an embodiment of the present invention may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 disposed between the first semiconductor layer 11 and the second semiconductor layer 13. For example, the light-emitting element LD can be implemented as a stack in which the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 are sequentially stacked.

[0068] According to an embodiment of the present invention, the light-emitting element LD can be provided in a rod-like shape extending along one direction. When the extending direction of the light-emitting element LD is referred to as the length direction, the light-emitting element LD can be provided with one end and the other end along the length direction.

[0069] In an embodiment of the present invention, one of the first semiconductor layer 11 and the second semiconductor layer 13 can be provided at one end, and the other of the first semiconductor layer 11 and the second semiconductor layer 13 can be provided at the other end.

[0070] In an embodiment of the present invention, the light-emitting element LD may be configured to have a rod shape. Here, the term "rod shape" may include a rod shape or a strip shape of a column such as a cylindrical or polygonal shape that is long in the length direction (i.e., the aspect ratio is greater than 1). For example, the length of the light-emitting element LD may be greater than its diameter. However, the present invention is not limited thereto. Additionally, the light-emitting element LD may be a light-emitting element having a core-shell structure.

[0071] The light-emitting element LD may be fabricated to have a diameter and / or length of, for example, about the micron scale or the nanometer scale. For example, the diameter of the light-emitting element LD may be 600 nm or less, and the length of the light-emitting element LD may be 4 μm or less. However, the size of the light-emitting element LD is not limited thereto, and the size of the light-emitting element LD may be changed to meet the requirements of the display device to which the light-emitting element LD is applied.

[0072] For example, the first semiconductor layer 11 may include at least one n-type semiconductor layer. For example, the first semiconductor layer 11 may include a semiconductor material of one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a semiconductor layer doped with a first dopant such as Si, Ge, Sn, Se, etc. The materials included in the first semiconductor layer 11 are not limited thereto, and the first semiconductor layer 11 may be made of various materials.

[0073] The active layer 12 is formed on the first semiconductor layer 11 and may be formed to have a single quantum well structure or a multiple quantum well structure. When the active layer 12 includes a material having a multiple quantum well structure, a plurality of quantum layers and well layers may be alternately stacked.

[0074] When an electric field of a predetermined voltage or higher is applied to each end of the light-emitting element LD, the light-emitting element LD emits light while electron-hole pairs are combined in the active layer 12. By controlling the light emission of the light-emitting element LD by utilizing this principle, in addition to the pixels of the display device, the light-emitting element LD can also be used as a light source for various light-emitting devices.

[0075] The active layer 12 may emit light having a wavelength in the range of 400 nm to 900 nm. For example, when the active layer 12 emits light in the blue wavelength band, the active layer 12 may include materials such as AlGaN or AlGaInN. In particular, when the active layer 12 has a structure in which quantum layers and well layers are alternately stacked in a multiple quantum well structure, the quantum layer may include an inorganic material such as AlGaN or AlGaInN, and the well layer may include a material such as GaN or AlInN. In an embodiment, the active layer 12 may include AlGaInN as the quantum layer and AlInN as the well layer, and as described above, the active layer 12 may emit blue light having a central wavelength band in the range from 450 nm to 495 nm.

[0076] However, the present invention is not limited thereto, and the active layer 12 may have a structure in which a semiconductor material having a large bandgap and a semiconductor material having a small bandgap are alternately stacked, or may include a group III to group V semiconductor material according to the wavelength band of the emitted light. The light emitted from the active layer 12 is not limited to light in the blue wavelength band, and in some cases, it may be light in the red wavelength band or the green wavelength band.

[0077] On the other hand, the light emitted from the active layer 12 may be emitted from both side surfaces and the outer surface of the light-emitting element LD in the longitudinal direction. The directivity of the light emitted from the active layer 12 is not limited to one direction.

[0078] The second semiconductor layer 13 is disposed on the active layer 12 and may include a semiconductor layer of a type different from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second semiconductor layer 13 may include at least one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a semiconductor layer doped with a second dopant such as Mg, Zn, Ca, and Ba. The materials included in the second semiconductor layer 13 are not limited thereto, and the second semiconductor layer 13 may be formed of various materials.

[0079] Meanwhile, in the drawings, the first semiconductor layer 11 and the second semiconductor layer 13 are both shown as being formed as a single layer, but the present invention is not limited thereto. For example, the first semiconductor layer 11 and the second semiconductor layer 13 may include a larger number of layers depending on the material of the active layer 12. For example, the first semiconductor layer 11 and the second semiconductor layer 13 may further include a cladding layer or a tensile strain barrier reduction (TSBR) layer.

[0080] According to an embodiment of the present invention, the light-emitting element LD may further include a phosphor layer, another active layer, another semiconductor layer, and / or an electrode layer above and / or below each of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 described above.

[0081] As an example, the light-emitting element LD may further include at least one electrode layer disposed on one end (e.g., the upper surface of the light-emitting element LD) side of the second semiconductor layer 13 or on one end (e.g., the lower surface of the light-emitting element LD) side of the first semiconductor layer 11. For example, as Figure 1bAs shown, the light-emitting element LD may further include an electrode layer 15 provided at one end side of the second semiconductor layer 13. The electrode layer 15 may be an ohmic electrode, but is not limited thereto. For example, the electrode layer 15 may be a Schottky contact electrode. The electrode layer 15 may include, for example, metals or metal oxides such as chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO), and oxides of the above metals or alloys of the above metals that may be used alone or in combination, but is not limited thereto. Additionally, in some embodiments, the electrode layer 15 may be substantially transparent or translucent. Thus, the light generated by the light-emitting element LD may pass through the electrode layer 15 to be emitted to the outside of the light-emitting element LD.

[0082] Additionally, the light-emitting element LD may further include an insulating film 14. However, according to an embodiment of the present invention, the insulating film 14 may be omitted, or the insulating film 14 may be provided so as to cover only some of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13. For example, the insulating film 14 may be provided at a portion other than the two end portions of the light-emitting element LD such that the two end portions of the light-emitting element LD may be exposed.

[0083] For ease of description, Figure 1a and Figure 1b a structure is shown in which a part of the insulating film 14 is removed and the entire side surface of the actual light-emitting element LD may be surrounded by the insulating film 14.

[0084] According to an embodiment of the present invention, the insulating film 14 may include a transparent insulating material. For example, the insulating film 14 may include at least one or more insulating materials such as SiO2, Si3N4, Al2O3, and TiO2, but is not limited thereto, and may include various materials having insulating properties.

[0085] The insulating film 14 may prevent an electrical short circuit that may occur when the active layer 12 contacts a conductive material other than the first semiconductor layer 11 and the second semiconductor layer 13. Additionally, by forming the insulating film 14, surface defects of the light-emitting element LD may be minimized, thereby improving the lifespan and efficiency. Additionally, when a plurality of light-emitting elements LD are closely arranged, the insulating film 14 may prevent an undesired short circuit that may occur between the respective light-emitting elements LD.

[0086] The type, structure, and shape of the light-emitting element LD according to an embodiment of the present invention may be variously changed.

[0087] Figure 2 A top plan view of a display device according to an embodiment is shown.

[0088] Referring to Figures 1a to 2, the display device 1000 may include a substrate SUB and a plurality of pixels PXL disposed on the substrate SUB. Additionally, the display device 1000 (or the substrate SUB) includes a display area DA in which a plurality of pixels PXL are arranged to display an image and a non-display area NDA other than the display area DA.

[0089] The display area DA may be an area in which pixels PXL are provided. The non-display area NDA may be an area in which drivers SDV and DDV for driving the pixels PXL and various lines for connecting the pixels PXL and the drivers are provided.

[0090] The display area DA may have various shapes. For example, the display area DA may be provided in various shapes such as a closed polygon including sides formed by straight lines, a circle including sides formed by curves, an ellipse, etc., a semi-circle including sides formed by straight lines and curves, a semi-ellipse, etc.

[0091] When the display area DA includes a plurality of areas, each area may also be provided in various shapes such as a closed polygon including sides formed by straight lines, a circle including sides formed by curves, an ellipse, etc., a semi-circle including sides formed by straight lines and curves, a semi-ellipse, etc. Additionally, the areas in the plurality of areas may be the same as or different from each other. In an embodiment of the present invention, as an example, the case where the display area DA is provided as a single area having a quadrilateral shape including straight lines will be described.

[0092] The non-display area NDA may be provided on at least one side of the display area DA. In an embodiment of the present invention, the non-display area NDA may surround the display area DA.

[0093] The pixels PXL may be disposed in the display area DA on the substrate SUB. Each of the pixels PXL may include at least one light-emitting element ( Figure 1a LD) connected to a scan line and a data line to be driven by corresponding scan signals and data signals.

[0094] Each of the pixels PXL may emit light of one of red, green, and blue, but is not limited thereto. For example, each of the pixels PXL may emit light of one of cyan, magenta, yellow, and white.

[0095] Specifically, the pixel PXL may include: a first pixel that emits light of a first color; a second pixel that emits a second color different from the first color; and a third pixel that emits a third color different from the first color and the second color. At least one first pixel, second pixel, and third pixel arranged adjacent to each other may constitute a pixel unit capable of emitting light of various colors.

[0096] In some embodiments, the first pixel may be a red pixel that emits red light, the second pixel may be a green pixel that emits green light, and the third pixel may be a blue pixel that emits blue light.

[0097] In an embodiment, each pixel PXL is provided with a light-emitting element that emits light of the same color as each other, but includes different color light conversion layers provided on each light-emitting element to emit light of different colors. In another embodiment, each pixel PXL may include light-emitting elements that emit light of different colors. However, there is no specific limitation on the color, type, and / or number of each pixel PXL.

[0098] A plurality of pixels PXL may be arranged and disposed along a first direction DR1 and a second direction DR2 that intersects the first direction DR1. However, there is no specific limitation on the arrangement form of the pixels PXL, and the pixels PXL may be arranged in various forms.

[0099] The driver provides signals to each pixel PXL through corresponding line portions (not shown), and thus can control the driving of each pixel PXL. In Figure 2 order to facilitate description, the line portions are omitted.

[0100] The driver may include: a scan driver SDV that provides a scan signal to the pixel PXL through a scan line; a data driver DDV that provides a data signal to the pixel PXL through a data line; and a timing controller (not shown). The timing controller may control the scan driver SDV and the data driver DDV. In some embodiments, the display device 1000 may further include a light-emitting driver that provides a light-emitting control signal to the pixel PXL through a light-emitting control line.

[0101] The scan driver SDV may be provided at one side of the substrate SUB and may be arranged along one direction (e.g., the second direction DR2). The scan driver SDV may be mounted on the substrate SUB as a separate component, but is not limited thereto. For example, the scan driver SDV may be directly formed on the substrate SUB. Additionally, the scan driver SDV may be located outside the substrate SUB and may be connected to each pixel PXL through a separate connection member. A plurality of scan drivers SDV may be provided at the same side of the substrate SUB, but is not limited thereto, and may be provided at different sides of the substrate SUB.

[0102] The data driver DDV may be provided at one side of the substrate SUB and may be arranged along a direction that intersects the direction in which the above-described scan driver SDV extends (e.g., the first direction DR1). The data driver DDV may be mounted on the substrate SUB as a separate component, or may be located outside the substrate SUB and connected to each pixel PXL through a separate connection member.

[0103] In an embodiment, each of the pixels PXL may be configured as an active pixel. However, the type, structure, and / or driving method of the pixel PXL applicable to the present invention are not particularly limited.

[0104] Meanwhile, the display device 1000 may include alignment lines ACL1, ACL2, GNDL1, and GNDL2 that are disposed on the substrate SUB and align (or dispose) the light-emitting elements LD of the respective pixels PXL. The alignment lines ACL1, ACL2, GNDL1, and GNDL2 may include alternating current voltage lines ACL1 and ACL2 and ground voltage lines GNDL1 and GNDL2.

[0105] The alternating current voltage lines ACL1 and ACL2 and the ground voltage lines GNDL1 and GNDL2 may be alternately disposed. For example, the first alternating current voltage line ACL1, the first ground voltage line GNDL1, the second alternating current voltage line ACL2, and the second ground voltage line GNDL2 may be sequentially arranged. Each of the alternating current voltage lines ACL1 and ACL2 and the ground voltage lines GNDL1 and GNDL2 may include a main line extending along a first direction DR1 and a plurality of branch lines branching from the main line to extend along a second direction DR2.

[0106] The pixels PXL may be disposed between the plurality of branch lines of the alternating current voltage lines ACL1 and ACL2 and the plurality of branch lines of the ground voltage lines GNDL1 and GNDL2. In the process of aligning the light-emitting elements LD on the substrate SUB, an alternating current voltage and a ground voltage may be respectively applied to each of the alternating current voltage lines ACL1 and ACL2 and the ground voltage lines GNDL1 and GNDL2. Dipoles are induced according to the electric field formed between the alternating current voltage lines ACL1 and ACL2 and the ground voltage lines GNDL1 and GNDL2, such that the light-emitting elements LD may be aligned in the respective pixels PXL by electrophoresis force.

[0107] The alignment lines ACL1, ACL2, GNDL1, and GNDL2 may be connected to each other and extended during the process of aligning the light-emitting elements LD, but after the light-emitting elements LD are aligned, at least some of the alignment lines ACL1, ACL2, GNDL1, and GNDL2 may be separated. For example, the alternating current voltage lines ACL1 and ACL2 or the ground voltage lines GNDL1 and GNDL2 may be separated from each other by a size (or length) corresponding to each of the pixels PXL. The process of aligning the light-emitting elements LD will be described in detail later with reference to Figures 13 to 18 The process of aligning the light-emitting elements LD will be described in detail.

[0108] Figures 3a to 3c Circuit diagrams of pixels according to embodiments are respectively shown. In particular, Figures 3a to 3c An example of a pixel constituting an active type light-emitting display panel is shown.

[0109] Refer to Figures 1a to 3a , the pixel PXL may include at least one light-emitting element LD and a driving circuit DC connected to the light-emitting element LD to drive the light-emitting element LD.

[0110] The first electrode (e.g., an anode electrode) of the light-emitting element LD may be connected to a second driving power supply VDD via the driving circuit DC, and the second electrode (e.g., a cathode electrode) of the light-emitting element LD may be connected to a first driving power supply VSS. The light-emitting element LD may emit light having a brightness corresponding to the amount of driving current controlled by the driving circuit DC.

[0111] Although only one light-emitting element LD is shown in Figure 3a , this is an exemplary configuration, and an actual pixel PXL may include a plurality of light-emitting elements LD. The plurality of light-emitting elements LD may be connected in parallel with each other and / or in series.

[0112] The first driving power supply VSS and the second driving power supply VDD may have different potentials. For example, the potential of the second driving power supply VDD may be higher than the potential of the first driving power supply VSS by the threshold voltage of the light-emitting element LD or more. That is, the voltage applied by the second driving power supply VDD may be greater than the voltage applied by the first driving power supply VSS.

[0113] According to an embodiment of the present invention, the driving circuit DC may include a first transistor M1, a second transistor M2, and a storage capacitor Cst.

[0114] The first electrode of the first transistor M1 (driving transistor) may be connected to the second driving power supply VDD, and its second electrode may be electrically connected to the first electrode (e.g., an anode electrode) of the light-emitting element LD. The gate electrode of the first transistor M1 may be connected to a first node N1. The first transistor M1 may control the amount of driving current supplied to the light-emitting element LD in response to the voltage of the first node N1.

[0115] The first electrode of the second transistor M2 (switching transistor) may be connected to the data line DL, and its second electrode may be connected to the first node N1. Here, the first electrode and the second electrode of the second transistor M2 may be different electrodes. For example, when the first electrode is a source electrode, the second electrode may be a drain electrode. The gate electrode of the second transistor M2 may be connected to the scan line SL.

[0116] When a scan signal that supplies a voltage (e.g., a gate turn-on voltage) capable of turning on the second transistor M2 is supplied from the scan line SL, the second transistor M2 turns on, enabling the second transistor M2 to electrically connect the data line DL and the first node N1. In this case, the data signal of the corresponding frame is supplied to the data line DL, and thus, the data signal can be transmitted to the first node N1. The data signal transmitted to the first node N1 can be stored in the storage capacitor Cst.

[0117] One electrode of the storage capacitor Cst can be connected to the second driving power supply VDD, and its other electrode can be connected to the first node N1. The storage capacitor Cst can be charged with a voltage corresponding to the data signal supplied to the first node N1 and can hold the charged voltage until the data signal of the next frame is supplied.

[0118] For better understanding and convenience of description, Figure 3a a relatively simple driving circuit DC is shown, which includes: a second transistor M2 for transmitting a data signal to each pixel PXL; a storage capacitor Cst for storing the data signal; and a first transistor M1 for supplying a driving current corresponding to the data signal to the light-emitting element LD.

[0119] However, the present invention is not limited thereto, and the structure of the driving circuit DC can be variously changed. For example, the driving circuit DC additionally includes various transistors (such as a compensation transistor for compensating the threshold voltage of the first transistor M1, an initialization transistor for initializing the first node N1, and / or a light-emitting control transistor for controlling the light-emitting time of the light-emitting element LD) and other circuit elements (such as a boosting capacitor for boosting the voltage of the first node N1).

[0120] In addition, the transistors included in the driving circuit DC (e.g., both the first transistor M1 and the second transistor M2) are shown as P-type transistors in Figure 3a However, the present invention is not limited thereto. That is, at least one of the first transistor M1 and the second transistor M2 included in the driving circuit DC can be changed to an N-type transistor.

[0121] For example, as shown in Figure 3b the first transistor M1 and the second transistor M2 of the driving circuit DC can be implemented as N-type transistors. Except for some changes in the connection positions of the constituent elements due to the change in the transistor type, Figure 3b the driving circuit DC shown in Figure 3a is similar in structure or operation to the driving circuit DC shown in

[0122] In addition, as another example, referring to Figure 3c, the pixel PXL may further include a third transistor M3 (sensing transistor).

[0123] The gate electrode of the third transistor M3 may be connected to the sensing signal line SSL. One electrode of the third transistor M3 may be connected to the sensing line SENL, and the other electrode of the third transistor M3 may be connected to the anode electrode of the light-emitting element LD. The third transistor M3 may transmit the voltage value at the anode electrode of the light-emitting element LD to the sensing line SENL according to the sensing signal supplied to the sensing signal line SSL during the sensing period. The voltage transmitted through the sensing line SENL may be provided to an external circuit (e.g., a timing controller), and the external circuit may extract the characteristic information (e.g., the threshold voltage of the first transistor M1) of the pixel PXL based on the provided voltage. The extracted characteristic information may be used to convert the image data so as to compensate for the characteristic deviation of the pixel PXL.

[0124] Figure 4 A circuit diagram of a pixel according to another embodiment is shown.

[0125] Referring to Figure 4 , a pixel PXL according to another embodiment of the present invention may include a light-emitting element LD, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cst.

[0126] The first electrode (e.g., anode electrode) of the light-emitting element LD may be connected to the first transistor T1 via the sixth transistor T6, and the second electrode (e.g., cathode electrode) of the light-emitting element LD may be connected to the first driving power supply VSS. The light-emitting element LD may emit light having a predetermined brightness corresponding to the amount of the driving current supplied from the first transistor T1.

[0127] One electrode of the first transistor T1 (driving transistor) may be connected to the second driving power supply VDD via the fifth transistor T5, and the other electrode of the first transistor T1 may be connected to the first electrode of the light-emitting element LD via the sixth transistor T6. The first transistor T1 may control the amount of current flowing from the second driving power supply VDD through the light-emitting element LD to the first driving power supply VSS in response to the voltage of the first node N1 serving as the gate electrode of the first transistor T1.

[0128] The second transistor T2 (switching transistor) may be connected between the data line DL and one electrode of the first transistor T1. In addition, the gate electrode of the second transistor T2 may be connected to the first scan line SL. The second transistor T2 may be turned on when a scan signal having a gate-on voltage is supplied to the first scan line SL to electrically connect the data line DL and one electrode of the first transistor T1.

[0129] The third transistor T3 may be connected between the other electrode of the first transistor T1 and the first node N1. Additionally, the gate electrode of the third transistor T3 may be connected to the first scan line SL. The third transistor T3 may be turned on when a scan signal having a gate-on voltage is supplied to the first scan line SL to electrically connect the other electrode of the first transistor T1 and the first node N1.

[0130] The fourth transistor T4 may be connected between the first node N1 and the initialization power supply Vint. Additionally, the gate electrode of the fourth transistor T4 may be connected to the second scan line SL-1. The fourth transistor T4 may be turned on when a scan signal having a gate-on voltage is supplied to the second scan line SL-1 to supply the voltage of the initialization power supply Vint to the first node N1. Here, the initialization power supply Vint may be set to be lower than the voltage of the data signal. The scan signal supplied to the second scan line SL-1 may have the same waveform as the scan signal supplied to the first scan line of the previous-stage pixel.

[0131] The fifth transistor T5 may be connected between the second driving power supply VDD and one electrode of the first transistor T1. The gate electrode of the fifth transistor T5 may be connected to the emission control line EL. The fifth transistor T5 may be turned on when an emission control signal having a gate-on voltage is supplied to the emission control line EL and may be turned off in other cases.

[0132] The sixth transistor T6 may be connected between the other electrode of the first transistor T1 and the first electrode of the light-emitting element LD. The gate electrode of the sixth transistor T6 may be connected to the emission control line EL. The sixth transistor T6 may be turned on when an emission control signal having a gate-on voltage is supplied to the emission control line EL and may be turned off in other cases.

[0133] The seventh transistor T7 may be connected between the initialization power supply Vint and the first electrode (e.g., the anode electrode) of the light-emitting element LD. Additionally, the gate electrode of the seventh transistor T7 may be connected to the third scan line SL+1. The seventh transistor T7 may be turned on when a scan signal having a gate-on voltage is supplied to the third scan line SL+1 to supply the voltage of the initialization power supply Vint to the first electrode of the light-emitting element LD. The scan signal supplied to the third scan line SL+1 may have the same waveform as the scan signal supplied to the first scan line of the next-stage pixel.

[0134] Figure 4This shows a case where the gate electrode of the seventh transistor T7 is connected to the third scan line SL+1. However, the technical concept of the present invention is not limited thereto. For example, in another embodiment of the present invention, the gate electrode of the seventh transistor T7 may be connected to the first scan line SL or the second scan line SL-1. In this case, when a scan signal of a gate turn-on voltage is supplied to the first scan line SL or the second scan line SL-1, the voltage of the initialization power supply Vint may be supplied to the anode electrode of the light-emitting element LD via the seventh transistor T7.

[0135] The storage capacitor Cst may be connected between the second driving power supply VDD and the first node N1. A data signal and a voltage corresponding to the threshold voltage of the first transistor T1 may be stored in the storage capacitor Cst.

[0136] Meanwhile, the transistors included in the driving circuit DC (e.g., the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7) are all shown as P-type transistors in Figure 4 but the present invention is not limited thereto. For example, at least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be changed to an N-type transistor.

[0137] Figure 5 This shows a plan view of a pixel according to an embodiment. Figure 6 This shows a cross-sectional view taken along line A-A' of Figure 5 This shows a cross-sectional view taken along line A-A' of Figures 7 to 11 This shows a cross-sectional view of a pixel according to various embodiments, and shows a cross-sectional view taken along line A-A' of Figure 5 This shows a cross-sectional view taken along line A-A' of

[0138] For better understanding and convenience of description, hereinafter, each of the electrodes is simplified and shown as a single electrode layer, but the present invention is not limited thereto, and each of the electrodes may be constructed of multiple electrode layers. Additionally, in the embodiments of the present invention, "formed and / or provided on the same layer" may mean formed in the same process and formed of the same material.

[0139] Additionally, in Figure 5 for better understanding and convenience of description, the illustration of the transistors connected to the light-emitting element and the signal lines connected to the transistors is omitted.

[0140] Referring to Figure 5 and Figure 6 a display device according to an embodiment of the present invention may include a substrate SUB and a pixel PXL1 provided on the substrate SUB.

[0141] The substrate SUB can be a rigid substrate or a flexible substrate, and there are no specific restrictions on its material or physical properties. For example, the substrate SUB can be a rigid substrate made of glass or tempered glass, or a flexible substrate made of a film made of plastic or metal. Additionally, the substrate SUB can be a transparent substrate, but is not limited thereto. For example, the substrate SUB can be a translucent substrate, an opaque substrate, or a reflective substrate.

[0142] Figure 5 The pixel PXL1 shown in Figure 2 can be one of the pixels PXL. A pixel PXL1 can be the smallest unit that emits light of a predetermined color. As described above, pixels that emit light of different colors can constitute a pixel unit. Hereinafter, the pixel PXL1 can represent a pixel or a sub-pixel.

[0143] The pixel PXL1 can include a pixel circuit layer PCL provided on the substrate SUB and a display element layer DPL provided on the pixel circuit layer PCL.

[0144] The pixel circuit layer PCL can include a plurality of circuit elements that constitute a driving circuit ( Figure 3a the DC in Figure 6 of the pixel PXL). An exemplary cross-sectional structure in which the pixel circuit layer PCL includes a transistor TR is shown. In this case, the transistor TR can be Figures 3a to 3c the first transistor M1. However, the structure of the pixel circuit layer PCL is not limited thereto, and the pixel circuit layer PCL can also include circuit elements located in a region different from the region of the transistor TR.

[0145] The transistors included in the pixel circuit layer PCL can have substantially the same or similar cross-sectional structures. Additionally, the structure of each transistor is not limited to Figure 6 the structure shown in

[0146] The pixel circuit layer PCL can include multiple layers. For example, the pixel circuit layer PCL can include a buffer layer BFL, a gate insulating layer GI, an interlayer insulating layer IL, a first passivation layer VIA1, and a second passivation layer VIA2 that are sequentially stacked on the substrate SUB. Each of the above layers can be an insulating layer including an organic insulating material or an inorganic insulating material. Additionally, the pixel circuit layer PCL can include a transistor TR, a bypass power line (also referred to as a "conductive line") BVL, and a first capacitor electrode CE1.

[0147] The buffer layer BFL can prevent impurities from diffusing into each circuit element. The buffer layer BFL can be set as a single-layer film, but can also be set as a multi-layer film with at least two layers. When the buffer layer BFL is set as a multi-layer film, each layer can be made of the same material or different materials. The buffer layer BFL can be omitted according to the material of the substrate SUB, process conditions, etc.

[0148] The transistor TR can be disposed on the buffer layer BFL. The transistor TR can include a semiconductor pattern ACT, a gate electrode GE, a first transistor electrode TET1, and a second transistor electrode TET2.

[0149] The semiconductor pattern ACT can be disposed between the buffer layer BFL and the gate insulating layer GI. When the pixel circuit layer PCL does not include the buffer layer BFL, the semiconductor pattern ACT can be disposed between the substrate SUB and the gate insulating layer GI. The semiconductor pattern ACT can include: a first region in contact with the first transistor electrode TET1; a second region connected to the second transistor electrode TET2; and a channel region located between the first region and the second region. One of the first region and the second region can be a source region, and the other of the first region and the second region can be a drain region.

[0150] The semiconductor pattern ACT can be a semiconductor pattern made of polysilicon, amorphous silicon, oxide semiconductor, etc. Additionally, the channel region of the semiconductor pattern ACT can be an intrinsic semiconductor (such as a semiconductor pattern not doped with impurities), and each of the first region and the second region of the semiconductor pattern ACT can be a semiconductor pattern doped with a predetermined impurity.

[0151] The gate electrode GE can be disposed between the gate insulating layer GI and the interlayer insulating layer IL, and can overlap at least a part of the semiconductor pattern ACT. The gate electrode GE can be insulated from the semiconductor pattern ACT through the gate insulating layer GI.

[0152] The first transistor electrode TET1 and the second transistor electrode TET2 can be disposed on the interlayer insulating layer IL. The first transistor electrode TET1 and the second transistor electrode TET2 can be electrically connected to the semiconductor pattern ACT. For example, the first transistor electrode TET1 and the second transistor electrode TET2 can respectively contact the first region and the second region of the semiconductor pattern ACT through contact holes passing through the gate insulating layer GI and the interlayer insulating layer IL.

[0153] The first transistor electrode TET1 can be connected to the second electrode RFE2 through a contact hole CTA that passes through the first passivation layer VIA1 and the second passivation layer VIA2. In another embodiment, a separate connection member can be provided between the first transistor electrode TET1 and the second electrode RFE2. In this case, the first transistor electrode TET1 can be connected to the connection member through a contact hole, and the connection member can be connected to the second electrode RFE2 through another contact hole. In this case, the position where the connection member is provided can be between the first passivation layer VIA1 and the second passivation layer VIA2, but is not limited thereto.

[0154] The second electrode RFE2 can receive a driving current through the first transistor electrode TET1.

[0155] The second transistor electrode TET2 can be connected to the second power line PL2. The second power line PL2 can be a power line connected to the second driving power supply ( Figure 3a VDD in). That is, the voltage of the second driving power supply VDD can be provided to the transistor TR through the second power line PL2. A passivation layer (e.g., the second passivation layer VIA2) can be provided between the second power line PL2 and the second electrode RFE2. Although Figure 5 not shown in, the second power line PL2 can extend along the second direction DR2 in a plan view. However, the second power line PL2 is not limited thereto and can extend along the first direction DR1.

[0156] In addition, the pixel circuit layer PCL can include a bypass power line BVL and a first capacitor electrode CE1 that are provided to be spaced apart from the transistor TR.

[0157] The bypass power line BVL can be a power line formed on the same layer as the gate electrode GE of the transistor TR described above. The bypass power line BVL can be formed in a region that does not overlap with the light-emitting region EA in a plan view. The light-emitting region EA can be a region where a light-emitting element LD is provided to emit light. The bypass power line BVL can be formed by extending along the first direction DR1 in a region that does not overlap with the light-emitting region EA in a plan view.

[0158] In addition, the bypass power line BVL can not overlap with the gate electrodes of the transistors included in the pixel circuit layer PCL. For example, the bypass power line BVL can not overlap with the gate electrode GE of the transistor TR.

[0159] The first capacitor electrode CE1 can be provided on the bypass power line BVL. The first capacitor electrode CE1 can overlap with the bypass power line BVL. For example, the first capacitor electrode CE1 can be formed to overlap with the bypass power line BVL and extend in the first direction DR1.

[0160] At least one insulating layer or passivation layer may be provided between the bypass power line BVL and the first capacitor electrode CE1. For example, the interlayer insulating layer IL and the first passivation layer VIA1 may be provided between the bypass power line BVL and the first capacitor electrode CE1.

[0161] The first capacitor electrode CE1 may contact the bypass power line BVL through a contact hole CTB. Thus, the voltage applied to the bypass power line BVL can be transmitted to the first capacitor electrode CE1.

[0162] At least a part of the first capacitor electrode CE1 may overlap with the first electrode RFE1 provided on the first capacitor electrode CE1. The area where the first capacitor electrode CE1 overlaps with the first electrode RFE1 may be the first capacitor region CA1. The first capacitor region CA1 may not overlap with the light-emitting region EA where the light-emitting element LD is provided.

[0163] At least one passivation layer or insulating layer may be provided between the first capacitor electrode CE1 and the first electrode RFE1. For example, the second passivation layer VIA2 may be provided between the first capacitor electrode CE1 and the first electrode RFE1. That is, in the first capacitor region CA1, the first capacitor electrode CE1 and the first electrode RFE1 may together with the second passivation layer VIA2 disposed therebetween form the first capacitor C1.

[0164] In the process of aligning the light-emitting element LD on the substrate SUB, a predetermined DC voltage may be supplied to the bypass power line BVL and the first electrode RFE1 respectively. The DC voltage supplied to the bypass power line BVL can be transmitted to the first capacitor electrode CE1. As described above, the first capacitor electrode CE1 and the first electrode RFE1 may form the first capacitor C1, and the first capacitor electrode CE1 may receive the noise component voltage (e.g., AC voltage component) of the voltage supplied to the first electrode RFE1 through the first capacitor C1. Thus, the noise component voltage (AC voltage component) of the DC voltage supplied to the first electrode RFE1 can be removed. In this regard, it will be described in detail later with reference to Figures 13 to 18 described in detail.

[0165] Meanwhile, the arrangement of the first capacitor electrode CE1 is not limited to the above description. For example, Figure 7 the pixel PXL1a of may include the first capacitor electrode CE1a provided between the interlayer insulating layer IL and the first passivation layer VIA1.

[0166] The first capacitor electrode CE1a can be connected to the bypass power line BVL through a contact hole CTB that penetrates the interlayer insulating layer IL. In the first capacitor region CA1, the first capacitor electrode CE1a and the first electrode RFE1 can together form the first capacitor C1a with the first passivation layer VIA1 and the second passivation layer VIA2 disposed therebetween.

[0167] As another example, Figure 8 the pixel PXL1b may not include a separate electrode provided between the bypass power line BVL and the first electrode RFE1. In this case, the bypass power line BVL can be used as the first capacitor electrode CE1b in the region overlapping with the first electrode RFE1. That is, in the first capacitor region CA1, the bypass power line BVL (or the first capacitor electrode CE1b) and the first electrode RFE1 can together form the first capacitor C1b with the interlayer insulating layer IL, the first passivation layer VIA1, and the second passivation layer VIA2 disposed therebetween.

[0168] Figure 7 the first capacitor electrode CE1a described in the embodiment of Figure 8 and the first capacitor electrode CE1b described in the embodiment of

[0169] Both can be applied to the following embodiments.

[0170] Meanwhile, in the above embodiment, the pixel circuit layer PCL included in the pixel PXL1 is illustrated as being disposed below the display element layer DPL so as to overlap the display element layer DPL when viewed from a cross-sectional view, but the present invention is not limited thereto. In some embodiments, the pixel circuit layer PCL can be disposed in a region that is disposed below the display element layer DPL but does not overlap the display element layer DPL.

[0170] Next, the display element layer DPL will be described. The display element layer DPL can be disposed on the pixel circuit layer PCL (or the second passivation layer VIA2) and can include a plurality of light-emitting elements LD.

[0171] Specifically, the display element layer DPL can include a first bank BNK1 and a second bank BNK2 disposed on the pixel circuit layer PCL, a first electrode RFE1 and a second electrode RFE2, a first insulating layer INS1, a light-emitting element LD, a fixing layer INSA, an insulating pattern INSP, a third electrode CTE1 and a fourth electrode CTE2, and a second insulating layer INS2. In some embodiments, the pixel PXL1 may further include a partition wall provided at the peripheral portion of the light-emitting element LD along the boundary of the pixel.

[0172] The first bank BNK1 and the second bank BNK2 may be disposed on the pixel circuit layer PCL. A space in which the light-emitting element LD is disposed may be provided between the first bank BNK1 and the second bank BNK2. In an embodiment, the first bank BNK1 and the second bank BNK2 may be spaced apart from each other along a first direction DR1 by a distance greater than the length of the light-emitting element LD. The first bank BNK1 and the second bank BNK2 may be disposed in the same layer as each other and may have the same height as each other, but is not limited thereto. Additionally, the first bank BNK1 and the second bank BNK2 may extend along a second direction DR2 that intersects the first direction DR1.

[0173] The first bank BNK1 and the second bank BNK2 may include an organic insulating film made of an organic material or an inorganic insulating film made of an inorganic material, but the materials of the first bank BNK1 and the second bank BNK2 are not limited thereto. Additionally, the first bank BNK1 and the second bank BNK2 may be formed of a single layer, but is not limited thereto, and may be formed of multiple layers. In this case, the first bank BNK1 and the second bank BNK2 may have a structure in which at least one organic insulating film and at least one inorganic insulating film are stacked.

[0174] Each of the first bank BNK1 and the second bank BNK2 may have a trapezoidal shape having sides that are inclined at a predetermined angle, but the shapes of the first bank BNK1 and the second bank BNK2 are not limited thereto, and they may have various shapes such as a semi-elliptical shape, a circular shape, and a quadrilateral shape.

[0175] The first electrode RFE1 and the second electrode RFE2 may be respectively disposed on the corresponding first bank BNK1 and second bank BNK2. For example, the first electrode RFE1 may be disposed on the first bank BNK1, the second electrode RFE2 may be disposed on the second bank BNK2, and they may be disposed to be spaced apart from each other. The first electrode RFE1 and the second electrode RFE2 may be spaced apart from each other along the first direction DR1 by a predetermined distance. Additionally, the first electrode RFE1 and the second electrode RFE2 may extend along the second direction DR2.

[0176] When the pixel PXL1 includes the first bank BNK1 and the second bank BNK2, the light-emitting element LD is stably disposed in the space in which the first bank BNK1 and the second bank BNK2 are spaced apart from each other, so that the reliability of the display device and the yield in the manufacturing process of the display device can be improved.

[0177] The first electrode RFE1 and the second electrode RFE2 can be set to have a substantially uniform thickness along the surfaces of the first bank BNK1 and the second bank BNK2, and the first electrode RFE1 and the second electrode RFE2 can be correspondingly set to the shapes of the first bank BNK1 and the second bank BNK2. For example, the first electrode RFE1 can have a shape corresponding to the slope of the first bank BNK1, and the second electrode RFE2 can have a shape corresponding to the slope of the second bank BNK2.

[0178] The first electrode RFE1 and the second electrode RFE2 can be disposed on the same plane as each other and can have the same height. When the first electrode RFE1 and the second electrode RFE2 have the same height, the light-emitting elements LD can be more stably connected to the first electrode RFE1 and the second electrode RFE2, respectively.

[0179] The first electrode RFE1 and the second electrode RFE2 can be made of a conductive material. The conductive material can include metals such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti or alloys thereof, but is not limited thereto.

[0180] In addition, the first electrode RFE1 and the second electrode RFE2 can be formed as a single-layer film, but are not limited thereto, and can be formed as a multi-layer film. For example, the first electrode RFE1 and the second electrode RFE2 can further include a cladding layer (not shown) made of a transparent conductive material. The cladding layer is provided to cover the first electrode RFE1 and the second electrode RFE2, thereby preventing damage to the first electrode RFE1 and the second electrode RFE2 that may occur during the manufacturing process of the display device.

[0181] Here, the materials of the first electrode RFE1 and the second electrode RFE2 are not limited to the above materials. For example, the first electrode RFE1 and the second electrode RFE2 can include a conductive material having a constant reflectivity. When the first electrode RFE1 and the second electrode RFE2 are made of a conductive material having a constant reflectivity, the light emitted from the two ends of the light-emitting element LD is reflected by the first electrode RFE1 and the second electrode RFE2 to travel in the display direction (e.g., the third direction DR3).

[0182] In particular, the first electrode RFE1 and the second electrode RFE2 can have shapes corresponding to the shapes of the first bank BNK1 and the second bank BNK2 and can have a predetermined angle with respect to the substrate SUB. The light emitted from the two ends of each of the light-emitting elements LD can be reflected by the first electrode RFE1 and the second electrode RFE2 to further travel in the third direction DR3. Therefore, the light output efficiency of the display device can be improved.

[0183] In addition, as Figure 5As shown in [figure], the first electrode RFE1 can be connected to the first connection line CNL1 through the first connection electrode CNE1. The first connection line CNL1 can be a line connected to the first power line PL1. Although not shown in the drawings, the first power line PL1 can be located on a different layer from the first connection line CNL1 and connected to the first connection line CNL1 through a separate connection member.

[0184] The first power line PL1 can be connected to the first driving power supply ( Figure 3a VSS in [figure]). That is, the voltage of the first driving power supply VSS can be provided to the first electrode RFE1 through the first power line PL1 (or the first connection line CNL1). The voltage of the first driving power supply VSS can be provided to the first end portion EP1 of the light emitting element LD through the first electrode RFE1.

[0185] At the same time, the first connection line CNL1 can extend along the second direction DR2 and can be commonly connected to other pixels.

[0186] The first connection electrode CNE1 can be disposed between the first electrode RFE1 and the first connection line CNL1 along the first direction DR1. At least a part of the first connection electrode CNE1 can be stacked with the first capacitor electrode CE1 disposed below the first connection electrode CNE1.

[0187] In an embodiment, the above-mentioned first electrode RFE1, first connection electrode CNE1, and first connection line CNL1 can be integrally formed and can be formed simultaneously in the same process, but this is not limited thereto.

[0188] As described above, the second electrode RFE2 can be connected to the first transistor electrode TET1 of the transistor TR through the contact hole CTA. The second electrode RFE2 can receive the driving current from the transistor TR and can transmit the driving current to the second end portion EP2 of the light emitting element LD. The light emitting element LD can emit light of a predetermined brightness in response to the driving current (or driving voltage) provided from the first electrode RFE1 and the second electrode RFE2.

[0189] One of the first electrode RFE1 and the second electrode RFE2 can be an anode electrode, and the other of the first electrode RFE1 and the second electrode RFE2 can be a cathode electrode. For example, the first electrode RFE1 can be a cathode electrode and the second electrode RFE2 can be an anode electrode, but the present invention is not limited thereto.

[0190] The first insulating layer INS1 may be disposed on the first electrode RFE1 and the second electrode RFE2. The first insulating layer INS1 may be entirely disposed on the substrate SUB to cover the first bank BNK1 and the second bank BNK2, as well as the first electrode RFE1 and the second electrode RFE2 as described above. Additionally, the first insulating layer INS1 may be disposed along the surface of the substrate SUB where the first bank BNK1, the second bank BNK2, the first electrode RFE1, and the second electrode RFE2 are not provided.

[0191] In an embodiment, the first insulating layer INS1 may be an inorganic insulating layer made of an inorganic material. In this case, the first insulating layer INS1 may be disposed to have a substantially uniform thickness along the surface of the substrate SUB and the surfaces of the first electrode RFE1 and the second electrode RFE2. In an embodiment, the first insulating layer INS1 in the region where the light-emitting element LD is disposed is formed to be substantially flat so that a space where the light-emitting element LD is stably disposed can be provided. In another embodiment, at least a partially empty space may be formed or a step may occur between the first insulating layer INS1 and the light-emitting element LD disposed on the first insulating layer INS1.

[0192] Meanwhile, the first insulating layer INS1 may include a first opening OP1 and a second opening OP2. The first opening OP1 and the second opening OP2 may expose at least a portion of the first electrode RFE1 and the second electrode RFE2.

[0193] The first opening OP1 and the second opening OP2 may be formed to overlap the corresponding first electrode RFE1 and second electrode RFE2, respectively. For example, the first opening OP1 may be formed to overlap the first electrode RFE1, and the second opening OP2 may be formed to overlap the second electrode RFE2.

[0194] The first opening OP1 and the second opening OP2 may have a thickness and / or depth corresponding to the thickness of the first insulating layer INS1. That is, the first opening OP1 and the second opening OP2 may completely penetrate the first insulating layer INS1 in the corresponding regions. Thus, the first electrode RFE1 and the second electrode RFE2 may be exposed to the outside to contact the third electrode CTE1 and the fourth electrode CTE2 to be described later.

[0195] The light-emitting element LD may be disposed on the first insulating layer INS1. The light-emitting element LD may be disposed in the space provided by the first bank BNK1 and the second bank BNK2 and may be electrically connected between the first electrode RFE1 and the second electrode RFE2. For example, the first end portion EP1 of the light-emitting element LD may be electrically connected to the first electrode RFE1, and the second end portion EP2 of the light-emitting element LD may be electrically connected to the second electrode RFE2.

[0196] A fixing layer INSA for stably supporting and fixing a light-emitting element LD may be disposed on the light-emitting element LD. The fixing layer INSA may be an inorganic insulating film including an inorganic material or an organic insulating film including an organic material. The fixing layer INSA may be disposed to fill a space between the light-emitting element LD and a second passivation layer VIA2. The fixing layer INSA may cover at least a portion of the outer peripheral surface of each of the light-emitting elements LD, and may be formed to expose a first end portion EP1 and a second end portion EP2 of the light-emitting element LD. Accordingly, the fixing layer INSA stably supports and fixes the light-emitting element LD, thereby preventing the light-emitting element LD from being separated from the display element layer DPL. The fixing layer INSA may be omitted according to the process conditions of the display element layer DPL.

[0197] In some embodiments, when the fixing layer INSA includes an organic insulating film made of an organic material and when an empty space is formed between the light-emitting element LD and a first insulating layer INS1, as Figure 9 shown, the fixing layer INSA' may fill the space between the light-emitting element LD and the first insulating layer INS1 and may support the light-emitting element LD. Alternatively, when the fixing layer INSA includes an inorganic insulating film made of an inorganic material, as Figure 10 shown, the fixing layer INSA” may cover at least a portion of the outer peripheral surface of the light-emitting element LD, and an air layer AIR may be at least partially formed between the light-emitting element LD and the first insulating layer INS1.

[0198] A third electrode CTE1 (or a first contact electrode) and a fourth electrode CTE2 (or a second contact electrode) may be disposed on the first insulating layer INS1, the light-emitting element LD, and the fixing layer INSA. Additionally, an insulating pattern INSP may be disposed between the third electrode CTE1 and the fourth electrode CTE2.

[0199] The third electrode CTE1 and the fourth electrode CTE2 may contact one of the two end portions of each light-emitting element LD. For example, the third electrode CTE1 may contact the first end portion EP1 of each light-emitting element LD, and the fourth electrode CTE2 may contact the second end portion EP2 of each light-emitting element LD.

[0200] The third electrode CTE1 may cover the first electrode RFE1 and may be superimposed on the first electrode RFE1 in a plan view. The third electrode CTE1 may be electrically connected to the first electrode RFE1 through a first opening OP1 of the first insulating layer INS1. That is, the third electrode CTE1 may contact the first end portion EP1 of the light-emitting element LD and the first electrode RFE1.

[0201] The fourth electrode CTE2 may cover the second electrode RFE2 and may be superposed on the second electrode RFE2 when observed in a plan view. The fourth electrode CTE2 may be electrically connected to the second electrode RFE2 through a second opening OP2 of the first insulating layer INS1. That is, the fourth electrode CTE2 may contact the second end portion EP2 of the light-emitting element LD and the second electrode RFE2.

[0202] Each of the third electrode CTE1 and the fourth electrode CTE2 may be made of a transparent conductive material. For example, the transparent conductive material may include indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), etc. When the third electrode CTE1 and the fourth electrode CTE2 are made of a transparent conductive material, light loss may be reduced when the light emitted from the light-emitting element LD travels in the third direction DR3. The materials of the third electrode CTE1 and the fourth electrode CTE2 are not limited to the above materials.

[0203] The insulating pattern INSP may be provided between the third electrode CTE1 and the fourth electrode CTE2. Specifically, the insulating pattern INSP may include an inorganic insulating film made of an inorganic material. The insulating pattern INSP may be provided to cover one of the third electrode CTE1 and the fourth electrode CTE2, and the other electrode may be provided on the insulating pattern INSP. For example, the insulating pattern INSP may be provided on the fourth electrode CTE2 to cover the fourth electrode CTE2, and the third electrode CTE1 may be provided on the insulating pattern INSP. That is, the third electrode CTE1 and the fourth electrode CTE2 may be electrically separated by the insulating pattern INSP.

[0204] However, the arrangement of the third electrode CTE1 and the fourth electrode CTE2 is not limited thereto, and the third electrode CTE1 and the fourth electrode CTE2 may be provided in the same layer. For example, as Figure 11 shown, the insulating pattern INSP may not be provided between the third electrode CTE1' and the fourth electrode CTE2'. In this case, the third electrode CTE1' and the fourth electrode CTE2' may be formed in the same layer. When the third electrode CTE1' and the fourth electrode CTE2' are formed simultaneously, the manufacturing process of the display device is simplified, and its manufacturing cost can be reduced.

[0205] The second insulating layer INS2 may be disposed on the third electrode CTE1 and the fourth electrode CTE2. The second insulating layer INS2 may be formed on the outermost side of the display element layer DPL to cover other components of the display element layer DPL. The second insulating layer INS2 may also serve as an encapsulation layer that may prevent the first electrode RFE1, the second electrode RFE2, the third electrode CTE1, and the fourth electrode CTE2 and the light emitting element LD from being damaged during the manufacturing process of the display device, and may prevent oxygen and / or moisture from penetrating into the interior of the display element layer DPL.

[0206] The second insulating layer INS2 may be formed as an inorganic insulating film including an inorganic material. The second insulating layer INS2 may be formed as a single layer, but is not limited thereto, and may have a multilayer structure. When the second insulating layer INS2 has a multilayer structure, the second insulating layer INS2 may further include an organic insulating film including an organic material, and may have a multilayer structure in which an organic insulating film and an inorganic insulating film are alternately provided.

[0207] Although not shown in the drawings, in some embodiments, a planarization layer (not shown) may be further provided on the second insulating layer INS2. The planarization layer may alleviate steps caused by various structures provided thereunder. The planarization layer may include an organic insulating film, but is not limited thereto, and may also include an inorganic insulating film.

[0208] Although not shown in the drawings, the pixel PXL1 may further include a partition wall disposed around the light emitting element LD. For example, the partition wall may be disposed to surround the pixel PXL1. The partition wall may be a pixel defining film that defines the light emitting area EA of the pixel PXL1. The partition wall may be configured to include at least one light blocking material and / or a reflective material to prevent a light leakage defect in which light leaks between adjacent pixels. In addition, the partition wall may prevent a solution including the light emitting element LD from leaking to adjacent pixels during a process of aligning the light emitting element LD. The partition wall may be omitted depending on the process conditions of the display device.

[0209] Figure 12 FIG. 2 shows a top plan view of a pixel according to another embodiment. Compared with the above embodiment, Figure 12 The embodiment of is different in that it further includes a fifth electrode RFE3 connected to the second electrode RFE2, and other configurations are substantially the same or similar, so the differences will be mainly described.

[0210] Reference Figure 5 , Figure 6 and Figure 12 , the pixel PXL1c may include a third bank BNK3, a fifth electrode RFE3, and a sixth electrode CTE3.

[0211] The third bank BNK3 may be located between the first electrode RFE1 and the first connection line CNL1. The third bank BNK3 may be disposed on the same layer as the first bank BNK1 and the second bank BNK2, and may be formed simultaneously with the first bank BNK1 and the second bank BNK2. Additionally, the third bank BNK3 may be formed to have the same shape and height as the first bank BNK1 and the second bank BNK2. The third bank BNK3 may be formed to be spaced apart from the first bank BNK1 by a distance greater than the length of the light-emitting element LD in the first direction DR1, and may extend along the second direction DR2.

[0212] The fifth electrode RFE3 may be formed to overlap with the third bank BNK3. The fifth electrode RFE3 may be located between the first electrode RFE1 and the first connection line CNL1. The fifth electrode RFE3 may be formed to be spaced apart from the first electrode RFE1 in the first direction DR1, and may extend along the second direction DR2.

[0213] The fifth electrode RFE3 may be connected to the second electrode RFE2 through the second connection electrode CNE2. The second connection electrode CNE2 may extend along the first direction DR1 between the second electrode RFE2 and the fifth electrode RFE3.

[0214] The second electrode RFE2, the fifth electrode RFE3, and the second connection electrode CNE2 may be formed simultaneously and integrally, but are not limited thereto. Additionally, at least one of the second electrode RFE2, the fifth electrode RFE3, and the second connection electrode CNE2 may be formed simultaneously with at least one of the first electrode RFE1, the first connection line CNL1, and the first connection electrode CNE1, but are not limited thereto. In an embodiment, the first electrode RFE1, the second electrode RFE2, the fifth electrode RFE3, the first connection electrode CNE1, the second connection electrode CNE2, and the first connection line CNL1 may all be formed simultaneously in the same process.

[0215] The light-emitting element LD may be disposed between the first electrode RFE1 and the fifth electrode RFE3. The first end portion EP1 of the light-emitting element LD may be electrically connected to the first electrode RFE1, and the second end portion EP2 of the light-emitting element LD may be electrically connected to the fifth electrode RFE3.

[0216] The sixth electrode CTE3 may be disposed on the fifth electrode RFE3. In a plan view, the sixth electrode CTE3 may cover the fifth electrode RFE3 and may overlap with the fifth electrode RFE3. The sixth electrode CTE3 may contact the second end portion EP2 of the light-emitting element LD and the fifth electrode RFE3.

[0217] The sixth electrode CTE3 may be formed on the same layer as at least one of the third electrode CTE1 and the fourth electrode CTE2. Additionally, the sixth electrode CTE3 may be made of the same material as the third electrode CTE1 and the fourth electrode CTE2.

[0218] As described above, when the fifth electrode RFE3 is further provided between the first electrode RFE1 and the first connection line CNL1, the light-emitting element LD may also be provided between the first electrode RFE1 and the fifth electrode RFE3. That is, since a larger number of light-emitting elements LD can be provided in one pixel PXL1c, the display brightness of the display device including the pixel PXL1c according to the present embodiment can be increased.

[0219] Meanwhile, in the present embodiment, a structure in which only the fifth electrode RFE3 is further provided is exemplarily described. However, in some embodiments, in addition to the fifth electrode RFE3, other electrodes connected to the first electrode RFE1 and the second electrode RFE2 may be formed to further provide a space in which the light-emitting element LD can be provided.

[0220] Figures 13 to 16 A top plan view for explaining a manufacturing method of a display device according to an embodiment is shown. Figure 17 A circuit diagram for explaining a noise removal method of a voltage supplied to a display device according to an embodiment when aligning a light-emitting element is shown. Figure 18 A waveform diagram of the voltage actually supplied to each electrode of a display device according to an embodiment when aligning a light-emitting element is shown. In particular, Figures 13 to 18 is for explaining the light-emitting element in Figure 5 and Figure 6 A diagram of a method for aligning in the structure shown in

[0221] will be schematically described by combining Figure 5 and Figure 6 and Figures 13 to 18 The manufacturing method of a display device according to an embodiment of the present invention will be schematically described with reference to the embodiments described in

[0222] First, as shown in Figure 13 a bypass power line BVL may be formed on a substrate SUB.

[0223] The bypass power line BVL may be formed in a region that does not overlap with a light-emitting region EA where a light-emitting element LD will be provided later. Additionally, the bypass power line BVL may be formed to extend along a first direction DR1 and may be extended to connect to other pixels.

[0224] Next, as shown in Figure 14As shown, a first capacitor electrode CE1 can be formed on a substrate SUB on which a bypass power line BVL is formed.

[0225] The first capacitor electrode CE1 can be formed on top of the bypass power line BVL (e.g., in the third direction DR3). At least a part of the first capacitor electrode CE1 can overlap with the bypass power line BVL. The first capacitor electrode CE1 can also be arranged not to overlap with the light-emitting region EA.

[0226] In addition, the first capacitor electrode CE1 can be electrically connected to the bypass power line BVL through a contact hole CTB. Thus, the bypass power line BVL can transmit the transmitted voltage to the first capacitor electrode CE1 through the contact hole CTB.

[0227] Next, as Figure 15 shown, on the substrate SUB on which the first capacitor electrode CE1 is formed, a first bank BNK1 and a second bank BNK2 can be formed, and a first connection line CNL1, a first electrode RFE1 connected to the first connection line CNL1, and a matrix electrode RFE2' spaced apart from the first electrode RFE1 can be formed.

[0228] The first bank BNK1 and the second bank BNK2 can be formed in the light-emitting region EA and can be spaced apart from each other by a predetermined distance along the first direction DR1 to provide a space in which a light-emitting element LD will be provided later.

[0229] The first connection line CNL1 can extend in a direction intersecting the bypass power line BVL. For example, the first connection line CNL1 can extend along the second direction DR2.

[0230] The first electrode RFE1 can be formed to overlap with the first bank BNK1. In addition, the first electrode RFE1 can be connected to the first connection line CNL1 through a first connection electrode CNE1. In this case, the first connection electrode CNE1 can be formed at a position overlapping with the first capacitor electrode CE1. Thus, in the first capacitor region CA1, the first capacitor electrode CE1 and the first connection electrode CNE1 (or the first electrode RFE1) can form a capacitor.

[0231] The matrix electrode RFE2' can be formed to overlap with the second bank BNK2. In addition, the matrix electrode RFE2' can be formed to be spaced apart from the first electrode RFE1 along a direction opposite to the first direction DR1 and can be formed to extend along the second direction DR2. The matrix electrode RFE2' can extend along the second direction DR2 to be connected to other pixels.

[0232] Before forming the second electrode RFE2, the base electrode RFE2' can be a base conductive layer. After the alignment process of the light-emitting element LD, the base electrode RFE2' can be separated to form the second electrode RFE2.

[0233] Next, as Figure 16 and Figure 17 shown, the light-emitting element LD can be aligned between the first electrode RFE1 and the second electrode RFE2.

[0234] An electric field is formed between the first electrode RFE1 and the second electrode RFE2. Therefore, the light-emitting element LD can be aligned between the first electrode RFE1 and the second electrode RFE2.

[0235] Specifically, the first electrode RFE1 can be connected to the first connection line CNL1 to receive the first voltage VA1. The first voltage VA1 can be a ground voltage provided through the ground voltage lines GNDL1 and GNDL2 described with reference to Figure 2 . The second electrode RFE2 (or the base electrode RFE2') can receive the second voltage VA2. The second voltage VA2 can be an alternating current voltage provided through the alternating current voltage lines ACL1 and ACL2 described with reference to Figure 2 . That is, when a ground voltage is applied to the first electrode RFE1 and an AC voltage is applied to the second electrode RFE2, an electric field can be formed between the first electrode RFE1 and the second electrode RFE2.

[0236] The light-emitting element LD can be prepared in a form dispersed in a predetermined solution and can be supplied to the light-emitting area EA of the pixel PXL by using an inkjet method or the like. For example, the light-emitting element LD can be mixed with a volatile solvent and dropped into the light-emitting area EA. The light-emitting element LD dropped into the light-emitting area EA can be self-aligned by the electric field formed between the first electrode RFE1 and the second electrode RFE2 to be set with a certain directionality. For example, the first end portion EP1 of the light-emitting element LD is set to be adjacent to the first electrode RFE1, and its second end portion EP2 is set to be adjacent to the second electrode RFE2, so that the light-emitting element LD can be set such that its length direction is parallel to the first direction DR1. These light-emitting elements LD can be arranged along the second direction DR2.

[0237] Meanwhile, the alignment lines connected to the first electrode RFE1 (for example, Figure 2 the ground voltage lines GNDL1 and GNDL2 in) and the alignment lines connected to the second electrode RFE2 (for example, the alternating current voltage lines ACL1 and ACL2) can overlap each other in at least a partial area.

[0238] For example, as Figure 2As shown, the branch line of the first AC voltage line ACL1 extends toward the display area DA and may overlap with the main line of the second ground voltage line GNDL1 in at least a partial area. The area where the ground voltage line and the AC voltage line overlap forms a capacitor, and voltage coupling may occur therein.

[0239] In particular, in the process of aligning the light-emitting element LD, a first voltage VA1 as a DC voltage (or ground voltage) may be applied to the first electrode RFE1, and a second voltage VA2 as an AC voltage may be applied to the second electrode RFE2. However, due to the coupling phenomenon between the above lines, a noise component voltage will be included in the DC voltage (or ground voltage) provided to the first electrode RFE1.

[0240] In the display device according to an embodiment of the present invention, a first capacitor C1 is formed by using the first electrode RFE1 and the first capacitor electrode CE1, and a third voltage VA3 different from the first voltage VA1 is applied to the first capacitor electrode CE1, so that the noise component voltage VN (or AC voltage component) of the voltage supplied to the first electrode RFE1 can bypass toward the first capacitor electrode CE1 through the first capacitor C1. Therefore, the noise component voltage VN of the voltage provided to the first electrode RFE1 can be removed, and as in Figure 18 the first waveform 1, a uniform DC voltage (or ground voltage) can be provided.

[0241] Here, the third voltage VA3 supplied to the bypass power line BVL may be a DC voltage similar to the first voltage VA1 supplied to the first electrode RFE1. However, the voltage level of the third voltage VA3 and the voltage level of the first voltage VA1 may be different from each other. Specifically, the third voltage VA3 may be a value between the positive peak voltage and the negative peak voltage of the second voltage VA2. For example, when the first voltage VA1 is a ground voltage and the peak voltage of the second voltage VA2 is -10V and 10V, the third voltage VA3 may be 3V or -3V. However, these voltage values are only examples of this embodiment, and the voltage values of the first voltage VA1, the second voltage VA2, and the third voltage VA3 are not limited thereto.

[0242] As described above, when aligning the light-emitting element LD during the manufacturing process of the display device, the noise (e.g., noise component voltage VN) of the first voltage VA1 supplied to the second electrode of the light-emitting element LD can be removed through the first capacitor C1, or the noise (e.g., noise component voltage VN) of the first voltage VA1 supplied to the second electrode of the light-emitting element LD can be minimized through the first capacitor C1. That is, in the alignment process of the light-emitting element LD, as in Figure 18As shown in the first waveform 1, a constant DC voltage (or ground voltage) is applied to the first electrode RFE1, and the noise component voltage VN can be bypassed toward the first capacitor electrode CE1 (or bypass power line BVL) (see Figure 18 The third waveform in 3).

[0243] Therefore, a uniform electric field can be formed between the first electrode RFE1 and the second electrode RFE2. Therefore, the light emitting element LD can be easily aligned between the first electrode RFE1 and the second electrode RFE2. That is, the alignment characteristics of the light emitting element LD can be improved. In addition, since the light emitting element LD is uniformly aligned in each pixel, the display quality and manufacturing efficiency of the display device can be improved.

[0244] Hereinafter, other embodiments of a pixel and a display device including the pixel will be described. In the following embodiments, components identical or similar to those in the previously described embodiments are denoted by the same reference numerals, and descriptions thereof will be omitted or simplified, and differences will be mainly described.

[0245] Figure 19 A top plan view of a pixel according to another embodiment is shown. Figure 20 Shown along Figure 19 A cross-sectional view taken along line BB'. Figure 21 A cross-sectional view of a pixel according to another embodiment is shown, and a Figure 19 A cross-sectional view taken along line BB'. Figure 22 A top plan view of a pixel according to another embodiment is shown.

[0246] Figures 19 to 22 Examples and Figure 5 and Figure 6 The embodiment is different in that a second capacitor electrode is further formed, and other constituent elements are substantially the same or similar.

[0247] Reference Figures 19 to 22 , a display device according to another embodiment of the present invention may include a substrate SUB and a pixel PXL2 disposed on the substrate SUB.

[0248] The pixel PXL2 may include a pixel circuit layer PCL disposed on the substrate SUB and a display element layer DPL disposed on the pixel circuit layer PCL.

[0249] The display element layer DPL of this embodiment can be Figure 5 and Figure 6 The display element layer DPL described is substantially the same or similar. Figures 9 to 11 All the embodiments described in can be applied to the display element layer DPL of this embodiment.

[0250] The pixel circuit layer PCL may further include a second capacitor electrode CE2 disposed to overlap with the second electrode RFE2.

[0251] The second capacitor electrode CE2 may extend along a second direction DR2 in a plan view. That is, the second capacitor electrode CE2 may be substantially parallel to the first connection line CNL1.

[0252] The second capacitor electrode CE2 may be connected to the second power line PL2 or may serve as the second power line PL2. That is, the second capacitor electrode CE2 may be connected to the second driving power supply ( Figure 3a VDD in it) to supply the voltage of the second driving power supply VDD to the transistor TR.

[0253] At least a part of the second capacitor electrode CE2 may overlap with the second electrode RFE2 disposed thereon. The region where the second capacitor electrode CE2 and the second electrode RFE2 overlap may be the second capacitor region CA2. At least a part of the second capacitor region CA2 may overlap with the light-emitting region EA in which the light-emitting element LD is disposed, but is not limited thereto.

[0254] At least one passivation layer or insulating layer may be provided between the second capacitor electrode CE2 and the second electrode RFE2. For example, the second capacitor electrode CE2 may be formed on the same layer as the first capacitor electrode CE1, and the second passivation layer VIA2 may be provided between the second capacitor electrode CE2 and the second electrode RFE2. That is, in the second capacitor region CA2, the second capacitor electrode CE2 and the second electrode RFE2 may constitute the second capacitor C2 together with the second passivation layer VIA2 disposed therebetween.

[0255] In the process of aligning the light-emitting element LD on the substrate SUB, a predetermined alternating voltage may be supplied to the second electrode RFE2. In this embodiment, the second electrode RFE2 may not be directly connected to the alternating voltage line, but may indirectly receive the alternating voltage through the second capacitor electrode CE2. As described above, the second electrode RFE2 and the second capacitor electrode CE2 may constitute the second capacitor C2, and the second electrode RFE2 may receive the alternating voltage supplied to the second capacitor electrode CE2 through the second capacitor C2. In this process, the second capacitor C2 may transmit only the voltage of the alternating voltage component to the second electrode RFE2 and may not transmit the noise component voltage (for example, the direct current voltage component). Therefore, the noise component voltage (direct current voltage component) of the alternating voltage supplied to the second electrode RFE2 can be removed. Details will be described later with reference to Figures 23 to 27 this.

[0256] Meanwhile, the setting of the second capacitor electrode CE2 is not limited to the above description. For example, Figure 21 the pixel PXL2a of Figure 21 may include a second capacitor electrode CE2a disposed between the interlayer insulating layer IL and the first passivation layer VIA1.

[0257] That is to say, the second capacitor electrode CE2a may be formed on the same layer as the second transistor electrode TET2. In some embodiments, the second capacitor electrode CE2a and the second transistor electrode TET2 may be integrally formed, but it is not limited thereto.

[0258] In the second capacitor region CA2, the second capacitor electrode CE2a and the second electrode RFE2 may together with the first passivation layer VIA1 and the second passivation layer VIA2 disposed between the second capacitor electrode CE2a and the second electrode RFE2 constitute the second capacitor C2a.

[0259] Figure 22 A top plan view of a pixel according to another embodiment is shown. Figure 22 The embodiment of Figure 22 is different from the above embodiment in that it further includes a fifth electrode RFE3 connected to the second electrode RFE2 and a third capacitor electrode CE3 connected to the second capacitor electrode CE2. The components other than these are basically the same or similar, so the differences will be mainly described below.

[0260] Referring to Figure 12 、 Figure 19 、 Figure 20 and Figure 22 , the pixel PXL2b may further include a third bank BNK3, a fifth electrode RFE3, a sixth electrode CTE3, and a third capacitor electrode CE3. In addition, the pixel PXL2b may include a second connection electrode CNE2 connecting the second electrode RFE2 and the fifth electrode RFE3 and a third connection electrode CNE3 connecting the second capacitor electrode CE2 and the third capacitor electrode CE3.

[0261] Figure 22 The third bank BNK3, the fifth electrode RFE3, the sixth electrode CTE3, and the second connection electrode CNE2 of the embodiment of Figure 22 are substantially the same as those of the embodiment of Figure 12 , so the detailed description thereof will be omitted.

[0262] The third capacitor electrode CE3 may be formed to overlap with the third bank BNK3 and the fifth electrode RFE3. That is, the third capacitor electrode CE3 may be located between the first electrode RFE1 and the first connection line CNL1. The third capacitor electrode CE3 may be formed to be spaced apart from the first electrode RFE1 in the first direction DR1 and may extend along the second direction DR2.

[0263] The third capacitor electrode CE3 may be connected to the second capacitor electrode CE2 through the third connection electrode CNE3. The second connection electrode CNE2 may extend along the first direction DR1 between the second electrode RFE2 and the fifth electrode RFE3.

[0264] The third capacitor electrode CE3 may be formed simultaneously with the second capacitor electrode CE2 in the same process. The third capacitor electrode CE3 and the second capacitor electrode CE2 may be located in the same layer.

[0265] The second capacitor electrode CE2, the third capacitor electrode CE3, and the third connection electrode CNE3 may be integrally formed, but are not limited thereto. Additionally, at least one of the second capacitor electrode CE2, the third capacitor electrode CE3, and the third connection electrode CNE3 may be formed simultaneously with the first capacitor electrode CE1, but are not limited thereto. In an embodiment, the first capacitor electrode CE1, the second capacitor electrode CE2, the third capacitor electrode CE3, and the third connection electrode CNE3 may all be formed simultaneously in the same process.

[0266] The third capacitor electrode CE3 and the third connection electrode CNE3 may be arranged to overlap with the fifth electrode RFE3 and the second connection electrode CNE2 located thereon. The second capacitor electrode CE2, the third capacitor electrode CE3, and the third connection electrode CNE3 that are electrically connected to each other may constitute a capacitor electrode and may form a second capacitor together with the second electrode RFE2, the fifth electrode RFE3, and the second connection electrode CNE2. Therefore, in a plan view, the second capacitor region CA2b may be a region including all of the second capacitor electrode CE2, the third capacitor electrode CE3, and the third connection electrode CNE3.

[0267] In the process of aligning the light-emitting element LD, the fifth electrode RFE3 may receive the same alignment voltage as the second electrode RFE2 from the third capacitor electrode CE3. Here, the alignment voltage supplied to the fifth electrode RFE3 may be an alternating current voltage. The third capacitor electrode CE3 may transmit only the alternating current component voltage to the fifth electrode RFE3 but may not transmit the noise component voltage (e.g., direct current voltage component). Therefore, the noise component voltage (direct current voltage component) of the alternating current voltage supplied to the fifth electrode RFE3 may be removed.

[0268] As described above, when the third capacitor electrode CE3 is further formed under the fifth electrode RFE3, an AC voltage from which noise has been removed can be applied to the fifth electrode RFE3 in the process of aligning the light-emitting element LD. Therefore, a uniform electric field is generated between the first electrode RFE1 and the fifth electrode RFE3, so that the light-emitting element LD can be aligned uniformly, and the manufacturing efficiency of the display device can be improved.

[0269] Meanwhile, in another embodiment, when other electrodes connected to the second electrode RFE2 are formed in addition to the fifth electrode RFE3, a capacitor electrode can be formed under the further formed other electrodes, and when aligning the light-emitting element, an AC voltage from which noise has been removed can be supplied to the upper electrode.

[0270] Figures 23 to 26 A top plan view for explaining a method of manufacturing a display device according to another embodiment is shown. Figure 27 A circuit diagram for explaining a noise removal method of a voltage supplied to a display device according to another embodiment when aligning a light-emitting element is shown. In particular, Figures 23 to 27 is for explaining that the light-emitting element is in Figure 19 and Figure 20 A diagram of a method of aligning in the structure shown.

[0271] Figures 23 to 27 The difference between the method of manufacturing the display device described in Figures 13 to 18 and the method of manufacturing the display device described in

[0272] is that the noise component voltage is further removed by the second capacitor electrode, and the other methods are basically the same or similar. For better understanding and convenience of description, the repeated content will be omitted. Figure 19 and Figure 20 and Figures 23 to 27 The method of manufacturing a display device according to another embodiment of the present invention will be schematically described by combining the embodiments described in

[0273] First, as shown in Figure 23 and Figure 24 a bypass power line BVL can be formed on the substrate SUB, and a first capacitor electrode CE1 and a second capacitor electrode CE2 can be formed on the substrate SUB on which the bypass power line BVL is formed.

[0274] The second capacitor electrode CE2 can be formed simultaneously with the first capacitor electrode CE1, but can be formed at different times. For example, the first capacitor electrode CE1 can be formed first, and then the second capacitor electrode CE2 can be formed.

[0275] The second capacitor electrode CE2 may extend along a second direction DR2. At least a part of the second capacitor electrode CE2 may overlap with the light-emitting region EA. Additionally, at least a part of the second capacitor electrode CE2 may overlap with the bypass power line BVL, but is not limited thereto.

[0276] Next, as Figure 25 shown in, on a substrate SUB on which a first capacitor electrode CE1 and a second capacitor electrode CE2 are formed, a first bank BNK1 and a second bank BNK2 may be formed, and a first connection line CNL1, a first electrode RFE1 connected to the first connection line CNL1, and a second electrode RFE2 spaced apart from the first electrode RFE1 may be formed.

[0277] The second electrode RFE2 may overlap with the second capacitor electrode CE2. As described above, the second electrode RFE2 may extend along the second direction DR2 to overlap with the second capacitor electrode CE2. The second electrode RFE2 and the second capacitor electrode CE2 may be insulated from each other by a second passivation layer VIA2 provided therebetween, and the second electrode RFE2 and the second capacitor electrode CE2 may together with the second passivation layer VIA2 constitute a second capacitor C2.

[0278] Next, as Figure 26 and Figure 27 shown in, the light-emitting element LD may be aligned between the first electrode RFE1 and the second electrode RFE2.

[0279] A DC voltage may be supplied to the first electrode RFE1, and an AC voltage may be supplied to the second electrode RFE2.

[0280] As described above, different alignment lines (e.g., Figure 2 the ground voltage lines GNDL1 and GNDL2 and the AC voltage lines ACL1 and ACL2) may overlap with each other in at least a partial region, and may be coupled to each other and affect each other in the overlapping region of the ground voltage line and the AC voltage line.

[0281] In particular, in the process of aligning the light-emitting element LD, a second voltage VA2 as an AC voltage may be applied to the second electrode RFE2, but due to the coupling phenomenon between the above lines, a noise component voltage of the DC voltage may be included in the AC voltage supplied to the second electrode RFE2.

[0282] A display device according to another embodiment of the present invention may constitute a second capacitor C2 by using the second electrode RFE2 and the second capacitor electrode CE2, and may indirectly receive an AC voltage through the second capacitor C2.

[0283] The DC voltage noise component voltage of the voltage supplied to the second capacitor electrode CE2 is not transmitted through the second capacitor C2, such that only the AC voltage from which the DC voltage noise component has been removed can be transmitted to the second electrode RFE2.

[0284] The noise component voltage (DC voltage) of the AC voltage transmitted to the second electrode RFE2 is removed, such that a more uniform electric field can be formed between the first electrode RFE1 and the second electrode RFE2. Accordingly, the light emitting element LD can be easily aligned between the first electrode RFE1 and the second electrode RFE2. That is to say, the alignment characteristics of the light emitting element LD can be improved. In addition, since the light emitting element LD is uniformly aligned in each pixel, the display quality and manufacturing efficiency of the display device can be improved.

[0285] Although embodiments of the invention have been described with reference to the accompanying drawings, those of ordinary skill in the art to which the present invention pertains will understand that the present invention can be implemented in other specific forms without changing the technical concept or basic features. Accordingly, it will be understood that the above embodiments are for illustrative purposes only and that the scope of the present invention is not limited thereto.

Claims

1. A display device, the display device comprising: a substrate; a conductive wire disposed on the substrate; a first capacitor electrode disposed on the conductive wire and connected to the conductive wire; a passivation layer disposed on the first capacitor electrode; a first electrode disposed on the passivation layer, at least partially overlapping with the first capacitor electrode, connected to a first power line, and receiving a first driving voltage through the first power line; a second electrode spaced apart from the first electrode, formed in the same layer as the first electrode, connected to a second power line, and receiving a second driving voltage greater than the first driving voltage through the second power line; and a light-emitting element disposed between the first electrode and the second electrode.

2. The display device according to claim 1, wherein the passivation layer includes an insulating material, and the first capacitor electrode, the passivation layer, and the first electrode form a first capacitor.

3. The display device according to claim 2, the display device further comprising: a transistor disposed between the substrate and the light-emitting element and electrically connected to the light-emitting element, wherein the transistor includes: a semiconductor pattern disposed on the substrate; a gate electrode disposed on the semiconductor pattern; and a first transistor electrode and a second transistor electrode disposed on the gate electrode to be connected to the semiconductor pattern, and the conductive wire and the gate electrode are disposed in the same layer.

4. The display device according to claim 3, wherein the first transistor electrode is connected to the second electrode, and the second transistor electrode is connected to the second power line and receives the second driving voltage through the second power line.

5. The display device according to claim 4, wherein the first capacitor electrode and the second power line are disposed in the same layer.

6. The display device according to claim 4, wherein at least a part of the second power line overlaps with the second electrode, the passivation layer is disposed between the second power line and the second electrode, and the second power line, the passivation layer, and the second electrode form a second capacitor.

7. The display device according to claim 3, wherein the first capacitor electrode and the first transistor electrode are disposed in the same layer.

8. The display device according to claim 3, wherein the conductive wire extends along a first direction in a plan view, and the first power line extends along a second direction intersecting the first direction in the plan view.

9. The display device according to claim 8, the display device further comprising: a first connection electrode connecting the first electrode and the first power line and extending along the first direction, wherein the first electrode extends along the second direction, at least a part of the first connection electrode overlaps with the first capacitor electrode, and the first electrode, the first connection electrode, and the first power line are integrally formed.

10. The display device according to claim 8, the display device further comprising: a third electrode disposed in the same layer as the second electrode, Among them, in the said planar graph, the first electrode is arranged between the second electrode and the third electrode, and the light-emitting element is also arranged between the first electrode and the third electrode.

11. The display device according to claim 10, further comprising: a second connection electrode, connecting the second electrode and the third electrode and extending along the first direction, wherein, the second electrode, the third electrode and the second connection electrode are integrally formed.

12. The display device according to claim 1, further comprising: a third electrode, making the first electrode contact the first end of the light-emitting element; and a fourth electrode, making the second electrode contact the second end of the light-emitting element.

13. The display device according to claim 12, further comprising: an insulating layer, arranged on the first electrode and the second electrode, wherein, the insulating layer includes a first opening exposing at least a part of the first electrode and a second opening exposing at least a part of the second electrode, the third electrode contacts the first electrode through the first opening, and the fourth electrode contacts the second electrode through the second opening.

14. The display device according to claim 13, further comprising: a fixing layer, arranged on the insulating layer and the light-emitting element, wherein, the fixing layer contacts at least a part of the outer peripheral surface of each of the light-emitting elements, and exposes the first end and the second end of each of the light-emitting elements.

15. The display device according to claim 1, further comprising: a first bank, arranged between the first electrode and the passivation layer and stacked with the first electrode; and a second bank, arranged between the second electrode and the passivation layer and stacked with the second electrode.

16. A display device, comprising: a substrate; a conductive wire, arranged on the substrate; a first capacitor electrode, arranged on the conductive wire and connected to the conductive wire; a second capacitor electrode, arranged on the conductive wire and spaced apart from the first capacitor electrode; a passivation layer, arranged on the first capacitor electrode and the second capacitor electrode; a first electrode, arranged on the passivation layer and at least partially stacked with the first capacitor electrode; a second electrode, spaced apart from the first electrode, formed on the same layer as the first electrode, and at least partially stacked with the second capacitor electrode; and a light-emitting element, arranged between the first electrode and the second electrode.

17. The display device according to claim 16, wherein, the passivation layer includes an insulating material, the first capacitor electrode, the passivation layer and the first electrode form a first capacitor, and the second capacitor electrode, the passivation layer and the second electrode form a second capacitor.

18. The display device according to claim 17, wherein, the first capacitor electrode and the second capacitor electrode are arranged on the same layer.

19. The display device according to claim 16, wherein the display device further comprises: a transistor disposed between the substrate and the light-emitting element and electrically connected to the light-emitting element, wherein the transistor comprises: a semiconductor pattern disposed on the substrate; a gate electrode disposed on the semiconductor pattern; and a first transistor electrode and a second transistor electrode disposed on the gate electrode to be connected to the semiconductor pattern, the first transistor electrode being connected to the second electrode, the second transistor electrode being connected to the second capacitor electrode, and the conductive wire and the gate electrode being disposed in the same layer.

20. The display device according to claim 16, wherein the conductive wire extends in a first direction in a plan view, and the second capacitor electrode extends in a second direction intersecting the first direction in the plan view.

21. The display device according to claim 20, wherein the display device further comprises: a third electrode disposed in the same layer as the second electrode; and a second connection electrode connecting the second electrode and the third electrode and extending along the first direction, wherein, in the plan view, the first electrode is disposed between the second electrode and the third electrode, and the light-emitting element is further disposed between the first electrode and the third electrode.

22. The display device according to claim 21, wherein the display device further comprises: a third capacitor electrode disposed in the same layer as the second capacitor electrode; and a third connection electrode connecting the second capacitor electrode and the third capacitor electrode and extending along the first direction, wherein at least a part of the third capacitor electrode overlaps with the third electrode, at least a part of the third connection electrode overlaps with the second connection electrode, and the first capacitor electrode, the second capacitor electrode, the third capacitor electrode, and the third connection electrode are formed in the same layer.

23. A method of manufacturing a display device, the method comprising the steps of: forming a bypass power line on a substrate; forming a first capacitor electrode connected to the bypass power line on an upper portion of the bypass power line; forming a first electrode at least partially overlapping with the first capacitor electrode and a second electrode spaced apart from the first electrode on an upper portion of the first capacitor electrode; and supplying a first voltage to the bypass power line, supplying a second voltage to the first electrode, and supplying a third voltage to the second electrode to align a light-emitting element between the first electrode and the second electrode, wherein the first voltage, the second voltage, and the third voltage are different voltages.

24. The method of manufacturing a display device according to claim 23, wherein the first voltage and the second voltage are DC voltages, and the third voltage is an AC voltage.

25. The method of manufacturing a display device according to claim 24, wherein in the alignment step of the light-emitting element, the first capacitor electrode and the first electrode form a first capacitor, and The first capacitor bypasses an AC voltage component of the voltage supplied to the first electrode to the bypass power line.

26. The method of manufacturing a display device according to claim 24, wherein, the step of forming the first capacitor electrode further includes forming a second capacitor electrode spaced apart from the first capacitor electrode, and at least a part of the second capacitor electrode overlaps with the second electrode.

27. The method of manufacturing a display device according to claim 26, wherein, in the alignment step of the light-emitting element, the second capacitor electrode and the second electrode form a second capacitor, and the second electrode receives the third voltage from the second capacitor electrode through the second capacitor.

28. The method of manufacturing a display device according to claim 24, wherein, the first voltage is a value between the positive peak voltage and the negative peak voltage of the third voltage, and the second voltage is a ground voltage.

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