Display substrate and display device

Abstract

A display substrate and a display device are provided. The display substrate includes: a substrate and a plurality of sub-pixels disposed on the substrate; each sub-pixel includes: a pixel circuit including a storage capacitor, the storage capacitor including a first electrode plate and a second electrode plate; and a light-emitting element; the display substrate further includes a pixel defining layer, each sub-pixel including a plurality of openings, the orthographic projection of the openings on the substrate overlapping the orthographic projection of the second electrode plate on the substrate, the second electrode plate including a first edge extending along a first direction and a second edge extending along the first direction, the openings including a first edge extending along the first direction and a second edge extending along the first direction, the first edge of the second electrode plate being closer to the first edge of the opening than the second edge of the second electrode plate, and the second edge of the second electrode plate being closer to the second edge of the opening than the first edge of the second electrode plate, the sub-pixel satisfying the following formula: ΔU=|U02-U01|≤k×|Xb-Xa| / KW, the display substrate and the display device can reduce color shift.

Description

[0001] This application is a divisional application of application number 202210025026.6, filed on January 11, 2022. Technical Field

[0002] Embodiments of this disclosure relate to a display substrate and a display device. Background Technology

[0003] With the rapid development of technology, display media have become an important part of people's lives. Organic light-emitting diode (OLED) displays, due to their self-emissive nature, possess superior color and image quality. Summary of the Invention

[0004] Embodiments of this disclosure provide a display substrate and a display device.

[0005] Embodiments of this disclosure provide a display substrate, including: a substrate and a plurality of sub-pixels disposed on the substrate; each sub-pixel includes: a pixel circuit including a storage capacitor, the storage capacitor including a first electrode and a second electrode, the first electrode being closer to the substrate than the second electrode; and a light-emitting element including a first electrode, a second electrode, and a light-emitting functional layer located between the first electrode and the second electrode, the pixel circuit being configured to drive the light-emitting element; the display substrate further includes a pixel defining layer, each sub-pixel including a plurality of openings, the openings being configured to expose at least a portion of the first electrode, the openings being configured to define a light-emitting area of ​​the sub-pixel, wherein the orthographic projection of the openings on the substrate overlaps with the orthographic projection of the second electrode on the substrate, the second electrode including a first edge extending along a first direction and a second edge extending along the first direction, the openings including a first edge extending along the first direction and a second edge extending along the first direction, the first edge of the second electrode being closer to the first edge of the opening than the second edge of the second electrode, the second edge of the second electrode being closer to the second edge of the opening than the first edge of the second electrode, and the sub-pixel satisfying the following formula:

[0006] △U=|U02-U01|≤k×|Xb-Xa| / KW, where k is the color shift influence coefficient, 0.009≤k≤0.03, △U<0.0020, Xa is the minimum distance between the first edge of the second electrode plate and the first edge of the opening in the second direction, Xb is the minimum distance between the second edge of the second electrode plate and the second edge of the opening in the second direction, the first direction and the second direction intersect; KW is the maximum size of the opening in the second direction, U01 is the coordinate distance between the chromaticity coordinate point in the first viewing angle and the chromaticity coordinate point in the 0-degree viewing angle, U02 is the coordinate distance between the chromaticity coordinate point in the second viewing angle and the chromaticity coordinate point in the 0-degree viewing angle, △U is the absolute value of the difference between U02 and U01, the chromaticity coordinate point in the 0-degree viewing angle is the chromaticity coordinate point at the normal line where the center of the display substrate is located, the first viewing angle and the second viewing angle are respectively located on opposite sides of the normal line and the included angle with the normal line is equal in value.

[0007] For example, U02 < 0.020, U01 < 0.020, ΔU < 0.0015.

[0008] For example, the first edge of the opening, the first edge of the second electrode plate, the second edge of the second electrode plate, and the second edge of the opening are arranged sequentially along the second direction, and the minimum distance between the first edge of the second electrode plate and the second edge of the second electrode plate in the second direction is Xc, where Xc / Xa > 1.5 or Xc / Xb > 1.5.

[0009] For example, the plurality of sub-pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, and the first sub-pixel, the second sub-pixel, and the third sub-pixel are arranged sequentially along the second direction.

[0010] For example, the first sub-pixel satisfies the following formula:

[0011] △U1=|U2-U1|≤k1×|X2-X1| / KW1,

[0012] Wherein, k1 is a coefficient, 0.009≤k1≤0.02, X1 is the minimum distance between the first edge of the second electrode plate in the first sub-pixel and the first edge of the opening of the first sub-pixel in the second direction; X2 is the minimum distance between the second edge of the second electrode plate in the first sub-pixel and the second edge of the opening of the first sub-pixel in the second direction; KW1 is the maximum size of the opening of the first sub-pixel in the second direction; U1 is the coordinate distance between the chromaticity coordinate point of the first sub-pixel in the first viewing angle and the chromaticity coordinate point in the 0-degree viewing angle; U2 is the coordinate distance between the chromaticity coordinate point of the first sub-pixel in the second viewing angle and the chromaticity coordinate point in the 0-degree viewing angle; and ΔU1 is the absolute value of the difference between U2 and U1.

[0013] For example, the second sub-pixel satisfies the following formula:

[0014] △U2=|U4-U3|≤k2×|X4-X3| / KW2,

[0015] Wherein, k2 is a coefficient, 0.004≤k2≤0.02; X3 is the minimum distance in the second direction between the first edge of the second electrode plate in the second sub-pixel and the first edge of the opening of the second sub-pixel; X4 is the minimum distance in the second direction between the second edge of the second electrode plate in the second sub-pixel and the second edge of the opening of the second sub-pixel; KW2 is the maximum size of the opening of the second sub-pixel in the second direction; U3 is the coordinate distance between the chromaticity coordinate point of the second sub-pixel in the first viewing angle and the chromaticity coordinate point in the 0-degree viewing angle; U4 is the coordinate distance between the chromaticity coordinate point of the second sub-pixel in the second viewing angle and the chromaticity coordinate point in the 0-degree viewing angle; and ΔU2 is the absolute value of the difference between U4 and U3.

[0016] For example, the ratio of k2 to k1 is less than 10 and greater than 0.1.

[0017] For example, the third sub-pixel satisfies the following formula:

[0018] △U3=|U6-U5|≤k3×|X6-X5| / KW3,

[0019] Wherein, k3 is a coefficient, 0.01≤k3≤0.03; X5 is the minimum distance in the second direction between the first edge of the second pole plate in the third sub-pixel and the first edge of the opening in the third sub-pixel; X6 is the minimum distance in the second direction between the second edge of the second pole plate in the third sub-pixel and the second edge of the opening; KW3 is the maximum size of the opening in the second direction; U5 is the coordinate distance between the chromaticity coordinate point of the third sub-pixel in the first viewing angle and the chromaticity coordinate point in the 0-degree viewing angle; U6 is the coordinate distance between the chromaticity coordinate point of the third sub-pixel in the second viewing angle and the chromaticity coordinate point in the 0-degree viewing angle; and ΔU3 is the absolute value of the difference between U6 and U5.

[0020] For example, the display substrate further includes: a data line configured to provide a data voltage to the pixel circuit; the display substrate further includes: a conductive structure, wherein the conductive structure includes a first signal line and a signal connection line, the conductive structure is configured to provide a voltage signal to the pixel circuit, the first signal line extends along a second direction, the signal connection line extends along the first direction, the signal connection line is electrically connected to the first signal line, and the orthographic projection of at least one of the signal connection line and the data line on the substrate overlaps with the orthographic projection of the opening of at least one of the plurality of sub-pixels on the substrate.

[0021] For example, the signal connection line includes at least one of a portion of a first power line extending in the first direction and a portion of an initialization line extending in the first direction.

[0022] For example, the display substrate further includes a second signal line, wherein the second signal line is configured to provide a voltage signal to the pixel circuit, the second signal line extends along the second direction, and the orthographic projection of the second signal line on the substrate overlaps with the orthographic projection of the opening of at least one of the plurality of sub-pixels on the substrate.

[0023] For example, the second signal line includes at least one of a gate line and an initialization signal line extending along the second direction.

[0024] For example, the overlap dimension of the signal connection line and the opening in the second direction is less than 10% of the line width of the signal connection line, or the overlap dimension of the data line and the opening in the second direction is less than 10% of the line width of the data line.

[0025] For example, the display substrate further includes an insulating layer and vias penetrating the insulating layer, wherein the vias include a first via, a second via, and a third via. The first electrodes of the light-emitting elements of the first sub-pixel, the second sub-pixel, and the third sub-pixel are respectively connected to the pixel circuits of the first sub-pixel, the second sub-pixel, and the third sub-pixel through the first via, the second via, and the third via. The spacing between the first via and the second via is KX1, and the spacing between the second via and the third via is KX2, wherein the ratio of KX1 / KX2 is 0.75-1.25.

[0026] For example, the distance between the axis of symmetry of the via extending in the first direction and the axis of symmetry of the opening closest to the via extending in the first direction is less than 8 micrometers, and the diameter of the via is 8-17 micrometers.

[0027] For example, the insulating layer includes a passivation layer and a planarization layer, wherein the material of the passivation layer includes an inorganic insulating material, the material of the planarization layer includes an organic insulating material, and the thickness of the planarization layer is 3-7 micrometers.

[0028] For example, the display substrate satisfies the following formula:

[0029] 1 / k = F1(CW / KW) - F2(DV / KW) + F3(DW / KW), where F1 is the capacitance influence coefficient, F2 is the via offset influence coefficient, F3 is the signal line influence coefficient, CW is the maximum dimension of the second plate of the storage capacitor in the second direction, CW / KW is the proportion of the storage capacitor to the opening, DV is the distance between the axis of symmetry of the via extending along the first direction and the axis of symmetry of the opening closest to the via extending along the first direction, and DW is the line width of the signal line, which includes the signal connection line.

[0030] For example, the display substrate satisfies the following formula: 1 / T=k×(CW-DV+DW) / KW, where 1 / T is the color shift improvement influence coefficient, the first sub-pixel satisfies 1 / T1=k1×(CW-DV+DW) / KW, the second sub-pixel satisfies 1 / T2=k2×(CW-DV+DW) / KW, and the third sub-pixel satisfies 1 / T3=k3×(CW-DV+DW) / KW, where 1 / T1<0.019, 1 / T2<0.019, and 1 / T3<0.019.

[0031] For example, 1 / T1 < 0.009, 1 / T2 < 0.014, 1 / T3 < 0.019.

[0032] For example, 1 / T1 < 0.008, 1 / T2 < 0.003, 1 / T3 < 0.016.

[0033] For example, 0.2 < Tx / Ty < 6, where Tx is one of T1, T2, and T3, and Ty is one of T1, T2, and T3.

[0034] For example, under the O-view and -O-view, the first sub-pixel satisfies 1 / T11=k11×(CW-DV+DW) / KW; under the P-view and -P-view, the first sub-pixel satisfies 1 / T12=k12×(CW-DV+DW) / KW, 1 / T11<0.009, 1 / T12<0.008.

[0035] For example, |1 / T12-1 / T11|<0.001.

[0036] For example, under the O-view and -O-view, the second sub-pixel satisfies 1 / T21=k21×(CW-DV+DW) / KW; under the P-view and -P-view, the second sub-pixel satisfies 1 / T22=k22×(CW-DV+DW) / KW, 1 / T21<0.014, 1 / T22<0.004.

[0037] For example, |1 / T22-1 / T21|<0.010.

[0038] For example, 1 / T21 < 0.009, 1 / T22 < 0.003.

[0039] For example, under the O-view and -O-view, the third sub-pixel satisfies 1 / T31=k31×(CW-DV+DW) / KW; under the P-view and -P-view, the third sub-pixel satisfies 1 / T32=k32×(CW-DV+DW) / KW, 1 / T31<0.016, 1 / T32<0.019.

[0040] For example, |1 / T32-1 / T31|<0.003.

[0041] For example, 1 / T31 < 0.012, 1 / T32 < 0.014.

[0042] For example, the signal connection line includes a first part, a second part, and a third part, the first part and the third part are connected through the second part, the first part and the third part are located in a first conductive pattern layer, and the second part is located in a second conductive pattern layer.

[0043] For example, the first conductive pattern layer is closer to the substrate than the second conductive pattern layer.

[0044] For example, the width of the second portion of the signal connection line in the second direction is greater than the width of either the first portion or the third portion of the signal connection line in the second direction.

[0045] For example, at least one of the first portion and the third portion of the signal connection line does not coincide with the centerline of the second portion of the signal connection line along the first direction.

[0046] For example, the pixel defining layer includes a plurality of first defining portions and a plurality of second defining portions, the plurality of second defining portions being arranged along the second direction and extending along the first direction, the plurality of first defining portions being configured as a plurality of groups, each group of first defining portions being located between two adjacent second defining portions, the first defining portions extending along the second direction, the first defining portions in each group being arranged along the first direction, the maximum height of the first defining portion to the planarization layer being less than the maximum height of the second defining portion to the planarization layer, the substrate including a display area and a peripheral area located on at least one side of the display area, the orthographic projection of the portion of the data line located in the display area on the substrate being located within the orthographic projection of the second defining portion on the substrate.

[0047] For example, the display substrate further includes a second conductive pattern layer and a third conductive pattern layer, wherein the data line includes a portion located in the second conductive pattern layer, the third conductive pattern layer further includes a first conductive portion and a second conductive portion, the second conductive pattern layer further includes a third conductive portion and a fourth conductive portion, the first conductive portion and the third conductive portion overlap in a direction perpendicular to the substrate and are located on one side of the second defining portion, the second conductive portion and the fourth conductive portion overlap in a direction perpendicular to the substrate and are located on the other side of the second defining portion, the center lines of the first conductive portion and the third conductive portion along the first direction do not coincide, and the center lines of the second conductive portion and the fourth conductive portion along the first direction do not coincide.

[0048] For example, the first conductive portion includes a main body portion and slope portions located on both sides of the main body portion, and the orthographic projection of one end of the third conductive portion near the second limiting portion on the substrate is located within the orthographic projection of the main body portion of the first conductive portion on the substrate.

[0049] For example, the third conductive part includes a main body and sloped portions located on both sides of the main body, wherein the slope angle of the sloped portion of the third conductive part is greater than the slope angle of the sloped portion of the first conductive part.

[0050] For example, the main body of the third conductive part includes a first main body and a second main body. The orthographic projection of the first main body on the substrate overlaps with the orthographic projection of the first conductive part on the substrate. The orthographic projection of the second main body on the substrate does not overlap with the orthographic projection of the first conductive part on the substrate. The distance between the surface of the second main body away from the substrate and the substrate is less than the distance between the surface of the first main body away from the substrate and the substrate.

[0051] For example, at least one of the third conductive portion and the fourth conductive portion includes a first sublayer, a second sublayer, and a third sublayer, which are stacked together, and the first sublayer is closer to the substrate than the third sublayer, and the second sublayer is recessed relative to the first sublayer and the third sublayer.

[0052] For example, the display substrate further includes multiple fan-out lines. The substrate includes a display area and a peripheral area located on at least one side of the display area. The data line is connected to one of the multiple fan-out lines. The multiple fan-out lines gradually converge from a position close to the connection point of the data line and the fan-out line to a position away from the connection point of the data line and the fan-out line. The multiple fan-out lines extend from the display area to the peripheral area. The multiple fan-out lines are located on different layers from the data line. The multiple fan-out lines are closer to the substrate than a portion of the data line.

[0053] For example, the display substrate satisfies the following formula: 1 / k=T'(CW-DV+DW) / KW+e F4(DH / PH) Where T' is a coefficient, T' is greater than or equal to 20 and less than 70, F4 is a coefficient, F4 is greater than 6 and less than 30, DH is the thickness of the data line, and PH is the thickness of the planarization layer.

[0054] For example, the first sub-pixel satisfies 1 / k1=T'(CW-DV+DW) / KW+e Fa(DH / PH) The second sub-pixel satisfies 1 / k2=T'(CW-DV+DW) / KW+e Fb(DH / PH) The third sub-pixel satisfies 1 / k3=T'(CW-DV+DW) / KW+e Fc(DH / PH) , 20≤T'≤30, Fa<27, Fb<26, Fc<23.

[0055] For example, T' = 20, 10 < Fa < 24.

[0056] For example, T' = 20, 10 < Fb < 23.

[0057] For example, T' = 20, 8 < Fc < 19.

[0058] For example, 0.09 < DH / PH < 0.16, 20 ≤ T' ≤ 25.

[0059] For example, 0.17 < DH / PH < 0.38, 25 ≤ T' ≤ 30.

[0060] For example, the display substrate further includes: a data line, a first gate line, a second gate line, a third gate line, a first power line, a first initialization line, and a second initialization line. The data line is configured to provide a data voltage to the pixel circuit; the first gate line is configured to provide a scan signal to the pixel circuit; the second gate line is configured to provide a first reset control signal to the pixel circuit; the third gate line is configured to provide a second reset control signal to the pixel circuit; the first power line is configured to provide a first voltage signal to the pixel circuit; the first initialization line is configured to provide a first initialization signal to the pixel circuit; and the second initialization line is configured to provide a second initialization signal to the pixel circuit. The pixel circuit further includes a driving transistor, a data writing transistor, a first reset transistor, and a second reset transistor. The first terminal of the data writing transistor is connected to the data line; the gate of the data writing transistor is connected to the first gate line; and the second terminal of the data writing transistor is connected to the gate of the driving transistor. The first terminal of the first reset transistor is connected to the first initialization line, and the second terminal of the first reset transistor is connected to the data writing transistor. The gate of the driving transistor is connected to the first reset transistor, and the gate of the first reset transistor is connected to the second gate line; the first electrode of the second reset transistor is connected to the second initialization line, the second electrode of the second reset transistor is connected to the first electrode of the light-emitting element, and the gate of the second reset transistor is connected to the third gate line; the first power line includes a first power signal line extending along the second direction and a first power connection line extending along the first direction, and the first power signal line and the first power connection line are connected; the first initialization line includes a first initialization signal line extending along the second direction and a first initialization connection line extending along the first direction, and the first initialization signal line and the first initialization connection line are connected; the second initialization line includes a second initialization signal line extending along the second direction and a second initialization connection line extending along the first direction, and the second initialization signal line and the second initialization connection line are connected; the orthographic projection of at least one of the first power connection line, the first initialization connection line, and the second initialization connection line on the substrate overlaps with the orthographic projection of the opening of the sub-pixel on the substrate.

[0061] Embodiments of this disclosure also provide a display substrate, comprising: a substrate and a plurality of sub-pixels disposed on the substrate, the sub-pixels including a plurality of first sub-pixels (R) and a plurality of second sub-pixels (G), the plurality of sub-pixels being arranged along a first direction or along a second direction, the first direction and the second direction intersecting; an active semiconductor layer located on one side of the substrate; a first conductive pattern layer located on the side of the active semiconductor layer away from the substrate; a second conductive pattern layer located on the side of the first conductive pattern layer away from the substrate; a first insulating layer located on the side of the second conductive pattern layer away from the substrate; a second insulating layer located on the side of the first insulating layer away from the substrate, wherein the second conductive pattern layer includes a plurality of conductive elements, the conductive elements including a first conductive element corresponding to the first sub-pixel and a second conductive element corresponding to the second sub-pixel; the second insulating layer includes a plurality of openings for defining an effective light-emitting area of ​​the sub-pixel, the openings including a first opening corresponding to the first sub-pixel and a second opening corresponding to the second sub-pixel, the first opening and the second opening being... The areas of the second openings are different; the first sub-pixel satisfies the following relationship: △U1=|U2-U1|≤k1×|X2-X1| / KW1, where k1 is a coefficient, 0.009≤k1≤0.02, X1 is the minimum distance in the second direction between the first edge of the first conductive element in the first sub-pixel and the first edge of the opening corresponding to the first sub-pixel; X2 is the minimum distance in the second direction between the second edge of the first conductive element in the first sub-pixel and the second edge of the opening corresponding to the first sub-pixel, KW1 Let U1 be the maximum size of the opening corresponding to the first sub-pixel in the second direction, U2 be the coordinate distance between the chromaticity coordinate point of the first sub-pixel in the first viewing angle and the chromaticity coordinate point in the 0-degree viewing angle, and ΔU1 be the absolute value of the difference between U2 and U1. The second sub-pixel satisfies the following relationship: ΔU2=|U4-U3|≤k2×|X4-X3| / KW2, where k2 is a coefficient, 0.004≤k2≤0.X2, X3 is the minimum distance in the second direction between the first edge of the second conductive element of the second sub-pixel and the first edge of the opening corresponding to the second sub-pixel; X4 is the minimum distance in the second direction between the second edge of the second conductive element of the second sub-pixel and the second edge of the opening corresponding to the second sub-pixel; KW2 is the maximum size of the opening corresponding to the second sub-pixel in the second direction; U3 is the coordinate distance between the chromaticity coordinate point of the second sub-pixel in the first viewing angle and the chromaticity coordinate point in the 0-degree viewing angle; U4 is the coordinate distance between the chromaticity coordinate point of the second sub-pixel in the second viewing angle and the chromaticity coordinate point in the 0-degree viewing angle; ΔU2 is the absolute value of the difference between U4 and U3; 0.1 < k2 / k1 < 10.

[0062] Embodiments of this disclosure also provide a display substrate, comprising: a substrate and a plurality of sub-pixels disposed on the substrate, the sub-pixels including a plurality of first sub-pixels (R) and a plurality of second sub-pixels (G), wherein the first sub-pixel includes a first pixel circuit including a first conductive element, the second sub-pixel includes a second pixel circuit including a second conductive element, the plurality of sub-pixels being arranged along a first direction or along a second direction, the first direction and the second direction intersecting; a pixel defining layer including a plurality of openings, the openings being configured to expose at least a portion of the first electrode, the openings being configured to define a light-emitting area of ​​the sub-pixel; The opening includes a first opening corresponding to a first sub-pixel and a second opening corresponding to a second sub-pixel, the areas of the first opening and the second opening being different; the first sub-pixel satisfies the following relationship: ΔU1=|U2-U1|≤k1×|X2-X1| / KW1, where k1 is a coefficient, 0.009≤k1≤0.02, X1 is the minimum distance in the second direction between the first edge of the first conductive element in the first sub-pixel and the first edge of the opening corresponding to the first sub-pixel; X2 is the minimum distance in the second direction between the second edge of the first conductive element in the first sub-pixel and the second edge of the opening corresponding to the first sub-pixel. The minimum distance is defined as follows: KW1 is the maximum size of the opening corresponding to the first sub-pixel in the second direction; U1 is the coordinate distance between the chromaticity coordinate point of the first sub-pixel in the first viewing angle and the chromaticity coordinate point in the 0-degree viewing angle; U2 is the coordinate distance between the chromaticity coordinate point of the first sub-pixel in the second viewing angle and the chromaticity coordinate point in the 0-degree viewing angle; ΔU1 is the absolute value of the difference between U2 and U1; the second sub-pixel satisfies the following relationship: ΔU2=|U4-U3|≤k2×|X4-X3| / KW2, where k2 is a coefficient, 0.004≤k2≤0.02, and X3 is the distance between the first edge and the second conductive element in the second sub-pixel. The minimum distance of the first edge of the opening in the second direction; X4 is the minimum distance of the second edge of the second conductive element in the second sub-pixel and the second edge of the opening corresponding to the second sub-pixel in the second direction; KW2 is the maximum size of the opening corresponding to the second sub-pixel in the second direction; U3 is the coordinate distance between the chromaticity coordinate point of the second sub-pixel in the first viewing angle and the chromaticity coordinate point in the 0-degree viewing angle; U4 is the coordinate distance between the chromaticity coordinate point of the second sub-pixel in the second viewing angle and the chromaticity coordinate point in the 0-degree viewing angle; △U2 is the absolute value of the difference between U4 and U3; 0.1 < k2 / k1 < 10.

[0063] Embodiments of this disclosure also provide a display device including any of the above-described display substrates. Attached Figure Description

[0064] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0065] Figure 1 This is a schematic diagram of the pixel arrangement of a display substrate.

[0066] Figure 2 This is a schematic diagram of a pixel circuit driving a light-emitting element to emit light in a display substrate.

[0067] Figure 3 This is a schematic diagram of the pixel circuitry and light-emitting elements in a sub-pixel.

[0068] Figure 4 This is a layout diagram of a display substrate provided in an embodiment of the present disclosure.

[0069] Figure 5 for Figure 4 A sectional view along line A1-A2.

[0070] Figures 6A to 6G for Figure 4 A plan view of a single layer of the display substrate.

[0071] Figures 7A to 7D for Figure 4 A plan view of a portion of the stacked layers of the display substrate.

[0072] Figure 8 A layout diagram of a display substrate is provided for one embodiment of this disclosure.

[0073] Figure 9A A plan view of a pixel-defining layer in a display substrate provided for an embodiment of this disclosure.

[0074] Figure 9B A plan view of a pixel-defining layer in a display substrate provided for an embodiment of this disclosure.

[0075] Figure 10 This is a schematic diagram of a display substrate provided in an embodiment of the present disclosure.

[0076] Figure 11 A plan view of a display substrate provided for an embodiment of this disclosure.

[0077] Figure 12 A schematic diagram of the center pixel of a display substrate provided for an embodiment of this disclosure.

[0078] Figure 13 for Figure 12 A cross-sectional view along line B1-B2.

[0079] Figure 14 This is a schematic diagram showing the coordinate distance between chromaticity coordinate points on a display substrate from two different viewing angles.

[0080] Figure 15A This is a schematic diagram of a display substrate provided in an embodiment of the present disclosure.

[0081] Figure 15B This is a schematic diagram of a display substrate provided in an embodiment of the present disclosure.

[0082] Figure 16 This is a schematic diagram of a display substrate provided in an embodiment of the present disclosure.

[0083] Figure 17 This is a schematic diagram of the color shift of a display substrate provided in an embodiment of this disclosure.

[0084] Figure 18 for Figure 4 The diagram shows a schematic of the conductive structure in the display substrate.

[0085] Figure 19 This is a schematic diagram of a display substrate.

[0086] Figure 20 This is a schematic diagram of a display substrate provided in one embodiment of the present disclosure.

[0087] Figure 21 This is a schematic diagram of a display substrate provided in one embodiment of the present disclosure.

[0088] Figure 22 This is a schematic diagram of a display substrate provided in one embodiment of the present disclosure.

[0089] Figure 23 This is a schematic diagram of a display substrate provided in one embodiment of the present disclosure.

[0090] Figure 24 This is a schematic diagram of a display substrate provided in one embodiment of the present disclosure.

[0091] Figure 25 for Figure 24 A plan view of part of the membrane layer.

[0092] Figure 26 for Figure 24 A plan view of the fourth conductive pattern layer in the image.

[0093] Figure 27 This is a schematic diagram of a display substrate provided in an embodiment of the present disclosure. Detailed Implementation

[0094] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0095] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0096] In typical organic light-emitting diode (OLED) displays, the organic light-emitting layer needs to be deposited using a vapor deposition process, which has stringent process requirements and is difficult to scale up to a large area.

[0097] Using inkjet printing to fabricate the OLED light-emitting material layer is the best way to achieve low-cost OLED production and enable OLEDs to compete in the mid-to-high-end market. Inkjet printing is a highly efficient process; compared to vapor deposition, it wastes less material and is extremely fast.

[0098] In inkjet printing to form the light-emitting functional layer of an organic light-emitting diode (OLED), a solvent is primarily used to dissolve the organic material to form a solution (ink). This solution (ink) is then directly sprayed onto the surface of a substrate to form the light-emitting functional layer for sub-pixels, such as red (R), green (G), and blue (B). Inkjet printing OLED technology offers significant advantages over vapor deposition technology in terms of manufacturing process, yield, and cost. For example, the light-emitting functional layer includes a light-emitting layer (light-emitting material layer), and may also include at least one of a hole injection layer, a hole transport layer, an electron transport layer, or an electron injection layer. The organic light-emitting functional layer can be selected as needed. At least one film layer in the light-emitting functional layer can be fabricated using an inkjet printing process.

[0099] Due to the large molecular weight of polymers, solution processing, such as spin coating or printing, is mainly used to form films. Inkjet printing technology is the best method for preparing luminescent polymer solutions. In recent years, much effort has been made to improve the pixel resolution, film uniformity, and lifespan of displays, and research on inkjet printing to form optoelectronic materials has become increasingly active. For example, the hole transport layer, hole injection layer, and luminescent layer of a display can all be prepared using inkjet printing technology, laying the foundation for the use of a fully printed method to manufacture displays.

[0100] When using inkjet printing to fabricate the emissive layer, a high degree of flatness is required. The flatter the emissive layer in each sub-pixel, the more color shift can be reduced or avoided, resulting in a better display effect. Achieving a flat emissive layer can be done by adjusting the structure of the display substrate.

[0101] Figure 1 This is a schematic diagram of the pixel arrangement of a display substrate. (Example) Figure 1 As shown, the display substrate includes a plurality of sub-pixels 100 located on a substrate, and the plurality of sub-pixels 100 are arranged in an array. Figure 1 As shown, multiple sub-pixels 100 are arranged in an array along the first direction Y and the second direction X. Embodiments of this disclosure use... Figure 1 The example shown is of multiple sub-pixels 100 arranged in an array, but the arrangement of multiple sub-pixels 100 is not limited to this. Figure 1 As shown.

[0102] like Figure 1 As shown, the display panel includes multiple pixels PX, and each pixel PX includes multiple sub-pixels 100. (See diagram) Figure 1 As shown, the plurality of sub-pixels 100 includes a first sub-pixel 101, a second sub-pixel 102, and a third sub-pixel 103. Figure 1 As shown, each pixel PX includes a first sub-pixel 101, a second sub-pixel 102, and a third sub-pixel 103. The first sub-pixel 101, the second sub-pixel 102, and the third sub-pixel 103 emit different colors. Sub-pixels in the same column are of the same color, and multiple pixels PX are arranged sequentially in the same row. This embodiment uses the first direction Y as the row direction and the second direction X as the column direction for illustration. In other embodiments, the first direction Y can be the column direction, and the second direction X can be the row direction.

[0103] The embodiments disclosed herein are illustrated by taking the first sub-pixel 101 as a red-emitting sub-pixel, the second sub-pixel 102 as a green-emitting sub-pixel, and the third sub-pixel 103 as a blue-emitting sub-pixel as examples.

[0104] like Figure 1As shown, the substrate BS includes a display area R01 and a peripheral area R02 located on at least one side of the display area R01. Figure 1 The following explanation uses the example of the surrounding area R02 surrounding the display area R01.

[0105] Figure 2 This is a schematic diagram of a pixel circuit driving a light-emitting element to emit light in a display substrate. Figure 2 As shown, each sub-pixel 100 includes a pixel circuit 100a and a light-emitting element 100b. The pixel circuit 100a is connected to the light-emitting element 100b, and the pixel circuit 100a is configured to drive the light-emitting element 100b to emit light. For example, the pixel circuit 100a is configured to drive the light-emitting element 100b to emit light. The light-emitting element 100b includes a light-emitting area. Figure 1 The pixel arrangement shown refers to the setting position of the light-emitting area of ​​the light-emitting element 100b in the sub-pixel 100.

[0106] Figure 3 This is a schematic diagram of the pixel circuitry and light-emitting elements in a sub-pixel. Figure 4 This is a layout diagram of a display substrate provided in an embodiment of the present disclosure. Figure 4 The display substrate DS1 is shown. Figure 5 for Figure 4 A sectional view along line A1-A2. Figures 6A to 6G for Figure 4 A plan view of a single layer of the display substrate. Figures 7A to 7D for Figure 4 A plan view of a portion of the stacked layers of the display substrate.

[0107] like Figure 3 and Figure 4 As shown, in sub-pixel 100, pixel circuit 100a includes a data writing transistor T1, a reset transistor T2, a driving transistor T3, a reset transistor T4, and a storage capacitor 20. Light-emitting element 100b is connected to driving transistor T3. Reset transistor T2 is configured to reset the gate T3g of driving transistor T3, and reset transistor T4 is configured to reset the first electrode E1 of light-emitting element 100b. Figure 3 and Figure 4 As shown, the storage capacitor 20 includes a first plate 201 and a second plate 202.

[0108] like Figure 3 and Figure 4As shown, the display panel includes gate lines G1, G2, G3, data line DT, first power line PL1, second power line PL2, initialization signal line INT1, and initialization signal line INT2. Gate lines G2 and G3 can also be referred to as reset control signal lines RST. For example, the first power line PL1 is configured to provide a constant first voltage signal VDD to the sub-pixel 100, and the second power line PL2 is configured to provide a constant second voltage signal VSS to the sub-pixel 100, wherein the first voltage signal VDD is greater than the second voltage signal VSS. Gate line G1 is configured to provide a scan signal SCAN to the sub-pixel 100, gate line G2 is configured to provide a reset control signal RESET1 to the sub-pixel 100, gate line G3 is configured to provide a reset control signal RESET2 to the sub-pixel 100, and data line DT is configured to provide a data signal (data voltage) DATA to the sub-pixel 100. The initialization signal line INT1 is configured to provide a first initialization signal Vinit1 to the sub-pixel 100. The initialization signal line INT2 is configured to provide a second initialization signal Vinit2 to the sub-pixel 100. For example, the first initialization signal Vinit1 and the second initialization signal Vinit2 are constant voltage signals, the magnitude of which may be between the first voltage signal VDD and the second voltage signal VSS, but are not limited thereto. For example, the first initialization signal Vinit1 and the second initialization signal Vinit2 may both be less than or equal to the second voltage signal VSS. For example, in some embodiments of this disclosure, the initialization signal line INT1 and the second initialization signal line INT2 are connected and both are configured to provide the initialization signal Vinit to the sub-pixel 100; that is, the initialization signal line INT1 and the initialization signal line INT2 are both called the initialization signal line INT, and the first initialization signal Vinit1 and the second initialization signal Vinit2 are equal, both being Vinit, but are not limited thereto. In other embodiments, the initialization signal line INT1 and the second initialization signal line INT2 are insulated from each other to provide different initialization signals.

[0109] like Figure 3 and Figure 4 As shown, the driving transistor T3 is electrically connected to the light-emitting element 100b, and outputs a driving current to drive the light-emitting element 100b to emit light under the control of signals such as the scan signal SCAN, the data signal DATA, the first voltage signal VDD, and the second voltage signal VSS.

[0110] For example, the light-emitting element 100b includes an organic light-emitting diode (OLED), which emits red light, green light, blue light, or white light under the drive of its corresponding pixel circuit 100a.

[0111] like Figure 3 and Figure 4As shown, the first electrode E1 of the light-emitting element 100b is connected to the first electrode T3a of the driving transistor T3, the second electrode E2 of the light-emitting element 100b is connected to the second power supply line PL2, the second electrode T3b of the driving transistor T3 is connected to the first power supply line PL1, the gate T3g of the driving transistor T3 is connected to the second electrode T1b of the data writing transistor T1, the first electrode T1a of the data writing transistor T1 is connected to the data line DT, and the gate T1g of the data writing transistor T1 is connected to the gate line G1.

[0112] like Figure 3 and Figure 4 As shown, the gate T3g of the driving transistor T3 is connected to the first plate 201 of the storage capacitor 20, and the second plate 202 of the storage capacitor 20 is connected to the first terminal T3a of the driving transistor T3. The first plate 201 of the storage capacitor 20 is also connected to the second terminal T1b of the data writing transistor T1.

[0113] like Figure 3 and Figure 4 As shown, the first terminal T2a of the reset transistor T2 is connected to the initialization line INT1, the second terminal T2b of the reset transistor T2 is connected to the gate T3g of the driving transistor T3, and the gate T2g of the reset transistor T2 is connected to the gate line G2.

[0114] like Figure 3 and Figure 4 As shown, the first electrode T4a of the reset transistor T4 is connected to the initialization line INT2, the second electrode T4b of the reset transistor T4 is connected to the first electrode E1 of the light-emitting element 100b, and the gate T4g of the reset transistor T4 is connected to the gate line G3.

[0115] like Figure 5 As shown, the display substrate includes a substrate BS, a barrier layer BR located on the substrate BS, and a buffer layer BF. Figure 5 As shown, an active semiconductor layer LY0 and a gate insulating layer GI are disposed on the buffer layer BF. A first conductive pattern layer LY1 is disposed on the gate insulating layer GI, an interlayer insulating layer ILD is disposed on the first conductive pattern layer LY1, a second conductive pattern layer LY2 is disposed on the interlayer insulating layer ILD, an insulating layer ISL is disposed on the second conductive pattern layer LY2, and a first electrode layer LY3 is disposed on the insulating layer ISL. Figure 5 The channel T3s of the driving transistor T3 in the active semiconductor layer LY0 is also shown.

[0116] like Figure 4 and Figure 5As shown, the display substrate also includes a pixel defining layer PDL, and the sub-pixel 100 includes a plurality of openings P0, which are configured to expose at least a portion of the first electrode E1 and to define the light-emitting area of ​​the sub-pixel 100.

[0117] For example, the slope angle of the portion of the defined opening P0 of the pixel-limited layer PDL is 40-65 degrees.

[0118] In embodiments of this disclosure, a plan view shows a first direction Y and a second direction X, and a cross-sectional view shows a third direction Z. Both the first direction Y and the second direction X are parallel to the main surface of the substrate BS. The third direction Z is perpendicular to the main surface of the substrate BS. For example, the first direction Y and the second direction X intersect. Embodiments of this disclosure are illustrated using the example of the first direction Y and the second direction X being perpendicular. Figure 5 As shown, the main surface of the substrate BS is the surface on which various components are fabricated. For example... Figure 5 As shown, the upper surface of the substrate BS is the main surface of the substrate BS.

[0119] For example, such as Figure 4 As shown, the multiple sub-pixels 100 include a first sub-pixel 101, a second sub-pixel 102, and a third sub-pixel 103, and the first sub-pixel 101, the second sub-pixel 102, and the third sub-pixel 103 are arranged sequentially along the second direction X. Of course, the sub-pixels within a pixel can also adopt other arrangements.

[0120] Figure 6G An opening P01 of a first sub-pixel 101, an opening P02 of a second sub-pixel 102, and an opening P03 of a third sub-pixel 103 are shown. In some embodiments, opening P01 may be referred to as the first opening P01, opening P02 as the second opening P02, and opening P03 as the third opening P03.

[0121] Figure 6A The active semiconductor layer LY0 is shown. The active semiconductor layer LY0 includes, but is not limited to, polysilicon.

[0122] Figure 6B The first conductive pattern layer LY1 is shown. (See diagram.) Figure 6B As shown, the first conductive pattern layer LY1 includes a first electrode 201, a connecting electrode CEa, a connecting electrode CEb, a connecting electrode CEc, a connecting electrode CEd, and a connecting electrode CEe.

[0123] Figure 6C The interlayer insulating layer (ILD) is shown, illustrated by vias within the ILD. Figure 6C Vias V1 to V12 and vias Va to Vh are shown.

[0124] Figure 6D The second conductive patterned layer LY2 is shown. (See figure) Figure 6D As shown, the second conductive pattern layer LY2 includes a second electrode 202 and a connecting electrode CEf.

[0125] Figure 6E The insulating layer ISL is shown, illustrated by vias within the insulating layer ISL. (See diagram.) Figure 6E As shown, the via VH includes a first via VH1, a first via VH2, and a third via VH3.

[0126] Figure 6F The first electrode layer LY3 of the light-emitting element is shown. Figure 6F Three first electrodes E1 are shown.

[0127] Figure 6G The pixel defining layer (PDL) is shown, with an opening P0 in the PDL. When at least one layer of the light-emitting functional layer (FL) is fabricated in the display substrate using an inkjet printing process, the inkjet-printed layer is located in the opening P0 of the pixel defining layer (PDL).

[0128] like Figure 3 , Figure 4 , Figures 6A to 6G , Figures 7A to 7D As shown, the connecting electrode CEa is connected to the gate line G3 through the via V9, and the connecting electrode CEa serves as the gate of the reset transistor T4.

[0129] like Figure 3 , Figure 4 , Figures 6A to 6G , Figures 7A to 7D As shown, one end of the connecting electrode CEb is connected to the initialization line INT2 through via V11, and the other end of the connecting electrode CEb is connected to the first electrode T4a of the reset transistor T4 through via V10.

[0130] like Figure 3 , Figure 4 , Figures 6A to 6G , Figures 7A to 7D As shown, the connection electrode CEc is connected to the gate line G1 through the via V12, and the connection electrode CEc serves as the gate of the data writing transistor T1.

[0131] like Figure 3 , Figure 4 , Figures 6A to 6G , Figures 7A to 7D As shown, the connecting electrode CEd is connected to the gate line G2 through the via V6, and the connecting electrode CEd serves as the gate of the reset transistor T2.

[0132] like Figure 3 , Figure 4 , Figures 6A to 6G, Figures 7A to 7D As shown, one end of the connecting electrode CEe is connected to the initialization line INT1 through via V7, and the other end of the connecting electrode CEe is connected to the first electrode T2a of the reset transistor T2 through via V8.

[0133] like Figure 3 , Figure 4 , Figures 6A to 6G , Figures 7A to 7D As shown, one end of the connecting electrode CEf is connected to the first electrode plate 201 through the via V3, and the other end of the connecting electrode CEf is connected to the second electrode T2b of the data writing transistor T1 through the via V5.

[0134] like Figure 3 , Figure 4 , Figures 6A to 6G , Figures 7A to 7D As shown, the second electrode 202 is connected to the second electrode T4b of the reset transistor T4 through the via V2. The second electrode T4b of the reset transistor T4 also serves as the first electrode T3a of the drive transistor T3.

[0135] like Figure 3 , Figure 4 , Figures 6A to 6G , Figures 7A to 7D As shown, the data line DT is connected to the first terminal T1a of the data writing transistor T1 through the via V4.

[0136] Figure 7B The channel T1s of the data writing transistor T1, the channel T2s of the reset transistor T2, the channel T3s of the driving transistor T3, and the channel T4s of the reset transistor T4 are shown.

[0137] In embodiments of this disclosure, elements located in the second conductive pattern layer LY2 can be connected to elements located in the first conductive pattern layer LY1 and elements located in the active semiconductor layer LY0 through vias, and elements located in the first conductive pattern layer LY1 and elements located in the active semiconductor layer LY0 can be connected through elements located in the second conductive pattern layer LY2.

[0138] For example, the insulating layer through which the via penetrates can be determined based on the condition of the insulating layer between the two conductive pattern layers connected by the via.

[0139] According to some embodiments of the present disclosure, the display substrate DS1 uses an active semiconductor layer LY0, a first conductive pattern layer LY1, and a second conductive pattern layer LY2 to form a pixel circuit 100a, thereby simplifying the manufacturing process and reducing the thickness of the display substrate. Initialization lines INT1, INT2, and / or the first power line PL1 can be referred to as conductive structure 40. Conductive structure 40 includes a first signal line 411 and a signal connection line 412. Conductive structure 40 is configured to provide a voltage signal to the sub-pixel 100. The first signal line 411 extends along a second direction X, and the signal connection line 412 extends along a first direction Y. The signal connection line 412 is electrically connected to the first signal line 411.

[0140] like Figure 4 As shown, the conductive structure 40 adopts a mesh structure, which includes a portion extending along the first direction Y (i.e., signal connection line 412) and a portion extending along the second direction X (i.e., first signal line 411).

[0141] like Figure 4 As shown, the conductive structure 40 includes a conductive structure 400, a conductive structure 401, and a conductive structure 402. For example... Figure 4 As shown, the first power line PL1 can be called conductive structure 400, the initialization line INT1 can be called conductive structure 401, and the initialization line INT2 can be called conductive structure 402.

[0142] like Figure 4 As shown, the first power line PL1 includes a first power signal line PL11 extending along the second direction X and a first power connection line PL12 extending along the first direction Y. The first power signal line PL11 and the first power connection line PL12 are connected.

[0143] like Figure 4 As shown, the initialization line INT1 includes an initialization signal line INT11 extending along the second direction X and an initialization connection line INT12 extending along the first direction Y. The initialization signal line INT11 and the initialization connection line INT12 are connected. Figure 4 As shown, the initialization signal line INT11 and the initialization connection line INT12 are connected through the via Vj.

[0144] like Figure 4 As shown, the initialization line INT2 includes an initialization signal line INT21 extending along the second direction X and an initialization connection line INT22 extending along the first direction Y. The initialization signal line INT21 and the initialization connection line INT22 are connected. Figure 4 As shown, the initialization signal line INT21 and the initialization connection line INT22 are connected through via Vi.

[0145] like Figure 4As shown, the pixel circuit 100a uses two conductive pattern layers to form the first power line PL1, initialization line INT1, initialization line INT2, and capacitor 20. The portions of the first power line PL1, initialization line INT1, and initialization line INT2 extending along the first direction Y are all segmented. The portions of the first power line PL1, initialization line INT1, and initialization line INT2 extending along the second direction X are all located in the second conductive pattern layer LY2.

[0146] For example, such as Figure 4 As shown, signal connection line 412 includes a first portion 412a, a second portion 412b, and a third portion 412c. The first portion 412a and the third portion 412c are connected through the second portion 412b. The first portion 412a and the third portion 412c are located in the first conductive pattern layer LY1, and the second portion 412b is located in the second conductive pattern layer LY2. Signal connection line 412 includes at least one of a first power connection line PL12, an initialization connection line INT12, and an initialization connection line INT22.

[0147] like Figure 4 As shown, the first and second parts of the first power connection line PL12 are connected through via Va, and the second and third parts of the first power connection line PL12 are connected through via Vb.

[0148] like Figure 4 As shown, the first part DTa and the second part DTb of the data line DT are connected through via Vc, and the second part DTb and the third part DTc of the data line DT are connected through via Vd.

[0149] like Figure 4 As shown, the first and second parts of the initialization connection line INT22 are connected through via Ve, and the second and third parts of the initialization connection line INT22 are connected through via Vf.

[0150] like Figure 4 As shown, the first and second parts of the initialization connection line INT12 are connected through via Vg, and the second and third parts of the initialization connection line INT12 are connected through via Vh.

[0151] For example, such as Figure 4 As shown, the data line DT extends along the first direction Y. The data line DT is also segmented. The data line DT includes a first part DTa, a second part DTb and a third part DTc. The first part DTa and the third part DTc are connected through the second part DTb. The first part DTa and the third part DTc are located in the first conductive pattern layer LY1, and the second part DTb is located in the second conductive pattern layer LY2.

[0152] Figure 8 A layout diagram of a display substrate is provided for one embodiment of this disclosure. Figure 8 The display substrate DS2 is shown.

[0153] Figure 8 The display substrate DS2 shown is Figure 4 Compared to the display substrate DS1 shown, the size of the opening P0 in the pixel definition layer PDL has been adjusted. For example... Figure 8 As shown, the size of the opening P0 of the third sub-pixel 103 along the second direction X is larger than the size of the opening P0 of the second sub-pixel 102 along the second direction X, and larger than the size of the opening P0 of the first sub-pixel 101 along the second direction X. Figure 8 As shown, the size of the opening P0 of the third sub-pixel 103 along the second direction X is larger than the size of the opening P0 of the first sub-pixel 101 along the second direction X, and the size of the opening P0 of the first sub-pixel 101 along the second direction X is larger than the size of the opening P0 of the second sub-pixel 102 along the second direction X.

[0154] Figure 8 The display substrate DS2 shown is Figure 4 Compared to the display substrate DS1 shown, the size of the opening P0 of the second sub-pixel 102 along the second direction X is adjusted to facilitate increasing the size of the opening P0 of the third sub-pixel 103 along the second direction X.

[0155] like Figure 8 As shown, the orthographic projection of the opening P0 of the second sub-pixel 102 on the substrate does not overlap with the orthographic projection of the second part of the initialization line INT1 (the part of the initialization connection line INT12 located in the second conductive pattern layer LY2) on the substrate, and also does not overlap with the orthographic projection of the second part of the initialization line INT2 (the part of the initialization connection line INT22 located in the second conductive pattern layer LY2) on the substrate.

[0156] Figure 8 The display substrate DS2 shown is Figure 4 Compared to the display substrate DS1 shown, in the second direction X, the two opposite edges of the opening P0 of the third sub-pixel 103 extend to the left and right respectively. For example, in the second direction X, one of the two opposite edges of the opening P0 of the third sub-pixel 103 extends beyond the data line providing the data signal of the third sub-pixel 103, and the other of the two opposite edges of the opening P0 of the third sub-pixel 103 extends beyond or is flush with the first power connection line PL12 overlapping with the third sub-pixel 103. Of course, in other embodiments, the other of the two opposite edges of the opening P0 of the third sub-pixel 103 overlaps with the first power connection line PL12 overlapping with the third sub-pixel 103. Thus, it is beneficial to reduce color shift in the left and right viewing angles of the display substrate.

[0157] like Figure 4 and Figure 8 As shown, the data line DT includes data line DT1, data line DT2, and data line DT3. Data line DT1 provides a data signal to the first sub-pixel 101, data line DT2 provides a data signal to the second sub-pixel 102, and data line DT3 provides a data signal to the third sub-pixel 103.

[0158] Figure 9A A plan view of a pixel-defining layer in a display substrate provided for an embodiment of this disclosure. Figure 9B A plan view of a pixel-defining layer in a display substrate provided for embodiments of this disclosure. For example, such as Figure 9A and Figure 9B As shown, the pixel limiting layer (PDL) includes a plurality of first limiting portions 301 and a plurality of second limiting portions 302. The plurality of second limiting portions 302 are arranged along a second direction X and extend along a first direction Y. The plurality of first limiting portions 301 are configured as a plurality of groups 0301. Each group of first limiting portions 301 is located between two adjacent second limiting portions 302. The first limiting portions 301 extend along the second direction X and the first limiting portions 301 in each group are arranged along the first direction Y.

[0159] like Figure 5 , Figure 9A and Figure 9B As shown, the maximum height h1 of the first limiting part 301 to the planarization layer is less than the maximum height h2 of the second limiting part 302 to the planarization layer.

[0160] Figure 10 This is a schematic diagram of a display substrate provided according to an embodiment of the present disclosure. Figure 10 As shown, the substrate BS includes a display area R01 and a peripheral area R02 located on at least one side of the display area R01. Figure 10 As shown, the orthographic projection of the portion DT01 of the data line DT located in the display area R01 onto the substrate BS lies within the orthographic projection of the second limiting portion 302 onto the substrate BS. Figure 10 As shown, the orthographic projection of the display area R01 on the substrate BS overlaps with the orthographic projection of the pixel defining layer PDL on the substrate BS. The orthographic projection of the opening P0 of the pixel defining layer PDL on the substrate BS falls within the orthographic projection of the display area R01 on the substrate BS.

[0161] Figure 10 Only two data lines DT are shown. For example, the second limiting part 302 may correspond to one data line, but it is not limited to this.

[0162] In embodiments of this disclosure, the pixel circuitry is not limited to... Figure 3As shown, other suitable pixel circuits can be used, and the layout of the display substrate is not limited to... Figure 4 and Figure 8 As shown, it is possible to Figure 4 and Figure 8 Based on this, adjustments can be made, or other layout methods can be adopted. For example, Figure 4 The positions of the initialization connection lines INT12 and INT22 of the initialization line INT1 and INT2 can be interchanged.

[0163] like Figure 4 and Figure 5 As shown, an embodiment of the present disclosure provides a display substrate, which includes a substrate BS and a plurality of sub-pixels 100 disposed on the substrate BS.

[0164] For example, such as Figure 4 and Figure 5 As shown, the sub-pixel 100 includes: a pixel circuit 100a, the pixel circuit 100a including a storage capacitor 20, the first electrode 201 being closer to the substrate BS than the second electrode 202; and a light-emitting element 100b, the light-emitting element 100b including a first electrode E1, a second electrode E2 and a light-emitting functional layer FL located between the first electrode E1 and the second electrode E2, the pixel circuit 100a being configured to drive the light-emitting element 100b.

[0165] Figure 11 A plan view of a display substrate provided for an embodiment of this disclosure. For example, such as... Figure 11 As shown, the orthographic projection of the opening P0 on the substrate BS overlaps with the orthographic projection of the second electrode plate 202 on the substrate BS.

[0166] For example, such as Figure 11 As shown, the second electrode 202 includes a first edge CL1 extending along the first direction Y and a second edge CL2 extending along the first direction Y. The opening P0 includes a first edge KL1 extending along the first direction Y and a second edge KL2 extending along the first direction Y. The first edge CL1 of the second electrode 202 is closer to the first edge KL1 of the opening P0 than the second edge CL2 of the second electrode 202. The second edge CL2 of the second electrode 202 is closer to the second edge KL2 of the opening P0 than the first edge CL1 of the second electrode 202.

[0167] For example, such as Figure 11 As shown, the second electrode plate 202 also includes a third edge CL3 extending along the second direction X and a fourth edge CL4 extending along the second direction X, and the opening P0 includes a third edge KL3 extending along the second direction X and a fourth edge KL4 extending along the second direction X.

[0168] like Figure 11 As shown, the orthographic projection of the third edge CL3 on the substrate is located outside the orthographic projection of the opening P0 on the substrate.

[0169] like Figure 11 As shown, the orthographic projection of the fourth edge CL4 onto the substrate lies within the orthographic projection of the opening P0 onto the substrate.

[0170] like Figure 11 As shown, the first edge CL1 and the second edge CL2 are positioned opposite each other, and the third edge CL3 is connected to the first edge CL1 and the second edge CL2 by rounded corners. The third edge CL3 and the fourth edge CL4 are positioned opposite each other, and the fourth edge CL4 is connected to the first edge CL1 and the second edge CL2 by rounded corners. Of course, in other embodiments, adjacent edges of the opening may not be connected by rounded corners.

[0171] Figure 12 A schematic diagram of the center pixel of a display substrate provided for an embodiment of this disclosure. Figure 13 for Figure 12 A cross-sectional view along line B1-B2. Figure 14 This is a schematic diagram showing the coordinate distance between chromaticity coordinate points on a display substrate from two different viewing angles.

[0172] Figure 12 The center pixel PXc is shown. For example, the center pixel PXc is the pixel PX located at the center of the display area R01.

[0173] For example, a non-contact spectrometer, such as the PR630, 730, CS2000, or 2000A, can be used to randomly sample (at least 10 panels, selecting the worst data) of the display panels (display substrates) under test in a dark room environment (illuminance below 1 lx). The test point is the center pixel of the display panel. The u' and v' coordinates of this point in the 1976 UV chromaticity coordinate system for the four colors RBGW are read. Measurements are performed at nine viewing angles: 0 degrees, ±15 degrees, ±30 degrees, ±45 degrees, and ±60 degrees. The u' and v' values ​​at each angle are obtained. Color shift at a -60 degree viewing angle is used as an example.

[0174]

[0175] u2' and v2' are the chromaticity coordinates at a -60 degree viewing angle. u1' and v1' are the chromaticity coordinates at a 0 degree viewing angle.

[0176] Substituting into the formula yields Δu'v' for -60 degrees; similarly, Δu'v' for 60 degrees is calculated. By optimizing the structure of the display substrate, the difference between two values ​​for the four colors (RGBW) can be less than 0.0015, and the Δu'v' value at each angle can be less than 0.025. The first sub-pixel 101 is a red-emitting sub-pixel, the second sub-pixel 102 is a green-emitting sub-pixel, and the third sub-pixel 103 is a blue-emitting sub-pixel. When measuring the color shift of white light, the first sub-pixel 101, the second sub-pixel 102, and the third sub-pixel 103 in the center pixel PXc are all lit.

[0177] The uniform color space CIE1976 is derived from CIE1931 XYZ.

[0178] The CIE1976 Luv calculation formula includes:

[0179]

[0180] In the formula, u' and v' are the chromaticity coordinates of the color sample, and X, Y, and Z are the tristimulus values ​​of the sample.

[0181] It should be noted that color shift measurement methods are not limited to those described above, and the measuring instruments used are not limited to the few listed. The same measuring instrument can be used to measure the chromaticity coordinates at different viewing angles, and the coordinate distance between the chromaticity coordinate points at each viewing angle and the chromaticity coordinate point at the 0-degree viewing angle can be obtained.

[0182] The embodiments disclosed herein are illustrated by taking the measurement of the color shift of the center pixel PXc as an example. Of course, the color shift of each sub-pixel in other suitable pixels can also be measured.

[0183] Figure 14 The coordinate distance between chromaticity coordinate points P2 and P1 is shown. For example... Figure 14 As shown, x0 is the x-coordinate distance between chromaticity coordinate points P2 and P1, y0 is the y-coordinate distance between chromaticity coordinate points P2 and P1, and z0 is the x-coordinate distance between chromaticity coordinate points P2 and P1.

[0184] For example, the coordinate distance between two chromaticity coordinate points from two different viewpoints is the square root of the sum of the squares of the differences in the x-coordinates and the squares of the differences in the y-coordinates of the two chromaticity coordinate points.

[0185] For example, such as Figure 11 As shown, sub-pixel 100 satisfies the following formula:

[0186] △U=|U02-U01|≤k×|Xb-Xa| / KW,

[0187] Where k is the color shift influence coefficient, 0.009≤k≤0.03, △U<0.0020, Xa is the minimum distance between the first edge CL1 of the second electrode plate 202 and the first edge KL1 of the opening P0 in the second direction X, Xb is the minimum distance between the second edge CL2 of the second electrode plate 202 and the second edge KL2 of the opening P0 in the second direction X, the first direction Y and the second direction X intersect; KW is the maximum size of the opening P0 in the second direction X, U01 is the coordinate distance between the chromaticity coordinate point in the first viewing angle and the chromaticity coordinate point in the 0-degree viewing angle, U02 is the coordinate distance between the chromaticity coordinate point in the second viewing angle and the chromaticity coordinate point in the 0-degree viewing angle, △U is the absolute value of the difference between U02 and U01, the chromaticity coordinate point in the 0-degree viewing angle is the chromaticity coordinate point at the normal line where the center of the display substrate is located, the first viewing angle and the second viewing angle are respectively located on opposite sides of the normal line and the included angle with the normal line is equal in value.

[0188] Figure 13 The normal L0 of the center of the display substrate is shown. The normal L0 is parallel to the third direction Z. Figure 13 The first viewpoint VW1 and the second viewpoint VW2 are shown. The angle between the first viewpoint VW1 and the normal L0 is +θ, and the angle between the second viewpoint VW2 and the normal L0 is -θ. Under the positive viewpoint θ, the rotation from the normal L0 to this viewpoint is clockwise by an angle θ, and under the negative viewpoint -θ, the rotation from the normal L0 to this viewpoint is counterclockwise by an angle θ.

[0189] Figure 12 and Figure 13 The situation shown is used to measure the color shift of the left and right viewpoints. When measuring the color shift of the up and down viewpoints, the first viewpoints VW1 and VW2 are set on both sides of the normal L0 in the first direction Y.

[0190] For example, U02 < 0.020, U01 < 0.020, ΔU < 0.0015.

[0191] For example, the first edge KL1 of the opening P0, the first edge CL1 of the second electrode 202, the second edge CL2 of the second electrode 202, and the second edge KL2 of the opening P0 are arranged sequentially along the second direction X. The minimum distance between the first edge CL1 of the second electrode 202 and the second edge CL2 of the second electrode 202 in the second direction X is Xc, where Xc / Xa > 1.5 or Xc / Xb > 1.5.

[0192] For example, the first sub-pixel 101 satisfies the following formula:

[0193] △U1=|U2-U1|≤k1×|X2-X1| / KW1,

[0194] Where k1 is a coefficient, 0.009≤k1≤0.02, X1 is the minimum distance between the first edge CL1 of the second pole plate 202 in the first sub-pixel 101 and the first edge KL1 of the opening P0 of the first sub-pixel 101 in the second direction X; X2 is the minimum distance between the second edge CL2 of the second pole plate 202 in the first sub-pixel 101 and the second edge KL2 of the opening P0 of the first sub-pixel 101 in the second direction X; KW1 is the maximum size of the opening P0 of the first sub-pixel 101 in the second direction X; U1 is the coordinate distance between the chromaticity coordinate point of the first sub-pixel 101 in the first viewing angle and the chromaticity coordinate point in the 0-degree viewing angle; U2 is the coordinate distance between the chromaticity coordinate point of the first sub-pixel 101 in the second viewing angle and the chromaticity coordinate point in the 0-degree viewing angle; and ΔU1 is the absolute value of the difference between U2 and U1.

[0195] For example, the second sub-pixel 102 satisfies the following formula:

[0196] △U2=|U4-U3|≤k2×|X4-X3| / KW2,

[0197] Wherein, k2 is a coefficient, 0.004≤k2≤0.02; X3 is the minimum distance in the second direction X between the first edge CL1 of the second pole plate 202 in the second sub-pixel 102 and the first edge KL1 of the opening P0 of the second sub-pixel 102; X4 is the minimum distance in the second direction X between the second edge CL2 of the second pole plate 202 in the second sub-pixel 102 and the second edge KL2 of the opening P0 of the second sub-pixel 102; KW2 is the maximum size of the opening P0 of the second sub-pixel 102 in the second direction X; U3 is the coordinate distance between the chromaticity coordinate point of the second sub-pixel 102 in the first viewing angle and the chromaticity coordinate point in the 0-degree viewing angle; U4 is the coordinate distance between the chromaticity coordinate point of the second sub-pixel 102 in the second viewing angle and the chromaticity coordinate point in the 0-degree viewing angle; and ΔU2 is the absolute value of the difference between U4 and U3.

[0198] For example, the ratio of k2 to k1 is less than 10 and greater than 0.1.

[0199] For example, the third sub-pixel 103 satisfies the following formula:

[0200] △U3=|U6-U5|≤k3×|X6-X5| / KW3,

[0201] Wherein, k3 is a coefficient, 0.01≤k3≤0.03; X5 is the minimum distance in the second direction X between the first edge CL1 of the second pole plate 202 in the third sub-pixel 103 and the first edge KL1 of the opening P0 of the third sub-pixel 103; X6 is the minimum distance in the second direction X between the second edge CL2 of the second pole plate 202 in the third sub-pixel 103 and the second edge KL2 of the opening P0; KW3 is the maximum size of the opening P0 of the third sub-pixel 103 in the second direction X; U5 is the coordinate distance between the chromaticity coordinate point of the third sub-pixel 103 in the first viewing angle and the chromaticity coordinate point in the 0-degree viewing angle; U6 is the coordinate distance between the chromaticity coordinate point of the third sub-pixel 103 in the second viewing angle and the chromaticity coordinate point in the 0-degree viewing angle; and △U3 is the absolute value of the difference between U6 and U5.

[0202] For example, such as Figure 11 As shown, the display substrate also includes a data line DT, which is configured to provide a data voltage to the sub-pixel 100. The orthographic projection of at least one of the signal connection line 412 and the data line DT on the substrate BS overlaps with the orthographic projection of the opening P0 of at least one of the plurality of sub-pixels 100 on the substrate BS. Figure 11 The orthographic projection of signal connection line 412 on substrate BS overlaps with the orthographic projection of opening P0 of sub-pixel 100 on substrate BS. See also Figure 8 For the third sub-pixel 103, the orthographic projection of the data line DT (data line DT3) on the substrate BS overlaps with the orthographic projection of the opening P0 of the sub-pixel 100 on the substrate BS.

[0203] When inkjet printing is performed, the flatter the bottom surface of the opening P0 of the sub-pixel 100 (i.e., the first electrode E1 of the light-emitting element), the more color deviation can be reduced or avoided, and the better the display effect of the display substrate.

[0204] The portion of the data cable DT or signal cable 412 located directly below the opening P0 can act as a leveling element to improve display quality.

[0205] For example, signal connection line 412 includes at least one of the portion of the first power line PL1 extending along the first direction Y and the portion of the initialization line extending along the first direction Y.

[0206] For example, such as Figure 11 As shown, signal connection line 412 and first signal line 411 are connected through via H0.

[0207] For example, such as Figure 4 and Figure 11As shown, to level the bottom surface of the opening P0 of the sub-pixel 100, the display substrate further includes a second signal line 502. The second signal line 502 is configured to provide a voltage signal to the sub-pixel 100. The second signal line 502 extends along a second direction X, and its orthographic projection on the substrate BS overlaps with the orthographic projection of the opening P0 of at least one of the sub-pixels 100 on the substrate BS. This facilitates longitudinal ink leveling during inkjet printing and reduces color shift at different viewing angles.

[0208] For example, refer to Figure 4 and Figure 8 The second signal line 502 includes at least one of gate line G1, gate line G2, and an initialization signal line INT1 extending along the second direction X.

[0209] For example, refer to Figure 4 and Figure 11 To balance improving PPI and reducing or avoiding color shift, the overlap dimension between signal connection line 412 and opening P0 in the second direction X is less than 10% of the line width of signal connection line 412, or the overlap dimension between data line DT and opening P0 in the second direction X is less than 10% of the line width of data line DT. The line width of a conductor refers to the dimension perpendicular to the direction of extension of the conductor.

[0210] For example, such as Figure 4 As shown, in the planar view, the size of the portion of the opening P0 of the first sub-pixel 101 that overlaps with the initialization connection line INT12 in the second direction X is less than 10% of the line width of the initialization connection line INT12.

[0211] For example, such as Figure 4 As shown, in the planar view, the size of the portion of the opening P0 of the second sub-pixel 102 that overlaps with the initialization connection line INT22 in the second direction X is less than 10% of the line width of the initialization connection line INT22.

[0212] For example, refer to Figure 5 The display substrate also includes an insulating layer ISL and vias VH penetrating the insulating layer ISL. The vias VH include a first via VH1, a second via VH2, and a third via VH3. (Reference) Figure 4 and Figure 8 The first electrodes E1 of the light-emitting elements 100b of the first sub-pixel 101, the second sub-pixel 102, and the third sub-pixel 103 are respectively connected to the pixel circuits 100a of the first sub-pixel 101, the second sub-pixel 102, and the third sub-pixel 103 through the first via VH1, the second via VH2, and the third via VH3.

[0213] In the accompanying drawings of the embodiments of this disclosure, the example given is that the orthographic projection of the sub-pixel opening P0 on the substrate and the orthographic projection of the via VH on the substrate do not overlap. However, in other embodiments, the orthographic projection of the sub-pixel opening P0 on the substrate and the orthographic projection of the via VH on the substrate may overlap.

[0214] For example, in embodiments of this disclosure, the design of the backplane film layer, such as the design of the elements in the second conductive pattern layer, can be used to adapt the openings of different sizes of sub-pixels to improve the flatness of the light-emitting functional layer and thereby reduce the color shift of the display substrate from the left and right viewing angles.

[0215] Since subpixels emitting different colors of light have different luminous efficiencies, color shift and display quality can be reduced by adjusting the size of the subpixel opening, adjusting the size of the second plate of the capacitor, and making the opening and signal lines overlap.

[0216] Figure 15A This is a schematic diagram of a display substrate provided in an embodiment of the present disclosure. Figure 15A The display substrate DS3 is shown. (As shown...) Figure 15A As shown, in the display substrate DS3, the size of the second electrode plate 202 of the first sub-pixel 101 in the second direction X is reduced. The size of the second electrode plate 202 of the first sub-pixel 101 in the second direction X is smaller than the size of the second electrode plate 202 of the second sub-pixel 102 in the second direction X, and smaller than the size of the second electrode plate 202 of the third sub-pixel 103 in the second direction X. For example, the size of the second electrode plate 202 of the second sub-pixel 102 in the second direction X can be equal to or smaller than the size of the second electrode plate 202 of the third sub-pixel 103 in the second direction X.

[0217] like Figure 15A As shown, in the display substrate DS3, the size of the opening P0 of the first sub-pixel 101 in the second direction X is reduced. The size of the opening P0 (opening P01) of the first sub-pixel 101 in the second direction X is smaller than the size of the opening P0 (opening P02) of the second sub-pixel 102 in the second direction X, and smaller than the size of the opening P0 (opening P03) of the third sub-pixel 103 in the second direction X.

[0218] like Figure 15A As shown, the areas of openings P01, P02, and P03 are all different. That is, the areas of opening P0 of the first sub-pixel 101, the second sub-pixel 102, and the third sub-pixel 103 are all different.

[0219] For example, the area of ​​opening P03 is larger than the area of ​​opening P01, and the area of ​​opening P01 is larger than the area of ​​opening P02, but it is not limited to this.

[0220] like Figure 15A As shown, in the display substrate DS3, the lateral dimensions of the opening P0 of the first sub-pixel 101 and the capacitor 20 are both reduced, the lateral dimension of the opening P0 of the third sub-pixel 101 is increased, and the left and right sides of the third sub-pixel 101 are flattened by signal lines.

[0221] refer to Figure 4 and Figure 15A The orthographic projection of the opening P0 of the third sub-pixel 101 on the substrate overlaps with the orthographic projection of the data line DT on the substrate, and also overlaps with the orthographic projection of the first power line PL1 on the substrate.

[0222] like Figure 15A As shown, neither the opening P0 of the first sub-pixel 101 nor the opening P0 of the second sub-pixel 101 on the left and right sides is flattened by signal lines. In other embodiments, the size of the opening P0 can be adjusted so that the orthographic projection of the opening P0 of the second sub-pixel 102 on the substrate overlaps with the orthographic projection of the initialization signal line INT2 (initialization signal connection line INT22) on the substrate, and / or, the orthographic projection of the opening P0 of the first sub-pixel 101 on the substrate overlaps with the orthographic projection of the initialization signal line INT1 (initialization signal connection line INT12) on the substrate, thereby making one side of the opening P0 of the second sub-pixel 102 and the opening P0 of the first sub-pixel 101 flattened by signal lines (e.g., Figure 4 (As shown).

[0223] Figure 15B This is a schematic diagram of a display substrate provided in an embodiment of the present disclosure. Figure 15B The display substrate DS4 is shown. (As shown...) Figure 15B As shown, in the display substrate DS4, in order to improve PPI, the orthographic projection of the opening P0 of the first sub-pixel 101 on the substrate overlaps with the orthographic projection of the initialization signal line INT1 (initialization signal connection line INT12) on the substrate. The size of the overlapping portion of the opening P0 of the first sub-pixel 101 and the initialization connection line INT12 in the second direction X is less than 10% of the line width of the initialization connection line INT12.

[0224] For example, in embodiments of this disclosure, the backplane film layer design, such as the via VH design for connecting the first electrode of the light-emitting element and the pixel circuit, can be used to adapt to the openings of different sizes of the sub-pixels, thereby improving the flatness of the light-emitting functional layer and reducing the color shift of the display substrate from the left and right viewing angles.

[0225] Figure 16 This is a schematic diagram of a display substrate provided in one embodiment of this disclosure. Figure 16As shown, the distance between the first via VH1 and the second via VH2 is KX1, and the distance between the second via VH2 and the third via VH3 is KX2, wherein the ratio of KX1 / KX2 is 0.75-1.25.

[0226] For example, the ratio of KX1 / KX2 is not 1. This balances etching process uniformity with reducing color shift in the display substrate. After widening the opening of the third sub-pixel 103 laterally, the openings of the first sub-pixel 101 and the second sub-pixel 102 are appropriately adjusted so that KX1 and KX2 are not equal.

[0227] like Figure 16 As shown, the distance between the third via VH3 and the first via VH1 is KX3, where the ratio of KX2 / KX3 is 0.75-1.25.

[0228] For example, the spacing KX3 is not equal to the spacing KX1, and the spacing KX3 is not equal to the spacing KX2.

[0229] For example, such as Figure 16 As shown, the distance DV between the axis of symmetry AXa extending along the first direction Y of the via VH and the axis of symmetry AXb extending along the first direction Y of the opening P0 closest to the via VH is less than 8 micrometers, and the diameter of the via VH is 8-17 micrometers. The distance DV represents the offset design of the via VH. For example, the thickness of the planarization layer PLN is 3-7 micrometers. For example, by controlling the thickness of the planarization layer, the diameter of the via VH, and the distance DV, color shift can be reduced.

[0230] For example, in embodiments of this disclosure, the thickness of an element refers to the dimension of the element in a direction perpendicular to the substrate.

[0231] For example, such as Figure 16 As shown, the orthographic projection of the via VH on the substrate does not overlap with the orthographic projection of the opening P0 on the substrate. The via VH and the opening P0 closest to the via VH are spaced apart from each other in the first direction Y.

[0232] For example, such as Figure 16 As shown, the size of the opening P0 of the first sub-pixel 101 in the second direction X is 28-36 micrometers, the size of the opening P0 of the second sub-pixel 102 in the second direction X is 30-38 micrometers, and the size of the opening P0 of the third sub-pixel 103 in the second direction X is 68-74 micrometers.

[0233] refer to Figure 9A The via VH is located on the axis of symmetry of the opening P0 extending along the first direction Y. That is, the via VH is not offset.

[0234] refer to Figure 9BThe via VH is not located on the axis of symmetry extending along the first direction Y of the opening P0. That is, the via VH is offset. Figure 16 The via VH in the design was also offset.

[0235] For example, in embodiments of this disclosure, the design of the backplane film layer, such as the design of the elements in the second conductive pattern layer, and the design of the via VH for connecting the first electrode of the light-emitting element and the pixel circuit, can be used to adapt the openings of different sizes of the sub-pixels, thereby improving the flatness of the light-emitting functional layer and reducing the color shift of the display substrate from the left and right viewing angles.

[0236] For example, refer to Figure 5 The insulating layer ISL comprises a passivation layer PVX and a planarization layer PLN. The passivation layer PVX is made of inorganic insulating materials, while the planarization layer PLN is made of organic insulating materials. For example, the thickness of the planarization layer PLN is 3-7 micrometers.

[0237] For example, the display substrate satisfies the following formula:

[0238] 1 / k=F1(CW / KW)-F2(DV / KW)+F3(DW / KW),

[0239] Wherein, F1 is the capacitance influence coefficient, F2 is the via offset influence coefficient, F3 is the signal line influence coefficient, CW is the maximum dimension of the second plate 202 of the storage capacitor 20 in the second direction X, CW / KW is the proportion of the storage capacitor 20 to the opening P0, DV is the distance between the axis of symmetry of the via extending along the first direction Y and the axis of symmetry of the opening P0 closest to the via extending along the first direction Y, and DW is the line width of the signal line, which includes the signal connection line 412. For example, as... Figure 4 As shown, signal connection line 412 includes one of the following: a portion of the first power line PL1 extending along the first direction Y; a portion of the first initialization line INT1 extending along the first direction Y; and a portion of the second initialization line INT2 extending along the first direction Y. That is, signal connection line 412 includes one of the first power line PL12, the first initialization connection line INT12, and the second initialization connection line INT22.

[0240] Figure 17 This is a schematic diagram illustrating the color shift of a display substrate provided for an embodiment of this disclosure. (See diagram below.) Figure 17As shown, compared to a smaller viewing angle, the color shift of the display substrate is more severe at a larger viewing angle. The color shift of the third sub-pixel is greater than that of the second sub-pixel, and the color shift of the second sub-pixel is greater than that of the first sub-pixel. The embodiments disclosed herein, through a backplane design, improve the color shift of the display substrate at larger viewing angles, resulting in U02 < 0.020, U01 < 0.020, and ΔU < 0.0015, thereby reducing color shift and improving display quality.

[0241] The display substrate provided in the embodiments of this disclosure can reduce color shift at left and right viewing angles to less than 0.015, in which case T is greater than 70. Furthermore, in the display substrate provided in the embodiments of this disclosure, by making the opening of the sub-pixel overlap with the signal connection line (designing the position of the vertical wiring), the color shift problem of the second sub-pixel (green sub-pixel) is significantly improved, with a deviation of only 0.0041 at left and right 60-degree viewing angles.

[0242] For example, the flatness of the light-emitting functional layer can be improved by adjusting at least one of the following: adjusting the positional relationship between the electrode plate of the capacitor near the opening of the sub-pixel and the opening; offsetting the position of the via for connecting the first electrode of the light-emitting element and the pixel circuit; and overlapping the signal line with the opening of the sub-pixel. This can reduce or avoid color shift. Further, for example, color shift in the left and right viewing angles can be reduced or avoided by using at least one of the designs given above.

[0243] For example, the display substrate satisfies the following formula:

[0244] 1 / T = k × (CW - DV + DW) / KW, where 1 / T is the color cast improvement coefficient. The first sub-pixel 101 satisfies 1 / T1 = k1 × (CW - DV + DW) / KW, the second sub-pixel 102 satisfies 1 / T2 = k2 × (CW - DV + DW) / KW, and the third sub-pixel 103 satisfies 1 / T3 = k3 × (CW - DV + DW) / KW, where 1 / T1 < 0.019, 1 / T2 < 0.019, and 1 / T3 < 0.019.

[0245] For example, after increasing the lateral dimension of the opening of the third sub-pixel, the size of the capacitor is not increased. Instead, the portion of the first power line PL1 extending along the first direction Y (the second part of the first power connection line PL12) is widened. While ensuring that the via VH is located as close to the center line as possible, the left and right sides of the opening of the third sub-pixel are flattened with signal lines, so that 1 / T3 < 0.019 and the color shift of the third sub-pixel at 45-degree and 60-degree viewing angles is less than 0.025.

[0246] For example, the ratio of any two of the storage capacitors 20 of the first sub-pixel 101, the storage capacitors 20 of the second sub-pixel 102, and the storage capacitors 20 of the third sub-pixel 103 is in the range of 0.8-1.2.

[0247] For example, 1 / T1 < 0.009, 1 / T2 < 0.014, 1 / T3 < 0.019.

[0248] For example, 1 / T1 < 0.008, 1 / T2 < 0.003, 1 / T3 < 0.016.

[0249] For example, for the third sub-pixel, while ensuring that the via VH is located as close to the center line as possible, and with the left and right sides of the opening of the third sub-pixel being padded with signal lines respectively, the width of the plate of the storage capacitor of the third sub-pixel can be further increased so that 1 / T3 < 0.016, thereby making the color shift less than 0.023.

[0250] For 1 / T2, since the deviation of the via VH from the opening P0 of the second sub-pixel 102 along the axis of symmetry (central axis) in the first direction Y is approximately 0.5 micrometers, and the size (lateral dimension) of the opening P0 of the second sub-pixel 102 in the second direction X is the smallest, for example, the CW / KW value of the second sub-pixel is greater than the CW / KW value of the first sub-pixel, and the CW / KW value of the first sub-pixel is greater than the CW / KW value of the third sub-pixel. For example, X4-X3 is less than X6-X5 is less than X2-X1, resulting in color shifts of only 0.0004 and 0.0002 for the second sub-pixel at 45-degree and 60-degree viewing angles, respectively. KW is the maximum size of the opening P0 in the second direction X, CW is the maximum size of the second plate 202 of the storage capacitor 20 in the second direction X, and CW / KW is the proportion of the storage capacitor 20 to the opening P0.

[0251] For example, 1 / T1 < 0.008, 1 / T2 < 0.010, 1 / T3 < 0.013.

[0252] For example, the widths of the first and second plates of the storage capacitor of the third sub-pixel can be further increased, i.e., the size of the second plate of the storage capacitor of the third sub-pixel in the second direction X can be increased. For example, the ratio of the size of the second plate of the storage capacitor of the third sub-pixel in the second direction X to the size of the second plate of the storage capacitor of the first or second sub-pixel in the second direction X is greater than 1.4, and the CW / KW values ​​of the second sub-pixel, the first sub-pixel, and the third sub-pixel are all between 0.8 and 1.2. This takes into account the color shift of the first sub-pixel 101, the second sub-pixel 102, and the third sub-pixel 103, and avoids the widening of the differences between 1 / T1, 1 / T2, and 1 / T3.

[0253] For example, 0.2 < Tx / Ty < 6, where Tx is one of T1, T2, and T3, and Ty is one of T1, T2, and T3.

[0254] For example, 1 < Tx / Ty < 6, where Tx is one of T1, T2, and T3, and Ty is one of the other two of T1, T2, and T3.

[0255] For example, 4 < Tx / Ty < 6, where Tx is one of T1, T2, and T3, and Ty is one of the other two of T1, T2, and T3.

[0256] For example, under the O-view and -O-view, the first sub-pixel 101 satisfies 1 / T11 = k11 × (CW - DV + DW) / KW; under the P-view and -P-view, the first sub-pixel 101 satisfies 1 / T12 = k12 × (CW - DV + DW) / KW, 1 / T11 < 0.009, 1 / T12 < 0.008. Further, for example, 1 / T11 < 0.007, 1 / T12 < 0.006. In some embodiments, 1 / T11 < 0.005, 1 / T12 < 0.004.

[0257] For example, |1 / T12-1 / T11| < 0.001. Further, for example, |1 / T12-1 / T11| < 0.0005.

[0258] For example, under the O-view and -O-view, the second sub-pixel 102 satisfies 1 / T21=k21×(CW-DV+DW) / KW; under the P-view and -P-view, the second sub-pixel 102 satisfies 1 / T22=k22×(CW-DV+DW) / KW, 1 / T21<0.014, 1 / T22<0.004.

[0259] For example, |1 / T22-1 / T21| < 0.010. Further, for example, |1 / T22-1 / T21| < 0.005.

[0260] For example, 1 / T21 < 0.010, 1 / T22 < 0.004. For example, 1 / T21 < 0.009, 1 / T22 < 0.003. In some embodiments, 1 / T21 < 0.008, 1 / T22 < 0.002. Further, for example, 1 / T21 < 0.005, 1 / T22 < 0.005.

[0261] For example, under the O-view and -O-view, the third sub-pixel 103 satisfies 1 / T31 = k31 × (CW - DV + DW) / KW; under the P-view and -P-view, the third sub-pixel 103 satisfies 1 / T32 = k32 × (CW - DV + DW) / KW, 1 / T31 < 0.016, 1 / T32 < 0.019. Further, for example, 1 / T31 < 0.010, 1 / T32 < 0.015. In some embodiments, 1 / T31 < 0.008, 1 / T32 < 0.010.

[0262] For example, |1 / T32-1 / T31| < 0.003. Further, for example, |1 / T32-1 / T31| < 0.0015.

[0263] For example, 1 / T31 < 0.012, 1 / T32 < 0.014.

[0264] For example, in some embodiments, the O-angle and -O-angle are 60-degree and -60-degree angles, respectively, and the P-angle and -P-angle are 45-degree and -45-degree angles, respectively.

[0265] For example, such as Figure 5 As shown, the first conductive pattern layer LY1 is closer to the substrate BS than the second conductive pattern layer LY2.

[0266] Because the slope angle of the components in the first conductive pattern layer LY1 is smaller than that of the components in the second conductive pattern layer LY2, and the components in the second conductive pattern layer LY2 consist of three stacked sublayers (Ti-Al-Ti) with the middle sublayer recessed, the exposed area of ​​the middle sublayer (Al layer) increases, which causes aluminum protrusions and poor adhesion to the passivation layer PVX. The poor adhesion between the components in the second conductive pattern layer LY2 and the passivation layer PVX can be improved by center-biasing the components located in different conductive pattern layers.

[0267] Figure 18 for Figure 4 A schematic diagram of the conductive structure in the display substrate is shown. For example, as... Figure 4 and Figure 18As shown, the width of the second portion 412b of the signal connection line 412 in the second direction X is greater than the width of one of the first portion 412a and the third portion 412c of the signal connection line 412 in the second direction X. For example, the widths of the first portion 412a and the third portion 412c in the second direction X may be the same, but are not limited thereto.

[0268] For example, such as Figure 4 and Figure 18 As shown, at least one of the first portion 412a and the third portion 412c of the signal connection line 412 does not coincide with the center line of the second portion 412b of the signal connection line 412 along the first direction Y. Figure 18 The center line C01 of the first part 412a along the first direction Y, the center line C02 of the second part 412b along the first direction Y, and the center line C03 of the third part 412c along the first direction Y are shown. Figure 18 As shown, the center line C01 of the first part 412a along the first direction Y does not coincide with the center line C02 of the second part 412b along the first direction Y, and the center line C03 of the third part 412c along the first direction Y does not coincide with the center line C02 of the second part 412b along the first direction Y. That is, the segmented signal lines adopt a center offset design between different parts. Figure 19 This is a schematic diagram of a display substrate. (Example) Figure 19 As shown, to reduce resistance, a third conductive pattern layer LY4 can be placed between the first conductive pattern layer LY1 and the second conductive pattern layer LY2 to reduce the resistance of at least one of the initialization signal lines INT1, INT2, and the first power supply line PL1. The material of the third conductive pattern layer LY4 can be the same as that of the first conductive pattern layer LY1, so that the slope angle θ1 of the components in the third conductive pattern layer LY4 is smaller than the slope angle θ2 of the components in the second conductive pattern layer LY2. Because the components in the second conductive pattern layer LY2 are composed of three sub-layers stacked (Ti-Al-Ti), with the middle sub-layer shrinking inward and the exposed area of ​​the middle sub-layer (Al layer) increasing, problems such as aluminum protrusions and poor adhesion to the passivation layer PVX can be caused. The problem of poor adhesion between the components in the second conductive pattern layer LY2 and the passivation layer PVX can be improved by center-biasing the components located in different conductive pattern layers.

[0269] like Figure 18 As shown, the second part 412b of the first power connection line PL12 has a larger dimension in the second direction X than the second part 412b of the initialization connection line INT22 in the second direction X, and is also larger than the second part 412b of the initialization connection line INT12 in the second direction X.

[0270] Figure 19Conductive components 82 and 81 are shown located in the second conductive pattern layer LY2. Conductive component 82 includes a first sublayer 821, a second sublayer 822, and a third sublayer 823. For example, the first sublayer 821 and the third sublayer 823 are made of Ti, and the second sublayer 822 is made of Al. Figure 19 The gate insulating layer GI and the interlayer insulating layer ILD0 are also shown.

[0271] For example, the thickness of the first sublayer 821 and the third sublayer 823 ranges from 800 to 1400 angstroms, but is not limited thereto. For example, the thickness of the conductive component 82 ranges from 5800 to 7800 angstroms, but is not limited thereto.

[0272] Figure 20 This is a schematic diagram of a display substrate provided in one embodiment of the present disclosure. Figure 20 The display substrate DS5 is shown. (As shown...) Figure 20 As shown, the orthographic projection of conductive component 81 on substrate BS overlaps with the orthographic projection of conductive component 82 on substrate BS, and the orthographic projections of the two ramp portions 820 of conductive component 82 on substrate BS are respectively located outside the orthographic projections of the two ramp portions 810 of conductive component 81 on substrate BS. Figure 20 The boundary between the main body and the ramp portion of the conductive component is shown by a dashed line.

[0273] Figure 21 This is a schematic diagram of a display substrate provided in one embodiment of the present disclosure. Figure 21 The display substrate DS6 is shown. (As shown...) Figure 21 As shown, the orthographic projection of conductive component 81 on the substrate BS overlaps with the orthographic projection of conductive component 82 on the substrate BS, and the orthographic projection of one ramp portion 820 of conductive component 82 on the substrate BS is located between the orthographic projections of the two ramp portions 810 of conductive component 81 on the substrate BS, and the orthographic projection of the other ramp portion 820 of conductive component 82 on the substrate BS is located outside the orthographic projections of the two ramp portions 810 of conductive component 81 on the substrate BS. Figure 21 The boundary between the main body and the ramp portion of the conductive component is shown by a dashed line.

[0274] Figure 22 This is a schematic diagram of a display substrate provided in one embodiment of the present disclosure. Figure 22 The display substrate DS7 is shown. (As shown...) Figure 22 As shown, the orthographic projection of conductive component 81 on substrate BS overlaps with the orthographic projection of conductive component 82 on substrate BS, and the orthographic projections of the two ramp portions 820 of conductive component 82 on substrate BS are located between the orthographic projections of the two ramp portions 810 of conductive component 81 on substrate BS. Figure 21The boundary between the main body and the ramp portion of the conductive component is shown by a dashed line.

[0275] The part between the two sloping sections is the main body. Figures 20 to 22 The main body portion 818 of the conductive component 81 and the main body portion 828 of the conductive component 82 are shown.

[0276] To address the poor adhesion between the components in the second conductive pattern layer LY2 and the passivation layer PVX, a method can be adopted where the centerlines of two overlapping components are offset in a direction perpendicular to the substrate. Alternatively, the linewidth of the components in the second conductive pattern layer LY2 can be reduced to be smaller than the linewidth of the components in the third conductive pattern layer LY4. When the first power line PL1 includes conductive components 81 and 82, due to the requirement of a high voltage on the first power line PL1, the linewidth of conductive component 82 can be made larger than the linewidth of conductive component 81, ensuring that the boundary of one side of the first sublayer 821 does not exceed the boundary of the upper surface of conductive component 81. That is, using... Figure 22 The structure shown.

[0277] Of course, initialization line INT1 may include conductive component 81 and conductive component 82, and initialization line INT2 may also include conductive component 81 and conductive component 82.

[0278] Figure 23 This is a schematic diagram of a display substrate provided in one embodiment of the present disclosure. Figure 23 The display substrate DS8 is shown.

[0279] like Figure 23 As shown, the orthographic projection of the data line DT on the substrate BS overlaps with the orthographic projection of the second limiting portion 302 of the pixel limiting layer PDL on the substrate BS, which allows the second limiting portion 302 to have a protrusion PR, so as to facilitate the flow of ink into the opening in the pixel limiting layer during inkjet printing.

[0280] For example, such as Figure 23 As shown, the display substrate also includes a fourth conductive pattern layer LY4 and a second conductive pattern layer LY2. The data line DT includes a portion located in the second conductive pattern layer LY2. The fourth conductive pattern layer LY4 also includes a first conductive portion 91 and a second conductive portion 92. The second conductive pattern layer LY2 also includes a third conductive portion 93 and a fourth conductive portion 94. The first conductive portion 91 and the third conductive portion 93 overlap in a direction perpendicular to the substrate BS and are located on one side of the second limiting portion 302. The second conductive portion 92 and the fourth conductive portion 94 overlap in a direction perpendicular to the substrate BS and are located on the other side of the second limiting portion 302. The center lines of the first conductive portion 91 and the third conductive portion 93 along the first direction Y do not coincide, and the center lines of the second conductive portion 92 and the fourth conductive portion 94 along the first direction Y do not coincide. Figure 23 The center line 91c of the first conductive part 91, the center line 92c of the second conductive part 92, the center line 93c of the third conductive part 93, and the center line 94c of the fourth conductive part 94 are shown.

[0281] For example, such as Figure 23 As shown, the first conductive portion 91 includes a main body portion 918 and slope portions 910 located on both sides of the main body portion 918. The orthographic projection of one end of the third conductive portion 93 near the second limiting portion 302 on the substrate BS is located within the orthographic projection of the main body portion 918 of the first conductive portion 91 on the substrate BS.

[0282] For example, such as Figure 23 As shown, the third conductive part 93 includes a main body part 938 and slope parts 930 located on both sides of the main body part 938. The slope angle θ4 of the slope part 930 of the third conductive part 93 is greater than the slope angle θ3 of the slope part 910 of the first conductive part 91.

[0283] For example, such as Figure 23 As shown, the main body 938 of the third conductive part 93 includes a first main body 93a and a second main body 93b. The orthographic projection of the first main body 93a on the substrate BS overlaps with the orthographic projection of the first conductive part 91 on the substrate BS. The orthographic projection of the second main body 93b on the substrate BS does not overlap with the orthographic projection of the first conductive part 91 on the substrate BS. The maximum distance h02 between the surface of the second main body 93b away from the substrate BS and the substrate BS is less than the maximum distance h01 between the surface of the first main body 93b away from the substrate BS and the substrate BS.

[0284] For example, such as Figure 23 As shown, at least one of the third conductive portion 93 and the fourth conductive portion 94 includes a first sublayer 901, a second sublayer 902 and a third sublayer 903, which are stacked together. The first sublayer 901 is closer to the substrate BS than the third sublayer 903, and the second sublayer 902 is recessed relative to the first sublayer 901 and the third sublayer 903.

[0285] like Figure 23 As shown, the portion of the first power line PL1 located in the second conductive pattern layer LY2 (the third conductive part 93) is designed to the left relative to the first conductive part 91, which can improve the flow of printing ink during inkjet printing and reduce the ink ramping problem.

[0286] Figure 24 This is a schematic diagram of a display substrate provided in one embodiment of the present disclosure. Figure 24 The display substrate DS9 is shown. Figure 23 It can be Figure 24Sectional view along line A3-A4. Figure 25 for Figure 24 A plan view of part of the membrane layer. Figure 26 for Figure 24 A plan view of the fourth conductive pattern layer in the image.

[0287] like Figures 24 to 26 As shown, the third conductive pattern layer LY4 includes a conductive component PL1a, a conductive component INT2a, and a conductive component INT1a. The conductive component PL1a can be a first conductive part 91.

[0288] like Figure 24 and Figure 25 As shown, the second part 412b of the first power line PL1 is connected to the conductive component PL1a through the via Vr to reduce the resistance of the first power line PL1. The second part 412b of the initialization line INT2 is connected to the conductive component INT2a through the via Vs to reduce the resistance of the initialization line INT2. The second part 412b of the initialization line INT1 is connected to the conductive component INT1a through the via Vt to reduce the resistance of the initialization line INT1.

[0289] Figure 27 This is a schematic diagram of a display substrate provided in an embodiment of the present disclosure. Figure 27 The display substrate DS10 is shown.

[0290] For example, such as Figure 27 As shown, the display substrate DS10 also includes multiple fan-out lines 86. The substrate BS includes a display area R01 and a peripheral area R02 located on at least one side of the display area R01. The data line DT is connected to one of the multiple fan-out lines 86. The multiple fan-out lines 86 gradually converge from near the connection point between the data line DT and the fan-out line 86 to away from the connection point between the data line DT and the fan-out line 86. The multiple fan-out lines extend from the display area R01 to the peripheral area R02. The multiple fan-out lines 86 and the data line DT are located on different layers. The multiple fan-out lines 86 are closer to the substrate BS than a portion of the data line DT. Reference Figure 4 and Figure 27 The multiple fan-out lines 86 are closer to the substrate BS than the second portion 412b of the data line DT. The first portion 412a and the third portion 412c of the data line DT are closer to the substrate BS than the multiple fan-out lines 86.

[0291] For example, such as Figure 27 As shown, the length of the portion of fan-out line 86 located in the display area R01 is greater than the length of the portion of fan-out line 86 located in the peripheral area R02. The display area is the area where the image is displayed. The peripheral area is the non-display area.

[0292] For example, multiple fan-out lines 86 can be located between the first conductive pattern layer LY1 and the second conductive pattern layer LY2. That is, it can be seen as replacing the pattern in the previously mentioned third conductive pattern layer LY4 with... Figure 27 The multiple fan-out lines shown are 86. For example... Figure 27 As shown, multiple fan-out lines 86 gradually converge from top to bottom.

[0293] Figure 27 Chips 98 and 99 are also shown; chips 98 and 99 can be chip-on-flex (COF). The data line DT is connected to the chip via fan-out line 86.

[0294] like Figure 27 As shown, a data line DT and a fan-out line 86 are connected through a via Vm, which penetrates the insulating layer between the data line DT and the fan-out line 86. For example, the via Vm penetrates the interlayer insulating layer ILD0.

[0295] For example, the display substrate satisfies the following formula: 1 / k=T'(CW-DV+DW) / KW+e F4(DH / PH) Where T' is a coefficient, greater than or equal to 20 and less than 70, F4 is a coefficient, greater than 6 and less than 30, DH is the thickness of the data line DT, and PH is the thickness of the planarization layer PLN. Further, for example, F4 is greater than 10 and less than 30.

[0296] For example, the thickness DH of the data line DT is 0.5 to 2.5 micrometers. In some embodiments, the thickness DH of the data line DT is 0.5 micrometers, 0.7 micrometers, 0.9 micrometers, 1.1 micrometers, 1.3 micrometers, 1.5 micrometers, 1.7 micrometers, 1.9 micrometers, or 2.1 micrometers.

[0297] For example, the first sub-pixel 101 satisfies 1 / k1=T'(CW-DV+DW) / KW+e Fa(DH / PH) ,

[0298] The second sub-pixel 102 satisfies 1 / k2=T'(CW-DV+DW) / KW+e Fb(DH / PH) ,

[0299] The third sub-pixel 103 satisfies 1 / k3=T'(CW-DV+DW) / KW+e Fc(DH / PH) ,

[0300] For example, 20≤T'≤50, Fa<27, Fb<26, Fc<23.

[0301] For example, 20≤T'≤30, Fa<27, Fb<26, Fc<23.

[0302] For example, in some embodiments, T' = 20.

[0303] For example, 20 ≤ T' ≤ 50, 10 < Fa < 24. Further, for example, 20 ≤ T' ≤ 40. In some embodiments, T' = 20.

[0304] For example, 20 ≤ T' ≤ 50, 10 < Fb < 23. In some embodiments, T' = 20.

[0305] For example, 20 ≤ T' ≤ 50, 8 < Fc < 19. In some embodiments, T' = 20.

[0306] In typical inkjet-printed products, the planarization layer (PLN) is thicker than in vapor-deposited products. However, the display substrate provided in the embodiments of this disclosure, through a backplane design, allows for a limited reduction in the thickness of the planarization layer. This, in turn, reduces the width of the vias (VH) to significantly improve color shift.

[0307] For example, in embodiments of this disclosure, the thickness of the planarization layer is 3-7 micrometers. Optional thicknesses of the planarization layer include 3 micrometers, 3.2 micrometers, 3.4 micrometers, 3.6 micrometers, 3.8 micrometers, 4 micrometers, 4.2 micrometers, 4.4 micrometers, 4.6 micrometers, 4.8 micrometers, 5 micrometers, 5.2 micrometers, 5.4 micrometers, 5.6 micrometers, 5.8 micrometers, 6 micrometers, 6.2 micrometers, 6.4 micrometers, 6.6 micrometers, 6.8 micrometers, or 7 micrometers.

[0308] refer to Figure 5 Generally, a thicker planarization layer results in better planarity of the light-emitting functional layer. However, due to the deviation of the via VH in the second direction X (lateral), as the planarization layer thickness increases, the depth of the via VH increases, and the diameter of the via VH also increases accordingly, which is detrimental to color shift improvement. Therefore, the thickness of the planarization layer is designed to be less than or equal to 7 micrometers. After adjusting the routing of the second conductive pattern layer, to further enhance the planarity effect, the minimum thickness of the planarization layer is 3 micrometers, so that U02 and U01 of the first sub-pixel 101, the second sub-pixel 102, and the third sub-pixel 103 are all less than 0.025 at both 45-degree and 60-degree viewing angles.

[0309] For example, Figure 5The insulating layer (ISL) shown can be composed of inorganic and organic material layers, or organic material layers and organic material layers. The fabrication of vias in the ISL is not limited to a single fabrication; to reduce the via diameter, multiple fabrications are used to create a nested via configuration, which facilitates the flatness of the light-emitting functional layer and thus reduces color shift. The ratio of the diameter of the uppermost via to the width of the sub-pixel opening is less than 0.3. Further examples include ratios of 0.22, 0.23, 0.24, 0.25, 0.26, 0.26, 0.28, or 0.29. The width of the sub-pixel opening can refer to the maximum dimension of the sub-pixel opening in the second direction X.

[0310] For example, 0.09 < DH / PH < 0.16, 20 ≤ T' ≤ 25.

[0311] For example, 0.17 < DH / PH < 0.38, 25 ≤ T' ≤ 30.

[0312] refer to Figure 4 , Figure 5 , Figure 8 , Figures 9A to 11 , Figures 15A to 16 ,as well as Figure 18Some embodiments of this disclosure provide a display substrate, including: a substrate BS and a plurality of sub-pixels 100 disposed on the substrate BS. The sub-pixels include a plurality of first sub-pixels 101(R) and a plurality of second sub-pixels 102(G). The plurality of sub-pixels 100 are arranged along a first direction Y or along a second direction X, and the first direction Y and the second direction X intersect; an active semiconductor layer LY0 is located on one side of the substrate BS; a first conductive pattern layer LY1 is located on the side of the active semiconductor layer LY0 away from the substrate BS; and a second conductive pattern layer LY2 is located on the side of the first conductive pattern layer LY1 away from the substrate BS. The second conductive pattern layer LY2 is located on one side of the substrate BS, and on the other side of the substrate BS. The second conductive pattern layer includes a plurality of conductive elements, each including a first conductive element corresponding to the first sub-pixel 101 and a second conductive element corresponding to the second sub-pixel 102. The second insulating layer includes a plurality of openings P0, each opening P0 defining an effective light-emitting area of ​​the sub-pixel. Each opening P0 includes a first opening P01 corresponding to the first sub-pixel 101 and a second opening corresponding to the second sub-pixel 102. P02, the areas of the first opening P01 and the second opening P02 are different; the first sub-pixel 101 satisfies the following relationship: △U1=|U2-U1|≤k1×|X2-X1| / KW1, where k1 is a coefficient, 0.009≤k1≤0.02, X1 is the minimum distance between the first edge CL1 of the first conductive element in the first sub-pixel 101 and the first edge KL1 of the opening P0 corresponding to the first sub-pixel 101 in the second direction X; X2 is the minimum distance between the second edge CL2 of the first conductive element in the first sub-pixel 101 and the second edge KL2 of the opening P0 corresponding to the first sub-pixel 101 in the second direction X. The minimum distance in direction X, KW1 is the maximum size of the opening P0 corresponding to the first sub-pixel 101 in the second direction X, U1 is the coordinate distance between the chromaticity coordinate point of the first sub-pixel 101 in the first viewing angle and the chromaticity coordinate point in the 0-degree viewing angle, U2 is the coordinate distance between the chromaticity coordinate point of the first sub-pixel 101 in the second viewing angle and the chromaticity coordinate point in the 0-degree viewing angle, ΔU1 is the absolute value of the difference between U2 and U1; the second sub-pixel 102 satisfies the following relationship: ΔU2=|U4-U3|≤k2×|X4-X3| / KW2, where k2 is a coefficient, 0.004≤k2≤0.X2, X3 is the minimum distance in the second direction X between the first edge CL1 of the second conductive element of the second sub-pixel 102 and the first edge KL1 of the opening P0 corresponding to the second sub-pixel 102; X4 is the minimum distance in the second direction X between the second edge CL2 of the second conductive element of the second sub-pixel 102 and the second edge KL2 of the opening P0 corresponding to the second sub-pixel 102; KW2 is the maximum size of the opening P0 corresponding to the second sub-pixel 102 in the second direction X; U3 is the coordinate distance between the chromaticity coordinate point of the second sub-pixel 102 in the first viewing angle and the chromaticity coordinate point in the 0-degree viewing angle; U4 is the coordinate distance between the chromaticity coordinate point of the second sub-pixel 102 in the second viewing angle and the chromaticity coordinate point in the 0-degree viewing angle; ΔU2 is the absolute value of the difference between U4 and U3; 0.1 < k2 / k1 < 10.

[0313] refer to Figure 4 , Figure 5 , Figure 8 , Figures 9A to 11 , Figures 15A to 16 ,as well as Figure 18Some embodiments of this disclosure provide a display substrate, including: a substrate BS and a plurality of sub-pixels 100 disposed on the substrate BS. The sub-pixels include a plurality of first sub-pixels 101(R) and a plurality of second sub-pixels 102(G). Each first sub-pixel 101 includes a first pixel circuit 100a1, which includes a first conductive element. Each second sub-pixel 102 includes a second pixel circuit 100a2, which includes a second conductive element. The plurality of sub-pixels 100 are arranged along a first direction Y or along a second direction X, where the first direction Y and the second direction X intersect. A pixel defining layer PDL includes a plurality of openings P0, which are configured to expose at least a portion of a first electrode E1. An opening P0 is configured to define the light-emitting area of ​​a sub-pixel; the opening P0 includes a first opening P01 corresponding to the first sub-pixel 101 and a second opening P02 corresponding to the second sub-pixel 102, the areas of the first opening P01 and the second opening P02 are different; the first sub-pixel 101 satisfies the following relationship: △U1=|U2-U1|≤k1×|X2-X1| / KW1, where k1 is a coefficient, 0.009≤k1≤0.02, X1 is the minimum distance in the second direction X between the first edge CL1 of the first conductive element in the first sub-pixel 101 and the first edge KL1 of the opening P0 corresponding to the first sub-pixel 101; X2 is the minimum distance in the second direction X between the second edge CL2 of the first conductive element in the first sub-pixel 101 and the first edge KL1 of the opening P0 corresponding to the first sub-pixel 102. The second edge KL2 of the opening P0 corresponding to pixel 101 is the minimum distance in the second direction X. KW1 is the maximum size of the opening P0 corresponding to the first sub-pixel 101 in the second direction X. U1 is the coordinate distance between the chromaticity coordinate point of the first sub-pixel 101 in the first viewing angle and the chromaticity coordinate point in the 0-degree viewing angle. U2 is the coordinate distance between the chromaticity coordinate point of the first sub-pixel 101 in the second viewing angle and the chromaticity coordinate point in the 0-degree viewing angle. ΔU1 is the absolute value of the difference between U2 and U1. The second sub-pixel 102 satisfies the following relationship: ΔU2=|U4-U3|≤k2×|X4-X3| / KW2, where k2 is a coefficient, 0.004≤k2≤0.02, and X3 is the second leading edge of the second sub-pixel 102. The minimum distance between the first edge CL1 of the electrical element and the first edge KL1 of the opening P0 in the second direction X; X4 is the minimum distance between the second edge CL2 of the second conductive element in the second sub-pixel 102 and the second edge KL2 of the opening P0 corresponding to the second sub-pixel 102 in the second direction X; KW2 is the maximum size of the opening P0 corresponding to the second sub-pixel 102 in the second direction X; U3 is the coordinate distance between the chromaticity coordinate point of the second sub-pixel 102 in the first viewing angle and the chromaticity coordinate point in the 0-degree viewing angle; U4 is the coordinate distance between the chromaticity coordinate point of the second sub-pixel 102 in the second viewing angle and the chromaticity coordinate point in the 0-degree viewing angle; ΔU2 is the absolute value of the difference between U4 and U3; 0.1 < k2 / k1 < 10.

[0314] For example, in some embodiments, 0.1 < k2 / k1 < 1. For example, in other embodiments, 1 < k2 / k1 < 10. For example, in other embodiments, 3 < k2 / k1 < 8. For example, in some embodiments, k2 / k1 = 1.

[0315] For example, the conductive element mentioned above, the first conductive element corresponding to the first sub-pixel 101, and the second conductive element corresponding to the second sub-pixel 102 are all the second electrode 202 of the storage capacitor. See also Figure 5 Insulating layer ISL1 refers to planarization layer PLN, and insulating layer ISL2 refers to pixel confinement layer PDL.

[0316] Figure 4 The pixel circuit 100a is shown to include a first pixel circuit 100a1, a second pixel circuit 100a2, and a third pixel circuit 100a3.

[0317] For example, gate line G1 can be called the first gate line, gate line G2 can be called the second gate line, gate line G3 can be called the third gate line, reset transistor T2 can be called the first reset transistor, and reset transistor T4 can be called the second reset transistor. In this case, the display substrate further includes: a data line, a first gate line, a second gate line, a third gate line, a first power line, a first initialization line, and a second initialization line. The data line is configured to provide a data voltage to the pixel circuit; the first gate line is configured to provide a scan signal to the pixel circuit; the second gate line is configured to provide a first reset control signal to the pixel circuit; the third gate line is configured to provide a second reset control signal to the pixel circuit; the first power line is configured to provide a first voltage signal to the pixel circuit; the first initialization line is configured to provide a first initialization signal to the pixel circuit; and the second initialization line is configured to provide a second initialization signal to the pixel circuit. The pixel circuit further includes a data writing transistor, a first reset transistor, and a second reset transistor. The first terminal of the data writing transistor is connected to the data line; the gate of the data writing transistor is connected to the first gate line; and the second terminal of the data writing transistor is connected to the gate of the driving transistor. The first terminal of the first reset transistor is connected to the first initialization line. The diode is connected to the gate of the driving transistor, and the gate of the first reset transistor is connected to the second gate line; the first electrode of the second reset transistor is connected to the second initialization line, the second electrode of the second reset transistor is connected to the first electrode of the light-emitting element, and the gate of the second reset transistor is connected to the third gate line; the first power line includes a first power signal line extending along the second direction and a first power connection line extending along the first direction, and the first power signal line and the first power connection line are connected; the first initialization line includes a first initialization signal line extending along the second direction and a first initialization connection line extending along the first direction, and the first initialization signal line and the first initialization connection line are connected; the second initialization line includes a second initialization signal line extending along the second direction and a second initialization connection line extending along the first direction, and the second initialization signal line and the second initialization connection line are connected; the orthographic projection of at least one of the first power connection line, the first initialization connection line, and the second initialization connection line on the substrate overlaps with the orthographic projection of the opening of the sub-pixel on the substrate.

[0318] For example, the active semiconductor layer of each transistor may include a source region, a drain region, and a channel located between the source region and the drain region. For example, the channel has semiconductor characteristics; the source region and the drain region are on both sides of the channel and may be doped with impurities, and thus have conductivity, and may serve as the first and second electrodes of the transistor, respectively, with one of the first and second electrodes of the transistor being the source and the other being the drain.

[0319] For example, the materials used to fabricate the semiconductor layer (semiconductor pattern) of the active semiconductor layer may include oxide semiconductors, organic semiconductors, amorphous silicon, polycrystalline silicon, etc. For example, oxide semiconductors include metal oxide semiconductors (e.g., indium gallium zinc oxide (IGZO)), and polycrystalline silicon includes low-temperature polycrystalline silicon or high-temperature polycrystalline silicon, etc. The embodiments of this disclosure are not limited in this regard. It should be noted that the source region and drain region mentioned above may be regions doped with n-type impurities or p-type impurities, and the embodiments of this disclosure are not limited in this regard.

[0320] For example, the substrate BS, buffer layer BL, barrier layer BR, gate insulating layer GI, interlayer insulating layer ILD, and planarization layer PLN are all made of insulating materials. For example, the substrate BS includes flexible materials such as polyimide, but is not limited to these. At least one of the buffer layer BF, barrier layer BR, gate insulating layer GI, and interlayer insulating layer ILD is made of inorganic or organic insulating materials. For example, inorganic insulating materials include silicon oxide, silicon nitride, and silicon oxynitride, while organic insulating materials include resins, but are not limited to these. For example, the planarization layer PLN can be made of organic materials, such as resins, but is not limited to these.

[0321] For example, both the first conductive pattern layer LY1 and the second conductive pattern layer LY2 are made of metallic materials, and the specific materials can be determined according to needs. For example, the material of the first conductive pattern layer LY1 includes molybdenum (Mo). The material of the second conductive pattern layer LY2 includes titanium (Ti) and aluminum (Al), and a Ti / Al / Ti three-layer stacked structure can be used, but it is not limited to this.

[0322] For example, the material of the first electrode E1 of the light-emitting element includes silver (Ag) and indium tin oxide (ITO). For example, the first electrode E1 of the light-emitting element has a three-layer stacked structure of ITO / Ag / ITO, but is not limited to this.

[0323] In the embodiments of this disclosure, the patterns and vias of each single layer can be fabricated using patterning processes. For example, forming a specific pattern includes forming a thin film, forming a photoresist pattern on the thin film, and using the photoresist pattern as a mask to pattern the thin film to form the specific pattern. The first conductive pattern layer LY1, the second conductive pattern layer LY2, the first electrode layer LY3, the third conductive pattern layer LY4, and vias in the insulating layer can all be formed using this method. For the active semiconductor layer LY0, a semiconductor pattern can be formed first, an insulating layer can be formed on the semiconductor pattern, a first conductive pattern layer LY1 can be formed on the insulating layer, and the semiconductor pattern can be doped using the first conductive pattern layer LY1 as a mask to form an active semiconductor layer LY0 including a channel and source and drain regions located on both sides of the channel.

[0324] It should be noted that the layout of the subpixels of the display panel provided in the embodiments of this disclosure is not limited to... Figure 5 As shown, it is possible to Figure 5 Based on this, transformations are made to form other layout diagrams. The above description uses a 4T1C sub-pixel as an example, but the embodiments disclosed herein are not limited to this. For example, each sub-pixel 101 may also include other numbers of transistors or other numbers of capacitors. The pixel circuit operates under the control of data signals transmitted through data lines and gate scan signals transmitted through gate lines and light emission control signals provided by light emission control signal lines, so as to drive the light emission element to emit light and thereby realize operations such as display.

[0325] It should be noted that the embodiments of this disclosure do not limit the number of thin-film transistors and capacitors included in the pixel circuit.

[0326] refer to Figure 4 and Figure 8 In the layout diagram of the display substrate provided in the embodiments of this disclosure, the connection position of the connecting electrode CEf and the first electrode plate 201 of the storage capacitor 20 is located at one corner of the first electrode plate 201. The connection position of the connecting electrode CEf and the first electrode plate 201 can be adjusted to other positions so that the ratio of the distance from the central axis (longitudinal central axis) of the connecting electrode CEf extending along the first direction Y to the central axis (longitudinal central axis) of the opening of the pixel limiting layer extending along the first direction Y to the size of the opening of the pixel limiting layer in the second direction X is less than 0.3.

[0327] In other embodiments, an opening may be provided in the second electrode plate 201, so that the via V3 is located in the opening of the second electrode plate 201. The opening provided in the second electrode plate 201 facilitates the connection of the electrode CEf to the first electrode plate 201 of the storage capacitor 20.

[0328] The display substrate provided in the embodiments of this disclosure may adopt other suitable layouts, and the wiring method is not limited to that shown in the figures.

[0329] This disclosure provides at least one embodiment of a display device, including any of the display substrates described above. The display device may be a large-size display device, and at least one film layer in the light-emitting functional layer is fabricated using an inkjet printing process.

[0330] For example, the display device can be an organic light-emitting diode (OLED) display device. The display device can be any product or component with a display function, including televisions, digital cameras, mobile phones, watches, tablets, laptops, navigators, etc., which include OLED display devices.

[0331] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display substrate, comprising: A substrate and a plurality of sub-pixels disposed on the substrate; The sub-pixels include: A pixel circuit includes a storage capacitor, the storage capacitor comprising a first electrode and a second electrode, the first electrode being closer to the substrate than the second electrode; and A light-emitting element, the light-emitting element including a first electrode, a second electrode and a light-emitting functional layer located between the first electrode and the second electrode, the pixel circuit being configured to drive the light-emitting element; The display substrate further includes a pixel defining layer, wherein each sub-pixel includes a plurality of openings configured to expose at least a portion of the first electrode and to define a light-emitting area of ​​the sub-pixel. Wherein, the orthographic projection of the opening on the substrate overlaps with the orthographic projection of the second electrode plate on the substrate. The second electrode plate includes a first edge extending along a first direction and a second edge extending along the first direction, and the opening includes a first edge extending along the first direction and a second edge extending along the first direction. The first edge of the second electrode is closer to the first edge of the opening than the second edge of the second electrode, and the second edge of the second electrode is closer to the second edge of the opening than the first edge of the second electrode. The sub-pixel satisfies the following formula: △U = |U02 - U01| ≤ k × |Xb - Xa| / KW, where k is the color shift influence coefficient, Xa is the minimum distance between the first edge of the second electrode plate and the first edge of the opening in the second direction, Xb is the minimum distance between the second edge of the second electrode plate and the second edge of the opening in the second direction, the first direction and the second direction intersect; KW is the maximum size of the opening in the second direction, U01 is the coordinate distance between the chromaticity coordinate point in the first viewing angle and the chromaticity coordinate point in the 0-degree viewing angle, U02 is the coordinate distance between the chromaticity coordinate point in the second viewing angle and the chromaticity coordinate point in the 0-degree viewing angle, △U is the absolute value of the difference between U02 and U01, the chromaticity coordinate point in the 0-degree viewing angle is the chromaticity coordinate point at the normal line where the center of the display substrate is located, the first viewing angle and the second viewing angle are located on opposite sides of the normal line and the angles between them are equal. The display substrate further includes: a data line, wherein the data line is configured to provide data voltage to the pixel circuit. The display substrate further includes an insulating layer and vias penetrating the insulating layer. The first electrode of the light-emitting element of the sub-pixel is connected to the pixel circuit of the sub-pixel through the vias. The insulating layer includes a passivation layer and a planarization layer. The display substrate further includes a conductive structure, wherein the conductive structure includes a first signal line and a signal connection line, the conductive structure is configured to provide a voltage signal to the pixel circuit, the first signal line extends along a second direction, the signal connection line extends along the first direction, and the signal connection line is electrically connected to the first signal line. It satisfies the following formula: 1 / k = T'(CW-DV+DW) / KW+e F4(DH / PH) Where T' is a coefficient, T' is greater than or equal to 20 and less than 70, F4 is a coefficient, F4 is greater than 6 and less than 30, DH is the thickness of the data line, PH is the thickness of the planarization layer, CW is the maximum dimension of the second plate of the storage capacitor in the second direction, DW is the linewidth of the signal line, the signal line includes the signal connection line, and DV is the distance between the axis of symmetry of the via extending in the first direction and the axis of symmetry of the opening nearest to the via extending in the first direction.

2. The display substrate according to claim 1, wherein, U02<0.020, U01<0.020, ΔU<0.0015.

3. The display substrate according to claim 1, wherein, The first edge of the opening, the first edge of the second electrode plate, the second edge of the second electrode plate, and the second edge of the opening are arranged sequentially along the second direction, and the minimum distance between the first edge of the second electrode plate and the second edge of the second electrode plate in the second direction is Xc. Xc / Xa > 1.5 or Xc / Xb > 1.

5.

4. The display substrate according to claim 1, wherein, The plurality of sub-pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, and the first sub-pixel, the second sub-pixel, and the third sub-pixel are arranged sequentially along the second direction.

5. The display substrate according to claim 4, wherein, The first sub-pixel satisfies the following formula: △U1 =|U2-U1|≤ k1×|X2-X1| / KW1, Wherein, k1 is a coefficient, 0.009≤k1≤0.02, X1 is the minimum distance between the first edge of the second electrode plate in the first sub-pixel and the first edge of the opening of the first sub-pixel in the second direction; X2 is the minimum distance between the second edge of the second electrode plate in the first sub-pixel and the second edge of the opening of the first sub-pixel in the second direction; KW1 is the maximum size of the opening of the first sub-pixel in the second direction; U1 is the coordinate distance between the chromaticity coordinate point of the first sub-pixel in the first viewing angle and the chromaticity coordinate point in the 0-degree viewing angle; U2 is the coordinate distance between the chromaticity coordinate point of the first sub-pixel in the second viewing angle and the chromaticity coordinate point in the 0-degree viewing angle; and ΔU1 is the absolute value of the difference between U2 and U1.

6. The display substrate according to claim 5, wherein, The second sub-pixel satisfies the following formula: △U2 =|U4-U3|≤k2×|X4-X3| / KW2, Wherein, k2 is a coefficient, 0.004≤k2≤0.02; X3 is the minimum distance in the second direction between the first edge of the second electrode plate in the second sub-pixel and the first edge of the opening of the second sub-pixel; X4 is the minimum distance in the second direction between the second edge of the second electrode plate in the second sub-pixel and the second edge of the opening of the second sub-pixel; KW2 is the maximum size of the opening of the second sub-pixel in the second direction; U3 is the coordinate distance between the chromaticity coordinate point of the second sub-pixel in the first viewing angle and the chromaticity coordinate point in the 0-degree viewing angle; U4 is the coordinate distance between the chromaticity coordinate point of the second sub-pixel in the second viewing angle and the chromaticity coordinate point in the 0-degree viewing angle; and ΔU2 is the absolute value of the difference between U4 and U3.

7. The display substrate according to claim 6, wherein, The ratio of k2 to k1 is less than 10 and greater than 0.

1.

8. The display substrate according to claim 6, wherein, The third sub-pixel satisfies the following formula: △U3 =|U6-U5|≤k3×|X6-X5| / KW3, Wherein, k3 is a coefficient, 0.01≤k3≤0.03; X5 is the minimum distance in the second direction between the first edge of the second pole plate in the third sub-pixel and the first edge of the opening in the third sub-pixel; X6 is the minimum distance in the second direction between the second edge of the second pole plate in the third sub-pixel and the second edge of the opening; KW3 is the maximum size of the opening in the second direction; U5 is the coordinate distance between the chromaticity coordinate point of the third sub-pixel in the first viewing angle and the chromaticity coordinate point in the 0-degree viewing angle; U6 is the coordinate distance between the chromaticity coordinate point of the third sub-pixel in the second viewing angle and the chromaticity coordinate point in the 0-degree viewing angle; and ΔU3 is the absolute value of the difference between U6 and U5.

9. The display substrate according to claim 8, wherein, The orthographic projection of at least one of the signal connection line and the data line on the substrate overlaps with the orthographic projection of the opening of at least one of the plurality of sub-pixels on the substrate.

10. The display substrate according to claim 9, wherein, The signal connection line includes at least one of a portion of a first power line extending in the first direction and a portion of an initialization line extending in the first direction.

11. The display substrate according to claim 9, further comprising: A second signal line, wherein the second signal line is configured to provide a voltage signal to the pixel circuit, and the second signal line extends along the second direction. The orthographic projection of the second signal line on the substrate overlaps with the orthographic projection of the opening of at least one of the plurality of sub-pixels on the substrate.

12. The display substrate according to claim 11, wherein, The second signal line includes at least one of a gate line and an initialization signal line extending along the second direction.

13. The display substrate according to claim 9, wherein, The overlap dimension between the signal connection line and the opening in the second direction is less than 10% of the line width of the signal connection line, or the overlap dimension between the data line and the opening in the second direction is less than 10% of the line width of the data line.

14. The display substrate according to claim 13, wherein, The via includes a first via, a second via, and a third via. The first electrodes of the light-emitting elements of the first sub-pixel, the second sub-pixel, and the third sub-pixel are respectively connected to the pixel circuits of the first sub-pixel, the second sub-pixel, and the third sub-pixel through the first via, the second via, and the third via. The distance between the first via and the second via is KX1, and the distance between the second via and the third via is KX2, wherein the ratio of KX1 / KX2 is 0.75-1.

25.

15. The display substrate according to claim 14, wherein, The distance between the axis of symmetry of the via extending along the first direction and the axis of symmetry of the opening closest to the via extending along the first direction is less than 8 micrometers, and the diameter of the via is 8-17 micrometers.

16. The display substrate according to claim 15, wherein, The passivation layer is made of inorganic insulating material, the planarization layer is made of organic insulating material, and the thickness of the planarization layer is 3-7 micrometers.

17. The display substrate according to claim 14, wherein, Satisfy the following formula: 1 / k = F1(CW / KW)-F2(DV / KW)+F3(DW / KW), Wherein, F1 is the capacitance influence coefficient, F2 is the via offset influence coefficient, F3 is the signal line influence coefficient, and CW / KW is the ratio of the storage capacitor to the opening.

18. The display substrate according to claim 17, wherein, Satisfy the following formula: 1 / T = k ×(CW-DV+DW) / KW, where 1 / T is the coefficient affecting color cast improvement. The first sub-pixel satisfies 1 / T1 = k1 ×(CW-DV+DW) / KW. The second sub-pixel satisfies 1 / T2 = k2 ×(CW-DV+DW) / KW. The third sub-pixel satisfies 1 / T3 = k3 ×(CW-DV+DW) / KW. Among them, 1 / T1 < 0.019, 1 / T2 < 0.019, and 1 / T3 < 0.

019.

19. The display substrate according to claim 18, wherein, 1 / T1<0.009, 1 / T2<0.014, 1 / T3<0.

019.

20. The display substrate according to claim 18, wherein, 1 / T1<0.008, 1 / T2<0.003, 1 / T3<0.

016.

21. The display substrate according to claim 18, wherein, 0.2 < Tx / Ty < 6, where Tx is one of T1, T2, and T3, and Ty is one of T1, T2, and T3.

22. The display substrate according to claim 18, wherein, Under both the O-view and -O-view, the first sub-pixel satisfies 1 / T11 = k11 ×(CW-DV+DW) / KW; Under both the P-view and -P-view perspectives, the first sub-pixel satisfies 1 / T12 = k12 ×(CW-DV+DW) / KW. 1 / T11<0.009, 1 / T12<0.

008.

23. The display substrate according to claim 22, wherein, |1 / T12-1 / T11|<0.

001.

24. The display substrate according to claim 18, wherein, Under both the O-view and -O-view perspectives, the second sub-pixel satisfies 1 / T21 = k21 ×(CW-DV+DW) / KW; Under both the P-view and -P-view perspectives, the second sub-pixel satisfies 1 / T22 = k22 ×(CW-DV+DW) / KW. 1 / T21<0.014, 1 / T22<0.

004.

25. The display substrate according to claim 24, wherein, |1 / T22-1 / T21|<0.

010.

26. The display substrate according to claim 24, wherein, 1 / T21<0.009, 1 / T22<0.

003.

27. The display substrate according to claim 18, wherein, Under both the O-view and -O-view perspectives, the third sub-pixel satisfies 1 / T31 = k31 ×(CW-DV+DW) / KW; Under both the P-view and -P-view perspectives, the third sub-pixel satisfies 1 / T32 = k32 ×(CW-DV+DW) / KW. 1 / T31<0.016, 1 / T32<0.

019.

28. The display substrate according to claim 27, wherein, |1 / T32-1 / T31|<0.

003.

29. The display substrate according to claim 27, wherein, 1 / T31<0.012, 1 / T32<0.

014.

30. The display substrate according to claim 9, wherein, The signal connection line includes a first part, a second part, and a third part. The first part and the third part are connected through the second part. The first part and the third part are located in a first conductive pattern layer, and the second part is located in a second conductive pattern layer.

31. The display substrate according to claim 30, wherein, The first conductive pattern layer is closer to the substrate than the second conductive pattern layer.

32. The display substrate according to claim 30, wherein, The width of the second portion of the signal connection line in the second direction is greater than the width of either the first portion or the third portion of the signal connection line in the second direction.

33. The display substrate according to claim 30, wherein, At least one of the first portion and the third portion of the signal connection line does not coincide with the centerline of the second portion of the signal connection line along the first direction.

34. The display substrate according to claim 9, wherein, The pixel defining layer includes a plurality of first defining portions and a plurality of second defining portions, the plurality of second defining portions being arranged along a second direction and extending along a first direction. The plurality of first defining portions are configured as a plurality of groups, each group of first defining portions being located between two adjacent second defining portions. The first defining portions extend along the second direction, and the first defining portions in each group are arranged along the first direction. The maximum height of the first defining portion to the planarization layer is less than the maximum height of the second defining portion to the planarization layer. The substrate includes a display area and a peripheral area located on at least one side of the display area. The orthographic projection of the portion of the data line located in the display area on the substrate is located within the orthographic projection of the second defining portion on the substrate.

35. The display substrate according to claim 34, further comprising a second conductive pattern layer and a third conductive pattern layer, wherein, The data line includes a portion located in the second conductive pattern layer. The third conductive pattern layer further includes a first conductive portion and a second conductive portion. The second conductive pattern layer further includes a third conductive portion and a fourth conductive portion. The first conductive portion and the third conductive portion overlap in a direction perpendicular to the substrate and are located on one side of the second defining portion. The second conductive portion and the fourth conductive portion overlap in a direction perpendicular to the substrate and are located on the other side of the second defining portion. The center lines of the first conductive portion and the third conductive portion along the first direction do not coincide. The center lines of the second conductive portion and the fourth conductive portion along the first direction do not coincide.

36. The display substrate according to claim 35, wherein, The first conductive portion includes a main body portion and slope portions located on both sides of the main body portion. The orthographic projection of one end of the third conductive portion near the second limiting portion on the substrate is located within the orthographic projection of the main body portion of the first conductive portion on the substrate.

37. The display substrate according to claim 36, wherein, The third conductive part includes a main body and sloped portions located on both sides of the main body, wherein the slope angle of the sloped portion of the third conductive part is greater than the slope angle of the sloped portion of the first conductive part.

38. The display substrate according to claim 37, wherein, The main body of the third conductive part includes a first main body and a second main body. The orthographic projection of the first main body on the substrate overlaps with the orthographic projection of the first conductive part on the substrate. The orthographic projection of the second main body on the substrate does not overlap with the orthographic projection of the first conductive part on the substrate. The distance between the surface of the second main body away from the substrate and the substrate is less than the distance between the surface of the first main body away from the substrate and the substrate.

39. The display substrate according to any one of claims 35-38, wherein, At least one of the third conductive portion and the fourth conductive portion includes a first sublayer, a second sublayer, and a third sublayer, which are stacked together, and the first sublayer is closer to the substrate than the third sublayer, and the second sublayer is recessed relative to the first and third sublayers.

40. The display substrate according to claim 9, further comprising a plurality of fan-out lines, wherein, The substrate includes a display area and a peripheral area located on at least one side of the display area. The data line is connected to one of the plurality of fan-out lines. The plurality of fan-out lines gradually converge in a direction from near the connection point of the data line and the fan-out line to away from the connection point of the data line and the fan-out line. The plurality of fan-out lines extend from the display area to the peripheral area. The plurality of fan-out lines are located on different layers from the data line. The plurality of fan-out lines are closer to the substrate than a portion of the data line.

41. The display substrate according to claim 34, wherein, The first sub-pixel satisfies 1 / k1 = T'(CW-DV+DW) / KW+e Fa(DH / PH) , The second sub-pixel satisfies 1 / k2 = T'(CW-DV+DW) / KW+e Fb(DH / PH) , The third sub-pixel satisfies 1 / k3 = T'(CW-DV+DW) / KW+e Fc(DH / PH) , 20≤T'≤30, Fa<27, Fb<26, Fc<23.

42. The display substrate according to claim 41, wherein, T' = 20, 10 < Fa < 24.

43. The display substrate according to claim 41, wherein, T' = 20, 10 < Fb < 23.

44. The display substrate according to claim 41, wherein, T' = 20, 8 < Fc < 19.

45. The display substrate according to any one of claims 1, 41-44, wherein, 0.09<DH / PH<0.16, 20≤T'≤25.

46. ​​The display substrate according to any one of claims 1, 41-44, wherein, 0.17<DH / PH<0.38, 25≤T'≤30.

47. The display substrate according to any one of claims 1-38, further comprising: The pixel circuit comprises a first gate line, a second gate line, a third gate line, a first power supply line, a first initialization line, and a second initialization line. The first gate line is configured to provide a scan signal to the pixel circuit. The second gate line is configured to provide a first reset control signal to the pixel circuit. The third gate line is configured to provide a second reset control signal to the pixel circuit. The first power supply line is configured to provide a first voltage signal to the pixel circuit. The first initialization line is configured to provide a first initialization signal to the pixel circuit. The second initialization line is configured to provide a second initialization signal to the pixel circuit. The pixel circuit further includes a driving transistor, a data writing transistor, a first reset transistor, and a second reset transistor. The first terminal of the data writing transistor is connected to the data line, the gate of the data writing transistor is connected to the first gate line, and the second terminal of the data writing transistor is connected to the gate of the driving transistor. The first terminal of the first reset transistor is connected to the first initialization line, the second terminal of the first reset transistor is connected to the gate of the driving transistor, and the gate of the first reset transistor is connected to the second gate line. The first electrode of the second reset transistor is connected to the second initialization line, the second electrode of the second reset transistor is connected to the first electrode of the light-emitting element, and the gate of the second reset transistor is connected to the third gate line. The first power line includes a first power signal line extending along the second direction and a first power connection line extending along the first direction, wherein the first power signal line and the first power connection line are connected. The first initialization line includes a first initialization signal line extending along the second direction and a first initialization connection line extending along the first direction, wherein the first initialization signal line and the first initialization connection line are connected. The second initialization line includes a second initialization signal line extending along the second direction and a second initialization connection line extending along the first direction, wherein the second initialization signal line and the second initialization connection line are connected. The orthographic projection of at least one of the first power connection line, the first initialization connection line, and the second initialization connection line on the substrate overlaps with the orthographic projection of the opening of the sub-pixel on the substrate.

48. The display substrate according to any one of claims 1-38, wherein, 0.009≤k≤0.03。 49. The display substrate according to any one of claims 1-38, wherein, △U＜0.0020。 50. A display substrate, comprising: A substrate and a plurality of sub-pixels disposed on the substrate, each sub-pixel including a pixel circuit and a light-emitting element, the pixel circuit being configured to drive the light-emitting element, each sub-pixel including a plurality of first sub-pixels and a plurality of second sub-pixels, the plurality of sub-pixels being arranged along a first direction or along a second direction, the first direction and the second direction intersecting. An active semiconductor layer is located on one side of the substrate. The first conductive pattern layer is located on the side of the active semiconductor layer away from the substrate. The second conductive pattern layer is located on the side of the first conductive pattern layer away from the substrate. A first insulating layer is located on the side of the second conductive pattern layer away from the substrate. as well as The second insulating layer is located on the side of the first insulating layer away from the substrate. The second conductive pattern layer includes a plurality of conductive elements, each conductive element including a second electrode plate corresponding to the storage capacitor of the first sub-pixel and a second electrode plate corresponding to the storage capacitor of the second sub-pixel; the second insulating layer includes a plurality of openings, each opening defining an effective light-emitting area of ​​the sub-pixel, each opening including a first opening corresponding to the first sub-pixel and a second opening corresponding to the second sub-pixel, the first opening and the second opening having different areas; The first sub-pixel satisfies the following relationship: △U1 =|U2-U1|≤ k1×|X2-X1| / KW1, where k1 is a coefficient, X1 is the minimum distance in the second direction between the first edge of the second plate of the storage capacitor in the first sub-pixel and the first edge of the opening corresponding to the first sub-pixel; X2 is the minimum distance in the second direction between the second edge of the second plate of the storage capacitor in the first sub-pixel and the second edge of the opening corresponding to the first sub-pixel; KW1 is the maximum size of the opening corresponding to the first sub-pixel in the second direction; U1 is the coordinate distance between the chromaticity coordinate point of the first sub-pixel in the first viewing angle and the chromaticity coordinate point in the 0-degree viewing angle; U2 is the coordinate distance between the chromaticity coordinate point of the first sub-pixel in the second viewing angle and the chromaticity coordinate point in the 0-degree viewing angle; and △U1 is the absolute value of the difference between U2 and U1. The second sub-pixel satisfies the following relationship: △U2 =|U4-U3|≤ k2×|X4-X3| / KW2, where k2 is a coefficient, X3 is the minimum distance in the second direction between the first edge of the second plate of the storage capacitor of the second sub-pixel and the first edge of the opening corresponding to the second sub-pixel; X4 is the minimum distance in the second direction between the second edge of the second plate of the storage capacitor of the second sub-pixel and the second edge of the opening corresponding to the second sub-pixel; KW2 is the maximum size of the opening corresponding to the second sub-pixel in the second direction, U3 is the coordinate distance between the chromaticity coordinate point of the second sub-pixel in the first viewing angle and the chromaticity coordinate point in the 0-degree viewing angle, U4 is the coordinate distance between the chromaticity coordinate point of the second sub-pixel in the second viewing angle and the chromaticity coordinate point in the 0-degree viewing angle, and △U2 is the absolute value of the difference between U4 and U3. 0.1 < k2 / k1 < 10, The display substrate further includes: a data line, wherein the data line is configured to provide data voltage to the pixel circuit. The display substrate further includes an insulating layer and vias penetrating the insulating layer. The first electrode of the light-emitting element of the sub-pixel is connected to the pixel circuit of the sub-pixel through the vias. The insulating layer includes a passivation layer and a planarization layer. The display substrate further includes a conductive structure, wherein the conductive structure includes a first signal line and a signal connection line, the conductive structure is configured to provide a voltage signal to the pixel circuit, the first signal line extends along a second direction, the signal connection line extends along the first direction, and the signal connection line is electrically connected to the first signal line. The first sub-pixel satisfies 1 / k1 = T'(CW-DV+DW) / KW+e Fa(DH / PH) , The second sub-pixel satisfies 1 / k2 = T'(CW-DV+DW) / KW+e Fb(DH / PH) , Wherein, T' is a coefficient, T' is greater than or equal to 20 and less than 70, Fa is a coefficient, Fa is greater than 6 and less than 30, Fa is a coefficient, Fb is greater than 6 and less than 30, DH is the thickness of the data line, PH is the thickness of the planarization layer, CW is the maximum dimension of the second plate of the storage capacitor in the second direction, DW is the linewidth of the signal line, the signal line includes the signal connection line, and DV is the distance between the axis of symmetry of the via extending in the first direction and the axis of symmetry of the opening nearest to the via extending in the first direction.

51. The display substrate according to claim 50, wherein, 0.009≤k1≤0.02, 0.004≤k2≤0.

02.

52. A display substrate, comprising: A substrate and a plurality of sub-pixels disposed on the substrate, each sub-pixel including a pixel circuit and a light-emitting element, the pixel circuit being configured to drive the light-emitting element, each sub-pixel including a plurality of first sub-pixels and a plurality of second sub-pixels, wherein each first sub-pixel includes a first pixel circuit including a second plate of a storage capacitor, each second sub-pixel includes a second pixel circuit including a second plate of a storage capacitor, the plurality of sub-pixels being arranged along a first direction or a second direction, the first direction and the second direction intersecting; and A pixel defining layer includes a plurality of openings configured to expose at least a portion of a first electrode of the sub-pixel and to define a light-emitting area of ​​the sub-pixel; The opening includes a first opening corresponding to the first sub-pixel and a second opening corresponding to the second sub-pixel, wherein the areas of the first opening and the second opening are different; The first sub-pixel satisfies the following relationship: △U1 =|U2-U1|≤ k1×|X2-X1| / KW1, where k1 is a coefficient, X1 is the minimum distance in the second direction between the first edge of the second plate of the storage capacitor in the first sub-pixel and the first edge of the opening corresponding to the first sub-pixel; X2 is the minimum distance in the second direction between the second edge of the second plate of the storage capacitor in the first sub-pixel and the second edge of the opening corresponding to the first sub-pixel; KW1 is the maximum size of the opening corresponding to the first sub-pixel in the second direction; U1 is the coordinate distance between the chromaticity coordinate point of the first sub-pixel in the first viewing angle and the chromaticity coordinate point in the 0-degree viewing angle; U2 is the coordinate distance between the chromaticity coordinate point of the first sub-pixel in the second viewing angle and the chromaticity coordinate point in the 0-degree viewing angle; and △U1 is the absolute value of the difference between U2 and U1. The second sub-pixel satisfies the following relationship: △U2 =|U4-U3|≤ k2×|X4-X3| / KW2, where k2 is a coefficient, X3 is the minimum distance between the first edge of the second plate of the storage capacitor in the second sub-pixel and the first edge of the opening in the second direction; X4 is the minimum distance between the second edge of the second plate of the storage capacitor in the second sub-pixel and the second edge of the opening corresponding to the second sub-pixel in the second direction; KW2 is the maximum size of the opening corresponding to the second sub-pixel in the second direction, U3 is the coordinate distance between the chromaticity coordinate point of the second sub-pixel in the first viewing angle and the chromaticity coordinate point in the 0-degree viewing angle, U4 is the coordinate distance between the chromaticity coordinate point of the second sub-pixel in the second viewing angle and the chromaticity coordinate point in the 0-degree viewing angle, and △U2 is the absolute value of the difference between U4 and U3. 0.1 < k2 / k1 < 10, The display substrate further includes: a data line, wherein the data line is configured to provide data voltage to the pixel circuit. The display substrate further includes an insulating layer and vias penetrating the insulating layer. The first electrode of the light-emitting element of the sub-pixel is connected to the pixel circuit of the sub-pixel through the vias. The insulating layer includes a passivation layer and a planarization layer. The display substrate further includes a conductive structure, wherein the conductive structure includes a first signal line and a signal connection line, the conductive structure is configured to provide a voltage signal to the pixel circuit, the first signal line extends along a second direction, the signal connection line extends along the first direction, and the signal connection line is electrically connected to the first signal line. The first sub-pixel satisfies 1 / k1 = T'(CW-DV+DW) / KW+e Fa(DH / PH) , The second sub-pixel satisfies 1 / k2 = T'(CW-DV+DW) / KW+e Fb(DH / PH) , Wherein, T' is a coefficient, T' is greater than or equal to 20 and less than 70, Fa is a coefficient, Fa is greater than 6 and less than 30, Fa is a coefficient, Fb is greater than 6 and less than 30, DH is the thickness of the data line, PH is the thickness of the planarization layer, CW is the maximum dimension of the second plate of the storage capacitor in the second direction, DW is the linewidth of the signal line, the signal line includes the signal connection line, and DV is the distance between the axis of symmetry of the via extending in the first direction and the axis of symmetry of the opening nearest to the via extending in the first direction.

53. The display substrate according to claim 52, wherein, 0.009≤k1≤0.02, 0.004≤k2≤0.

02.

54. A display device comprising a display substrate according to any one of claims 1-53.

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