Display panel, display module, and electronic device and driving method therefor

Abstract

A display panel (10), a display module (40), and an electronic device (1) and a driving method therefor, relating to the technical field of electronics, for use in achieving seamless switching between a normal mode and an always on display (AOD) mode when a low-power-consumption requirement is satisfied. By using a relatively high fundamental frequency as a driving timing for normal display, a high-refresh-rate requirement can be satisfied. By using a relatively low fundamental frequency as a driving timing for AOD, the power consumption of AOD can be reduced. Moreover, during mode switching, voltage compensation is performed on a transition frame, thereby achieving transitionless scenario switching without flicker, color shift, and black frame insertion, and thus achieving a low-power-consumption and high-performance AOD mode.

Description

Display panel, display module, electronic device and its driving method

[0001] This application claims priority to Chinese Patent Application No. 202411742019.3, filed with the State Intellectual Property Office of China on November 28, 2024, entitled "Display Panel, Display Module, Electronic Device and Driving Method Thereof", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of electronic technology, and in particular to a display panel, display module, electronic device and driving method thereof. Background Technology

[0003] With the development of display technology, display panels can use different refresh rates in different modes to balance display quality and power consumption. For example, in normal mode, a higher refresh rate is used to drive dynamic images to ensure smoothness. In always-on display (AOD) mode, a lower refresh rate is used to drive static images to reduce power consumption. This achieves a balance between display quality and power consumption.

[0004] However, how to achieve seamless switching between normal mode and AOD mode is a challenging issue that requires further research by those skilled in the art. Summary of the Invention

[0005] This application provides a display panel, display module, electronic device and driving method thereof, for achieving seamless switching between normal mode and AOD mode while meeting low power consumption requirements.

[0006] A first aspect of this application provides a display panel, which includes a gate driving circuit and a multi-row pixel circuit.

[0007] The gate driving circuit receives a first scan start signal and a first clock signal to generate a first gate scan signal. The multi-row pixel circuit receives a first voltage signal and the first gate scan signal to control the display panel to display a first image in a first mode. In an image frame, the base frequency of the first scan start signal and the first clock signal is a first frequency, and the width of the multiple pulses included in the first gate scan signal is a first fixed value. For example, if the pulse widths of the gate scan signals output by the gate driving circuit to each row are equal, the display panel enters the first mode and can display the image normally.

[0008] The gate driving circuit receives a second scan start signal and a second clock signal, generating a first sub-gate scan signal, a second sub-gate scan signal, and a third sub-gate scan signal. The first row pixel circuit receives a first compensation voltage signal and a first sub-gate scan signal; the Mth row pixel circuit receives a second compensation voltage signal and a second sub-gate scan signal; and the last row pixel circuit receives a third compensation voltage signal and a third sub-gate scan signal to control the display panel to display the second image. The Mth row pixel circuit is any row pixel circuit located between the first row pixel circuit and the last row pixel circuit. In an image frame, the base frequency of the second scan start signal and the second clock signal is a second frequency. The width of the multiple pulses included in the first sub-gate scan signal is a first fixed value; the width of the multiple pulses included in the third sub-gate scan signal is a second fixed value; and the widths of the multiple pulses included in the second sub-gate scan signal are unequal and fall within the range of the first fixed value to the second fixed value. In other words, the pulse width of the gate scan signals output by the gate driving circuit to different rows gradually changes, transitioning from the pulse timing of the first gate scan signal to the pulse timing of the second gate scan signal to complete the mode switching.

[0009] The gate driving circuit is also used to generate a second gate scan signal based on the second scan start signal and the second clock signal; the multi-row pixel circuit is used to receive the second voltage signal and the second gate scan signal, and control the display panel to display the third image in the second mode; in an image frame, the base frequency of the second scan start signal and the second clock signal is the second frequency; the width of the multiple pulses included in the second gate scan signal is a second fixed value. That is, in the second mode, the pulse width of the gate scan signal output by the gate driving circuit to each row is equal. The second mode can be, for example, a always-on display mode.

[0010] The display panel provided in this application provides different gate scanning signals output by the gate driving circuit to the pixel circuit in different modes. For everyday display scenarios, such as the first mode, a larger base frequency, such as the first frequency, is used as the driving timing for the normal display mode to meet the requirements of high refresh rate displays. For always-on display scenarios, such as the second mode, a low-power base frequency, such as the second frequency, is used as the driving timing for the always-on display mode to meet the power consumption requirements of digital and analog circuits. Based on this, during the switching between the first and second frequencies, seamless switching is achieved through transition frames. In the transition frames, voltage signals are compensated so that the brightness of the second image displayed in the transition frame is as close as possible to the brightness of the first image displayed in the target switching mode. This achieves scene switching without black insertion, while maintaining stable brightness, and almost achieves flicker-free, color-shift-free, and black insertion-free scene switching, thereby achieving a low-power, high-efficiency always-on display mode.

[0011] In one possible implementation, the compensation coefficients of the first, second, and third compensation voltage signals are different. That is, in the transition frame, the compensation degree received by the pixel circuits in different rows may be different. Because the pulse widths of the sub-gate scan signals received by the pixel circuits in different rows are different, the luminous intensity of the pixel circuits in different rows is different. Therefore, by assigning different compensation coefficients to the pixel circuits in different rows, different degrees of compensation are performed on the pixel circuits in different rows, so that the luminous intensity of each row in the compensation frame is more uniform.

[0012] In one possible implementation, the compensation coefficients of the first, second, and third compensation voltage signals are adjusted to a first set of values ​​to make the second and third images identical. For example, the display panel process is as follows: displaying the first image in the first mode – displaying the second image of the transition frame – displaying the second image (or third image) in the second mode. After the fundamental frequency changes, the display panel has no intermediate image, which can be referred to as voltage compensation. Since the second and third images are identical, their image data is the same. The compensation target of the compensation voltage signal is to compensate the brightness of the transition frame to be as close as possible to the brightness of the first frame in the second mode, requiring only brightness compensation and simplifying the compensation scheme.

[0013] In one possible implementation, the compensation coefficients of the first, second, and third compensation voltage signals are adjusted to a second set of values, making the second and third images different. For example, the display panel's display process is: displaying the first image in the first mode – displaying the second image in the transition frame – displaying the third image in the second mode. Since the second and third images are different, their image data is also different. Based on this different image data, voltage compensation can be performed, for example. That is, in addition to displaying different images, the brightness of the transition frame can be compensated to be as close as possible to the brightness of the first frame in the second mode. Therefore, inserting a second image different from the third image in the transition frame can reduce flicker caused by the difference in brightness, thus improving the user experience.

[0014] In one possible implementation, voltage compensation for the transition frame includes data voltage compensation. The first voltage signal includes a first data voltage signal, the second voltage signal includes a second data voltage signal, the first compensation voltage signal includes a first compensation data voltage signal, the second compensation voltage signal includes a second compensation data voltage signal, and the third compensation voltage signal includes a third compensation data voltage signal. Using data voltage compensation to adjust the luminous intensity in the second mode is a mature, easy-to-implement method with good compensation effect.

[0015] In one possible implementation, voltage compensation for the transition frame includes initialization voltage compensation. The first voltage signal includes a first initialization voltage signal, the second voltage signal includes a second initialization voltage signal, the first compensation voltage signal includes a first compensation initialization voltage signal, the second compensation voltage signal includes a second compensation initialization voltage signal, and the third compensation voltage signal includes a third compensation initialization voltage signal. Using the compensation initialization voltage method to adjust the luminous brightness in the second mode offers a wide variation range, high precision, and good compensation effect.

[0016] In one possible implementation, the first frequency is greater than the second frequency; the base frequency of the display panel changes from the first frequency to the second frequency, and the width of the multiple pulses included in the second sub-gate scan signal increases; conversely, when the base frequency of the display panel changes from the second frequency to the first frequency, the width of the multiple pulses included in the second sub-gate scan signal decreases. The pulse width exhibits a regular changing trend, and the compensation coefficient corresponding to the input compensation voltage is easily determined, resulting in a simple and easy-to-implement driving scheme.

[0017] In one possible implementation, in the second mode, during the first N image frames, the multi-row pixel circuit receives a fourth compensation voltage signal and a second gate scan signal to control the display panel to display the fourth image. Starting from the (N+1)th image frame, the multi-row pixel circuit receives a second voltage signal and a second gate scan signal to control the display panel to display the third image; N is a positive integer. That is, after entering the second mode, during the first N image frames, the voltage signal received by the display panel is the compensated voltage signal. Starting from the (N+1)th image frame, the voltage signal received by the display panel is the uncompensated voltage signal. In other words, when switching from the first mode to the third mode, the first N image frames after entering the third mode also need to undergo voltage signal compensation, further increasing the number of brightness transition image frames to ensure a smooth transition in display brightness. This achieves a seamless switching from the last image frame of the current mode to the transition mode image frame, then to the first N image frames of the target mode, and finally to the (N+1)th image frame of the target mode, ultimately achieving the goal of seamless switching between different modes as much as possible.

[0018] In one possible implementation, the M-row pixel circuit includes multiple pixel circuits, and the second compensation voltage signal includes multiple sub-compensation voltage signals. The multiple pixel circuits are used to receive the multiple sub-compensation voltage signals, and the compensation coefficients of the multiple sub-compensation voltage signals are the same. Since the compensation coefficients of the sub-compensation voltage signals received by the pixel circuits in the same row are the same, the compensation scheme can be simplified without affecting the display effect.

[0019] A second aspect of this application provides a display module, which includes a display driver integrated circuit and a display panel; the display driver integrated circuit is coupled to the display panel, and the display panel includes any of the display panels described in the first aspect. The beneficial effects of the display module provided in this application are the same as those of the display panel in the first aspect, and will not be repeated here.

[0020] In one possible implementation, the display driver integrated circuit is used to output a first clock signal, a first scan start signal, and a first voltage signal to the display panel for displaying a first image; the display driver integrated circuit is also used to output a second clock signal, a second scan start signal, a first compensation voltage signal, a second compensation voltage signal, and a third compensation voltage signal to the display panel for displaying a second image; the display driver integrated circuit is also used to output a second clock signal, a second scan start signal, and a second voltage signal to the display panel for displaying a third image.

[0021] A third aspect of the embodiments of this application provides an electronic device, which includes a drive controller and a display module, wherein the drive controller is coupled to the display module, and the display module includes the display module of the second aspect.

[0022] In one possible implementation, the drive controller sends a first baseband command to the display module, controlling the display module to output a first clock signal and a first scan start signal. The drive controller also sends a second baseband command to the display module, controlling the display module to output a second clock signal and a second scan start signal.

[0023] A fourth aspect of this application provides a driving method for an electronic device. The electronic device includes a driving controller, a display driving integrated circuit, and a display panel. The display panel includes a gate driving circuit and a multi-row pixel circuit. The driving method includes: the driving controller sending a first base frequency command; the display driving integrated circuit outputting a first scan start signal, a first clock signal, and a first voltage signal according to the first base frequency command; the gate driving circuit receiving the first scan start signal and the first clock signal to generate a first gate scan signal; the multi-row pixel circuit receiving the first gate scan signal and the first voltage signal; and controlling the display panel to display a first image in a first mode. In an image frame, the base frequency of the first scan start signal and the first clock signal is a first frequency, and the width of the multiple pulses included in the first gate scan signal is a first fixed value. The drive controller sends a second base frequency command, and the display drive integrated circuit outputs a second start scan signal, a second clock signal, a first compensation voltage signal, a second compensation voltage signal, and a third compensation voltage signal according to the second base frequency command. The gate drive circuit receives the second start scan signal and the second clock signal and generates a first sub-gate scan signal, a second sub-gate scan signal, and a third sub-gate scan signal. The first row pixel circuit receives the first compensation voltage signal and the first sub-gate scan signal, the Mth row pixel circuit receives the second compensation voltage signal and the second sub-gate scan signal, and the last row pixel circuit receives the third compensation voltage signal and the third sub-gate scan signal, controlling the display panel to display the second image. The Mth row pixel circuit is any row pixel circuit located between the first row pixel circuit and the last row pixel circuit. In an image frame, the base frequency of the second scan start signal and the second clock signal is the second frequency. The width of the multiple pulses included in the first sub-gate scan signal is a first fixed value, the width of the multiple pulses included in the third sub-gate scan signal is a second fixed value, and the width of the multiple pulses included in the second sub-gate scan signal is not equal and is within the range of the first fixed value to the second fixed value. The display driver integrated circuit also outputs a second start scan signal, a second clock signal, and a second voltage signal according to the second base frequency command. The gate drive circuit receives the second scan start signal and the second clock signal to generate a second gate scan signal. The multi-row pixel circuit receives the second voltage signal and the second gate scan signal to control the display panel to display a third image in the second mode. In an image frame, the base frequency of the second scan start signal and the second clock signal is a second frequency. The width of the multiple pulses included in the second gate scan signal is a second fixed value. The beneficial effects of the driving method provided in this application embodiment are the same as those of the display panel in the first aspect, and will not be repeated here.

[0024] In one possible implementation, the second and third screens are identical.

[0025] In one possible implementation, the second and third screens are different.

[0026] In one possible implementation, in the second mode, during the first N image frames, the display driver integrated circuit outputs a second start scan signal, a second clock signal, and a fourth compensation voltage signal according to a second base frequency instruction. The gate drive circuit receives the second scan start signal and the second clock signal to generate a second gate scan signal. The multi-row pixel circuit receives the fourth compensation voltage signal and the second gate scan signal to control the display panel to display a fourth image. Starting from the (N+1)th image frame, the multi-row pixel circuit receives the second voltage signal and the second gate scan signal to control the display panel to display a third image. N is a positive integer. Attached Figure Description

[0027] Figure 1 is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0028] Figure 2A is a schematic diagram of the topology of a pixel circuit provided in an embodiment of this application;

[0029] Figure 2B is a schematic diagram of a light emission control signal generation circuit provided in an embodiment of this application;

[0030] Figure 2C is a driving timing diagram of a pixel circuit provided in an embodiment of this application;

[0031] Figure 3A shows a mode switching scenario.

[0032] Figure 3B shows another mode switching scenario.

[0033] Figure 4 is a driving timing diagram of a display panel provided in an embodiment of this application;

[0034] Figure 5A shows another mode switching scenario provided by an embodiment of this application;

[0035] Figure 5B is another mode switching scenario diagram provided by an embodiment of this application;

[0036] Figure 6 is a driving timing diagram of another display panel provided in an embodiment of this application;

[0037] Figure 7 is a waveform diagram of luminous intensity provided in an embodiment of this application. Detailed Implementation

[0038] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0039] Hereinafter, the terms "second," "first," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "second," "first," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0040] This application provides an electronic device, which may be, for example, a foldable electronic device. The electronic device may be, for example, a consumer electronics product, a home electronics product, an in-vehicle electronics product, or a financial electronics product. Consumer electronics products include mobile phones, tablets, laptops, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop monitors, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) electronic devices, augmented reality (AR) electronic devices, mixed reality (MR) electronic devices, artificial intelligence (AI) electronic devices, drones, etc. Home electronics products include smart door locks, televisions, refrigerators, and rechargeable small household appliances (e.g., soymilk makers, robot vacuum cleaners), etc. In-vehicle electronics products include in-vehicle navigation systems, in-vehicle DVDs, etc. Financial electronics products include ATMs and self-service electronic devices, etc.

[0041] This application does not impose any special restrictions on the specific form of the above-mentioned electronic device. For the sake of convenience, the following embodiments all use mobile phones as an example for illustration.

[0042] Figure 1 is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0043] As shown in Figure 1, the electronic device 1 includes a display module 40 and a drive controller 30. In some embodiments, the electronic device 1 also includes a power management integrated circuit (PMIC) (not shown in Figure 1), which supplies power to the display driver integrated circuit 20 and the drive controller 30.

[0044] The drive controller 30, as the core of the electronic device 1, is used for overall system processing and control. The drive controller 30 is coupled to the display module 40 and receives image signals and control signals (e.g., provided by a central processing unit (CPU)). The drive controller 30 outputs image data that matches the interface specifications of the display module 40 based on the image signals. The drive controller 30 may include, for example, a system-on-chip (SOC). The drive controller 30 can be coupled to the display module 40 via a mobile industry processor interface (MIPI). Alternatively, the drive controller 30 can also be coupled to the display module 40 via other high-speed serial / deserial (SerDes) interfaces.

[0045] The display module 40 includes, for example, a display panel 10 and a display driver integrated circuit 20. The display driver integrated circuit 20 serves as the control core of the display panel 10, driving the display panel 10 to work and receiving data from the drive controller 30.

[0046] The display driver integrated circuit 20 is coupled to, for example, the drive controller 30, receives signals output by the drive controller 30, and provides the display panel 10 with the scanning signals and data signals required for light emission. The signals sent by the display driver integrated circuit 20 will be explained in detail below in conjunction with the structure of the pixel circuit.

[0047] For example, the display driver integrated circuit 20 receives data control signals and image data from the driver controller 30. The display driver integrated circuit 20 converts the image data into data signals and outputs the data signals to multiple data signal lines. The data signals are analog voltages corresponding to the grayscale values ​​of the image data. The display driver integrated circuit 20 is also used to output scan control signals such as clock signals, gate activation signals (STV), and reset signals required for display to the display panel 10. The display driver integrated circuit 20 may include, for example, a display driver integrated circuit (DDIC).

[0048] As the screen refresh rate changes, the display driver IC 20 sends a tearing effect (TE) signal to the driver controller 30. The driver controller 30 then sends image data to the display driver IC 20 according to the frequency of the TE signal. The TE signal ensures that the frequency at which the driver controller 30 sends image data matches the frequency at which the display driver IC 20 needs to receive image data, so that the actual screen refresh rate can respond promptly to the image refresh rate (i.e., the theoretical screen refresh rate) of the driver controller 30.

[0049] Display panel 10 serves as a data presentation unit, used to display and control data sent by drive controller 30. For example, display panel 10 may be a self-emissive display module 40 such as an organic light-emitting diode (OLED) display module 40, an active-matrix organic light-emitting diode (AMOLED) display module 40, a mini organic light-emitting diode (Mini-OLED) display module 40, a micro light-emitting diode (Micro-LED) display module 40, a micro organic light-emitting diode (Micro-OLED) display module 40, or a quantum dot light-emitting diode (QLED) display module 40. Exemplarily, display panel 10 may be a rigid display panel or a flexible display panel.

[0050] For any of the above-described display panels 10, the display panel 10 includes an active display area (AA) and a non-display area BB located around the active display area AA. The active display area AA is used to display images and includes multiple sub-pixels (SPs). Each sub-pixel is provided with a pixel circuit 11, which receives data signals provided by the display driver integrated circuit 20. The non-display area BB includes a driving circuit, which receives scan control signals provided by the display driver integrated circuit 20.

[0051] In this application, the pixel circuits 11 are described using a matrix arrangement as an example. Pixel circuits 11 arranged in a row along the horizontal direction X are called the same row pixel circuits 11, and pixel circuits 11 arranged in a row along the vertical direction Y are called the same column pixel circuits 11.

[0052] In some embodiments, the pixel circuit 11 typically includes a driving circuit composed of multiple transistors and a light-emitting device. The driving circuit generates a driving current to drive the light-emitting device to emit light, thereby realizing the light emission of the pixel circuit 11. Multiple pixel circuits 11 are arrayed on a substrate. For example, the structure including a substrate and multiple arrayed driving circuits is called an array substrate. Multiple light-emitting devices are disposed on the array substrate, and each light-emitting device is coupled to a pixel circuit. Alternatively, the display panel 10 includes an array substrate and multiple light-emitting devices. The array substrate includes a substrate and an arrayed driving circuit, and the driving circuit and light-emitting devices are coupled to form the pixel circuit 11.

[0053] Figure 2A is a schematic diagram of the topology of a pixel circuit provided in an embodiment of this application.

[0054] In some embodiments, as shown in FIG2A, the pixel circuit 11 includes an anode reset circuit 111, a second node initialization circuit 112, a first node initialization circuit 113, a write and threshold compensation circuit 114, a light emission control circuit 115, and a light emission device 116. The pixel circuit 11 shown in FIG2A is only an illustration and is not intended to limit anything.

[0055] The anode reset circuit 111 includes a seventh transistor T7, the second node initialization circuit 112 includes an eighth transistor T8, the first node initialization circuit 113 includes a fourth transistor T4 and a third transistor T3, the write and threshold compensation circuit 114 includes a second transistor T2, a first transistor T1, a third transistor T3, and a storage capacitor Cst, and the light-emitting control circuit 115 includes a fifth transistor T5 and a sixth transistor T6. The first transistor T1 is a driving transistor, and the remaining transistors are switching transistors. The first node initialization circuit 113 and the write and threshold compensation circuit 114 share the third transistor T3. The light-emitting device 116 is, for example, an OLED. The gates of the seventh transistor T7 and the eighth transistor T8 are controlled by a first control signal terminal S1, the gate of the fourth transistor T4 is controlled by a second control signal terminal S2, the gate of the third transistor T3 is controlled by a third control signal terminal S3, and the gate of the second transistor T2 is controlled by a fourth control signal terminal S4.

[0056] In some embodiments, the display panel 10 includes an array substrate and a plurality of light-emitting devices 116 disposed on the array substrate. The array substrate includes a substrate and an anode reset circuit 111, a second node initialization circuit 112, a first node initialization circuit 113, a write and threshold compensation circuit 114, and a light-emitting control circuit 115 disposed on the substrate.

[0057] The light-emitting device 116 includes a first electrode layer, a first light-emitting layer, a conductive connection layer, a second light-emitting layer, and a second electrode layer sequentially disposed on an array substrate. This type of display panel 10 is referred to in the art as a single-layer OLED panel.

[0058] In other embodiments, the light-emitting device 116 includes a first electrode layer, a first light-emitting layer, a conductive connection layer, a second light-emitting layer, and a second electrode layer sequentially disposed on an array substrate. This type of display panel 10 is referred to in the art as a tandem OLED panel. Exemplarily, the light-emitting device 116 is equivalent to including a first sub-light-emitting device and a second sub-light-emitting device connected in series via a conductive connection layer.

[0059] The first and second light-emitting layers are used to emit light of the same color. Taking the first light-emitting layer as an example, the first light-emitting layer includes an organic light-emitting layer, and may further include at least one of a hole injection layer, a hole transport layer, an electron blocking layer, an electron transport layer, and an electron injection layer. The organic light-emitting layer in the first and second light-emitting layers can be used to emit light of the same color or to emit light of different colors. Of course, the light-emitting device 116 may include more light-emitting layers, and a conductive connection layer is disposed between adjacent light-emitting layers.

[0060] For example, the first electrode layer serves as the anode of the light-emitting device 116, and the second electrode layer serves as the cathode. A relatively high potential is applied to the first electrode layer, and a relatively low potential is applied to the second electrode layer. Holes are injected from the first electrode layer into the first light-emitting layer, and electrons are injected from the second electrode layer through the conductive connection layer into the first light-emitting layer. The energy generated after the holes and electrons recombine in the first light-emitting layer can excite it to emit light. Similarly, holes are injected from the first electrode layer through the conductive connection layer into the second light-emitting layer, and electrons are injected from the second electrode layer into the second light-emitting layer. The energy generated after the holes and electrons recombine in the second light-emitting layer can excite it to emit light. Both the second electrode layer and the conductive connection layer are transparent conductive layers. Light of the same color emitted by the first and second light-emitting layers is superimposed and emitted from the second electrode layer side.

[0061] As shown in Figure 1, in some embodiments, the display panel 10 further includes a light emission control signal generation circuit 12, which is used to transmit a light emission control signal em to the light emission control signal terminals EM of the plurality of pixel circuits 11 in the display panel 10.

[0062] Figure 2B is a schematic diagram of a light emission control signal generation circuit provided in an embodiment of this application.

[0063] In some embodiments, as shown in FIG2B, the light emission control signal generation circuit 12 includes at least two cascaded shift registers RS(1) to RS(n). The signal input terminal VI of the first-stage shift register RS(1) is used to receive the light emission control start signal STV-em. Except for the first-stage shift register RS(1), the signal input terminal VI of each stage shift register RS(m) is coupled to the output terminal GO of its previous stage shift register RS(m-1). When the light emission control start signal STV-em is an on signal, the first-stage shift register RS1 of the light emission control signal generation circuit 12 starts working, and subsequently, the multi-stage shift registers start working one after another.

[0064] For example, the light emission control start signal STV-em is provided by the display driver integrated circuit 20. The display panel 10 is used to receive the light emission control start signal STV-em sent by the display driver integrated circuit 20 and generate the light emission control signal em required by the pixel circuit 11. The timing of the light emission control signal em received by each row of pixel circuits is the same as the timing of the light emission control start signal STV-em.

[0065] Similarly, in some embodiments, the display panel 10 further includes a first control signal generation circuit (or can be understood as an anode reset control signal generation circuit) 13, which is used to transmit a first control signal s1 for each row of pixel circuits 11. The reset start signal STV-s1 required by the first control signal generation circuit 13 is provided by the display driver integrated circuit 20. The timing of the first control signal s1 received by each row of pixel circuits is the same as the timing of the reset start signal STV-s1.

[0066] The display panel 10 also includes a second control signal generation circuit 14, which transmits a second control signal s2 to each row of pixel circuits 11. The initialization start signal STV-s2 required by the second control signal generation circuit 14 is provided by the display driver integrated circuit 20. The timing of the second control signal s2 received by each row of pixel circuits is the same as the timing of the initialization start signal STV-s2.

[0067] The display panel 10 also includes a third control signal generation circuit 15, which transmits a third control signal s3 to each row of pixel circuits 11. The compensation start signal STV-s3 required by the third control signal generation circuit 15 is provided by the display driver integrated circuit 20. The timing of the third control signal s3 received by each row of pixel circuits is the same as the timing of the compensation start signal STV-s3.

[0068] The display panel 10 also includes a fourth control signal generation circuit 16, which transmits a fourth control signal s4 to each row of pixel circuits 11. The write start signal STV-s4 required by the fourth control signal generation circuit 16 is provided by the display driver integrated circuit 20. The timing of the fourth control signal s4 received by each row of pixel circuits is the same as the timing of the write start signal STV-s4.

[0069] Therefore, the display state of the display panel 10 can be adjusted by adjusting the timing of the light emission control start signal STV-em, the reset start signal STV-s1, the initialization start signal STV-s2, the compensation start signal STV-s3, and the write start signal STV-s4.

[0070] Figure 2C is a driving timing diagram of a pixel circuit provided in an embodiment of this application.

[0071] As shown in Figures 2A and 2C, the light emission process of the pixel circuit 11 in one frame can be divided into an initialization stage t1, a threshold compensation stage t2, a light emission stage t3, and an anode reset stage t4.

[0072] During initialization phase t1:

[0073] The second control signal s2 at the second control signal terminal S2 and the third control signal s3 at the third control signal terminal S3 change from low to high and then back to low. Consequently, the fourth transistor T4 and the third transistor T3 change from off to on and then back to off. The first control signal s1 at the first control signal terminal S1, the fourth control signal s4 at the fourth control signal terminal S4, and the light emission control signal em at the light emission control signal terminal EM all remain at high levels. Therefore, the seventh transistor T7, the eighth transistor T8, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 all remain off.

[0074] During initialization phase t1, the first transistor T1, the third transistor T3, and the fourth transistor T4 are turned on, enabling voltage control of the fourth node N4, the second node N2, and the first node N1. Since the third transistor T3 and the fourth transistor T4 act as switches, and the first node N1 is electrically connected to the control electrode of the first transistor T1, and the second node N2 is electrically connected to the fourth node N4, initialization phase t1 achieves voltage control of the control electrode of the first transistor T1, the first node N1, the second node N2, and the fourth node N4. This makes the control electrode voltage of the first transistor T1, the voltage of the first node N1, the voltage of the second node N2, and the voltage of the fourth node N4 the first initialization voltages of the first initialization voltage terminal Vinit1, effectively resetting the voltages of the control electrode of the first transistor T1, the first node N1, the second node N2, and the fourth node N4.

[0075] During the threshold compensation phase t2:

[0076] The first control signal s1 at the first control signal terminal S1 changes from high to low and then back to high. Consequently, the second transistor T2 changes from off to on and then back to off. The third control signal s3 at the third control signal terminal S3 changes from low to high and then back to low. Consequently, the third transistor T3 changes from off to on and then back to off. The first control signal s1 at the first control signal terminal S1 and the light emission control signal em at the light emission control signal terminal EM both remain high, while the second control signal s2 at the second control signal terminal S2 remains low. Therefore, the seventh transistor T7, the eighth transistor T8, the fifth transistor T5, the sixth transistor T6, and the fourth transistor T4 all remain off.

[0077] In the threshold compensation stage t2, the second transistor T2, the third transistor T3, and the first transistor T1 are turned on, realizing the storage of the data voltage at the data voltage terminal Vd in the storage capacitor Cst, thus completing the writing of the data voltage. This also compensates for the threshold voltage of the first transistor T1. The threshold voltage compensation process of the first transistor T1 can be considered as the process of the first transistor T1 changing from the on state to the off state.

[0078] During the luminescence stage t3:

[0079] The light-emitting control signal em at the light-emitting control signal terminal EM changes from high level to low level, and then from low level to high level. Consequently, the sixth transistor T6 and the fifth transistor T5 change from off to on, and then from on to off. The second control signal s2 at the second control signal terminal S2 and the third control signal s3 at the third control signal terminal S3 remain at low level, while the fourth transistor T4 and the third transistor T3 remain off. The first control signal s1 at the first control signal terminal S1 and the fourth control signal s4 at the fourth control signal terminal S4 remain at high level, while the seventh transistor T7, the eighth transistor T8, and the second transistor T2 remain off.

[0080] During the light-emitting stage t3, the fifth transistor T5, the first transistor T1, and the sixth transistor T6 are turned on respectively, transmitting driving current to the light-emitting device 116, and the light-emitting device 116 emits light under the drive of the driving current.

[0081] Anode reset stage t:

[0082] The first control signal s1 at the first control signal terminal S1 changes from high to low and then back to high. Consequently, the seventh transistor T7 and the eighth transistor T8 change from off to on and then back to off. The second control signal s2 at the second control signal terminal S2 and the third control signal s3 at the third control signal terminal S3 remain low. The fourth control signal s4 at the fourth control signal terminal S4 and the light emission control signal em at the light emission control signal terminal EM remain high. The third transistor T3, the fourth transistor T4, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 all remain off.

[0083] During the anode reset phase t, the seventh transistor T7 and the eighth transistor T8 are turned on, realizing the control of the voltage of the second node N2 and the anode voltage of the light-emitting device 116. This makes the voltage of the second node N2 the third initialization voltage of the third initialization voltage terminal Vinit3, and the voltage of the anode of the light-emitting device 116 the second initialization voltage of the second initialization voltage terminal Vinit2, thus realizing the reset of the voltage of the second node N2 and the anode voltage of the light-emitting device 116.

[0084] When the display panel 10 displays at different brightness levels, the control signals or voltages received by the pixel circuit 11 in the display panel 10 will be dynamically adjusted in real time.

[0085] To enhance user experience, the current electronic device 1 employs an always-on display (AOD) mode to continuously display some time and image information on the display panel 10 of the electronic device 1. This requires the AOD mode to have low power consumption and be able to switch continuously with the normal mode to achieve a dynamically optimal display experience.

[0086] Figure 3A shows a mode switching scenario.

[0087] In some embodiments, as shown in Figure 3A, a low refresh rate full-screen AOD mode is used for display. Normal mode displays the image, while AOD mode uses a 1Hz refresh rate. In other words, AOD mode is the normal mode at 1Hz. This allows for lossless switching between normal and AOD modes. However, in full-screen AOD mode, the base frequency of the display panel 10 remains unchanged (the clock signal frequency remains unchanged), resulting in higher power consumption for the display panel 10. Furthermore, since the base frequency is the same in AOD mode and normal mode, only the refresh rate differs, some dynamic displays in AOD mode directly revert to normal mode, failing to achieve power saving.

[0088] Figure 3B shows another mode switching scenario.

[0089] In other embodiments, as shown in Figure 3B, a low-base-frequency All-Day AOD mode is used for display. In normal mode, the display panel 10 uses a higher base-frequency; in All-Day AOD mode, the base-frequency of the display panel 10 is reduced, thus significantly reducing the power consumption of the display panel 10. However, since the base-frequency in All-Day AOD mode is different from that in normal mode, a completely black screen is inserted when switching between All-Day AOD mode and normal mode to eliminate flicker and color shift issues, but this also affects the user experience.

[0090] This application provides an electronic device that, by using a reduced base frequency as the basic driving frequency for AOD mode, achieves seamless switching between AOD mode and normal mode without flickering or black bars, ultimately achieving low power consumption and high performance for the electronic device 1.

[0091] Figure 4 is a driving timing diagram of a display panel provided in an embodiment of this application.

[0092] This application provides a display panel 10, which includes a gate driving circuit and a multi-row pixel circuit 11. The gate driving circuit may be, for example, a light emission control signal generation circuit 12 in the display panel 10, and the gate scan signal output by the gate driving circuit is a light emission control signal em. Alternatively, the gate driving circuit may be, for example, a first control signal generation circuit 13 in the display panel 10, and the gate scan signal output by the gate driving circuit is a first control signal s1. Another example is a second control signal generation circuit 14 in the display panel 10, and the gate scan signal output by the gate driving circuit is a second control signal s2. A third control signal generation circuit 15 in the display panel 10, and the gate scan signal output by the gate driving circuit is a third control signal s3. Finally, a fourth control signal generation circuit 16 in the display panel 10, and the gate scan signal output by the gate driving circuit is a fourth control signal s4.

[0093] The gate drive circuit receives the first scan start signal stv1 and the first clock signal clk1 shown in Figure 4, and generates the first gate scan signal vo1. The multi-row pixel circuit 11 receives the first voltage signal v1 and the first gate scan signal vo1, and controls the display panel 10 to display the first image in the first mode. Therefore, each row of sub-pixels in the display panel 10 is refreshed using the first frequency as the basic refresh frequency. The timing of the gate scan signals received by each row pixel circuit 11 is the same, and the magnitude of the first voltage signal v1 received by each row pixel circuit 11 is related to the image to be displayed. For example, the first voltage signal v1 is an uncompensated voltage signal.

[0094] The base frequency can be understood as the basic refresh rate of the display panel 10. The base frequency multiplied by the number of pulses in one image frame equals the refresh rate of the display panel 10. Taking Figure 4 as an example, the first mode is the normal mode, the first frequency of the display panel 10 is 120HZ, one image frame includes 3 pulses, and the refresh rate of the display panel 10 is 360 (3*120)HZ.

[0095] In the first mode, in an image frame, the base frequency of the first clock signal clk1 and the first gate scan signal stv1 is a first frequency (e.g., 120 Hz), and the width of the plurality of first scan pulses included in the first gate scan signal stv1 is a first fixed value. This application embodiment does not limit the specific value of the first fixed value; the value of the first fixed value may differ in different electronic devices 1.

[0096] In this embodiment of the application, the pulse width can be understood as the duration of a signal being enabled within a pulse cycle, such as the duration of a low-level signal.

[0097] The gate drive circuit is also used to receive the second scan start signal stv2 and the second clock signal clk2, and generate the second gate scan signal vo2. The multi-row pixel circuit 11 is used to receive the second voltage signal v2 and the second gate scan signal vo2, and control the display panel 10 to display the third image in the second mode. Therefore, each row of sub-pixels in the display panel 10 is refreshed using the second base frequency as the basic refresh frequency. The timing of the gate scan signals received by each row pixel circuit 11 is the same, and the magnitude of the second voltage signal v2 received by each row pixel circuit 11 is related to the image to be displayed. For example, the second voltage signal v2 is an uncompensated voltage signal.

[0098] Taking Figure 4 as an example, the second mode is AOD mode, the second base frequency of the display panel 10 is 30 Hz, one image frame includes 3 pulses, and the refresh rate of the display panel 10 is 90 (3*30) Hz. In the second mode, in one image frame, the base frequency of the second scan start signal stv2 and the second clock signal clk2 is the second frequency (e.g., 30 Hz), and the width of the multiple second scan pulses included in the second gate scan signal stv2 is the second fixed value. This application embodiment does not limit the specific value of the second fixed value; the value of the second fixed value may differ in different electronic devices 1.

[0099] When switching from the first mode to the second mode, the base frequency of the display panel 10 changes, and there will be a transition frame in between, during which the displayed image will flicker.

[0100] Based on this, in some embodiments, the gate driving circuit is also used to receive the second scan start signal stv2 and the second clock signal clk2 shown in FIG. 4, generate the first sub-gate scan signal vo31, the second sub-gate scan signal vo32, and the third sub-gate scan signal vo33, and control the display panel 10 to display a transition frame image. The transition frame image can be understood as a transition image inserted in the middle when the first mode and the second mode are switched. The width of the multiple first sub-gate pulses included in the first sub-gate scan signal vo31 is the same as the width of the first gate pulses included in the first gate scan signal vo1, which is a first fixed value. The width of the multiple third sub-gate pulses included in the third sub-gate scan signal vo33 is the same as the width of the second gate pulses included in the second gate scan signal vo2, which is a second fixed value, so as to complete the transition of the base frequency change. The width of the multiple second sub-gate pulses included in the second sub-gate scan signal vo32 is not equal and is located in the range between the first fixed value and the second fixed value. That is, the width of the second sub-gate pulse can be equal to the first fixed value, the width of the second sub-gate pulse can be equal to the second fixed value, or the width of the second sub-gate pulse can be any value within the range of the first fixed value to the second fixed value. The widths of the multiple second sub-gate pulses included in the second sub-gate scan signal vo32 can be completely unequal, that is, the widths of the multiple second sub-gate pulses are all different, for example, the gate scan signal received by the pixel circuit in the Mth row of Figure 4. The widths of the multiple second sub-gate pulses included in the second sub-gate scan signal vo32 can also not be completely unequal, that is, the widths of some of the second sub-gate pulses can be equal, for example, the gate scan signal received by the pixel circuit in the second row of Figure 4.

[0101] The first row pixel circuit 11 is used to receive the first compensation voltage signal v. 补偿1 And the first sub-gate scan signal vo31, the M-row pixel circuit 11 is used to receive the second compensation voltage signal v 补偿2 The second sub-gate scan signal vo32, and the last row pixel circuit 11 are used to receive the third compensation voltage signal v 补偿3 The third sub-gate scan signal vo33 is used to control the display panel 10 to display the second screen.

[0102] The Mth row of pixel circuits refers to any row of pixel circuits located between the first row of pixel circuits 11 and the last row of pixel circuits 11. When M takes different values, the width of the second sub-gate pulses included in the second sub-gate scan signal vo32 may be different. For example, the larger the value of M, the closer the width of each second sub-gate pulse included in the second sub-gate scan signal vo32 is to the second fixed value.

[0103] The flickering problem of the display panel 10 is improved by compensating for the voltage signal in the transition frame.

[0104] In some embodiments, the first compensation voltage signal v 补偿1 Second compensation voltage signal v 补偿2 and the third compensation voltage signal v 补偿3 The compensation coefficients are not exactly the same or completely different. For example, the first compensation voltage signal v 补偿1 The compensation coefficient is 0, and the second compensation voltage signal v 补偿2 and the third compensation voltage signal v 补偿3 The compensation coefficient is an integer greater than 0, and the second compensation voltage signal v 补偿2 and the third compensation voltage signal v 补偿3 The compensation coefficients are different. When M takes different values, the second compensation voltage signal v 补偿2 The compensation coefficients may also differ.

[0105] Because the pulse widths of the sub-gate scanning signals received by different row pixel circuits 11 are different, the luminous intensity of different row pixel circuits 11 is different. Therefore, by assigning different compensation coefficients to different row pixel circuits 11, different degrees of compensation are performed on the different row pixel circuits 11 to make the luminous intensity of each row of the compensation frame more uniform.

[0106] The frequency of the TE signal is consistent with the refresh rate of the display panel 10, and the frequency of the TE signal is the frequency at which the display driver integrated circuit 20 needs to receive image data.

[0107] Of course, this embodiment of the application illustrates the case where each row of pixel circuits 11 receives the same gate scan signal. Alternatively, multiple adjacent rows of pixel circuits 11 may receive the same gate scan signal. For example, the multiple rows of pixel circuits 11 can be regarded as a whole.

[0108] The display panel 10 provided in this application embodiment outputs different gate scanning signals from the gate driving circuit to the pixel circuit 11 in different modes. For everyday regular display scenarios, a larger base frequency, such as the first frequency, is used as the driving timing for normal display, thereby meeting the requirements of high refresh rate regular display. For AOD display scenarios, a low-power base frequency, such as the second base frequency, is used as the driving timing for maintaining display, to meet the power consumption requirements of digital and analog circuits. Based on this, during the switching between the first frequency and the second frequency, seamless switching is achieved through transition frames. In the transition frames, voltage signals are compensated so that the brightness of the second image displayed in the transition frame is as close as possible to the brightness of the first image displayed in the target switching mode. This achieves scene switching without black insertion, but the brightness remains stable, almost achieving flicker-free, color-shift-free, and black insertion-free scene switching, thereby achieving a low-power, high-performance AOD mode.

[0109] In some embodiments, when the base frequency of the display panel 10 switches from a first frequency to a second frequency, the first compensation voltage signal v 补偿 1. Second compensation voltage signal v 补偿2 and the third compensation voltage signal v 补偿3 The compensation coefficient is the first set of values. The second screen displayed on the display panel 10 under the transition frame is the same as the third screen displayed on the display panel 10 under the second mode.

[0110] The first set of values ​​includes the first compensation voltage signal v. 补偿1 Second compensation voltage signal v 补偿2 and the third compensation voltage signal v 补偿3 Each factor has its own compensation coefficient. The compensation coefficient can be greater than 1 or less than 1. For example, when increasing brightness is needed, the compensation coefficient is greater than 1. When decreasing brightness is needed, the compensation coefficient is less than 1.

[0111] For example, the image data of the second and third frames are the same. The compensation target of the compensation voltage signal is to compensate the brightness of the transition frame to be as close as possible to the brightness of the first frame in the second mode. Only brightness compensation is needed, simplifying the compensation scheme. As shown in Figure 5A, the display process of the display panel 10 is as follows: display the first frame in the first mode - display the third frame of the transition frame - display the third frame in the second mode. After the fundamental frequency changes, the display panel 10 has no intermediate frame, which can be called voltage compensation.

[0112] In other embodiments, when the base frequency of the display panel 10 switches from a first frequency to a second frequency, the first compensation voltage signal v 补偿1 Second compensation voltage signal v 补偿2 and the third compensation voltage signal v 补偿3 The compensation coefficient is the second set of values, and the second screen displayed on the display panel 10 in the transition frame and the third screen displayed on the display panel 10 in the second mode are different.

[0113] For example, the image data of the second and third frames are different. Based on the different image data, voltage compensation can also be performed, for example. That is, in addition to displaying different frames, the brightness of the transition frame can be compensated to be as close as possible to the brightness of the first frame in the second mode. As shown in Figure 5B, the display process of the display panel 10 is as follows: displaying the first frame in the first mode - displaying the second frame of the transition frame - displaying the third frame in the second mode. After the fundamental frequency changes, the display panel 10 has an intermediate frame, which can be called user interface (UI) compensation. Inserting a second frame that is different from the third frame in the transition frame can reduce the flicker caused by the difference in brightness and improve the user experience because the frames themselves are different.

[0114] The second set of values ​​includes the first compensation voltage signal v. 补偿1 Second compensation voltage signal v 补偿2 and the third compensation voltage signal v 补偿3 Each has its own compensation coefficient. The compensation coefficients for each compensation voltage when the second and third screens are the same may differ from those when the second and third screens are the same. For example, the two schemes can be applied to different electronic devices 1.

[0115] In some embodiments, the voltage signal includes a data voltage signal. For example, the first voltage signal v1 includes a first data voltage signal, the second voltage signal v2 includes a second data voltage signal, and the first compensation voltage signal v 补偿1 Includes a first compensation data voltage signal and a second compensation voltage signal v. 补偿2 Includes the second compensation data voltage signal and the third compensation voltage signal v. 补偿3 This includes the third data voltage signal.

[0116] For example, by measuring the data voltage during scene switching and comparing the data voltage of the transition frame with that of the target mode, it can be confirmed whether data voltage compensation exists during the switching process. This application does not limit the method for determining the data voltage compensation coefficient; related technologies that achieve uniform display brightness through data voltage compensation are applicable to this application.

[0117] The scheme for compensating for transition frames includes compensating for the data voltage within the transition frames. By compensating for the data voltage of the transition frames, brightness compensation of the displayed image is achieved, enabling flicker-free switching.

[0118] In other embodiments, the voltage signal includes an initialization voltage signal. A first voltage signal v1 includes a first initialization voltage signal, a second voltage signal v2 includes a second initialization voltage signal, and a first compensation voltage signal v... 补偿1 Includes a first compensation initialization voltage signal and a second compensation voltage signal v. 补偿2 Includes the second compensation initialization voltage signal and the third compensation voltage signal v. 补偿3 This includes the third initialization voltage signal.

[0119] The initialization voltage signal includes one or more of the following: the first initialization voltage at the first initialization voltage terminal Vinit1, the second initialization voltage at the second initialization voltage terminal Vinit2, or the third initialization voltage at the third initialization voltage terminal Vinit3. That is, when compensating for the initialization voltage, one or more of the first initialization voltage, the second initialization voltage, and the third initialization voltage can be compensated. When compensating for multiple initialization voltages, the compensation coefficients of the multiple initialization voltages can be completely different or not completely the same for pixel circuits 11 in different rows.

[0120] By measuring the initialization voltage during scene switching and comparing it with the initialization voltage in the target mode, it can be confirmed whether initialization voltage compensation exists during the switching process. This application does not limit the method for determining the initialization voltage compensation coefficient; related technologies that achieve uniform display brightness through initialization voltage compensation are applicable to this application.

[0121] The scheme for compensating for transition frames includes compensating for the initial voltage within the transition frame. By compensating for the initial voltage of the transition frame, high brightness compensation of the displayed image is achieved, enabling flicker-free switching.

[0122] Table 1 shows that when the display brightness is 200 nits, the grayscale of each pixel row of an electronic device 1 in AOD mode is L1. In the transition frame, the grayscale of each pixel row is L2 obtained through compensation of data voltage and / or initialization voltage.

[0123] In some embodiments, as shown in Table 1, the compensation coefficients of the voltage signals received by the pixel circuits 11 in different rows are not entirely the same. As described above, in the transition frame, the timing of the sub-gate scan signals received by the pixel circuits 11 in different rows is different. Therefore, by performing different degrees of data voltage compensation on the pixel circuits 11 in different rows, the uniformity of the full-screen brightness can be improved.

[0124] In some embodiments, as shown in Table 1, the compensation coefficients of the voltage signals received by the pixel circuits 11 in the same row are the same. For example, the pixel circuit 11 in the Mth row includes multiple pixel circuits 11, and the second compensation voltage signal v 补偿2 It includes multiple sub-compensation voltage signals, and multiple pixel circuits 11 are used to receive multiple sub-compensation voltage signals, and the compensation coefficients of the multiple sub-compensation voltage signals are the same. This can make the luminous brightness of sub-pixels in the same row consistent.

[0125] Table 1 Luminous intensity 200 nits

[0126] Table 2 Luminous intensity 90 nits

[0127] Table 2 shows the grayscale of each pixel row in AOD mode of an electronic device 1 when the display brightness is 90 nits, according to an embodiment of this application. In the transition frame, the grayscale of each pixel row is L2 obtained through compensation of data voltage and / or initialization voltage. Comparing Table 1 and Table 2, it can be seen that in some embodiments, the compensation coefficient of the voltage signal may also be different under different luminous brightness. That is to say, in the embodiments of this application, the compensation of the voltage signal has great flexibility.

[0128] In some embodiments, the first frequency is 120Hz, and the refresh rate of the display panel 10 can be, for example, 360Hz or an integer multiple of 360Hz. This allows for switching between 90Hz and 120Hz in the first mode, meeting the requirements for normal display. The second frequency is 30Hz, which, while meeting the display requirements in AOD mode, can reduce power consumption.

[0129] In some embodiments, the first frequency is greater than the second frequency, the base frequency of the display panel 10 changes from the first frequency to the second frequency, and the width of the plurality of second sub-gate pulses included in the second sub-gate scan signal vo32 shows an increasing trend.

[0130] For example, the second sub-gate scan signal vo32 includes three second sub-gate pulses. Depending on the value of M, the widths of the three second sub-gate pulses can increase sequentially. Alternatively, the widths of the first two second sub-gate pulses can be the same, and the width of the third second sub-gate pulse can increase. Another possibility is that the width of the second second sub-gate pulse is greater than the width of the first second sub-gate pulse and equal to the width of the third second sub-gate pulse.

[0131] For example, the scan time for one row is 8.33ms, the time difference between each row is 0.03ms, and in the second sub-gate scan signal vo32 received by the pixel circuit of the Mth row, the width of the second sub-gate pulse appearing in the first (8.33-M*0.33)ms is a first fixed value, and the width of the second sub-gate pulse appearing in the remaining M*0.33ms is greater than the first fixed value and less than or equal to the second fixed value.

[0132] In other embodiments, the first frequency is greater than the second frequency, the first mode is the normal mode, and the second mode is the AOD mode. For example, the first frequency is 120 Hz, and the second frequency is 30 Hz. The base frequency of the display panel 10 changes from the second frequency to the first frequency, and the width of the plurality of second sub-gate pulses included in the second sub-gate scan signal vo32 decreases.

[0133] For example, the second sub-gate scan signal vo32 includes three second sub-gate pulses. Depending on the value of M, the widths of the three second sub-gate pulses can decrease sequentially. Alternatively, the widths of the first two second sub-gate pulses can be the same, and the width of the third second sub-gate pulse can decrease. Another possibility is that the width of the second second sub-gate pulse is less than or greater than the width of the first second sub-gate pulse, but equal to the width of the third second sub-gate pulse.

[0134] Figure 6 is a driving timing diagram of another display panel provided in an embodiment of this application.

[0135] In some embodiments, as shown in FIG6, when the base frequency of the display panel 10 changes from a first frequency to a second frequency, and the gate drive circuit receives a second scan start signal stv2 and a second clock signal clk2 to generate a second gate scan signal vo2, in the first N image frames, the multi-row pixel circuit 11 receives a fourth compensation voltage signal v 补偿4 The second gate scan signal vo2 controls the display panel 10 to display the fourth image. Starting from the (N+1)th image frame, the multi-row pixel circuit 11 receives the second voltage signal v2 and the second gate scan signal vo2 to control the display panel 10 to display the third image. N is a positive integer, such as 1, 2, 3, 4, etc. The fourth image and the third image can be the same or different; this embodiment does not limit this.

[0136] In other words, after entering the second mode, the voltage signal received by the display panel 10 in the first N image frames is the compensated voltage signal. Starting from the (N+1)th image frame, the voltage signal received by the display panel 10 is the uncompensated voltage signal. That is, when switching from the first mode to the second mode, the voltage signal also needs to be compensated in the first N image frames after entering the second mode, further increasing the number of image frames with brightness transition, so that the display brightness of the display panel 10 transitions smoothly, in order to achieve as little flicker as possible to the naked eye when switching scenes.

[0137] For example, when switching from normal mode to AOD mode, the first N image frames after entering AOD mode need to be compensated for voltage signals. Or, for example, when switching from AOD mode to normal mode, the first N image frames after entering normal mode need to be compensated for voltage signals.

[0138] When N is greater than 1, the voltage signals of multiple image frames after entering the second mode need to be compensated. The compensation coefficients for the voltage signals in multiple image frames can be the same or different. For example, the compensation coefficients for the voltage signals can be determined based on the brightness difference between two image frames. In addition, the compensation coefficients for the voltage signals received by different row pixel circuits 11 in the same image frame may also be different.

[0139] Figure 7 is a waveform diagram of luminous intensity provided in an embodiment of this application.

[0140] For example, as shown in Figure 7, taking the grayscale of the normal mode frame as L64 and the grayscale of the AOD mode frame as L57 as an example, there will naturally be a transition frame when switching from normal mode to AOD mode. By performing voltage signal compensation on the transition frame, or further performing voltage signal compensation on the first frame or more frames of AOD mode, it is possible to achieve the goal that the instantaneous brightness of the last frame of normal mode, the instantaneous brightness of the transition mode frame, the instantaneous brightness of the first frame of AOD mode, and the instantaneous brightness of subsequent frames of AOD mode are different, but the average brightness of the last frame of normal mode, the average brightness of the first frame of AOD mode, and the average brightness of subsequent frames of AOD mode are almost the same or have a smooth transition, so as to achieve seamless switching between different modes.

[0141] The display panel 10 provided in this application embodiment can be applied in the display module 40 provided in this application embodiment. The display driver integrated circuit 20 is coupled to the display panel 10 and is used to provide the above-mentioned scan start signal and clock signal to the display panel 10.

[0142] For example, the display driver integrated circuit 20 is used to output a first clock signal clk1, a first scan start signal stv1 and a first voltage signal v1 required to display the first image to the display panel 10.

[0143] For example, the drive controller 30 in the electronic device 1 sends a first baseband command to the display driver integrated circuit 20, controlling the display driver integrated circuit 20 to output a first clock signal clk1 and a first scan start signal stv1 with a baseband frequency of a first frequency. The first baseband command indicates that the display panel 10 enters a first mode.

[0144] The display driver integrated circuit 20 is also used to output to the display panel 10 a second clock signal clk2, a second scan start signal stv2, and a first compensation voltage signal v required for displaying the second image. 补偿1 Second compensation voltage signal v 补偿2 and the third compensation voltage signal v 补偿3 .

[0145] The display driver integrated circuit 20 is also used to output a second clock signal clk2, a second scan start signal stv2, and a second voltage signal v2 to the display panel 10 for displaying the third screen.

[0146] For example, the drive controller 30 in electronic device 1 sends a second baseband command to the display driver integrated circuit 20, controlling the display driver integrated circuit 20 to output a second clock signal clk2 with a baseband frequency of a second frequency and a second scan start signal stv2. The second baseband command indicates that the display panel 10 enters a second mode.

[0147] When the electronic device 1 provided in this application embodiment includes the above-described display panel 10, the driving method of the electronic device 1 provided in this application embodiment includes:

[0148] The drive controller 30 sends a first baseband command, and the display drive integrated circuit 20, according to the first baseband command, outputs the aforementioned first scan start signal stv1, first clock signal clk1, and first voltage signal v1 to the display panel 10 to drive the display panel 10 to display the first image in the first mode. For example, the display enters normal mode and displays the image normally.

[0149] The drive controller 30 sends a second base frequency command, and the display drive integrated circuit 20 outputs the second start scan signal stv2, the second clock signal clk2, and the first compensation voltage signal v to the display panel 10 according to the second base frequency command. 补偿1 Second compensation voltage signal v 补偿2 and the third compensation voltage signal v 补偿3 The control display panel 10 displays the second screen.

[0150] The display driver integrated circuit 20 continues to follow the second baseband command, continuously outputting the aforementioned second start scan signal stv2, second clock signal clk2, and second voltage signal v2 to the display panel 10, controlling the display panel 10 to display the third screen in the second mode. For example, the display enters AOD mode, displaying a low-frequency image.

[0151] In some embodiments, the driving method of the electronic device 1 further includes: in a second mode, during the first N image frames, the display driving integrated circuit 20 outputs a second start scan signal stv2, a second clock signal clk2, and a fourth compensation voltage signal v. 补偿4 The display panel 10 is controlled to display the fourth frame after voltage compensation. Starting from the (N+1)th image frame, the display driver integrated circuit 20 outputs the second start scan signal stv2, the second clock signal clk2, and the second voltage signal v2, controlling the display panel 10 to display the third frame without voltage compensation. The image data of the third and fourth frames can be the same.

[0152] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A display panel, characterized in that, The display panel includes a gate driving circuit and a multi-row pixel circuit; The gate driving circuit is used to receive a first scan start signal and a first clock signal to generate a first gate scan signal; the multi-row pixel circuit is used to receive a first voltage signal and the first gate scan signal to control the display panel to display a first image in a first mode; in an image frame, the base frequency of the first scan start signal and the first clock signal is a first frequency, and the width of the multiple pulses included in the first gate scan signal is a first fixed value. The gate driving circuit is used to receive a second scan start signal and a second clock signal, and generate a first sub-gate scan signal, a second sub-gate scan signal, and a third sub-gate scan signal; the pixel circuit in the first row is used to receive a first compensation voltage signal and the first sub-gate scan signal, the pixel circuit in the Mth row is used to receive a second compensation voltage signal and the second sub-gate scan signal, and the pixel circuit in the last row is used to receive a third compensation voltage signal and the third sub-gate scan signal, so as to control the display panel to display a second image; the pixel circuit in the Mth row is any row of pixel circuits located between the pixel circuits in the first row and the pixel circuits in the last row; in an image frame, the base frequency of the second scan start signal and the second clock signal is a second frequency; the width of the multiple pulses included in the first sub-gate scan signal is a first fixed value, the width of the multiple pulses included in the third sub-gate scan signal is a second fixed value, and the width of the multiple pulses included in the second sub-gate scan signal is not equal and is within the range of the first fixed value to the second fixed value; The gate driving circuit is further configured to generate a second gate scan signal based on the second scan start signal and the second clock signal; the multi-row pixel circuit is configured to receive the second voltage signal and the second gate scan signal, and control the display panel to display a third image in the second mode; in an image frame, the base frequency of the second scan start signal and the second clock signal is the second frequency; the width of the multiple pulses included in the second gate scan signal is the second fixed value.

2. The display panel according to claim 1, characterized in that, The compensation coefficients of the first compensation voltage signal, the second compensation voltage signal, and the third compensation voltage signal are different.

3. The display panel according to claim 1 or 2, characterized in that, The second screen and the third screen are the same; or, The second screen and the third screen are different.

4. The display panel according to any one of claims 1-3, characterized in that, The first voltage signal includes a first data voltage signal, the second voltage signal includes a second data voltage signal, the first compensation voltage signal includes a first compensation data voltage signal, the second compensation voltage signal includes a second compensation data voltage signal, and the third compensation voltage signal includes a third compensation data voltage signal.

5. The display panel according to any one of claims 1-4, characterized in that, The first voltage signal includes a first initialization voltage signal, the second voltage signal includes a second initialization voltage signal, the first compensation voltage signal includes a first compensation initialization voltage signal, the second compensation voltage signal includes a second compensation initialization voltage signal, and the third compensation voltage signal includes a third compensation initialization voltage signal.

6. The display panel according to any one of claims 1-5, characterized in that, The first frequency is greater than the second frequency; The base frequency of the display panel changes from the first frequency to the second frequency, and the width of the multiple pulses included in the second sub-gate scanning signal increases. The base frequency of the display panel changes from the second frequency to the first frequency, and the width of the multiple pulses included in the second sub-gate scan signal decreases.

7. The display panel according to any one of claims 1-6, characterized in that, In the second mode, during the first N image frames, the multi-row pixel circuit receives the fourth compensation voltage signal and the second gate scan signal to control the display panel to display the fourth image; starting from the (N+1)th image frame, the multi-row pixel circuit receives the second voltage signal and the second gate scan signal to control the display panel to display the third image; N is a positive integer.

8. The display panel according to any one of claims 1-7, characterized in that, The pixel circuit in the Mth row includes a plurality of pixel circuits, and the second compensation voltage signal includes a plurality of sub-compensation voltage signals. The plurality of pixel circuits are used to receive the plurality of sub-compensation voltage signals, and the compensation coefficients of the plurality of sub-compensation voltage signals are the same.

9. A display module, characterized in that, The display module includes a display driver integrated circuit and a display panel; the display driver integrated circuit is coupled to the display panel, and the display panel includes the display panel according to any one of claims 1-8.

10. The display module according to claim 9, characterized in that, The display driver integrated circuit is used to output the first clock signal, the first scan start signal and the first voltage signal required for displaying the first image to the display panel; The display driver integrated circuit is also used to output the second clock signal, the second scan start signal, the first compensation voltage signal, the second compensation voltage signal and the third compensation voltage signal required for displaying the second image to the display panel; The display driver integrated circuit is also used to output the second clock signal, the second scan start signal, and the second voltage signal required for displaying the third image to the display panel.

11. An electronic device, characterized in that, The electronic device includes a drive controller and a display module, wherein the drive controller is coupled to the display module, and the display module includes the display module as described in claim 9.

12. The electronic device according to claim 11, characterized in that, The drive controller is used to send a first base frequency command to the display module, and control the display module to output the first clock signal and the first scan start signal; The drive controller is also used to send a second base frequency command to the display module, and control the display module to output the second clock signal and the second scan start signal.

13. A driving method for an electronic device, characterized in that, The electronic device includes a drive controller, a display driver integrated circuit, and a display panel, wherein the display panel includes a gate drive circuit and a multi-row pixel circuit. The driving method includes: The drive controller sends a first base frequency command, and the display driver integrated circuit outputs a first scan start signal, a first clock signal, and a first voltage signal according to the first base frequency command; the gate drive circuit receives the first scan start signal and the first clock signal to generate a first gate scan signal, and the multi-row pixel circuit receives the first gate scan signal and the first voltage signal to control the display panel to display a first image in a first mode; in an image frame, the base frequency of the first scan start signal and the first clock signal is a first frequency, and the width of the multiple pulses included in the first gate scan signal is a first fixed value; The drive controller sends a second base frequency command, and the display driver integrated circuit outputs a second start scan signal, a second clock signal, a first compensation voltage signal, a second compensation voltage signal, and a third compensation voltage signal according to the second base frequency command. The gate drive circuit receives the second start scan signal and the second clock signal and generates a first sub-gate scan signal, a second sub-gate scan signal, and a third sub-gate scan signal. The pixel circuit in the first row receives the first compensation voltage signal and the first sub-gate scan signal, the pixel circuit in the Mth row receives the second compensation voltage signal and the second sub-gate scan signal, and the pixel circuit in the last row receives the third compensation voltage signal and the third sub-gate scan signal, controlling the display panel to display a second image. The pixel circuit in the Mth row is any row of pixel circuits located between the pixel circuits in the first row and the pixel circuits in the last row. In an image frame, the base frequency of the second scan start signal and the second clock signal is a second frequency. The width of the multiple pulses included in the first sub-gate scan signal is a first fixed value, the width of the multiple pulses included in the third sub-gate scan signal is a second fixed value, and the widths of the multiple pulses included in the second sub-gate scan signal are not equal and are within the range of the first fixed value to the second fixed value. The display driver integrated circuit also outputs a second start scan signal, a second clock signal, and a second voltage signal according to the second base frequency command. The gate drive circuit receives the second scan start signal and the second clock signal to generate a second gate scan signal. The multi-row pixel circuit receives the second voltage signal and the second gate scan signal to control the display panel to display a third image in the second mode. In an image frame, the base frequency of the second scan start signal and the second clock signal is the second frequency. The width of the multiple pulses included in the second gate scan signal is the second fixed value.

14. The driving method according to claim 13, characterized in that, The second screen and the third screen are the same; or, the second screen and the third screen are different.

15. The driving method according to claim 13 or 14, characterized in that, In the second mode, in the first N image frames, the display driver integrated circuit outputs the second start scan signal, the second clock signal, and the fourth compensation voltage signal according to the second base frequency instruction. The gate drive circuit receives the second scan start signal and the second clock signal to generate a second gate scan signal. The multi-row pixel circuit receives the fourth compensation voltage signal and the second gate scan signal to control the display panel to display the fourth image. Starting from the (N+1)th image frame, the multi-row pixel circuit receives the second voltage signal and the second gate scan signal to control the display panel to display the third image. N is a positive integer.

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