Display device and method for manufacturing the same

Abstract

A display device and a method for manufacturing the same. The display device includes a substrate and at least one pixel circuit formed on the substrate. The pixel circuit includes a driving transistor, a first transistor, and a second transistor; the substrate includes a doped semiconductor body and a first conductive layer and a second conductive layer located on the semiconductor body; the first transistor includes a first doping region in contact with a first electrode of the first transistor, a second doping region in contact with a second electrode of the first transistor, the first doping region of the first transistor and the second doping region of the first transistor are spaced apart from each other, have the same doping type, and are both located in the semiconductor body; the first transistor also includes a drift doping region in contact with the first doping region, the drift doping region of the first transistor and the second doping region of the first transistor are spaced apart from each other, have the same doping type, and are both located in the semiconductor body. The display device can reduce or avoid the risk of being broken down by high voltage.

Description

[0001] This invention is a divisional application based on a patent application with an application date of August 23, 2019, application number 201980001449.0, and invention name “Display device and preparation method thereof”. Technical Field

[0002] Embodiments of the present disclosure relate to a display device and a method for manufacturing the same. Background Art

[0003] Micro-OLED (Micro Organic Light-Emitting Diode) display is a new type of OLED display with silicon substrate as substrate, also known as silicon-based organic light-emitting diode (silicon-based OLED) display. Silicon-based OLED display has the advantages of small size and high resolution. It is manufactured using mature CMOS integrated circuit technology, can realize active addressing of pixels, and can manufacture various functional circuits including TCON (timing control) circuit, OCP (operation control) circuit, etc. on silicon-based substrate, which can achieve lightweight. Summary of the invention

[0004] At least one embodiment of the present disclosure provides a display device, comprising a substrate and at least one pixel circuit formed on the substrate, wherein the pixel circuit comprises a driving transistor, a first transistor and a second transistor; the driving transistor comprises a control electrode, a first electrode and a second electrode, and is configured to control a driving current for driving a light-emitting element to emit light flowing through the first electrode and the second electrode of the driving transistor according to a voltage of the control electrode of the driving transistor; the first electrode of the first transistor is connected to the control electrode of the driving transistor, and is configured to write a data signal to the control electrode of the driving transistor in response to a first scanning signal; the first electrode of the second transistor is connected to the control electrode of the driving transistor, and is configured to write the data signal to the control electrode of the driving transistor in response to a second scanning signal; the substrate comprises a doped semiconductor body and a first conductive layer and a second conductive layer located on the semiconductor body; The first transistor includes a first doping region in contact with a first electrode of the first transistor, and a second doping region in contact with a second electrode of the first transistor, the first doping region of the first transistor and the second doping region of the first transistor are spaced apart from each other, have the same doping type, and are both located in the semiconductor body; the first transistor also includes a drift doping region in contact with the first doping region, the drift doping region of the first transistor and the second doping region of the first transistor are spaced apart from each other, have the same doping type, and are both located in the semiconductor body; the orthographic projection of the gate of the first transistor on the substrate partially overlaps with the orthographic projection of the drift doping region of the first transistor on the substrate, and the orthographic projection of the first doping region of the first transistor on the substrate is located in the orthographic projection of the drift doping region of the first transistor on the substrate; the doping concentration of the drift doping region of the first transistor is lower than the doping concentration of the first doping region of the first transistor.

[0005] For example, in a display device provided in an embodiment of the present disclosure, the substrate also includes a first insulating layer located between the semiconductor body and the first conductive layer; the first insulating layer includes a first portion of a first doped region close to the first transistor and a second portion of a second doped region away from the first transistor.

[0006] For example, in a display device provided in an embodiment of the present disclosure, the thickness of the first portion of the first insulating layer is greater than the thickness of the second portion of the first insulating layer, and the thickness is the thickness in a direction perpendicular to the base substrate.

[0007] At least one embodiment of the present disclosure provides a display device, comprising a substrate and at least one pixel circuit formed on the substrate, wherein the pixel circuit comprises a driving transistor, a first transistor and a second transistor; the driving transistor comprises a control electrode, a first electrode and a second electrode, and is configured to control a driving current for driving a light-emitting element to emit light flowing through the first electrode and the second electrode of the driving transistor according to a voltage of the control electrode of the driving transistor; the first electrode of the first transistor is connected to the control electrode of the driving transistor, and is configured to write a data signal to the control electrode of the driving transistor in response to a first scanning signal; the first electrode of the second transistor is connected to the control electrode of the driving transistor, and is configured to write the data signal to the control electrode of the driving transistor in response to a second scanning signal; wherein the substrate substrate The board includes a doped semiconductor body and a first conductive layer and a second conductive layer formed on the surface of the semiconductor body; the first transistor includes a first doped region in contact with the first electrode of the first transistor and a second doped region in contact with the second electrode of the first transistor, the first doped region of the first transistor and the second doped region of the first transistor are spaced apart from each other, have the same doping type and are both located in the semiconductor body; the substrate also includes a first insulating layer formed between the semiconductor body and the first conductive layer, the first insulating layer includes a first part close to the first doped region of the first transistor and a second part away from the second doped region of the first transistor; the thickness of the first part of the first insulating layer is greater than the thickness of the second part of the first insulating layer, and the thickness is the thickness in a direction perpendicular to the substrate.

[0008] For example, in a display device provided in an embodiment of the present disclosure, the first transistor also includes a drift doping region in contact with the first doping region of the first transistor, the drift doping region of the first transistor and the second doping region of the first transistor are spaced apart from each other, have the same doping type and are both located in the semiconductor body; the orthographic projection of the gate of the first transistor on the substrate partially overlaps with the orthographic projection of the drift doping region of the first transistor on the substrate, and the orthographic projection of the first doping region of the first transistor on the substrate is located in the orthographic projection of the drift doping region of the first transistor on the substrate; the doping concentration of the drift doping region of the first transistor is lower than the doping concentration of the first doping region of the first transistor.

[0009] For example, in a display device provided in an embodiment of the present disclosure, the first transistor is a P-type MOS transistor, and the doping type of the first doped region in the first transistor is P-type; the semiconductor body is bulk silicon or silicon on an insulating layer with a doping type of P-type.

[0010] For example, in a display device provided by an embodiment of the present disclosure, the first doping region, the second doping region and the drift doping region of the first transistor are located in a first well in the semiconductor body, and the doping type of the first well is N-type; the orthographic projection of the gate of the first transistor on the substrate is located in the orthographic projection of the first well on the substrate, and the part of the first well located between the first doping region of the first transistor and the second doping region of the first transistor constitutes a channel region of the first transistor.

[0011] For example, in a display device provided in an embodiment of the present disclosure, the first transistor also includes an auxiliary doping region, the doping type of the auxiliary doping region of the first transistor is N-type, the auxiliary doping region of the first transistor is in contact with the second doping region of the first transistor, the auxiliary doping region of the first transistor is electrically connected to the second electrode of the first transistor, and the orthographic projection of the auxiliary doping region of the first transistor on the substrate is located in the orthographic projection of the first well on the substrate.

[0012] For example, in a display device provided in an embodiment of the present disclosure, the first transistor is an N-type MOS transistor, and the doping type of the first doping region in the first transistor is N-type; the semiconductor body is bulk silicon or silicon on an insulating layer with a doping type of P-type.

[0013] For example, in a display device provided in an embodiment of the present disclosure, the first transistor also includes an auxiliary doping region, the doping type of the auxiliary doping region of the first transistor is P-type, the auxiliary doping region of the first transistor is in contact with the second doping region of the first transistor, and the auxiliary doping region is electrically connected to the second electrode of the first transistor.

[0014] For example, in a display device provided in an embodiment of the present disclosure, the base substrate further includes a planarization insulating layer, the planarization insulating layer covers the gate of the first transistor, and the light emitting element is located on the planarization insulating layer.

[0015] For example, in a display device provided in an embodiment of the present disclosure, the second transistor includes a first doped region in contact with a first pole of the second transistor, and a second doped region in contact with a second pole of the second transistor. The first doped region of the second transistor and the second doped region of the second transistor are spaced apart from each other, have the same doping type, and are both located in the semiconductor body.

[0016] For example, in a display device provided in an embodiment of the present disclosure, the second transistor also includes an auxiliary doping region, the auxiliary doping region of the second transistor is in contact with the second doping region of the second transistor, the auxiliary doping region of the second transistor is electrically connected to the second electrode of the second transistor, and the doping type of the auxiliary doping region of the second transistor is opposite to the doping type of the second doping region of the second transistor.

[0017] For example, in a display device provided by an embodiment of the present disclosure, the doping type of the first doping region of the first transistor is opposite to the doping type of the first doping region of the second transistor.

[0018] For example, in a display device provided in an embodiment of the present disclosure, the first transistor is a P-type MOS transistor, and the doping type of the first doping region of the first transistor is P-type; the second transistor is an N-type MOS transistor, and the doping type of the first doping region of the second transistor is N-type; the semiconductor body is bulk silicon or silicon on an insulating layer with a doping type of P-type; the second transistor includes a first doping region contacting a first pole of the second transistor, and a second doping region contacting a second pole of the second transistor; the first doping region of the second transistor and the second doping region of the second transistor are spaced apart from each other, have the same doping type, and are both located in the semiconductor body.

[0019] For example, in a display device provided in an embodiment of the present disclosure, the second transistor also includes a drift doping region in contact with the first doping region of the second transistor, the drift doping region of the second transistor and the second doping region of the second transistor are spaced apart from each other, have the same doping type and are both located in the semiconductor body; the orthographic projection of the gate of the second transistor on the substrate partially overlaps with the orthographic projection of the drift doping region of the second transistor on the substrate, and the orthographic projection of the first doping region of the second transistor on the substrate is located in the orthographic projection of the drift doping region of the second transistor on the substrate; the doping concentration of the drift doping region of the second transistor is lower than the doping concentration of the first doping region of the second transistor.

[0020] For example, in a display device provided by an embodiment of the present disclosure, the first doping region, the second doping region and the drift doping region of the first transistor are located in a first well in the semiconductor body, the doping type of the first well is N-type, the orthographic projection of the gate of the first transistor on the substrate is located in the orthographic projection of the first well on the substrate, and the portion of the first well located between the first doping region of the first transistor and the second doping region of the first transistor constitutes a channel region of the first transistor.

[0021] For example, in a display device provided in an embodiment of the present disclosure, the first transistor further includes an auxiliary doping region, the doping type of the auxiliary doping region of the first transistor is N-type, the auxiliary doping region of the first transistor is in contact with the second doping region of the first transistor, the auxiliary doping region of the first transistor is electrically connected to the second electrode of the first transistor, and the orthographic projection of the auxiliary doping region of the first transistor on the substrate is located in the orthographic projection of the first well on the substrate; the second transistor further includes an auxiliary doping region, the doping type of the auxiliary doping region of the second transistor is P-type, the auxiliary doping region of the second transistor is in contact with the second doping region of the second transistor, and the auxiliary doping region of the second transistor is electrically connected to the second electrode of the second transistor.

[0022] For example, in a display device provided by an embodiment of the present disclosure, the substrate also includes a first insulating layer and a second insulating layer formed between the semiconductor body and the first conductive layer; the first insulating layer includes a first portion of the first doping region close to the first transistor and a second portion of the first doping region away from the first transistor; the second insulating layer includes a first portion of the first doping region close to the second transistor and a second portion of the first doping region away from the second transistor.

[0023] For example, in a display device provided in an embodiment of the present disclosure, the thickness of the first part of the first insulating layer is greater than the thickness of the second part of the first insulating layer, and the thickness of the first part of the second insulating layer is greater than the thickness of the second part of the second insulating layer, and the thickness is the thickness in a direction perpendicular to the base substrate.

[0024] For example, in a display device provided in an embodiment of the present disclosure, the pixel circuit also includes a third transistor, which is connected to the first electrode of the driving transistor and is configured to apply a first power supply voltage to the first electrode of the driving transistor in response to a light emitting control signal.

[0025] For example, in a display device provided in an embodiment of the present disclosure, the substrate is a P-type silicon substrate, the first transistor is a P-type MOS transistor, and the second transistor, the third transistor and the driving transistor are all N-type MOS transistors.

[0026] For example, a display device provided by an embodiment of the present disclosure further includes a driving circuit located in the base substrate, and the driving circuit is configured to provide the first scanning signal, the second scanning signal and the light emitting control signal to at least one pixel circuit in the display device.

[0027] At least one embodiment of the present disclosure also provides a method for preparing a display device, comprising: forming a pixel circuit on a substrate; the pixel circuit comprises a driving transistor, a first transistor and a second transistor; the driving transistor comprises a control electrode, a first electrode and a second electrode, and is configured to control a driving current for driving a light-emitting element to emit light flowing through the first electrode of the driving transistor and the second electrode of the driving transistor according to a voltage of the control electrode of the driving transistor; the first electrode of the first transistor is connected to the control electrode of the driving transistor, and is configured to write a data signal to the control electrode of the driving transistor in response to a first scan signal; the first electrode of the second transistor is connected to the control electrode of the driving transistor, and is configured to write the data signal to the control electrode of the driving transistor in response to a second scan signal; the substrate comprises a doped semiconductor body; the preparation method further comprises: forming a first conductive layer and a second conductive layer of the substrate on the semiconductor body, wherein the first transistor comprises a gate electrode located in the first conductive layer and a gate electrode located in the second conductive layer a first pole and a second pole in a layer; forming a first doping region of a first transistor in contact with the first pole of the first transistor and a second doping region of the first transistor in contact with the second pole of the first transistor in the semiconductor body, the first doping region of the first transistor and the second doping region of the first transistor being spaced apart from each other, having the same doping type and both being located in the semiconductor body; and forming a drift doping region of the first transistor having the same doping type as the second doping region of the first transistor in the semiconductor body, wherein the drift doping region of the first transistor is located in the semiconductor body and spaced apart from the second doping region of the first transistor, the orthographic projection of the gate of the first transistor on the substrate partially overlaps with the orthographic projection of the drift doping region of the first transistor on the substrate, and the orthographic projection of the first doping region of the first transistor on the substrate is located in the orthographic projection of the drift doping region of the first transistor on the substrate, and the doping concentration of the drift doping region of the first transistor is lower than the doping concentration of the first doping region of the first transistor.

[0028] For example, a preparation method provided by an embodiment of the present disclosure also includes: forming a first insulating layer of the substrate between the semiconductor body and the first conductive layer, the first insulating layer including a first portion close to the first doping region of the first transistor and a second portion away from the first doping region of the first transistor; a thickness of the first portion of the first insulating layer is greater than a thickness of the second portion of the first insulating layer, and the thickness is a thickness in a direction perpendicular to the substrate.

[0029] At least one embodiment of the present disclosure also provides a method for preparing a display device, comprising: forming a pixel circuit on a substrate; the pixel circuit comprises a driving transistor, a first transistor and a second transistor; the driving transistor comprises a control electrode, a first electrode and a second electrode, and is configured to control a driving current for driving a light-emitting element to emit light flowing through the first electrode of the driving transistor and the second electrode of the driving transistor according to a voltage of the control electrode of the driving transistor; the first electrode of the first transistor is connected to the control electrode of the driving transistor, and is configured to write a data signal to the control electrode of the driving transistor in response to a first scan signal; the first electrode of the second transistor is connected to the control electrode of the driving transistor, and is configured to write the data signal to the control electrode of the driving transistor in response to a second scan signal; the substrate comprises a doped semiconductor body; the preparation method further comprises: forming the first electrode of the substrate on the semiconductor body A conductive layer and a second conductive layer, wherein the first transistor includes a gate located in the first conductive layer and a first electrode and a second electrode located in the second conductive layer; a first doped region of the first transistor in contact with the first electrode of the first transistor and a second doped region of the first transistor in contact with the second electrode of the first transistor are formed in the semiconductor body, the first doped region of the first transistor and the second doped region of the first transistor are spaced apart from each other, have the same doping type and are both located in the semiconductor body; and a first insulating layer of the substrate is formed between the semiconductor body and the first conductive layer, wherein the first insulating layer includes a first portion close to the first doped region of the first transistor and a second portion away from the first doped region of the first transistor; the thickness of the first portion of the first insulating layer is greater than the thickness of the second portion of the first insulating layer, and the thickness is the thickness in a direction perpendicular to the substrate.

[0030] For example, the preparation method provided by an embodiment of the present disclosure also includes: forming a drift doping region of the first transistor with the same doping type as the second doping region of the first transistor in the semiconductor body, the drift doping region of the first transistor is located in the semiconductor body and is separated from the second doping region of the first transistor, the orthographic projection of the gate of the first transistor on the substrate partially overlaps with the orthographic projection of the drift doping region of the first transistor on the substrate, and the orthographic projection of the first doping region of the first transistor on the substrate is located in the orthographic projection of the drift doping region of the first transistor on the substrate, and the doping concentration of the drift doping region of the first transistor is lower than the doping concentration of the first doping region of the first transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0032] Figure 1 is a cross-sectional schematic diagram of a display substrate;

[0033] Figure 2 A circuit diagram of a display device provided by at least one embodiment of the present disclosure;

[0034] Figure 3 Corresponding to at least one embodiment of the present disclosure Figure 2 Schematic diagram of the layout;

[0035] Figures 4A-4E They are shown respectively Figure 3 A plan view of the five-layer layout of the display device is shown;

[0036] Figure 5 A schematic diagram illustrating an area where a storage capacitor is located, provided for at least one embodiment of the present disclosure;

[0037] Figure 6 A schematic diagram of a layout of a storage capacitor provided for at least one embodiment of the present disclosure;

[0038] Figure 7A-7D They are shown respectively Figure 6 A plan view of the four-story distribution shown;

[0039] Fig. 7E A cross-sectional schematic diagram of a storage capacitor provided for at least one embodiment of the present disclosure;

[0040] Figure 8 A cross-sectional schematic diagram of a first transistor and a second transistor provided for at least one embodiment of the present disclosure;

[0041] Fig. 9 Another cross-sectional schematic diagram of a first transistor and a second transistor provided for at least one embodiment of the present disclosure;

[0042] Fig.10 A cross-sectional schematic diagram of a first transistor and a second transistor provided for at least one embodiment of the present disclosure; and

[0043] Fig.11 A schematic diagram of a display device provided by at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0045] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0046] At present, silicon-based OLED display panels are widely used in near-eye display fields such as virtual reality (VR) or augmented reality (AR). As users have higher and higher requirements for display quality, for example, higher resolution and PPI (Pixels Per Inch) need to be achieved. In order to achieve a higher PPI, the layout of the display device needs to be designed to reduce the occupied layout area, so that more pixel units can be set in a display area of ​​the same size, thereby achieving a high PPI.

[0047] At least one embodiment of the present disclosure provides a display device and a method for manufacturing the same, which can reduce the layout area occupied by the display device through layout design, thereby making it easier for the display device to achieve a high PPI. In addition, at least one embodiment of the present disclosure also provides a transistor structural design that can reduce or avoid the risk of breakdown by high voltage.

[0048] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0049] Figure 1 FIG. 1 is a schematic diagram of the structure of a display substrate 1000. Figure 1 As shown, the display substrate 1000 includes a base substrate 600 and a light emitting element 620. For example, the light emitting element 620 is disposed on the base substrate 600, and a first electrode 621 of the light emitting element 620 is closer to the base substrate 600 than a second electrode 629 of the light emitting element 620.

[0050] For example, in some examples, the substrate 600 is a silicon-based substrate, and the embodiments of the present disclosure include but are not limited to this. For example, the semiconductor manufacturing process used by the silicon-based substrate is mature and has stable performance, which is conducive to the manufacture of micro display devices.

[0051] For example, in some examples, the silicon-based substrate 600 includes a driving circuit, which is electrically connected to the light-emitting element 620 to drive the light-emitting element 620 to emit light. Figure 1 As shown, the driving circuit includes a transistor T. It should be noted that the specific circuit structure of the driving circuit can be set according to actual needs. For example, Figure 1 The entire structure of the driving circuit is not shown in the figure, and the driving circuit may also include, for example, other transistors, and storage capacitors, etc., which are not limited in the embodiments of the present disclosure.

[0052] For example, Figure 1 As shown, transistor T includes a gate electrode G, a source electrode S and a drain electrode D. The three electrodes correspond to three electrode connection parts respectively. For example, the gate electrode G is electrically connected to the gate electrode connection part 610g, the source electrode S is electrically connected to the source electrode connection part 610s, and the drain electrode D is electrically connected to the drain electrode connection part 610d. For example, the three electrodes are electrically connected to the three electrode connection parts through the tungsten via 605.

[0053] For example, Figure 1As shown, the source electrode connection portion 610s is electrically connected to the first electrode 621 of the light-emitting element 620 through a tungsten via. For example, the source electrode connection portion 610s is electrically connected to the metal reflective layer 622 of the first electrode 621 through a tungsten via, and at the same time, in the first electrode 621, the transparent conductive layer 626 is electrically connected to the metal reflective layer 622 through a via 624a in the inorganic insulating layer 624. When the transistor T is in the on state, the electrical signal provided by the power line can be transmitted to the transparent conductive layer 626 through the source electrode S of the transistor T, the source electrode connection portion 610s, and the metal reflective layer 622. Due to the voltage difference formed between the transparent conductive layer 626 and the second electrode 629, an electric field is formed between the two, and holes and electrons are injected into the light-emitting functional layer 627, and the light-emitting functional layer 627 emits light under the action of the electric field. It can be understood that in the transistor T, the positions of the source electrode S and the drain electrode D are interchangeable (correspondingly, the positions of the source electrode connecting portion 610s and the drain electrode connecting portion 610d are also interchangeable), that is, one of the source electrode S and the drain electrode D of the transistor (i.e., the source electrode S or the drain electrode D) and the light-emitting element 620 can be electrically connected to each other.

[0054] For example, the materials of the gate electrode connection portion 610g, the source electrode connection portion 610s, and the drain electrode connection portion 610d may include a metal material. Figure 1 As shown, an anti-oxidation layer 607 can be provided on at least one side (eg, the upper side and / or the lower side) of each of the gate electrode connection 610g, the source electrode connection 610s, and the drain electrode connection 610d, so as to effectively prevent these electrode connections from being oxidized and improve their conductive properties.

[0055] For example, Figure 1 As shown, the display substrate 1000 further includes a defining layer 728 for defining the light-emitting functional layer 727 . The defining layer 728 defines the organic light-emitting functional layer 727 in its opening 728 a to avoid crosstalk between adjacent sub-pixels.

[0056] It should be noted that in Figure 1 In the display substrate 1000 shown, the via hole 624a in the inorganic insulating layer 624 may be disposed between the transparent conductive layer 626 and the edge region of the metal reflective layer 622. For example, in some examples, the orthographic projection of the light-emitting functional layer 627 on the base substrate 600 and the orthographic projection of the via hole 624a on the base substrate 600 are both located within the orthographic projection of the metal reflective layer 622 on the base substrate 600, and at the same time, there is no overlap between the orthographic projection of the light-emitting functional layer 627 on the base substrate 600 and the orthographic projection of the via hole 624a on the base substrate 600, so that when the metal reflective layer reflects the light emitted by the light-emitting functional layer 627, the via hole 624a has substantially no effect on the reflection process.

[0057] At least one embodiment of the present disclosure provides a display device 100, which includes a substrate substrate, at least one pixel circuit formed on the substrate substrate, and a light-emitting element driven by the pixel circuit. The substrate substrate is, for example, a silicon-based substrate substrate, which may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The pixel circuit may be prepared in the substrate substrate by a silicon semiconductor process (e.g., a CMOS process), and the light-emitting element is prepared on the silicon substrate having the pixel circuit.

[0058] Combine the following Figure 2 and Figure 3 Introducing the display device 100, it should be noted that: Figure 2 and Figure 3 The substrate is not shown in the figure. For more information about the substrate, please refer to Figure 1 The substrate substrate 600 is shown in FIG.

[0059] like Figure 2 As shown, the pixel circuit includes a driving transistor 140, a first transistor 110, a second transistor 120 and a third transistor 130. It should be noted that in some embodiments, the pixel circuit may not include the third transistor 130, and the embodiments of the present disclosure are not limited to this.

[0060] For example, the driving transistor 140 includes a control electrode 143, a first electrode 141, and a second electrode 142, and the driving transistor 140 is configured to control a driving current for driving the light-emitting element LE to emit light, flowing through the first electrode 141 of the driving transistor 140 and the second electrode 142 of the driving transistor 140, according to a voltage of the control electrode 143 of the driving transistor 140. The light-emitting element LE can emit light of different intensities according to the magnitude of the driving current.

[0061] It should be noted that the source and drain of the transistor used in the embodiments of the present disclosure may be symmetrical in structure, so the source and drain may be indistinguishable in structure. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, one pole is directly described as the first pole and the other pole is the second pole, so the first pole and the second pole of all or part of the transistors in the embodiments of the present disclosure can be interchangeable as needed. For example, the first pole of the transistor described in the embodiments of the present disclosure may be the source, and the second pole may be the drain; or, the first pole of the transistor may be the drain, and the second pole may be the source. The following embodiments are described by taking the first pole of the transistor as the drain and the second pole as the source as an example, and no further description is given.

[0062] For example, the first transistor 110 is connected to the control electrode 143 of the driving transistor 140 , and is configured to write the data signal DATA into the control electrode 143 of the driving transistor 140 in response to the first scan signal SCAN1 .

[0063] For example, the second transistor 120 is connected to the control electrode 143 of the driving transistor 140 , and is configured to write the data signal DATA into the control electrode 143 of the driving transistor 140 in response to the second scan signal SCAN2 .

[0064] For example, the third transistor 130 is connected to the first electrode 141 of the driving transistor 140, and is configured to apply the first power supply voltage ELVDD to the first electrode 141 of the driving transistor 140 in response to the light emission control signal EN. For example, the first power supply voltage ELVDD in the embodiment of the present disclosure is a high level voltage, for example, the first power supply voltage ELVDD is 5V.

[0065] like Figure 2 As shown, in some embodiments, the first electrode 111 (e.g., drain) of the first transistor 110 and the first electrode 121 (e.g., drain) of the second transistor 120 are connected to obtain a common electrode, and are connected to the control electrode 143 of the driving transistor 140 through the common electrode.

[0066] In the above embodiment, a first scan signal line SL1, a second scan signal line SL2, a data line DL, a first power supply voltage line VL1, and a light emitting control line EL are also provided to provide corresponding electrical signals. The control electrode 113 of the first transistor 110 is configured to receive a first scan signal SCAN1 from the first scan signal line SL1, and the second electrode 112 (e.g., source) of the first transistor 110 is configured to receive a data signal DATA from the data line DL. The control electrode 123 of the second transistor 120 is configured to receive a second scan signal SCAN2 from the second scan signal line SL2, and the second electrode 122 (e.g., source) of the second transistor 120 is configured to receive a data signal DATA from the data line DL. The control electrode 133 of the third transistor 130 is configured to receive a light emitting control signal EN from the light emitting control line EL, the first electrode 131 (e.g., the drain) of the third transistor 130 is configured to receive a first power supply voltage ELVDD from the first power supply voltage line VL1, and the second electrode 132 (e.g., the source) of the third transistor 130 is connected to the first electrode 141 (e.g., the drain) of the driving transistor 140.

[0067] The second electrode 142 (e.g., source electrode) of the driving transistor 140 is configured to be connected to the first electrode of the light emitting element LE. For example, when the light emitting element LE is an OLED, the second electrode 142 of the driving transistor 140 can be connected to the anode of the OLED. For example, the second electrode of the light emitting element LE is configured to receive the fourth power supply voltage VCOM. For example, the fourth power supply voltage VCOM in the embodiment of the present disclosure is a low level voltage.

[0068] For example, in an embodiment of the present disclosure, the light-emitting element LE can be an OLED. When a plurality of pixel units constitute a pixel array in a display panel, the second electrodes (e.g., cathodes) of a plurality of light-emitting elements OLED in the plurality of pixel units can be electrically connected together, for example, respectively connected to the same electrode or formed as one, to receive a fourth power supply voltage VCOM, that is, the plurality of light-emitting elements OLED in the plurality of pixel units adopt a common cathode connection method.

[0069] For example, the light emitting element OLED may be of various types, such as top emission, bottom emission, etc., and may emit red light, green light, blue light or white light, etc., and the embodiments of the present disclosure are not limited in this regard.

[0070] For example, Figure 2 As shown, the pixel circuit also includes a storage capacitor CST to store the data signal DATA written to the control electrode 143 of the driving transistor 140, so that the driving transistor 140 can control the magnitude of the driving current of the driving light-emitting element LE according to the voltage of the stored data signal DATA. The first electrode of the storage capacitor CST is connected to the control electrode 143 of the driving transistor 140, and the second electrode of the storage capacitor CST is configured to receive the third power supply voltage AVSS. For example, the third power supply voltage AVSS in the embodiment of the present disclosure is a low-level voltage. It should be noted that in the embodiment of the present disclosure, the third power supply voltage AVSS can be the same as the fourth power supply voltage VCOM. For example, the third power supply voltage AVSS can be grounded together with the fourth power supply voltage VCOM, and the embodiments of the present disclosure include but are not limited to this.

[0071] like Figure 2 As shown, in some embodiments of the present disclosure, the first transistor 110 can be a P-type MOS transistor, and the second transistor 120, the third transistor 130 and the driving transistor 140 can be N-type MOS transistors. For example, the first transistor 110, the second transistor 120, the third transistor 130 and the driving transistor 140 are formed in a substrate.

[0072] For example, Figure 2 As shown, the third stage of the first transistor 110 is configured to receive the second power voltage VDD. For example, the third stage of the first transistor 110 is connected to the second power voltage line VL2 to receive the second power voltage VDD.

[0073] For example, the third electrodes of the second transistor 120, the third transistor 130 and the driving transistor 140 are configured to be grounded (GND). It should be noted that in the embodiment of the present disclosure, the third electrode of a transistor is an electrode opposite to the control electrode (gate) 113 of the transistor, and the following embodiments are the same and will not be repeated.

[0074] In the embodiment of the present disclosure, since the first transistor 110 and the second transistor 120 are MOS transistors with opposite semiconductor types, the first transistor 110 and the second transistor 120 can constitute a transmission gate switch with complementary characteristics. In this case, for example, the first scan signal SCAN1 provided to the first transistor 110 and the second scan signal SCAN2 provided to the second transistor 120 can be mutually inverted signals, so that it can be ensured that at the same time, one of the first transistor 110 and the second transistor 120 is always in a conducting state, so that the data signal DATA can be transmitted to the storage capacitor CST without voltage loss, thereby improving the reliability and stability of the pixel circuit.

[0075] Figure 3 Shows the corresponding Figure 2 The layout diagram of the display device 100 on the substrate is shown in FIG. Figure 3 As shown, in the embodiment of the present disclosure, the direction along the first pole 111 of the first transistor 110 to the second pole 112 of the first transistor 110 is called the first direction D1, the direction along the first pole 121 of the second transistor 120 to the second pole 122 of the second transistor 120 is called the second direction D2, the direction along the first pole 131 of the third transistor 130 to the second pole 132 of the third transistor 130 is called the third direction D3, and the direction along the first pole 141 of the driving transistor 140 to the second pole 142 of the driving transistor 140 is called the fourth direction D4.

[0076] For example, at least one of the first direction D1 and the second direction D2 intersects with the fourth direction D4. For example, in the case where the pixel circuit includes the third transistor 130, at least one of the first direction D1, the second direction D2, and the third direction D3 intersects with the fourth direction D4. For example, the fourth direction D4 is Figure 3 In horizontal direction from left to right.

[0077] In the pixel circuit, since the size of the driving transistor 140 is generally larger than that of other switching transistors (for example, the first transistor 110, the second transistor 120 and the third transistor 130), when laying out the positions of the transistors, the driving transistor 140 can be arranged along the fourth direction D4, and at least one of the first direction D1, the second direction D2 and the third direction D3 intersects with the fourth direction D4. In this way, the layout of the four transistors can be more compact, thereby reducing the layout area occupied by the display device 100, so that the display device 100 can be easier to achieve high PPI.

[0078] In some embodiments of the present disclosure, the first direction D1 and the second direction D2 may intersect with the fourth direction D4; for another example, the first direction D1, the second direction D2 and the third direction D3 may intersect with the fourth direction D4. Figure 3 As shown, the fourth direction D4 is a transverse direction, and the first direction D1, the second direction D2 and the third direction D3 are all Figure 3 The longitudinal direction is perpendicular to the transverse direction.

[0079] For example, in some embodiments of the present disclosure, the first direction D1 and the second direction D2 are both perpendicular to the fourth direction D4; for another example, the first direction D1, the second direction D2, and the third direction D3 are all perpendicular to the fourth direction D4. For the case where a plurality of pixel units in the display area of ​​the display device are arranged in a multi-row and multi-column manner, this method can make the layout of the display device 100 more compact, thereby further reducing the layout area occupied by the display device 100, so that the display device 100 can be more easily achieved with a high PPI.

[0080] For example, Figure 3 As shown, the first transistor 110 includes a first active area 114 extending along a first direction D1, and the first active area 114 includes a first electrode 111 of the first transistor 110, a second electrode 112 of the first transistor 110, and a channel area formed between the first electrode 111 of the first transistor 110 and the second electrode 112 of the first transistor 110.

[0081] The second transistor 120 includes a second active region 124 extending along the second direction D2 , and the second active region 124 includes a first electrode 121 of the second transistor 120 , a second electrode 122 of the second transistor 120 , and a channel region formed between the first electrode 121 and the second electrode 122 of the second transistor 120 .

[0082] The third transistor 130 includes a third active region 134 extending along a third direction D3 , and the third active region 134 includes a first electrode 131 of the third transistor 130 , a second electrode 132 of the third transistor 130 , and a channel region formed between the first electrode 131 of the third transistor 130 and the second electrode 132 of the third transistor 130 .

[0083] The driving transistor 140 includes a fourth active region 144 extending along a fourth direction D4, and the fourth active region 144 includes a first electrode 141 of the fourth transistor 140, a second electrode 142 of the fourth transistor 140, and a channel region formed between the first electrode 141 and the second electrode 142 of the fourth transistor 140.

[0084] For example, the substrate in the display device 100 provided in the embodiment of the present disclosure is a silicon-based substrate, and the above-mentioned first active area 114, second active area 124, third active area 134 and fourth active area 144 are all doped areas in the silicon-based substrate. These doped areas are obtained, for example, by an ion implantation process or an ion diffusion process. For amorphous silicon, P-type doping can be achieved by doping boron (B), and N-type doping can be achieved by doping phosphorus (P) or arsenic (As). The embodiments of the present disclosure are not limited to this.

[0085] For example, in some embodiments of the present disclosure, the doping types of the first active region 114 and the second active region 124 are opposite. For example, the doping type of the first active region 114 is P-type, and the doping type of the second active region 124 is N-type.

[0086] like Figure 3 As shown, the two ends of the first active region 114 and the two ends of the second active region 124 are aligned with each other in the fourth direction D4, and for example, the two ends of the first active region 114 and the second active region 124 are arranged adjacent to each other. In this way, the layout design of the display device 100 can be simplified.

[0087] A line connecting one edge of the first active region 114 along the first direction D1 and one edge of the second active region 124 along the second direction D2 is parallel to the fourth direction D4; a line connecting another edge of the first active region 114 along the first direction D1 and another edge of the second active region 124 along the second direction D2 is parallel to the fourth direction D4. This method can simplify the layout design of the display device 100.

[0088] Compared with silicon-based analog CMOS circuits for non-display purposes, the driving current for the light-emitting element LE in the display device 100 provided by the embodiment of the present disclosure is 1 to 2 orders of magnitude smaller. The current characteristic of the driving transistor 140 in the saturation state is:

[0089]

[0090] Among them, I D is the driving current provided by the driving transistor 140, W / L is the width-to-length ratio of the driving transistor 140, K is a constant value, V GS4 is the voltage difference between the gate and source of the driving transistor 140, V th is the threshold voltage of the driving transistor 140 .

[0091] It can be seen from the above formula that in order to achieve a lower driving current, the L value of the driving transistor 140 must be increased during size design, which is not conducive to reducing the layout area of ​​the display device 100 using the driving transistor 140 .

[0092] The pixel circuit 100 provided in some embodiments of the present disclosure can improve or avoid the above problems by adjusting the relative relationship between the doping concentrations of the first active area 114 , the second active area 124 , the third active area 134 , and the fourth active area 144 .

[0093] For example, the doping concentration of the fourth active region 144 is less than the doping concentration of the third active region 134. For example, the doping concentration of the third active region 134 is about 10 17 cm -3 , the doping concentration of the fourth active region 144 is about 10 13 cm -3 , the doping concentration of the fourth active region 144 is 4 orders of magnitude lower than the doping concentration of the third active region 134. In the embodiment of the present disclosure, by reducing the doping concentration of the fourth active region 144, the driving transistor 140 can output a smaller driving current without changing the size of the driving transistor 140 (for example, the width-to-length ratio W / L remains unchanged), and the output driving current changes more slowly, so that the grayscale value when the pixel circuit using the driving transistor 140 drives the light-emitting element LE (for example, OLED) to emit light can obtain better uniformity.

[0094] For example, in the display device 100 provided in some embodiments of the present disclosure, the doping concentration of at least one of the first active region 114 and the second active region 124 is greater than the doping concentration of the third active region 134 .

[0095] For example, the doping concentrations of the first active region 114 and the second active region 124 are both greater than the doping concentration of the third active region. 20 cm -3 In this case, the doping concentrations of the first active region 114 and the second active region 124 are three orders of magnitude greater than the doping concentration of the third active region 134 .

[0096] like Figure 2 As shown, the first transistor 110 and the second transistor 120 are used as switching transistors in the pixel circuit, so they need to have good switching characteristics. When the doping concentration of the first active area 114 or / and the second active area 124 is large, a large driving current can be obtained and the driving current changes more quickly, so that the first transistor 110 or / and the second transistor 120 have better switching characteristics.

[0097] For example, in an embodiment of the present disclosure, the first transistor 110 is a first semiconductor type MOS transistor, the second transistor, the third transistor and the driving transistor are all second semiconductor type MOS transistors, and the first semiconductor type and the second semiconductor type are opposite. For example, the first semiconductor type is P type, and the second semiconductor type is N type, and the embodiments of the present disclosure include but are not limited to this.

[0098] like Figure 3 As shown, the display device 100 provided in some embodiments of the present disclosure further includes a first scan signal line SL1 for transmitting a first scan signal SCAN1 and a second scan signal line SL2 for transmitting a second scan signal SCAN2, and the first scan signal line SL1 is arranged in parallel with the second scan signal line SL2.

[0099] For example, the first scan signal line SL1 is connected to the control electrode 113 of the first transistor 110 to provide the first scan signal SCAN1 , and the second scan signal line SL2 is connected to the control electrode 123 of the second transistor 120 to provide the second scan signal SCAN2 .

[0100] For example, the extension directions of the first scan signal line SL1 and the second scan signal line SL2 are parallel to the fourth direction D4. The orthographic projection of the first scan signal line SL1 on the substrate is parallel to the orthographic projection of the second scan signal line SL2 on the substrate, for example, both are parallel to the fourth direction D4.

[0101] For example, the area where the orthographic projection of the pixel circuit on the base substrate is located is the pixel area, and the first scanning signal line SL1 and the second scanning signal line SL2 are located side by side on one side of the pixel area.

[0102] like Figure 3 As shown, the display device 100 provided by some embodiments of the present disclosure further includes a data line DL for transmitting a data signal DATA, and the orthographic projection of the second scanning signal line SL2 on the substrate at least partially overlaps with the orthographic projection of the data line DL on the substrate. For example, the second scanning signal line SL2 overlaps with the data line DL in a direction perpendicular to the substrate. For example, Figure 3 As shown, you can Figure 3 The plane where the substrate is located is regarded as the plane where the substrate is located, and the plane perpendicular to the substrate is perpendicular to the substrate. Figure 3 In the embodiment of the present disclosure, by making the second scan signal line SL2 overlap with the data line DT in a direction perpendicular to the base substrate, the data line DL does not occupy an additional layout area, thereby further reducing the layout area occupied by the display device 100, which is more conducive to achieving a high PPI.

[0103] like Figure 3As shown, the display device 100 provided by some embodiments of the present disclosure further includes a first power voltage line VL1 for transmitting a first power voltage ELVDD and a light emitting control line EL for transmitting a light emitting control signal EN.

[0104] For example, part of the extension direction of the first power supply voltage line VL1 and the light-emitting control line EL is parallel to the fourth direction D4, and the orthographic projection of the first scanning signal line SL1, the second scanning signal line SL2, the first power supply voltage line VL1 and the light-emitting control line EL on the substrate is arranged in sequence along a direction perpendicular to the fourth direction D4.

[0105] It should be noted that in the display device 100 provided in some embodiments of the present disclosure, Figure 3 As shown, the orthographic projection of the first power supply voltage line VL1 on the substrate is located between the orthographic projection of the second scanning signal line SL2 on the substrate and the orthographic projection of the light-emitting control line EL on the substrate. Since the first power supply voltage ELVDD transmitted by the first power supply voltage line VL1 is a DC signal, and the second scanning signal SCAN2 transmitted by the second scanning signal line SL2 and the light-emitting control signal EN transmitted by the light-emitting control line EL are both jump signals, the above arrangement can effectively shield the mutual interference between the second scanning signal SCAN2 and the light-emitting control signal EN.

[0106] like Figure 3 As shown, the display device 100 provided in some embodiments of the present disclosure further includes a second power supply voltage line VL2 for transmitting a second power supply voltage VDD, and the third electrode of the first transistor 110 is electrically connected to the second power supply voltage line VL2 to receive the second power supply voltage VDD. For example, the second power supply voltage VDD in the embodiment of the present disclosure is a high level voltage, for example, the second power supply voltage is 5V.

[0107] For example, the first transistor 110 is a P-type MOS transistor, and its channel region is P-type doped. Figure 2 As shown, the third electrode opposite to the control electrode (gate) 113 of the first transistor 110 receives the second power supply voltage VDD. For example, the second transistor 120, the third transistor 130 and the driving transistor 140 are all N-type MOS transistors, whose channel regions are N-type doped, and the third electrodes of the second transistor 120, the third transistor 130 and the driving transistor 140 are all configured to be grounded (GND).

[0108] For example, the orthographic projection of the second power voltage line VL2 on the substrate is located between the orthographic projection of the first power voltage line VL1 on the substrate and the orthographic projection of the light emitting control line EL on the substrate, and a portion of the extension direction of the second power voltage line VL2 is parallel to the fourth direction D4.

[0109] like Figure 3As shown, the second power supply voltage line VL2 has a bending area when extending along the fourth direction D4; in addition, the light emitting control line EL also has a bending area when extending along the fourth direction D4, and the bending directions of the second power supply voltage line VL2 and the light emitting control line EL are different. This routing method can, for example, leave layout space for the first transfer electrode AE1 described below.

[0110] For example, Figure 3 As shown, the first transistor 110 and the second transistor 120 are both arranged between the second scanning signal line SL2 and the light emitting control line EL, and the first transistor 110 intersects with the first power supply voltage line VL1 and the second power supply voltage line VL2, and the second transistor 120 intersects with the first power supply voltage line VL1 and the second power supply voltage line VL2.

[0111] For example, the orthographic projection of the first active area 114 of the first transistor 110 on the substrate and the orthographic projection of the second active area 124 of the second transistor 120 on the substrate are both located between the orthographic projection of the second scanning signal line SL2 on the substrate and the orthographic projection of the light emitting control line EL on the substrate.

[0112] The orthographic projection of the first active area 114 of the first transistor 110 on the substrate intersects with the orthographic projection of the first power voltage line VL1 on the substrate, and the orthographic projection of the first active area 114 of the first transistor 110 on the substrate intersects with the orthographic projection of the second power voltage line VL2 on the substrate.

[0113] The orthographic projection of the second active area 124 of the second transistor 120 on the substrate intersects with the orthographic projection of the first power voltage line VL1 on the substrate, and the orthographic projection of the second active area 124 of the second transistor 120 on the substrate intersects with the orthographic projection of the second power voltage line VL2 on the substrate.

[0114] like Figure 3 As shown, the display device 100 provided in some embodiments of the present disclosure further includes a first switching electrode AE1 disposed on a first side of the light emitting control line EL, and a second switching electrode AE2 extending from the first side of the light emitting control line EL to the second side of the light emitting control line EL.

[0115] For example, the orthographic projection of the second switching electrode AE2 on the base substrate intersects with the orthographic projection of the light emitting control line EL on the base substrate. The two ends of the first switching electrode AE1 are electrically connected to the first electrode 111 of the first transistor 110 and the first electrode 121 of the second transistor 120, respectively, the first switching electrode AE1 is electrically connected to the second switching electrode AE2, and the second switching electrode AE2 is electrically connected to the control electrode 143 of the driving transistor 140.

[0116] For example, the extending direction of the second transition electrode AE2 is perpendicular to the extending direction of the first transition electrode AE1 and perpendicular to the fourth direction D4.

[0117] Since the second transfer electrode AE2 is connected to the storage capacitor CST, the level on the second transfer electrode AE2 may fluctuate greatly during operation of the pixel circuit, and the fluctuation may cause crosstalk to the first power supply voltage line VL1, thereby generating noise. In the display device 100 provided by the embodiment of the present disclosure, the first power supply voltage line VL1 and the second transfer electrode AE2 are separated by the second power supply voltage line VL2, thereby reducing the crosstalk caused by the level fluctuation on the second transfer electrode AE2 to the first power supply voltage line VL1, thereby isolating the noise.

[0118] In addition, the display device 100 provided by some embodiments of the present disclosure reserves a wiring channel for the second power supply voltage line VL2 by extending the first active area 114 of the first transistor 110 and extending the second active area 124 of the second transistor 120 .

[0119] For example, the layout size of the pixel circuit (rectangular shape) provided by the embodiment of the present disclosure is approximately 4.5um×2.9um.

[0120] Figures 4A-4E They are shown respectively Figure 3 1 is a plan view of the layout of each layer of the display device 100 shown in FIG.

[0121] Figure 4A The first active region 114 of the first transistor 110, the second active region 124 of the second transistor 120, the third active region 134 of the third transistor 130, and the fourth active region 144 of the driving transistor 140 are shown. Figure 4A The layer shown is called the active appearance (AA) layer.

[0122] Figure 4B The control electrode 113 of the first transistor 110, the control electrode 123 of the second transistor 120, the control electrode 133 of the third transistor 130, and the control electrode 143 of the driving transistor 140 are shown. The layer shown in 4B can be called a first conductive layer, which will be further described below. For example, the material of the first conductive layer can be polysilicon.

[0123] Figure 4C The first power supply voltage line VL1, the second power supply voltage line VL2, the light emitting control line EL, the data line DL, the ground line GND, the first transfer electrode AE1, etc. can be Figure 4C The layer shown is referred to as the first metal layer (metal1).

[0124] Figure 4DThe second transfer electrode AE2, the electrode connecting the first scanning signal line SL1 and the first transistor 110, and the electrode connecting the second scanning signal line SL2 and the second transistor 120 are shown. Figure 4D The layer shown is referred to as the second metal layer (metal2).

[0125] Figure 4E The first scanning signal line SL1 and the second scanning signal line SL2 are shown. Figure 4E The layer shown is referred to as the third metal layer (metal3).

[0126] It should be noted that, in order to clarify the embodiments of the present disclosure, Figure 3 The storage capacitor CST is not shown in the figure. Figure 5-7E right Figure 2 The storage capacitor CST shown in FIG. 1 is further described.

[0127] like Figure 5 As shown, Figure 5 The region 800 shown in FIG. 8 is a region where the storage capacitor CST is disposed. It should be noted that, for the sake of clarity, Figure 5 The corresponding marks of all structures are not shown in the figure. The omitted parts can be referred to Figure 3 The corresponding mark in .

[0128] Figure 6 is the layout diagram of the storage capacitor CST, Figure 7A-7D For the corresponding Figure 6 Floor plan of the layout of each floor, Fig. 7E Schematic diagram of the cross section of the storage capacitor CST.

[0129] Figure 6 A four-layer structure is shown, namely a third metal layer metal3, a fourth metal layer metal4, an auxiliary metal layer metal4', and a fifth metal layer metal5; in addition, a first via V1 and a second via V2 are also shown. The first via V1 and the second via V2 will be described in conjunction with the cross-sectional schematic diagram below, and will not be repeated here.

[0130] For example, Fig. 7A The third metal layer metal3 is shown. For example, the third metal layer and Figure 4E The layers shown in are the same layer. Fig. 7AAs shown, the third metal layer metal3 includes two parts, namely, an electrode 811 serving as a first electrode of the first capacitor C1 and an electrode 812 serving as a second electrode of the first capacitor C1. For example, the electrode 811 is configured to receive a third power supply voltage AVSS; the electrode 812 is electrically connected to the electrode 840 in the fifth metal layer metal5 through the second via V2, thereby achieving electrical connection with the control electrode 143 of the driving transistor 140.

[0131] The electrode 811 includes a plurality of strip electrodes, and the electrode 812 includes a plurality of strip electrodes. The plurality of strip electrodes of the electrode 811 and the plurality of strip electrodes of the electrode 812 are arranged alternately, and the electrode 811 and the electrode 812 and the interval therebetween form a first capacitor C1. For example, the first capacitor C1 is a part of the storage capacitor CST, for example, the first capacitor C1 and the second capacitor C2 described below are connected in parallel to form the storage capacitor CST.

[0132] For example, Figure 7B An electrode 820 located on the fourth metal layer metal4 is shown. For example, the electrode 820 is a planar electrode, and the electrode 820 serves as a first electrode of the second capacitor C2.

[0133] For example, Figure 7C An electrode 830 located on the auxiliary metal layer metal4 ′ is shown. For example, the electrode 830 is a planar electrode, and the electrode 830 serves as the second electrode of the second capacitor C2 .

[0134] For example, Fig.7D An electrode 840 located at a fifth metal layer metal5, as well as a first via hole V1 and a second via hole V2 are shown.

[0135] Fig. 7E A schematic cross-sectional view of a partial structure of the storage capacitor CST is shown. Fig. 7E As shown, the electrode 840 located in the fifth metal layer metal5 is electrically connected to the electrode 830 located in the auxiliary metal layer metal4' through the first via hole V1; in addition, the electrode 840 located in the fifth metal layer metal5 is electrically connected to the electrode 812 located in the third metal layer metal3 through the second via hole V2. It should be noted that the second via hole V2 will penetrate the fourth metal layer metal4, Fig. 7E Not shown in FIG.

[0136] like Fig. 7E As shown, the electrode 820 located on the fourth metal layer metal4 and the electrode 830 located on the auxiliary metal layer metal4' and the space therebetween form a second capacitor C2; for example, the first capacitor C1 and the second capacitor C2 described above are connected in parallel to form a storage capacitor CST.

[0137] In the embodiments of the present disclosure, Fig. 7E As shown, an auxiliary metal layer Metal4' is provided between the fourth metal layer Metal4 and the fifth metal layer Metal5, so that the distance between the fourth metal layer Metal4 and the auxiliary metal layer Metal4' can be, for example, about 1 / 10 of the distance between the fourth metal layer Metal4 and the fifth metal layer Metal5, thereby effectively increasing the capacitance value per unit area of ​​the second capacitor C2.

[0138] like Figure 2 and Figure 3 As shown, the embodiment of the present disclosure further provides a display device 100, including a substrate and at least one pixel circuit formed on the substrate. The pixel circuit includes a driving transistor 140, a first transistor 110, a second transistor 120 and a third transistor 130.

[0139] The driving transistor 140 includes a control electrode 143, a first electrode 141 and a second electrode 142, and is configured to control a driving current flowing through the first electrode 141 and the second electrode 142 of the driving transistor 140 for driving the light emitting element LE to emit light according to a voltage of the control electrode 143 of the driving transistor 140.

[0140] The first transistor 110 is connected to the control electrode 143 of the driving transistor 140, and is configured to write the data signal DATA to the control electrode 143 of the driving transistor 140 in response to the first scan signal SCAN1. The second transistor 120 is connected to the control electrode 143 of the driving transistor 140, and is configured to write the data signal DATA to the control electrode 143 of the driving transistor 140 in response to the second scan signal SCAN2. The third transistor 130 is connected to the first electrode 141 of the driving transistor 140, and is configured to apply the first power supply voltage ELVDD to the first electrode 141 of the driving transistor 140 in response to the light emission control signal EN.

[0141] The display device 100 also includes a first scan signal line SL1 for transmitting a first scan signal SCAN1 and a second scan signal line SL2 for transmitting a second scan signal SCAN2, a first power supply voltage line VL1 for transmitting a first power supply voltage ELVDD, and a light control line EL for transmitting a light control signal EN; the first scan signal line SL1, the second scan signal line SL2, the first power supply voltage line VL1 and the light control line EL are arranged in sequence along the direction perpendicular to the fourth direction D4 along the orthographic projection of the substrate.

[0142] For example, the direction from the first electrode 111 of the first transistor 110 to the second electrode 112 of the first transistor 110 is the first direction D1, the direction from the first electrode 121 of the second transistor 120 to the second electrode 122 of the second transistor 120 is the second direction D2, the direction from the first electrode 131 of the third transistor 130 to the second electrode 132 of the third transistor 130 is the third direction D3, and the direction from the first electrode 141 of the driving transistor 140 to the second electrode 142 of the driving transistor 140 is the fourth direction D4, and the first direction D1, the second direction D2 and the third direction D3 all intersect with the fourth direction D4. For example, the first direction D1, the second direction D2 and the third direction D3 are all perpendicular to the fourth direction D4.

[0143] At least one embodiment of the present disclosure further provides a method for manufacturing a display device 100 , the method comprising: forming a pixel circuit on a base substrate.

[0144] The pixel circuit includes a driving transistor 140 , a first transistor 110 , and a second transistor 120 .

[0145] The driving transistor 140 includes a control electrode 143, a first electrode 141 and a second electrode 142, and is configured to control a driving current flowing through the first electrode 141 and the second electrode 142 of the driving transistor 140 for driving the light emitting element LE to emit light according to a voltage of the control electrode 143 of the driving transistor 140.

[0146] The first transistor 110 is connected to the control electrode 143 of the driving transistor 140 and is configured to write the data signal DATA to the control electrode 143 of the driving transistor 140 in response to the first scan signal SCAN1. The second transistor 120 is connected to the control electrode 143 of the driving transistor 140 and is configured to write the data signal DATA to the control electrode 143 of the driving transistor 140 in response to the second scan signal SCAN2.

[0147] The direction along the first pole 111 of the first transistor 110 to the second pole 112 of the first transistor 110 is the first direction D1, the direction along the first pole 121 of the second transistor 120 to the second pole 122 of the second transistor 120 is the second direction D2, and the direction along the first pole 141 of the driving transistor 140 to the second pole 142 of the driving transistor 140 is the fourth direction D4. At least one of the first direction D1 and the second direction D2 intersects with the fourth direction D4; for example, the first direction D1 and the second direction D2 are both perpendicular to the fourth direction D4.

[0148] At present, as users' demand for high-brightness display of silicon-based OLED display devices continues to increase, the pixel circuit in the display device needs to output a higher driving current to the anode of the OLED. Figure 2 As shown, when the OLED needs to output a higher brightness, the OLED anode voltage needs a higher voltage V anode At this time, a high voltage V appears at the first electrode 111 (eg, drain) of the first transistor 110 and the first electrode 121 (eg, drain) of the second transistor 120. anode +V GS4 (V GS4 = is the voltage difference between the gate and the second electrode of the driving transistor 140), a high voltage will appear between the gate and the first electrode of the first transistor 110 and the second transistor 120. In this case, the first transistor 110 and the second transistor 120 in the pixel circuit will be subjected to a high voltage and may be broken down, which may affect the reliability and stability of the pixel circuit.

[0149] At least one embodiment of the present disclosure also provides a structural design of a transistor that can reduce or avoid the risk of breakdown by high voltage, so that a pixel circuit using the transistor is not easily broken down by high voltage and high-brightness display driving of the pixel circuit can be achieved.

[0150] At least one embodiment of the present disclosure provides a display device 100, including a substrate and a pixel circuit formed on the substrate. The pixel circuit includes a driving transistor 140, a first transistor 110 and a second transistor 120; the driving transistor 140 includes a control electrode 143, a first electrode 141 and a second electrode 142, and is configured to control the driving current for driving the light-emitting element LE to emit light flowing through the first electrode 141 of the driving transistor 140 and the second electrode 142 of the driving transistor 140 according to the voltage of the control electrode 143 of the driving transistor 140; the first electrode 111 of the first transistor 110 is connected to the control electrode 143 of the driving transistor 140, and is configured to write a data signal DATA to the control electrode 143 of the driving transistor 140 in response to a first scan signal SCAN1; the second transistor 120 is connected to the control electrode 143 of the driving transistor 140, and is configured to write a data signal DATA to the control electrode 143 of the driving transistor 140 in response to a second scan signal SCAN2.

[0151] For example, Figure 8 As shown, the substrate includes a doped semiconductor body 330 and a first conductive layer 310 and a second conductive layer 320 located on the semiconductor body 330 .

[0152] The first transistor 110 includes a gate GE1 located in the first conductive layer 310, a second electrode SE1 and a first electrode DE1 located in the second conductive layer 320, and a first doping region DR1 in contact with the first electrode DE1 of the first transistor 110, and a second doping region SR1 in contact with the second electrode SE1 of the first transistor 110. The first doping region DR1 of the first transistor 110 and the second doping region SR1 of the first transistor 110 are spaced apart from each other, have the same doping type, and are both located in the semiconductor body 330. The channel region of the first transistor 110 is between the first doping region DR1 and the second doping region SR1. When the first transistor 110 is turned on due to the control voltage applied to the gate GE1, the first doping region DR1 and the second doping region SR1 are turned on through the channel region. It should be noted that the gate GE1 of the first transistor 110 here is the control electrode 113 of the first transistor 110 described above, and the following embodiments are the same and will not be repeated.

[0153] like Figure 8 As shown, the first transistor 110 further includes a drift doping region DF1 in contact with the first doping region DR1, and the drift doping region DF1 of the first transistor 110 and the second doping region SR1 of the first transistor 110 are spaced apart from each other, have the same doping type, and are both located in the semiconductor body 330. For example, the first transistor 110 is a P-type MOS transistor, and the doping types of the first doping region DR1, the second doping region SR1, and the drift doping region DF1 of the first transistor 110 are all P-type doping, and the semiconductor body 330 is bulk silicon or silicon on an insulating layer with a P-type doping type.

[0154] For example, the orthographic projection of the gate GE1 of the first transistor 110 on the substrate partially overlaps with the orthographic projection of the drift doping region DF1 of the first transistor 110 on the substrate, and the orthographic projection of the first doping region DR1 of the first transistor 110 on the substrate is located in the orthographic projection of the drift doping region DF1 of the first transistor 110 on the substrate; the doping concentration of the drift doping region DF1 of the first transistor 110 is lower than the doping concentration of the first doping region DR1 of the first transistor 110. When the first transistor 110 is turned on due to the control voltage applied to the gate GE1, the first doping region DR1 and the second doping region SR1 are turned on through the channel region and the drift doping region DF1 of the first transistor 110.

[0155] The pixel circuit in the display device 100 provided by the embodiment of the present disclosure provides a drift doping region DF1 in the first transistor 110, and makes the doping concentration of the drift doping region DF1 of the first transistor 110 lower than the doping concentration of the first doping region DR1 of the first transistor 110, thereby increasing the breakdown voltage between the first electrode DE1 and the second electrode SE1 of the first transistor 110, so that the first transistor 110 can reduce or avoid the risk of being broken down by a high voltage. For example, the first transistor 110 is a P-type MOS transistor.

[0156] like Figure 8 As shown, in at least one embodiment, the drift doping region DF1 of the first transistor 110 includes a first portion DF11 and a second portion DF12; the orthographic projection of the second portion DF12 on the substrate substrate overlaps with the orthographic projection of the first doping region DR1 of the first transistor 110 on the substrate substrate, and at this time, it can be considered that the second portion DF12 of the first doping region DF1 of the first transistor 110 constitutes a part of the channel region and is different from other parts of the channel region. For example, the first doping region DR1 of the first transistor 110 is within the drift doping region DF1 of the first transistor 110. For example, the doping depth of the first doping region DR1 of the first transistor 110 in the semiconductor body 330 can be less than, equal to, or greater than the doping depth of the drift doping region DF1 of the first transistor 110.

[0157] like Figure 8 As shown, in the first transistor 110 provided in some embodiments of the present disclosure, the first doping region DR1, the second doping region SR1 and the drift doping region DF1 of the first transistor 110 are located in the first well WL1 in the semiconductor body 330, for example, the doping type of the first well WL1 is N-type doping.

[0158] The orthographic projection of the gate GE1 of the first transistor 110 on the substrate is located in the orthographic projection of the first well WL1 on the substrate, and the portion of the first well WL1 between the first doping region DR1 of the first transistor 110 and the second doping region SR1 of the first transistor 110 constitutes the channel region of the first transistor 110. For example, Figure 3 The region where the first well WL1 is located is shown in FIG.

[0159] For example, Figure 8As shown, the first transistor 110 further includes an auxiliary doping region BR; for example, the doping type of the auxiliary doping region BR of the first transistor 110 is N-type doping, the auxiliary doping region BR of the first transistor 110 is in contact with the second doping region SR1 of the first transistor 110, the auxiliary doping region BR of the first transistor 110 is electrically connected to the second electrode SE1 of the first transistor 110, and the positive projection of the auxiliary doping region BR of the first transistor 110 on the substrate is located in the positive projection of the first well WL1 on the substrate. The auxiliary doping region BR can play an isolation role to prevent leakage.

[0160] like Figure 8 As shown, the substrate in the display device 100 provided in some embodiments of the present disclosure further includes a first insulating layer IS1 located between the semiconductor body 330 and the first conductive layer 310, and the first insulating layer IS1 can insulate the gate GE1 of the first transistor 110 from the semiconductor body 330. For example, the first insulating layer IS1 can be a gate insulating layer, such as a silicon oxide layer, and can be formed by a vapor deposition process, or obtained by directly oxidizing the silicon-based substrate through a thermal oxidation process.

[0161] The first insulating layer IS1 includes a first portion IS11 close to the first doping region DR1 of the first transistor 110 and a second portion IS12 away from the first doping region DR1 of the first transistor 110 .

[0162] For example, in at least one embodiment, the thickness of the first portion IS11 of the first insulating layer IS1 is greater than the thickness of the second portion IS12 of the first insulating layer IS1, and the thickness is the thickness in a direction perpendicular to the substrate. For example, the thickness of the first portion IS11 of the first insulating layer IS1 is 7 to 8 nanometers, and the thickness of the second portion IS12 of the first insulating layer IS1 is 2 to 3 nanometers.

[0163] In an embodiment of the present disclosure, by thickening the first portion IS11 of the first insulating layer IS1, for example, thickening it to more than twice the thickness of the second portion IS12, the risk of breakdown by high voltage between the gate GE1 of the first transistor 110 and the first electrode DE1 of the first transistor 110 can be reduced or avoided.

[0164] like Figure 8As shown, the substrate further includes a planarization insulating layer PL, which covers the gate GE1 of the first transistor 110, and the light emitting element LE is located on the planarization insulating layer PL. The planarization insulating layer PL can cover the above-mentioned pixel circuit, so that the surface of the planarization insulating layer PL is relatively flat, which is more conducive to forming the light emitting element LE on the planarization insulating layer PL. The planarization insulating layer PL can be silicon oxide, silicon oxynitride, silicon nitride, etc., and can be obtained by vapor deposition and other processes.

[0165] For example, in Figure 8 In the embodiment shown, the first transistor 110 adopts a structural design that can reduce or avoid the risk of breakdown by high voltage, while the second transistor 120 adopts a common MOS transistor structure design. Figure 8 As shown, the second transistor 120 includes a gate GE2 located in the first conductive layer 310, a first electrode DE2 and a second electrode SE2 located in the second conductive layer 320, and a first doping region DR2 in contact with the first electrode DE2 of the second transistor 120, and a second doping region SR2 in contact with the second electrode SE2 of the second transistor 120. The first doping region DR2 of the second transistor 120 and the second doping region SR2 of the second transistor 120 are spaced apart from each other, have the same doping type, and are both located in the semiconductor body 330. It should be noted that the gate GE2 of the second transistor 120 here is the control electrode 123 of the second transistor 120 described above, and the following embodiments are the same and will not be repeated. For example, the second transistor 120 is an N-type MOS transistor, and the doping types of the first doping region DR2 and the second doping region SR2 of the second transistor 120 are both N-type doping.

[0166] For example, Figure 8 As shown, the second transistor 120 further includes an auxiliary doping region BR2, the auxiliary doping region BR2 of the second transistor 120 contacts the second doping region SR2 of the second transistor 120, the auxiliary doping region BR2 of the second transistor 120 is electrically connected to the second electrode SE2 of the second transistor 120, and the doping type of the auxiliary doping region BR2 of the second transistor 120 is opposite to the doping type of the second doping region SR2 of the second transistor 120, for example, the doping type of the auxiliary doping region BR2 of the second transistor 120 is P-type doping. The auxiliary doping region BR2 can play an isolation role to prevent leakage.

[0167] It should be noted that the embodiments of the present disclosure include but are not limited to the above-mentioned situations. The first transistor 110 can also adopt an N-type MOS transistor. The doping type of the first doping region DR1 in the first transistor 110 is N-type, and the semiconductor body 330 is bulk silicon or silicon on an insulating layer with a doping type of P-type.

[0168] For example, when the first transistor 110 is an N-type MOS transistor, the first transistor 110 may further include an auxiliary doping region. At this time, the doping type of the auxiliary doping region of the first transistor 110 is P-type, and the auxiliary doping region of the first transistor 110 is in contact with the second doping region SR1 of the first transistor 110, and the auxiliary doping region is electrically connected to the second electrode SE1 of the first transistor 110.

[0169] like Fig. 9 As shown, in the pixel unit provided in some embodiments of the present disclosure, the second transistor 120 adopts a structural design that can reduce or avoid the risk of breakdown by high voltage, while the first transistor 110 adopts a common MOS transistor structure design.

[0170] like Fig. 9 As shown, the second transistor 120 includes a gate GE2 located in the first conductive layer 310, a first electrode DE2 and a second electrode SE2 located in the second conductive layer 320, and a first doping region DR2 in contact with the first electrode DE2 of the second transistor 120, and a second doping region SR2 in contact with the second electrode SE2 of the second transistor 120. The first doping region DR2 of the second transistor 120 and the second doping region SR2 of the second transistor 120 are spaced apart from each other, have the same doping type, and are both located in the semiconductor body 330.

[0171] For example, the second transistor 120 further includes a drift doping region DF2 in contact with the first doping region DR2, and the drift doping region DF2 of the second transistor 120 and the second doping region SR2 of the second transistor 120 are spaced apart from each other, have the same doping type, and are both located in the semiconductor body 330. For example, the second transistor 120 is a P-type MOS transistor, and the doping types of the first doping region DR2, the second doping region SR2, and the drift doping region DF2 of the second transistor 120 are all N-type doping, and the semiconductor body 330 is bulk silicon or silicon on an insulating layer with a P-type doping type.

[0172] For example, the orthographic projection of the gate GE2 of the second transistor 120 on the substrate partially overlaps with the orthographic projection of the drift doping region DF2 of the second transistor 120 on the substrate, and the orthographic projection of the first doping region DR2 of the second transistor 120 on the substrate is located in the orthographic projection of the drift doping region DF2 of the second transistor 120 on the substrate; the doping concentration of the drift doping region DF2 of the second transistor 120 is lower than the doping concentration of the first doping region DR2 of the second transistor 120.

[0173] The pixel circuit in the display device 100 provided by the embodiment of the present disclosure sets a drift doping region DF2 in the second transistor 120, and makes the doping concentration of the drift doping region DF2 of the second transistor 120 lower than the doping concentration of the first doping region DR2 of the second transistor 120, thereby increasing the breakdown voltage between the first electrode DE2 and the second electrode SE2 of the second transistor 120, so that the second transistor 120 can reduce or avoid the risk of being broken down by high voltage. Fig. 9 As shown, the drift doping region DF2 of the second transistor 120 includes a first portion DF21 and a second portion DF22; the orthographic projection of the second portion DF22 on the substrate overlaps with the orthographic projection of the first doping region DR2 of the second transistor 120 on the substrate. For example, the first doping region DR2 of the second transistor 120 is within the drift doping region DF2 of the second transistor 120.

[0174] For example, Fig. 9 As shown, the second transistor 120 further includes an auxiliary doping region BR2; for example, the doping type of the auxiliary doping region BR2 of the second transistor 120 is P-type doping, the auxiliary doping region BR2 of the second transistor 120 is in contact with the second doping region SR2 of the second transistor 120, and the auxiliary doping region BR2 of the second transistor 120 is electrically connected to the second electrode SE2 of the second transistor 120. The auxiliary doping region BR2 can play an isolation role to prevent leakage.

[0175] like Fig. 9 As shown, the substrate in the display device 100 provided in some embodiments of the present disclosure further includes a second insulating layer IS2 located between the semiconductor body 330 and the first conductive layer 310, and the second insulating layer IS2 can insulate the gate GE2 of the second transistor 120 from the semiconductor body 330. For example, the second insulating layer IS2 can be a gate insulating layer, such as a silicon oxide layer, and can be formed by a vapor deposition process, or obtained by directly oxidizing the silicon-based substrate through a thermal oxidation process.

[0176] The second insulating layer IS2 includes a first portion IS21 close to the first doping region DR2 of the second transistor 120 and a second portion IS22 away from the first doping region DR2 of the second transistor 120 .

[0177] For example, the thickness of the first portion IS21 of the second insulating layer IS2 is greater than the thickness of the second portion IS22 of the second insulating layer IS2, and the thickness is the thickness in a direction perpendicular to the substrate. For example, the thickness of the first portion IS21 of the second insulating layer IS2 is 7 to 8 nanometers, and the thickness of the second portion IS22 of the second insulating layer IS2 is 2 to 3 nanometers.

[0178] In an embodiment of the present disclosure, by thickening the thickness of the first portion IS21 of the second insulating layer IS2, for example, thickening it to more than twice the thickness of the second portion IS22, the risk of breakdown by high voltage between the gate GE2 of the second transistor 120 and the first electrode DE2 of the second transistor 120 can be reduced or avoided.

[0179] like Fig. 9 As shown, the substrate also includes a planarization insulating layer PL, which covers the gate GE2 of the second transistor 120, and the light-emitting element LE is located on the planarization insulating layer PL. The planarization insulating layer PL can cover the above-mentioned pixel circuit, so that the surface of the planarization insulating layer PL is relatively flat, which is more conducive to forming the light-emitting element on the planarization insulating layer PL. The planarization insulating layer PL can be silicon oxide, silicon oxynitride, silicon nitride, etc., and can be obtained by vapor deposition and other processes.

[0180] For example, in Fig. 9 In the embodiment shown, the second transistor 120 adopts a structural design that can reduce or avoid the risk of breakdown by high voltage, while the first transistor 110 adopts a common MOS transistor structure design. Fig. 9 As shown, the first transistor 110 includes a gate GE1 located in the first conductive layer 310, a first electrode DE1 and a second electrode SE1 located in the second conductive layer 320, and a first doping region DR1 in contact with the first electrode DE1 of the first transistor 110, and a second doping region SR1 in contact with the second electrode SE1 of the first transistor 110. The first doping region DR1 of the first transistor 110 and the second doping region SR1 of the first transistor 110 are spaced apart from each other, have the same doping type, and are both located in the semiconductor body 330. For example, the first transistor 110 is a P-type MOS transistor, and the doping types of the first doping region DR1 and the second doping region SR1 of the first transistor 110 are both P-type doping.

[0181] like Fig. 9 As shown, in the first transistor 110 provided in some embodiments of the present disclosure, the first doping region DR1 and the second doping region SR1 of the first transistor 110 are located in the second well WL2 in the semiconductor body 330 , for example, the doping type of the second well WL2 is N-type doping.

[0182] The orthographic projection of the gate GE1 of the first transistor 110 on the substrate is located in the orthographic projection of the second well WL2 on the substrate, and the part of the second well WL2 located between the first doping region DR1 of the first transistor 110 and the second doping region SR1 of the first transistor 110 constitutes the channel region of the first transistor 110.

[0183] For example, Fig. 9As shown, the first transistor 110 further includes an auxiliary doping region BR; for example, the doping type of the auxiliary doping region BR of the first transistor 110 is N-type doping, the auxiliary doping region BR of the first transistor 110 is in contact with the second doping region SR1 of the first transistor 110, the auxiliary doping region BR of the first transistor 110 is electrically connected to the second electrode SE1 of the first transistor 110, and the positive projection of the auxiliary doping region BR of the first transistor 110 on the substrate is located in the positive projection of the second well WL2 on the substrate. The auxiliary doping region BR can play an isolation role to prevent leakage.

[0184] like Fig.10 As shown, in the display device provided in some embodiments of the present disclosure, the first transistor 110 and the second transistor 120 are both designed to reduce or avoid the risk of breakdown by high voltage. For the specific structure of the first transistor 110 and the second transistor 120, please refer to Figure 5 and Figure 6 The corresponding description in the illustrated embodiment will not be repeated here.

[0185] In the display device provided in the embodiment of the present disclosure, by making the first transistor 110 and the second transistor 120 both adopt a structural design that can reduce or avoid the risk of breakdown by high voltage, the risk of breakdown by high voltage can be improved or avoided, thereby improving the reliability and stability of the display device.

[0186] For example, in the display device 100 provided in some embodiments of the present disclosure, the substrate is a P-type silicon substrate, the first transistor 110 is a P-type MOS transistor, and the second transistor 120, the third transistor 130 and the driving transistor 140 are all N-type MOS transistors.

[0187] At least one embodiment of the present disclosure further provides a method for manufacturing a display device 100 , the method comprising: forming a pixel circuit on a base substrate.

[0188] The pixel circuit includes a driving transistor 140 , a first transistor 110 and a second transistor 120 .

[0189] The driving transistor 140 includes a control electrode 143, a first electrode 141 and a second electrode 142, and is configured to control a driving current flowing through the first electrode 141 and the second electrode 142 of the driving transistor 140 for driving the light-emitting element LE to emit light according to the voltage of the control electrode 143 of the driving transistor 140.

[0190] The first transistor 110 is connected to the control electrode 143 of the driving transistor 140 and is configured to write the data signal DATA to the control electrode 143 of the driving transistor 140 in response to the first scan signal SCAN1. The second transistor 120 is connected to the control electrode 143 of the driving transistor 140 and is configured to write the data signal DATA to the control electrode 143 of the driving transistor 140 in response to the second scan signal SCAN2.

[0191] The above-mentioned substrate also includes a doped semiconductor body 330; the above-mentioned preparation method also includes: forming a first conductive layer 310 and a second conductive layer 320 of the substrate on the semiconductor body 330, and the first transistor 110 includes a gate GE1 located in the first conductive layer 310 and a first electrode DE1 and a second electrode SE1 located in the second conductive layer 320.

[0192] The above-mentioned preparation method also includes: forming a first doping region DR1 of the first transistor 110 in contact with the first electrode DE1 of the first transistor 110 and a second doping region SR1 of the first transistor 110 in contact with the second electrode SE1 of the first transistor 110 in the semiconductor body 330, the first doping region DR1 of the first transistor 110 and the second doping region SR1 of the first transistor 110 are spaced apart from each other, have the same doping type and are both located in the semiconductor body 330.

[0193] The above-mentioned preparation method also includes: forming a drift doping region DF1 of the first transistor 110 with the same doping type as the second doping region SR1 of the first transistor 110 in the semiconductor body 330; the drift doping region DF1 of the first transistor 110 is located in the semiconductor body 330 and is separated from the second doping region SR1 of the first transistor 110, the orthographic projection of the gate GE1 of the first transistor 110 on the substrate partially overlaps with the orthographic projection of the drift doping region DF1 of the first transistor 110 on the substrate, and the orthographic projection of the first doping region DR1 of the first transistor 110 on the substrate is located in the orthographic projection of the drift doping region DF1 of the first transistor 110 on the substrate, and the doping concentration of the drift doping region DF1 of the first transistor 110 is lower than the doping concentration of the first doping region DR1 of the first transistor 110.

[0194] The manufacturing method further includes: forming a first insulating layer IS1 of the substrate between the semiconductor body 330 and the first conductive layer 310. The first insulating layer IS1 includes a first portion IS11 close to the first doping region DR1 of the first transistor 110 and a second portion IS12 away from the first doping region DR1 of the first transistor 110; the thickness of the first portion IS11 of the first insulating layer IS1 is greater than the thickness of the second portion IS12 of the first insulating layer IS1, and the thickness is the thickness in a direction perpendicular to the substrate.

[0195] At least one embodiment of the present disclosure further provides a method for manufacturing a display device 100 , the method comprising: forming a pixel circuit on a base substrate.

[0196] The pixel circuit includes a driving transistor 140 , a first transistor 110 and a second transistor 120 .

[0197] The driving transistor 140 includes a control electrode 143, a first electrode 141 and a second electrode 142, and is configured to control a driving current flowing through the first electrode 141 and the second electrode 142 of the driving transistor 140 for driving the light-emitting element LE to emit light according to the voltage of the control electrode 143 of the driving transistor 140.

[0198] The first transistor 110 is connected to the control electrode 143 of the driving transistor 140 and is configured to write the data signal DATA to the control electrode 143 of the driving transistor 140 in response to the first scan signal SCAN1. The second transistor 120 is connected to the control electrode 143 of the driving transistor 140 and is configured to write the data signal DATA to the control electrode 143 of the driving transistor 140 in response to the second scan signal SCAN2.

[0199] The first transistor 110 includes a first active area 114, the second transistor 120 includes a second active area 124, and the driving transistor 140 includes a fourth active area 144; the above-mentioned preparation method also includes: doping the first active area 114, the second active area 124 and the fourth active area 144 so that the doping concentration of at least one of the first active area 114 and the second active area 124 is greater than the doping concentration of the fourth active area 144.

[0200] The above-mentioned pixel circuit also includes a third transistor 130, which is connected to the first electrode 141 of the driving transistor 140 and is configured to apply the first power supply voltage ELVDD to the first electrode 141 of the driving transistor 140 in response to the light emitting control signal EN, and the third transistor 130 includes a third active area 134; the above-mentioned preparation method also includes: doping the third active area 134 so that the doping concentration of the fourth active area 144 is less than the doping concentration of the third active area 134.

[0201] It should be noted that the technical effects of the method for preparing the display device 100 provided in the embodiment of the present disclosure can refer to the corresponding description in the above embodiment of the display device 100, which will not be repeated here.

[0202] Below Figure 8 The illustrated embodiment is used as an example to describe a method for manufacturing a display device 100 provided in an embodiment of the present disclosure.

[0203] like Figure 8 As shown, a semiconductor body 330 is first provided, and then N-type doping is performed in the semiconductor body 330 to form a first well WL1; then, P-type doping is performed in the first well WL1 to form a drift doping region DF1 of the first transistor 110; then, P-type doping is performed in the drift doping region DF1 of the first transistor 110 to form a first doping region DR1 of the first transistor 110, and the doping concentration of the first doping region DR1 of the first transistor 110 is higher than the doping concentration of the drift doping region DF1 of the first transistor 110; at the same time, P-type doping is performed in the first well WL1 to form a second doping region SR1 of the first transistor 110, and N-type doping is performed to form an auxiliary doping region BR of the first transistor 110.

[0204] Then, a first insulating layer IS1 is formed on the semiconductor body 330, and the thickness of the first part IS11 of the first insulating layer IS1 is greater than the thickness of the second part IS12 of the first insulating layer IS1; then, a first conductive layer 310 is formed on the first insulating layer IS1, and the first conductive layer 310 includes the gate GE1 of the first transistor 110.

[0205] Then, a planarization insulating layer PL is formed to cover the gate GE1 of the first transistor 110 ; then, a via hole is formed in the planarization insulating layer PL to expose the first doping region DR1 of the first transistor, the second doping region SR1 of the first transistor 110 , and the auxiliary doping region BR of the first transistor 110 .

[0206] Finally, a second conductive layer 320 is formed. The second conductive layer 320 includes a first electrode DE1 of the first transistor 110 electrically connected to the first doped region DR1 of the first transistor 110 through a via in the planarization insulating layer PL, and a second electrode SE1 of the first transistor 110 electrically connected to the second doped region SR1 of the first transistor 110 through a via in the planarization insulating layer PL.

[0207] It should be noted that the method for preparing the second transistor 120 is similar to the above and will not be described in detail here.

[0208] At least one embodiment of the present disclosure further provides a display device 100, such as Fig.11 As shown, for example, the display device 100 includes a display panel, which includes a plurality of pixel units PU arranged in an array in a display area 300. For example, at least one of the plurality of pixel units PU can adopt a pixel circuit in any display device 100 provided in an embodiment of the present disclosure.

[0209] For example, Fig.11As shown, the display device 100 further includes a driving circuit 200 prepared in the substrate, and the driving circuit 200 is configured to provide a first scanning signal SCAN1, a second scanning signal SCAN2, and a light emitting control signal EN to pixel circuits in a plurality of pixel units PU in the display device 100. For example, the driving circuit 200 is disposed in a peripheral area 400 surrounding the display area 300.

[0210] For example, the display device 100 provided in the embodiment of the present disclosure may be any product or component with a display function, such as electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or the like.

[0211] The above description is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A display device, comprising a base substrate and at least one pixel circuit and a light-emitting element formed on the base substrate, wherein: The pixel circuit includes a driving transistor, the driving transistor includes a control electrode, a first electrode, and a second electrode, and is configured to control a driving current flowing through the first electrode of the driving transistor and the second electrode of the driving transistor for driving the light-emitting element to emit light according to a voltage of the control electrode of the driving transistor, the control electrode includes a first square main body portion and a first square protrusion portion, the first square main body portion overlaps with an active layer of the driving transistor, The first square protrusion extends from the first square main body, and the first square protrusion and the first square main body are located in the same layer. 2 . The display device according to claim 1 , wherein an area of ​​the first square main body portion is larger than an area of ​​the first square protrusion portion. 3 . The display device according to claim 1 , wherein the first square protrusion is closer to the second electrode of the driving transistor than to the first electrode of the driving transistor. 4 . The display device according to claim 1 , wherein the pixel circuit further comprises a first transistor, a first electrode of the first transistor being connected to the control electrode of the driving transistor via a switching electrode. The display device according to claim 4 , wherein the switching electrode is connected to the first square protrusion. 6 . The display device according to claim 5 , wherein the first square protrusion is located on a side of the driving transistor close to the first transistor. 7 . The display device according to claim 4 , wherein the control electrode of the first transistor comprises a second square body portion and a second square protrusion portion. 8 . The display device according to claim 7 , wherein the second square protrusion is located on a side of the control electrode of the first transistor away from the driving transistor. 9 . The display device according to claim 1 , wherein the pixel circuit further comprises a third transistor connected to the first electrode of the driving transistor. 10 . The display device according to claim 9 , wherein the control electrode of the third transistor comprises a third rectangular main portion and a third rectangular protruding portion. 11 . The display device according to claim 10 , wherein the third rectangular protrusion is located on a side of the control electrode of the third transistor close to the driving transistor.

12. The display device according to claim 1, wherein the pixel circuit further comprises a first transistor and a third transistor, the control electrode of the first transistor comprises a second square main body portion and a second square protrusion portion, the control electrode of the third transistor comprises a third square main body portion and a third square protrusion portion, and the areas of the first square protrusion portion, the second square protrusion portion, and the third square protrusion portion are each smaller than the area of ​​the second square main body portion.

13. The display device according to claim 1, wherein the pixel circuit further comprises a first transistor and a third transistor, the control electrode of the first transistor comprises a second square main body portion and a second square protrusion portion, the control electrode of the third transistor comprises a third square main body portion and a third square protrusion portion, and the areas of the first square protrusion portion, the second square protrusion portion, and the third square protrusion portion are each smaller than the area of ​​the third square main body portion.

14. The display device according to claim 1, wherein the pixel circuit further comprises a first transistor and a second transistor, and the first transistor and the second transistor each have a first electrode connected to the control electrode of the driving transistor, wherein the substrate comprises a semiconductor body and a first conductive layer and a second conductive layer formed on a surface of the semiconductor body; The first transistor comprises a first doped region contacting the first electrode of the first transistor and a second doped region contacting the second electrode of the first transistor, wherein the first doped region of the first transistor and the second doped region of the first transistor are spaced apart from each other, have the same doping type, and are both located in the semiconductor body; The substrate also includes a first insulating layer formed between the semiconductor body and the first conductive layer, the first insulating layer including a first portion of the first doped region close to the first transistor and a second portion of the first doped region away from the first transistor; The thickness of the first portion of the first insulating layer is greater than the thickness of the second portion of the first insulating layer, and the thickness of the first portion and the thickness of the second portion are thicknesses along a direction perpendicular to the base substrate.

15. The display device according to claim 14, wherein the first transistor further comprises a drift doping region contacting the first doping region of the first transistor, the drift doping region of the first transistor and the second doping region of the first transistor are spaced apart from each other, have the same doping type and are both located in the semiconductor body. 16 . The display device according to claim 15 , wherein an orthographic projection of the gate of the first transistor on the substrate partially overlaps with an orthographic projection of the drift doping region of the first transistor on the substrate. 17 . The display device according to claim 15 , wherein an orthographic projection of the first doped region of the first transistor on the substrate is located in an orthographic projection of the drift doped region of the first transistor on the substrate. 18 . The display device according to claim 15 , wherein a doping concentration of the drift doping region of the first transistor is lower than a doping concentration of the first doping region of the first transistor.

19. The display device according to claim 14, wherein the second transistor includes a first doped region in contact with the first electrode of the second transistor, a second doped region in contact with the second electrode of the second transistor, and a drift doped region in contact with the first doped region of the second transistor, the first doped region, the second doped region and the drift doped region of the second transistor are all located in the semiconductor body, and the first doped region of the second transistor and the second doped region of the second transistor are spaced apart from each other, and the drift doped region of the second transistor and the second doped region of the second transistor are spaced apart from each other.

20. The display device according to claim 19 further includes a second insulating layer formed between the semiconductor body and the first conductive layer, the second insulating layer including a first portion of the first doping region close to the second transistor and a second portion of the first doping region away from the first transistor, wherein the thickness of the first portion of the second insulating layer is greater than the thickness of the second portion of the second insulating layer, and the thickness of the first portion and the thickness of the second portion are thicknesses along the direction perpendicular to the substrate.

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