Macro pixel display backplane

Abstract

A micro-light emitting diode display backplane includes a plurality of macro-pixels. Each macro-pixel includes: a continuous two-dimensional array of bit cells, the continuous two-dimensional array of bit cells storing display data bits for driving a group of micro-LEDs in a 2D array of micro-LEDs; and a driving circuit configured to generate a pulse width modulated driving signal for driving a group of micro-LEDs in a 2D array of micro-LEDs based on the display data bits stored in the continuous 2D array of bit cells. In one example, the plurality of macro-pixels are grouped into a plurality of sub-arrays, wherein each of the plurality of sub-arrays includes a group of macro-pixels and local peripheral circuits adjacent to the group of macro-pixels. The local peripheral circuits include, for example, buffers, repeaters, clock gating circuits for gating input clock signals to sub-arrays, and / or sub-array decoders for selecting sub-arrays.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the benefit of and priority to U.S. Provisional Patent Application Serial No. 62 / 954,358, filed on December 27, 2019, entitled “Macro-Pixel Display Backplane,” which is assigned to its assignee.

[0003] background

[0004] An artificial reality system (e.g., a head-mounted display (HMD) or a head-up display (HUD) system) typically includes a near-eye display system in the form of a head-mounted device (headset) or a pair of glasses. The artificial reality system can be configured to present content to a user via an electronic or optical display, for example, within about 10 mm to 20 mm in front of the user's eyes. As in virtual reality (VR) applications, augmented reality (AR) applications, or mixed reality (MR) applications, a near-eye display system can display virtual objects or combine images of real objects with virtual objects. For example, in an AR system, a user can view virtual objects (e.g., computer-generated images (CGI)) and images of the surrounding environment, for example, by viewing through transparent display glasses or lenses, or by viewing a displayed image of the surrounding environment captured by a camera. The near-eye display system may include one or more light sources that are driven to output light at various brightness levels to display an image.

[0005] Light emitting diodes (LEDs) convert electrical energy into light energy and offer many advantages over other light sources, such as reduced size, improved durability, and increased efficiency. LEDs can be used as light sources in many display systems (e.g., televisions, computer monitors, laptops, tablets, smartphones, projection systems, and wearable electronic devices). Micro LEDs ("μLEDs") based on III-V semiconductors (such as alloys of AlN, GaN, InN, AlGaInP, other quaternary phosphide components, etc.) have begun to be developed for various display applications due to their small size (e.g., linear dimensions less than 100 μm, less than 50 μm, less than 10 μm, less than 5 μm, or less than 2 μm), high packing density (thus higher resolution), and high brightness. For example, micro LEDs emitting different colors (e.g., red, green, and blue) can be used to form sub-pixels of a display system (e.g., a near-eye display system).

[0006] Overview

[0007] The present disclosure generally relates to display systems. More specifically, the present disclosure relates to circuits for driving LED-based display panels. According to a first aspect of the present disclosure, a display device is provided, comprising: a two-dimensional (2D) array of micro light emitting diodes (microLEDs) in a display area; and a microLED driver backplane aligned with and bonded to the 2D array of microLEDs, the microLED driver backplane comprising a 2D array of subarrays, wherein each subarray in the 2D array of subarrays comprises: a drive circuit configured to generate a pulse width modulated (PWM) drive signal to drive a group of microLEDs in the 2D array of microLEDs; and a local peripheral circuit for controlling the drive circuit, the local peripheral circuit being located within the display area and comprising at least one of: a buffer, a repeater, a clock gating circuit for gating an input clock signal to a subarray, or a subarray decoder for selecting a subarray. The pitch of the 2D array of microLEDs may be equal to or less than, for example, about 2 μm.

[0008] In some embodiments of the display device, each subarray in the 2D array of subarrays may include a macropixel array. Each macropixel in the macropixel array may include a continuous 2D array of bit cells (bitcells) storing display data bits for driving a microLED subset of a group of microLEDs. In some embodiments, each bit cell in the continuous 2D array of bit cells may include a six-transistor (6T) static random access memory (SRAM) cell, which includes a word line, two bit lines, and two internal state storage nodes for storing a corresponding display data bit in the display data bits. Each bit cell in the continuous 2D array of bit cells may be configured to read a corresponding display data bit in the display data bits from the bit cell via two bit lines.

[0009] In some embodiments, each macro-pixel in the macro-pixel array may further include a corresponding current driver for each micro-LED in the micro-LED subset and configured to provide a drive current to the micro-LED; a comparator configured to compare a display data bit for driving the micro-LED with a counter value for each micro-LED in the micro-LED subset; and a corresponding PWM latch for each micro-LED in the micro-LED subset. The corresponding PWM latch may be configured to generate a PWM control signal based on an output for the micro-LED generated by the comparator, the PWM control signal being used to modulate a drive current of a corresponding current driver for the micro-LED to generate a corresponding PWM drive signal in the PWM drive signal. The corresponding current drivers for two or more micro-LEDs in the micro-LED subset may be arranged continuously in an area of ​​the macro-pixel, the area of ​​the macro-pixel being separated from an area of ​​the macro-pixel for other circuits by a transition area. The corresponding current driver for the micro-LED subset may be connected to the micro-LED subset in the 2D array of micro-LEDs through an interconnect layer including a redistribution routing interconnect. In some embodiments, the corresponding PWM latches for two or more micro-LEDs in the micro-LED subset may be arranged continuously in an area of ​​the macro-pixel. In some embodiments, the comparator can be configured to read and compare display data bits used to drive a first micro LED in the micro LED subset within a first time window, and read and compare display data bits used to drive a second micro LED in the micro LED subset within a second time window.

[0010] In some embodiments, each macropixel in the macropixel array may include a corresponding design-for-test (DFT) circuit for each micro-LED in the micro-LED subset. In some embodiments, each macropixel in the macropixel array may include a corresponding input / output circuit configured to read a display data bit stored in each row or column of the continuous 2D array of bit cells. In some embodiments, the continuous 2D array of bit cells may include at least 6 bit cells for each micro-LED in the micro-LED subset. The micro-LED subset may include, for example, 8 or more micro-LEDs.

[0011] In some embodiments, multiple sub-arrays in the 2D array of sub-arrays may be included in a slice of a micro LED driver backplane, the slice including slice peripheral circuitry for controlling the multiple sub-arrays. The slice peripheral circuitry may include at least one of a counter or a lookup table for gamma correction.

[0012] In some embodiments, the micro LED driver backplane may include peripheral circuitry external to the 2D array of sub-arrays. The peripheral circuitry may include at least one of a counter or a lookup table for gamma correction. The lookup table may store display data codes and corresponding counter values. The corresponding counter value of at least one display data code in the lookup table may be different from an ideal counter value determined for at least one display data code based on a gamma value. The repeater may be configured to replicate a control signal generated by the peripheral circuitry and used to control a drive circuit of the sub-array. The peripheral circuitry may be configured to send a control signal to a clock gating circuit for gating an input clock signal to the sub-array to disable a drive circuit configured to generate a PWM drive signal.

[0013] According to a second aspect of the present disclosure, there is provided a micro light emitting diode (micro LED) display backplane comprising a plurality of macro pixels, each of the plurality of macro pixels comprising: a continuous two-dimensional (2D) array of bit cells storing display data bits for driving a group of micro LEDs in the 2D array of micro LEDs; and a driving circuit configured to generate a pulse width modulation (PWM) drive signal for driving a group of micro LEDs in the 2D array of micro LEDs based on the display data bits stored in the continuous 2D array of bit cells.

[0014] In some embodiments, each bit cell in the continuous 2D array of bit cells may include a six-transistor (6T) static random access memory (SRAM) cell including a word line, two bit lines, and two internal state storage nodes for storing a corresponding one of the display data bits. Each bit cell in the continuous 2D array of bit cells may be configured to read a corresponding one of the display data bits from the bit cell via the two bit lines.

[0015] In some embodiments, each macropixel in a plurality of macropixels may include a corresponding current driver for each microLED in a group of microLEDs and configured to provide a drive current to the microLED; a comparator configured to compare a display data bit for driving the microLED with a counter value for each microLED in a group of microLEDs; and a corresponding PWM latch for each microLED in a group of microLEDs. The corresponding PWM latch may be configured to generate a PWM control signal based on an output for the microLED generated by the comparator, the PWM control signal being used to modulate a drive current of a corresponding current driver for the microLED to generate a corresponding PWM drive signal in the PWM drive signal. The corresponding current drivers for two or more microLEDs in a group of microLEDs may be arranged continuously in an area of ​​the macropixel, the area of ​​the macropixel being separated from an area of ​​the macropixel for other circuits by a transition area. In some embodiments, the corresponding current driver for each microLED in a group of microLEDs may include a thick gate-oxide transistor having a channel length greater than about 400nm. The drive current of the corresponding current drivers of the plurality of macropixels may be characterized by a standard deviation of less than about 20nA. The corresponding PWM latches for two or more micro-LEDs in a group of micro-LEDs can be arranged consecutively in the area of ​​the macro-pixel. The comparator can be configured to read and compare the display data bits for driving the first micro-LED in the group of micro-LEDs within a first time window, and read and compare the display data bits for driving the second micro-LED in the group of micro-LEDs within a second time window.

[0016] In some embodiments, each macropixel in a plurality of macropixels may include a corresponding design for testability (DFT) circuit for each microLED in a group of microLEDs. In some embodiments, each macropixel in a plurality of macropixels may include a corresponding input / output circuit configured to read a display data bit stored in each row or column of a continuous 2D array of bit cells. The continuous 2D array of bit cells may include, for example, at least 6 bit cells for each microLED in a group of microLEDs. A group of microLEDs may include, for example, 8 or more microLEDs. The pitch of a group of microLEDs may be equal to or less than, for example, about 2 μm.

[0017] In some embodiments, a plurality of macro pixels may be grouped into a plurality of sub-arrays, wherein each of the plurality of sub-arrays may include a group of macro pixels and local peripheral circuits adjacent to the group of macro pixels. The local peripheral circuit may include, for example, at least one of the following: a buffer, a repeater, a clock gating circuit for gating an input clock signal to a sub-array, or a sub-array decoder for selecting a sub-array. The repeater may be configured to replicate a control signal for controlling a drive circuit of a group of macro pixels in a sub-array. In some embodiments, a plurality of sub-arrays may be grouped into a plurality of slices, wherein each of the plurality of slices may include a group of sub-arrays and a slice peripheral circuit adjacent to the group of sub-arrays. The slice peripheral circuit may include at least one of a counter or a lookup table for gamma correction, wherein the lookup table may store display data codes and corresponding counter values. In some embodiments, the corresponding counter value of at least one display data code in the lookup table may be different from an ideal counter value determined for at least one display data code based on a gamma value. In some embodiments, the slice peripheral circuit may include a calibration table for calibrating the drive circuit of the macro pixels in the slice.

[0018] This summary is neither intended to identify key or essential features of the claimed subject matter nor to be used in isolation to determine the scope of the claimed subject matter. The subject matter should be understood with reference to appropriate portions of the entire specification of the disclosure, any or all of the drawings, and each claim. The foregoing and other features and examples will be described in more detail below in the following description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Illustrative examples are described in detail below with reference to the following figures.

[0021] Figure 1 is a simplified block diagram of an example of an artificial reality system environment including a near-eye display according to certain examples.

[0022] Figure 2 is a perspective view of an example of a near-eye display in the form of a head-mounted display (HMD) device for implementing some of the examples disclosed herein.

[0023] Figure 3 is a perspective view of an example of a near-eye display in the form of a pair of glasses for implementing some of the examples disclosed herein.

[0024] Figure 4 An example of an optical see-through augmented reality system including a waveguide display is shown according to certain examples.

[0025] Figure 5AExamples of near-eye display devices including waveguide displays according to certain examples are shown.

[0026] Figure 5B Examples of near-eye display devices including waveguide displays according to certain examples are shown.

[0027] Figure 6 An example of an image source assembly in an augmented reality system according to certain examples is shown.

[0028] Fig. 7A An example of a light emitting diode (LED) having a vertical mesa structure is shown, according to certain examples.

[0029] Figure 7B is a cross-sectional view of an example of an LED having a parabolic mesa structure according to some examples.

[0030] Fig. 8A An example of a method for die-to-wafer bonding of an LED array according to certain examples is shown.

[0031] Figure 8B An example of a method for wafer-to-wafer bonding of an LED array according to certain examples is shown.

[0032] Figure 9A-9D An example of a hybrid bonding method for an LED array according to certain examples is shown.

[0033] Fig.10 Examples of LED arrays with secondary optics fabricated thereon are shown, according to certain examples.

[0034] Fig.11 is a simplified block diagram of an example of a display device according to certain examples.

[0035] Fig. 12A An example of a static random access memory (SRAM) cell that can be used as a bit cell for storing intensity data is shown.

[0036] Fig. 12B is a simplified block diagram of a portion of an example of a display panel including an array of unit pixels and a customized SRAM bit cell.

[0037] Fig.13A An example of a unit pixel in an example of a display panel is shown.

[0038] Fig. 13B An example of a display panel including a two-dimensional array of unit pixels is shown.

[0039] Fig.14 An example of a plan view of a driver circuit for an example of a micro LED display panel is shown.

[0040] Fig.15A An example of improving perceived bit depth by modifying pulse width modulation timing based on a nonlinear power-law transformation is shown, according to certain examples.

[0041] Fig. 15B Examples of using temporal dithering to improve perceived bit depth are shown according to certain examples.

[0042] Fig.16A Shown in Fig.14 A simplified model of the driver circuit in the example of a micro LED display panel shown in FIG.

[0043] Fig. 16B Shown in Fig.16A An example of a simulated waveform at the end of the driver circuit is shown in FIG.

[0044] Fig.17A A simplified model of a bit cell with a long bit line is shown.

[0045] Fig. 17B Examples of simulated write noise margins for bit cells with different bit line conductor resistances are shown.

[0046] Fig.18 An example of the distribution of simulated drive current of a CMOS driver due to variations in the LED drive transistor is shown.

[0047] Fig.19A Examples of macropixels in a display panel according to certain examples are shown.

[0048] Fig.19B An example of a plan view of a display panel including macro pixels according to certain examples is shown.

[0049] Fig. 20A Another example of a macropixel in a display panel according to certain examples is shown.

[0050] Fig. 20B Including showing according to some examples Fig. 20A A simplified schematic diagram of the circuitry of an example macropixel is shown in FIG.

[0051] Fig.21A simplified schematic diagram of a 2D array of SRAM bit cells coupled to PWM logic through bit lines and input / output circuits in an example of a macropixel according to certain examples is shown.

[0052] Fig. 22 An example of a plan view of an example of a macropixel according to certain examples is shown.

[0053] Fig.23A An example of a portion of a plan view of a display panel including a unit pixel array is shown.

[0054] Fig. 23B An example of a portion of a plan view of a display panel including a macropixel array according to some examples is shown.

[0055] Fig.24A A simplified block diagram illustrating an example of a slice of a display panel including a macropixel array according to some examples.

[0056] Fig. 24B A simplified block diagram of an example of a display backplane including a 2D array of macropixels arranged in a hierarchical structure is shown, according to certain examples.

[0057] Fig.25 Examples of Verilog simulation results of the operation of a macropixel in a display panel according to certain examples are shown.

[0058] Fig.26 Examples of Spice simulation results of the operation of macropixels in a display panel according to certain examples are shown.

[0059] Fig. 27 Simulated output pulse width modulation signals of a macropixel for different display values ​​are shown according to some examples.

[0060] Fig.28 Simulated output PWM signals of macropixels for different display values ​​utilizing power law transformation are shown according to some examples.

[0061] Fig.29 An example of simulation results for a macropixel in rolling update mode with power-law (gamma) updating according to certain examples is shown.

[0062] Fig.30 A simplified schematic diagram of an example of design for testability (DFT) circuitry in a macropixel-based display backplane according to certain examples is included.

[0063] Fig.31 It is shown that driving current uniformity and LED brightness uniformity are improved by increasing the size of the LED driving transistor according to certain examples.

[0064] Fig.32 A simplified cross-sectional view of a device including a display backplane wafer bonded to a micro LED wafer via an interconnect layer is shown, according to certain examples.

[0065] Fig.33 is a simplified block diagram of an electronic system for an example near-eye display according to certain examples.

[0066] The accompanying drawings depict embodiments of the present disclosure for purposes of illustration only. Those skilled in the art will readily recognize from the following description that alternative embodiments and examples of the structures and methods shown may be employed without departing from the principles or benefits of the present disclosure.

[0067] In the drawings, similar components and / or features may have the same reference number. In addition, various components of the same type may be distinguished by following the reference number with a dash and a second reference that distinguishes between the similar components. If only the first reference number is used in the specification, the description applies to any one of the similar components having the same first reference number, regardless of the second reference number.

[0068] Detailed Description

[0069] The present disclosure generally relates to display systems. More specifically and without limitation, disclosed herein are techniques for controlling the operation of light emitting diodes (LEDs) in LED-based display panels. The techniques disclosed herein can be used to improve display quality, reduce power consumption, improve manufacturability and testability, and improve uniformity in near-eye display systems (e.g., virtual reality (VR), augmented reality (AR), or mixed reality (MR) display systems). Various embodiments and examples are described herein, including devices, systems, modules, circuits, chips, wafers, packages, methods, materials, etc.

[0070] In some LED-based displays, one or more two-dimensional (2D) arrays of microLEDs ("μLEDs") may be used to display color images. Each 2D array of microLEDs may include thousands or millions of microLEDs that may emit light of the same color (e.g., red, green, or blue) at a desired intensity to generate an image, wherein each microLED may form part of a color pixel and may (in conjunction with a corresponding driver circuit) be referred to herein as a pixel. Each 2D array of microLEDs may be controlled by a pixel array driver circuit so that the microLEDs may emit light at a desired intensity. The 2D array of microLEDs may be fabricated on a III-V semiconductor substrate, and the pixel array driver circuit may be fabricated on a silicon substrate. In order to facilitate bonding and electrically connecting the 2D array of microLEDs to the pixel array driver circuit, and in order to avoid long interconnects, the pixel array driver circuit may need to have a pixel pitch that matches the pixel pitch of the 2D array of microLEDs, which may, for example, be less than about 20 μm, less than about 10 μm, less than about 5 μm, or less than about 2 μm.

[0071] The pixel array driver circuit can upload display data to a local memory at each pixel and generate a pulse width modulation (PWM) signal based on the display data to modulate the brightness of the micro-LED. The pixel array driver circuit may include, for example, a bit cell (e.g., a local static random access memory (SRAM) cell) for storing display data (e.g., intensity data), a digital circuit for generating a PWM signal; and an analog circuit for interfacing with the high-voltage micro-LED and controlling the current of the micro-LED using the PWM signal. The pixel array driver circuit can be controlled by a pixel array peripheral circuit that loads the image data into the bit cell, sequences the logic, and generates a counter value to generate a corresponding pulse width modulated analog current for each micro-LED.

[0072] The bit depth (e.g., the number of bits) of the intensity data of each pixel can affect the number of intensity levels of the light emitted by the pixel. It is generally desirable that the bit depth is greater than, for example, 6, so as to display an image with a sufficient number of brightness changes. However, the capacity and density of the bit cells in the local memory (e.g., SRAM) may be limited by the design and processing technology (e.g., certain physical design rules) of the pixel circuit. In some display driver architectures, pixels may be evenly arranged in a 2D array, wherein each pixel may have its own bit cell, comparator, PWM latch circuit, and analog driver, and are therefore referred to herein as unit pixels. Transition regions and / or intervals may be required between different types of devices (e.g., SRAM cells, digital logic, analog circuits, high-voltage circuits, etc.) in each unit pixel and between unit pixels. Therefore, a larger portion of the 2D array of unit pixels may be used as a transition region or interval between different types of devices. Therefore, the number of bit cells that can be adapted in each unit pixel in the local memory may be limited. For example, where each pixel has its own pixel driver circuit, in 28nm CMOS technology, a 2-um unit pixel can accommodate about 6 physical bit cells, while a 1.8-um unit pixel can accommodate about 4 physical bit cells. Optimizing the layout design can help reduce the transition area, but it may not be possible to minimize the transition area as desired to make more room for additional circuits (e.g., more bit cells) because transition areas are still required between different types of devices.

[0073] In some LED-based displays, various techniques can be used to increase the perceived bit depth beyond the number of physical bit cells in each unit pixel. In one example, the perceived bit depth can be increased by modifying the PWM timing according to a nonlinear power law (e.g., by about 1.5 effective bits). In another example, time dithering can be used to increase the perceived bit depth. However, the power consumption of time dithering can be much higher because some parts of the backplane and display subsystem can operate at a much higher (e.g., 2x, 4x, or more) subframe rate in order to implement time dithering.

[0074] In addition, in order to achieve good display quality, the pixel array driver circuit and the pixel array peripheral circuit may need to meet certain circuit specifications. For example, the pixel array driver circuit may need to pass a low-variance analog drive current to avoid brightness variations. However, due to the variability of the LED driver transistors (e.g., caused by random dopant fluctuations and the small size of each LED driver transistor), the drive current and therefore the brightness may vary significantly. The brightness variation may be visible and may need to be offset by calibration using some bits of the intensity data, and the effective bit depth of the intensity data may therefore be reduced.

[0075] In addition, in displays where each unit pixel has its own pixel driver circuit, the yield may be low and the pixel array driver circuit may not be robust due to, for example, large arrays of unit pixels and customer-designed non-standard SRAM circuits (these customer-designed non-standard SRAM circuits have not yet been supported by mature traditional wafer foundry processes). For example, in a large array of unit pixels, the bit lines of some unit pixels (e.g., unit pixels in the middle of the array) may be very long (e.g., longer than 1 mm) and may therefore have high resistance, inductance, and / or capacitance. The high bit line resistance may form a voltage divider with the bit cell access transistor, which may reduce the signal level at the bit cell and, therefore, may reduce the write noise margin and prevent writing to the bit cells in the large array of unit pixels. In order to improve the write noise margin, it may be necessary to use a higher VDD or a wider (e.g., 2 times or wider) interconnect wire. However, these solutions may increase power consumption and / or may be difficult for device layout (to route wider traces) in devices with fine pitch pixels. Furthermore, long wires may have high inductance and capacitance and thus increase time delays and reduce the bandwidth of the circuit (thereby increasing the rise / fall times of the signal) and thus also reduce the timing margin of the circuit.

[0076] In addition, in order to facilitate circuit design and manufacturing process development, the pixel array driver circuit may need to include some design for testability (DFT) circuits for debugging and testing. For example, in process debugging, it may be necessary to connect external electrical measuring instruments to the pixel array driver circuit in situ, and it may be necessary to measure the current-voltage (IV) characteristics of devices and components in the circuit to find the root cause of design or manufacturing defects. DFT circuits can also be used for mass production testing by electrically controlling and observing internal signals in digital logic, SRAM, analog devices and other circuit components.

[0077] Therefore, in a micro-LED display where each unit pixel has its own pixel drive circuit, it can be very difficult to achieve the desired bit depth (e.g., ≥6 bits), low drive current and brightness variation, high noise tolerance, low power consumption, high yield using traditional foundry processes, and the above-mentioned DFT functionality due to the limited real estate available for the pixel array drive circuits required to drive thousands or millions of micro-LEDs with small pitches.

[0078] According to certain examples, a macropixel architecture can be used to accommodate more bit cells and circuits with other functions in the same available area for a microLED array. The macropixel architecture can enable some circuits to be shared between pixels and reduce some transition areas, so that for each pixel in a pixel array with a small pitch (e.g., ≤2μm, such as about 1.8μm), a bit depth of 6 or more (e.g., 8 or 9) is possible, additional logic functions can be included, and the circuit can be made more robust and manufacturable (e.g., with standard SRAM cells, wider interconnects, and low analog circuit mismatch). In the macropixel architecture disclosed herein, some circuits (e.g., comparators) can be shared between multiple adjacent pixels (e.g., through time division multiplexing). In addition, bit cells (e.g., memories such as SRAM cells), digital logic, and high-voltage LED drive transistors can each be combined together in a continuous layout area to reduce the transition area that may otherwise be required, because according to design and process rules, adjoining different types of circuits will require transition areas and spacing. Clustering circuits of the same type in a continuous layout can minimize the "transition area" between different types of circuits and leave more space for other circuits or components.

[0079] According to an example disclosed herein, a macro pixel may include 8 or more pixels, for example, 12 pixels. The macro pixel may include a bit cell (e.g., an SRAM cell) organized in a continuous 2D array, the continuous 2D array including 12 words, each of which is 6 bits. The continuous 2D array of bit cells may include SRAM cells of standard wafer foundry, rather than custom-designed bit cells as in the unit pixel design, and may therefore be more reliably manufactured in a wafer foundry. The input and output (I / O) circuits for the continuous 2D array of bit cells may perform functions similar to those of the SRAM peripheral circuits in the SRAM array of standard wafer foundry. The macro pixel may also include other types of circuits (e.g., digital logic, analog circuits, high-voltage circuits, etc.), and these circuits may also be arranged in a continuous array based on the type of circuit, thereby reducing the transition area between different types of circuits and leaving more space for additional circuits and functions. In addition, the comparator logic that compares the pixel value from the SRAM with the counter value may be shared by 12 pixels through time division multiplexing to further reduce the silicon area used. The PWM latch circuit for each pixel can be set or cleared based on a comparator output, which can be generated based on the state of the PWM signal relative to the counter value. The output of the PWM latch circuit can control an analog circuit (e.g., a micro-LED driver or a current mirror) including a thick-oxide transistor to provide a constant current to the micro-LED for different durations to produce light of different intensities.

[0080] Due to the additional available space as a result of circuit sharing and reduced transition area, DFT circuits can be included in the pixel array driver circuits to gain observability of, for example, PWM latch states, current mirrors, and / or micro-LED IV characteristics, etc. The high area efficiency of macro pixels can also enable more design flexibility, such as using the standard bit cells and design rules described above, thereby increasing manufacturing portability and enabling flexibility in selecting manufacturing partners based on other technology or business capabilities.

[0081] In addition, with the macro-pixel architecture, the peripheral logic circuits that drive signals to sort the macro-pixels and feed data to the macro-pixels can be located both outside the pixel array and inside the pixel array. Repeaters or buffers can also be added in the pixel array to improve signal integrity. Peripheral logic circuits and repeaters in the pixel array can help solve some challenges associated with the unit pixel array architecture. For example, as described above, the signal broadcast on a large (e.g., millimeter-level) pixel array may suffer from large attenuation or time delay due to large wire resistance and capacitance, which may affect timing and noise tolerance and cause errors, reliability or other performance issues. These challenges can be at least partially solved in a macro-pixel architecture that makes room for repeaters in the pixel array. In the macro-pixel architecture, the macro-pixels can be arranged according to a hierarchy including multiple levels, wherein local peripheral circuits and / or repeaters can be included in different hierarchical levels. For example, macro-pixels can be grouped into sub-arrays, sub-arrays can be grouped into slices, and slices can form a 2D pixel array. Each slice, each sub-array and / or each macro-pixel can include some local peripheral circuits and / or repeaters to achieve effective and electrically robust movement of data in SRAM and PWM logic. Therefore, the signal level and timing (eg, rising / falling edges) of the signal from the peripheral circuit can be restored at the macro-pixel, thereby improving the timing and noise margin (eg, write time margin of the bit cell).

[0082] In addition, local peripheral circuits at various hierarchical levels may include power saving features to control the pixel array at various granularities (e.g., at a macropixel level, at a subarray level, or at a slice level). In an AR / VR display system, some displayed images may, for example, have a low fill factor only in the area where the user's eyes are focused, without significantly affecting the user experience. Therefore, based on the gaze direction of the user's eyes determined by eye tracking, only a portion of the display panel may need to have a high-quality image, and therefore only the PWM signal for that portion of the display panel may be calculated. Therefore, image data and PWM signals may not be required for areas outside the gaze area of ​​the user's eyes. In some embodiments, areas outside the gaze area of ​​the user's eyes may be turned off, or may be kept at a low illumination intensity (e.g., by gating the clock of the area outside the gaze area), thereby reducing the total power consumption of the display panel. In the macropixel architecture disclosed herein, clock gating may be performed at the slice, subarray, or macropixel level, so that pixels outside the area of ​​interest may be clock-gated for low-power, low-fill factor workloads, thereby reducing the power consumption of the display panel.

[0083] The macropixel architecture disclosed herein is also robust in a "rolling update" mode and is compatible with power-law transformations (e.g., gamma correction). Analog circuits (e.g., LED driver transistors) may also be upsized due to the additional space freed by the macropixel architecture. The upsized analog circuits may have reduced variations (e.g., variations in drive current of the LED driver transistor) due to, for example, averaging of random dopant variations over a larger area.

[0084] Therefore, the macro-pixel architecture disclosed in this article can accommodate more bit cells per pixel to improve display quality without incurring time jitter power overhead. The macro-pixel architecture can also reduce the variation of micro-LED drive current for more uniform brightness, improve the design tolerance of SRAM cells and other circuits that are prone to degrade signal levels and timing tolerances, combine new test and debugging capabilities, achieve fine-grained local clock gating for low-power, low-fill factor AR image displays, and avoid strict process design rules to improve foundry portability. Therefore, the macro-pixel architecture can have improved quality, power efficiency, and robustness. The macro-pixel architecture can achieve these benefits by reorganizing pixel and array functions to maximize the continuous layout of the same type of circuits and minimize hardware duplication.

[0085] The micro-LEDs described herein can be used in conjunction with a variety of technologies, such as artificial reality systems. Artificial reality systems, such as head-mounted displays (HMDs) or head-up display (HUD) systems, typically include displays configured to present artificial images depicting objects in a virtual environment. As in virtual reality (VR), augmented reality (AR), or mixed reality (MR) applications, the display can present virtual objects or combine images of real objects with virtual objects. For example, in an AR system, a user can view both a displayed image of a virtual object (e.g., a computer-generated image (CGI)) and the surrounding environment by, for example, viewing through transparent display glasses or lenses (commonly referred to as optical perspective) or viewing a displayed image of the surrounding environment captured by a camera (commonly referred to as video perspective). In some AR systems, an LED-based display subsystem can be used to present artificial images to the user.

[0086] As used herein, the term "light emitting diode (LED)" refers to a light source that includes at least an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting region (i.e., an active region) between the n-type semiconductor layer and the p-type semiconductor layer. The light emitting region may include one or more semiconductor layers forming one or more heterostructures (e.g., quantum wells). In some examples, the light emitting region may include multiple semiconductor layers forming one or more multi-quantum wells (MQWs), each multi-quantum well (MQW) including multiple (e.g., about 2 to 6) quantum wells.

[0087] As used herein, the term "micro-LED" or "μLED" refers to an LED having a chip wherein the linear dimension of the chip is less than about 200 μm, such as less than 100 μm, less than 50 μm, less than 20 μm, less than 10 μm, or less. For example, the linear dimension of a micro-LED may be as small as 6 μm, 5 μm, 4 μm, 2 μm, or less. Some micro-LEDs may have a linear dimension (e.g., length or diameter) comparable to a minority carrier diffusion length. However, the disclosure herein is not limited to micro-LEDs, but may also be applied to mini-LEDs and large LEDs.

[0088] As used herein, the term "bonding" may refer to various methods for physically connecting and / or electrically connecting two or more devices and / or wafers, such as adhesive bonding, metal-to-metal bonding, metal oxide bonding, wafer-to-wafer bonding, wafer-to-wafer bonding, hybrid bonding, welding, under-bump metallization, etc. For example, adhesive bonding can use a curable adhesive (e.g., epoxy resin) to physically bond two or more devices and / or wafers by bonding. Metal-to-metal bonding can include, for example, wire bonding or flip chip bonding using a welding interface (e.g., pad or ball), a conductive adhesive or a welding joint between metals. Metal oxide bonding can form metal and oxide patterns on each surface, bond the oxide portions together, and then bond the metal portions together to form a conductive path. Wafer-to-wafer bonding can bond two wafers (e.g., silicon wafers or other semiconductor wafers) without any intermediate layer and is based on chemical bonds between the surfaces of the two wafers. Wafer-to-wafer bonding may include wafer cleaning and other pre-processing, alignment and pre-bonding at room temperature, and annealing at elevated temperatures, such as about 250°C or higher. Wafer-to-wafer bonding may use bumps on one wafer to align features of a prefabricated chip with the drivers of the wafer. Hybrid bonding may include, for example, wafer cleaning, high-precision alignment of contacts of one wafer with contacts of another wafer, dielectric bonding of dielectric materials within the wafer at room temperature, and metal bonding of contacts annealed, for example, at 250°C-300°C or higher. As used herein, the term "bump" may broadly refer to metal interconnects used or formed during bonding.

[0089] In the following description, for the purpose of explanation, specific details are set forth in order to provide a thorough understanding of the examples of the present disclosure. However, it will be apparent that various examples can be implemented without these specific details. For example, equipment, systems, structures, assemblies, methods and other components can be shown as components in block diagram form to avoid blurring the examples in unnecessary details. In other cases, well-known equipment, processes, systems, structures and techniques can be shown without the necessary details to avoid blurring the examples. The accompanying drawings and descriptions are not intended to be restrictive. The terms and expressions used in the present disclosure are used as descriptive terms rather than restrictive terms, and when using such terms and expressions, it is not intended to exclude any equivalents of the features shown and described or parts thereof. The word "example" is used herein to mean "used as an example, instance or illustration". Any embodiment or design described herein as an "example" is not necessarily interpreted as being more preferred or more advantageous than other embodiments or designs.

[0090] Figure 1is a simplified block diagram of an example of an artificial reality system environment 100 including a near-eye display 120 according to certain examples. Figure 1 The illustrated artificial reality system environment 100 may include a near-eye display 120, an optional external imaging device 150, and an optional input / output interface 140, each of which may be coupled to an optional console 110. Figure 1 An example of an artificial reality system environment 100 including one near-eye display 120, one external imaging device 150, and one input / output interface 140 is shown, but any number of these components may be included in the artificial reality system environment 100, or any of these components may be omitted. For example, there may be multiple near-eye displays 120 that are monitored by one or more external imaging devices 150 that communicate with the console 110. In some configurations, the artificial reality system environment 100 may not include the external imaging device 150, the optional input / output interface 140, and the optional console 110. In alternative configurations, different or additional components may be included in the artificial reality system environment 100.

[0091] The near-eye display 120 may be a head-mounted display that presents content to a user. Examples of content presented by the near-eye display 120 include one or more of the following: images, video, audio, or any combination thereof. In some examples, the audio may be presented via an external device (e.g., a speaker and / or headphones) that receives audio information from the near-eye display 120, the console 110, or both the near-eye display 120 and the console 110 and presents audio data based on the audio information. The near-eye display 120 may include one or more rigid bodies that may be rigidly or non-rigidly coupled to each other. Rigid couplings between rigid bodies may cause the coupled rigid bodies to act as a single rigid entity. Non-rigid couplings between rigid bodies may allow the rigid bodies to move relative to each other. In various examples, the near-eye display 120 may be implemented in any suitable form factor, including a pair of glasses. Referring below to Figure 2 and Figure 3 Some examples of near-eye displays 120 are further described. Additionally, in various examples, the functionality described herein can be used in a head-mounted device that combines an image of an environment external to the near-eye display 120 with artificial reality content (e.g., computer-generated images). Thus, the near-eye display 120 can augment the image of the physical, real-world environment external to the near-eye display 120 with generated content (e.g., images, videos, sounds, etc.) to present an augmented reality to the user.

[0092] In various examples, the near eye display 120 may include one or more of display electronics 122, display optics 124, and an eye tracking unit 130. In some examples, the near eye display 120 may also include one or more positioners 126, one or more position sensors 128, and an inertial measurement unit (IMU) 132. In various examples, the near eye display 120 may omit any of the eye tracking unit 130, the positioners 126, the position sensors 128, and the IMU 132, or include additional elements. Additionally, in some examples, the near eye display 120 may include a combination of the eye tracking unit 130 and the position sensors 128. Figure 1 The functions of the various components are described in detail.

[0093] The display electronics 122 may display an image or facilitate the display of an image to a user based on data received from, for example, the console 110. In various examples, the display electronics 122 may include one or more display panels, such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display, an inorganic light emitting diode (ILED) display, a micro light emitting diode (μLED) display, an active matrix OLED display (AMOLED), a transparent OLED display (TOLED), or some other display. For example, in one embodiment of the near-eye display 120, the display electronics 122 may include a front TOLED panel, a rear display panel, and optical components (e.g., an attenuator, a polarizer, or a diffractive or spectral film) between the front display panel and the rear display panel. The display electronics 122 may include pixels that emit light of a predominant color, such as red, green, blue, white, or yellow. In some embodiments, the display electronics 122 may display a three-dimensional (3D) image through a stereoscopic effect produced by a two-dimensional panel to create a subjective perception of image depth. For example, the display electronics 122 may include a left display and a right display located in front of the left eye and the right eye of the user, respectively. The left and right displays may present copies of an image that are horizontally offset relative to each other to create a stereoscopic effect (ie, the perception of depth in the image by a user viewing the image).

[0094] In some examples, the display optics 124 can optically display image content (e.g., using optical waveguides and couplers), or amplify image light received from the display electronics 122, correct optical errors associated with the image light, and present the corrected image light to a user of the near-eye display 120. In various examples, the display optics 124 can include one or more optical elements, such as, for example, a substrate, an optical waveguide, an aperture, a Fresnel lens, a convex lens, a concave lens, an optical filter, an input / output coupler, or any other suitable optical element that can affect the image light emitted from the display electronics 122. The display optics 124 can include a combination of different optical elements and mechanical couplings to maintain the relative spacing and orientation of the optical elements in the combination. One or more of the optical elements in the display optics 124 can have an optical coating, such as an anti-reflective coating, a reflective coating, a filter coating, or a combination of different optical coatings.

[0095] The amplification of the image light by the display optics 124 can allow the display electronics 122 to be physically smaller, lighter, and consume less power than a larger display. Additionally, the amplification can increase the field of view of the displayed content. The amplification of the image light by the display optics 124 can be changed by adjusting optical elements, adding optical elements, or removing optical elements from the display optics 124. In some examples, the display optics 124 can project the displayed image to one or more image planes that can be farther away from the user's eyes than the near eye display 120.

[0096] The display optics 124 may also be designed to correct one or more types of optical errors, such as two-dimensional optical errors, three-dimensional optical errors, or any combination thereof. Two-dimensional errors may include optical aberrations that occur in two dimensions. Example types of two-dimensional errors may include barrel distortion, pincushion distortion, longitudinal chromatic aberration, and lateral chromatic aberration. Three-dimensional errors may include optical errors that occur in three dimensions. Example types of three-dimensional errors may include spherical aberration, comatic aberration, field curvature, and astigmatism.

[0097] The locators 126 may be objects located at specific locations on the near eye display 120 relative to each other and relative to reference points on the near eye display 120. In some embodiments, the console 110 may identify the locators 126 in an image captured by the external imaging device 150 to determine the position, orientation, or both of the artificial reality head mounted device. The locators 126 may be LEDs, corner cube reflectors, reflective markers, a light source that contrasts with the environment in which the near eye display 120 operates, or any combination thereof. In examples where the locators 126 are active components (e.g., LEDs or other types of light emitting devices), the locators 126 may emit light in the visible light band (e.g., about 380 nm to 750 nm), light in the infrared (IR) band (e.g., about 750 nm to 1 mm), light in the ultraviolet band (e.g., about 10 nm to about 380 nm), light in another portion of the electromagnetic spectrum, or light in any combination of portions of the electromagnetic spectrum.

[0098] The external imaging device 150 may include one or more cameras, one or more video cameras, any other device capable of capturing an image including one or more locators 126, or any combination thereof. Additionally, the external imaging device 150 may include one or more filters (e.g., to improve the signal-to-noise ratio). The external imaging device 150 may be configured to detect light emitted or reflected from the locators 126 in the field of view of the external imaging device 150. In examples where the locators 126 include passive elements (e.g., retroreflectors), the external imaging device 150 may include a light source that illuminates some or all of the locators 126, which may reflect light back into the external imaging device 150. Slow calibration data may be transmitted from the external imaging device 150 to the console 110, and the external imaging device 150 may receive one or more calibration parameters from the console 110 for adjusting one or more imaging parameters (e.g., focal length, focus, frame rate, sensor temperature, shutter speed, aperture, etc.).

[0099] Position sensor 128 may generate one or more measurement signals in response to movement of near-eye display 120. Examples of position sensor 128 may include accelerometers, gyroscopes, magnetometers, other motion detection or error correction sensors, or any combination thereof. For example, position sensor 128 may include multiple accelerometers that measure translational motion (e.g., forward / backward, up / down, or left / right) and multiple gyroscopes that measure rotational motion (e.g., pitch, yaw, or roll). In some examples, the individual position sensors may be oriented orthogonally to each other.

[0100] The IMU 132 may be an electronic device that generates fast calibration data based on measurement signals received from one or more position sensors 128. The position sensors 128 may be located outside the IMU 132, inside the IMU 132, or any combination thereof. Based on one or more measurement signals from the one or more position sensors 128, the IMU 132 may generate fast calibration data that indicates an estimated position of the near eye display 120 relative to an initial position of the near eye display 120. For example, the IMU 132 may integrate the measurement signals received from the accelerometer over time to estimate a velocity vector, and integrate the velocity vector over time to determine an estimated position of a reference point on the near eye display 120. Alternatively, the IMU 132 may provide the sampled measurement signals to the console 110, which may determine the fast calibration data. Although the reference point may generally be defined as a point in space, in various examples, the reference point may also be defined as a point within the near eye display 120 (e.g., the center of the IMU 132).

[0101] The eye tracking unit 130 may include one or more eye tracking systems. Eye tracking may refer to determining the position of an eye relative to the near-eye display 120, including the orientation and position of the eye. The eye tracking system may include an imaging system that images one or more eyes, and may optionally include a light emitter that may generate light directed toward the eye so that light reflected by the eye can be captured by the imaging system. For example, the eye tracking unit 130 may include an incoherent light source or a coherent light source (e.g., a laser diode) that emits light in the visible spectrum or infrared spectrum, and a camera that captures light reflected by the user's eye. As another example, the eye tracking unit 130 may capture reflected radio waves emitted by a miniature radar unit. The eye tracking unit 130 may use a low-power light emitter that emits light at a frequency and intensity that does not harm the eye or cause physical discomfort. The eye tracking unit 130 may be arranged to increase the contrast in the eye image captured by the eye tracking unit 130 while reducing the total power consumed by the eye tracking unit 130 (e.g., reducing the power consumed by the light emitter and imaging system included in the eye tracking unit 130). For example, in some implementations, eye tracking unit 130 may consume less than 100 milliwatts of power.

[0102] For example, the near-eye display 120 can use the orientation of the eyes to perform the following operations: determine the user's interpupillary distance (IPD), determine the gaze direction, introduce depth cues (e.g., blur images outside the user's primary line of sight), collect heuristics about user interactions in VR media (e.g., based on the time spent on any particular subject, object, or frame based on the stimulus experienced), some other function based at least in part on the orientation of at least one user's eye, or any combination thereof. Because the orientation of the user's eyes can be determined, the eye tracking unit 130 can determine where the user is looking. For example, determining the direction of the user's gaze can include determining a point of convergence based on the determined orientation of the user's left and right eyes. The convergence point can be the point where the two foveal axes of the user's eyes intersect. The direction of the user's gaze can be the direction of a line passing through the convergence point and the midpoint between the pupils of the user's eyes.

[0103] The input / output interface 140 may be a device that allows a user to send an action request to the console 110. The action request may be a request to perform a specific action. For example, the action request may be to start or end an application, or to perform a specific action within an application. The input / output interface 140 may include one or more input devices. Example input devices may include a keyboard, a mouse, a game controller, a glove, a button, a touch screen, or any other suitable device for receiving an action request and transmitting the received action request to the console 110. The action request received by the input / output interface 140 may be transmitted to the console 110, and the console 110 may perform an action corresponding to the requested action. In some examples, the input / output interface 140 may provide tactile feedback to the user according to the instructions received from the console 110. For example, when an action request is received, or when the console 110 has performed the requested action and transmitted the instruction to the input / output interface 140, the input / output interface 140 may provide tactile feedback. In some examples, the external imaging device 150 may be used to track the input / output interface 140, such as tracking the position or location of a controller (which may include, for example, an IR light source) or a user's hand to determine the user's movement. In some examples, near-eye display 120 may include one or more imaging devices to track input / output interface 140 , such as tracking the position or location of a controller or a user's hand to determine the user's movements.

[0104] The console 110 may provide content to the near-eye display 120 for presentation to the user based on information received from one or more of the external imaging device 150, the near-eye display 120, and the input / output interface 140. Figure 1In the example shown, the console 110 may include an application store 112, a head mounted device tracking module 114, an artificial reality engine 116, and an eye tracking module 118. Some examples of the console 110 may include a combination of Figure 1 The functionality described further below may be allocated among the components of console 110 in a manner different from that described here.

[0105] In some examples, console 110 may include a processor and a non-transitory computer-readable storage medium storing instructions executable by the processor. The processor may include multiple processing units that execute instructions in parallel. The non-transitory computer-readable storage medium may be any memory, such as a hard drive, a removable memory, or a solid-state drive (e.g., flash memory or dynamic random access memory (DRAM)). In various examples, in combination with Figure 1 The described modules of the console 110 may be encoded as instructions in a non-transitory computer-readable storage medium that, when executed by a processor, cause the processor to perform the functions described further below.

[0106] The application storage 112 may store one or more applications for execution by the console 110. An application may include a set of instructions that, when executed by a processor, generates content for presentation to a user. The content generated by the application may respond to input received from the user via movement of the user's eyes or from input / output interface 140. Examples of applications may include: gaming applications, conferencing applications, video playback applications, or other suitable applications.

[0107] The head mounted device tracking module 114 may use the slow calibration information from the external imaging device 150 to track the movement of the near eye display 120. For example, the head mounted device tracking module 114 may use the observed localizers from the slow calibration information and the model of the near eye display 120 to determine the position of the reference point of the near eye display 120. The head mounted device tracking module 114 may also use the position information from the fast calibration information to determine the position of the reference point of the near eye display 120. Additionally, in some examples, the head mounted device tracking module 114 may use the fast calibration information, portions of the slow calibration information, or any combination thereof to predict a future position of the near eye display 120. The head mounted device tracking module 114 may provide the estimated or predicted future position of the near eye display 120 to the artificial reality engine 116.

[0108] The artificial reality engine 116 can execute an application within the artificial reality system environment 100 and receive position information of the near-eye display 120, acceleration information of the near-eye display 120, velocity information of the near-eye display 120, predicted future position of the near-eye display 120, or any combination thereof from the head mounted device tracking module 114. The artificial reality engine 116 can also receive estimated eye position and orientation information from the eye tracking module 118. Based on the received information, the artificial reality engine 116 can determine the content to be provided to the near-eye display 120 for presentation to the user. For example, if the received information indicates that the user has looked to the left, the artificial reality engine 116 can generate content for the near-eye display 120 that reflects (mirror) the movement of the user's eyes in the virtual environment. Additionally, the artificial reality engine 116 can perform an action within an application executed on the console 110 in response to an action request received from the input / output interface 140, and provide feedback to the user indicating that the action has been performed. The feedback can be visual or auditory feedback via the near-eye display 120, or tactile feedback via the input / output interface 140.

[0109] The eye tracking module 118 may receive eye tracking data from the eye tracking unit 130 and determine the position of the user's eyes based on the eye tracking data. The position of the eyes may include the orientation, position, or both of the eyes relative to the near-eye display 120 or any element thereof. Because the rotational axis of the eye changes depending on the position of the eye in the socket, determining the position of the eye in the socket may allow the eye tracking module 118 to more accurately determine the orientation of the eyes.

[0110] Figure 2 2 is a perspective view of an example of a near-eye display in the form of an HMD device 200 for implementing some of the examples disclosed herein. The HMD device 200 may be, for example, part of a VR system, an AR system, an MR system, or any combination thereof. The HMD device 200 may include a body 220 and a headband 230. Figure 2 The bottom side 223, front side 225, and left side 227 of the body 220 are shown in perspective. The headband 230 can have an adjustable or extendable length. There can be enough space between the body 220 of the HMD device 200 and the headband 230 to allow the user to mount the HMD device 200 on the user's head. In various examples, the HMD device 200 can include additional, fewer, or different components. For example, the HMD device 200 can include, for example, the following Figure 3 Eyeglass temples and temple tips are shown, rather than headband 230 .

[0111] The HMD device 200 can present media including virtual and / or augmented views of a physical, real-world environment with computer-generated elements to a user. Examples of media presented by the HMD device 200 can include images (e.g., two-dimensional (2D) or three-dimensional (3D) images), video (e.g., 2D or 3D video), audio, or any combination thereof. The images and videos can be displayed via one or more display components (e.g., a display unit 220) enclosed in the body 220 of the HMD device 200. Figure 2 The HMD device 200 may include two eye box regions.

[0112] In some embodiments, the HMD device 200 may include various sensors (not shown), such as depth sensors, motion sensors, position sensors, and eye tracking sensors. Some of these sensors may sense using structured light patterns. In some embodiments, the HMD device 200 may include an input / output interface for communicating with a console. In some embodiments, the HMD device 200 may include a virtual reality engine (not shown) that may execute applications within the HMD device 200 and receive depth information, position information, acceleration information, velocity information, predicted future positions, or any combination thereof of the HMD device 200 from various sensors. In some embodiments, the information received by the virtual reality engine may be used to generate signals (e.g., display instructions) to one or more display components. In some embodiments, the HMD device 200 may include a locator (not shown, such as the locator 126) that is located at a fixed position on the body 220 relative to each other and relative to a reference point. Each locator may emit light that may be detected by an external imaging device.

[0113] Figure 3 is a perspective view of an example of a near-eye display 300 in the form of a pair of glasses for implementing some examples disclosed herein. The near-eye display 300 may be Figure 1 Specific embodiments of near-eye display 120 can be configured for use as a virtual reality display, an augmented reality display, and / or a mixed reality display. Near-eye display 300 can include frame 305 and display 310. Display 310 can be configured to present content to a user. In some examples, display 310 can include display electronics and / or display optics. For example, as described above with reference to Figure 1As described above with respect to the near-eye display 120 , the display 310 may include an LCD display panel, an LED display panel, or an optical display panel (eg, a waveguide display component).

[0114] The near-eye display 300 may also include various sensors 350a, 350b, 350c, 350d, and 350e on or within the frame 305. In some examples, the sensors 350a-350e may include one or more depth sensors, motion sensors, position sensors, inertial sensors, or ambient light sensors. In some examples, the sensors 350a-350e may include one or more image sensors configured to generate image data representing different fields of view in different directions. In some examples, the sensors 350a-350e may be used as input devices to control or affect the display content of the near-eye display 300, and / or to provide an interactive VR / AR / MR experience to the user of the near-eye display 300. In some examples, the sensors 350a-350e may also be used for stereoscopic imaging.

[0115] In some examples, the near-eye display 300 may also include one or more illuminators 330 to project light into the physical environment. The projected light may be associated with different frequency bands (e.g., visible light, infrared light, ultraviolet light, etc.) and may serve various purposes. For example, the illuminator 330 may project light in a dark environment (or in an environment with low-intensity infrared light, ultraviolet light, etc.) to help the sensors 350a-350e capture images of different objects in the dark environment. In some examples, the illuminator 330 may be used to project a specific light pattern onto an object in the environment. In some examples, the illuminator 330 may be used as a locator, such as in the above reference Figure 1 The locator 126 is described.

[0116] In some examples, the near-eye display 300 may also include a high-resolution camera 340. The camera 340 may capture images of the physical environment in the field of view. The captured images may be generated, for example, by a virtual reality engine (e.g., Figure 1 The captured image may be processed by an artificial reality engine 116) to add virtual objects to the captured image or modify physical objects in the captured image, and the processed image may be displayed to the user by a display 310 for AR or MR applications.

[0117] Figure 4An example of an optical see-through augmented reality system 400 including a waveguide display according to certain examples is shown. The augmented reality system 400 may include a projector 410 and a combiner 415. The projector 410 may include a light source or image source 412 and a projector optical device 414. In some examples, the light source or image source 412 may include one or more of the above-mentioned micro-LED devices. In some examples, the image source 412 may include a plurality of pixels displaying a virtual object, such as an LCD display panel or an LED display panel. In some examples, the image source 412 may include a light source that generates coherent light or partially coherent light. For example, the image source 412 may include a laser diode, a vertical cavity surface emitting laser, an LED, and / or the above-mentioned micro-LED. In some examples, the image source 412 may include a plurality of light sources (e.g., an array of the above-mentioned micro-LEDs), each of which emits a monochromatic image light corresponding to a primary color (e.g., red, green, or blue). In some examples, the image source 412 may include three two-dimensional arrays of micro-LEDs, each of which may include micro-LEDs configured to emit primary color (e.g., red, green, or blue) light. In some examples, the image source 412 may include an optical pattern generator, such as a spatial light modulator. The projector optics 414 may include one or more optical components that may adjust the light from the image source 412, such as expanding, collimating, scanning, or projecting the light from the image source 412 to the combiner 415. For example, the one or more optical components may include one or more lenses, liquid lenses, mirrors, apertures, and / or gratings. For example, the image source 412 may include one or more one-dimensional arrays or elongated two-dimensional arrays of micro-LEDs, and the projector optics 414 may include one or more one-dimensional scanners (e.g., micro-mirrors or prisms) configured to scan the one-dimensional array or elongated two-dimensional array of micro-LEDs to generate an image frame. In some examples, projector optics 414 may include a liquid lens (eg, a liquid crystal lens) having multiple electrodes that allows light from image source 412 to be scanned.

[0118] The combiner 415 may include an input coupler 430 for coupling light from the projector 410 into the substrate 420 of the combiner 415. The combiner 415 may transmit at least 50% of the light in a first wavelength range and reflect at least 25% of the light in a second wavelength range. For example, the first wavelength range may be visible light from about 400 nm to about 650 nm, and the second wavelength range may be in the infrared band, for example, from about 800 nm to about 1000 nm. The input coupler 430 may include a volume holographic grating, a diffractive optical element (DOE) (e.g., a surface relief grating), an inclined surface of the substrate 420, or a refractive coupler (e.g., a wedge or a prism). For example, the input coupler 430 may include a reflective volume Bragg grating or a transmissive volume Bragg grating. The input coupler 430 may have a coupling efficiency greater than 30%, 50%, 75%, 90% or more for visible light. The light coupled into the substrate 420 may propagate within the substrate 420 by, for example, total internal reflection (TIR). Substrate 420 can be in the form of a lens of a pair of glasses. Substrate 420 can have a flat surface or a curved surface and can include one or more types of dielectric materials, such as glass, quartz, plastic, polymer, poly(methyl methacrylate) (PMMA), crystal, or ceramic. The thickness of the substrate can range, for example, from less than about 1 mm to about 10 mm or more. Substrate 420 can be transparent to visible light.

[0119] The substrate 420 may include or may be coupled to a plurality of output couplers 440, each of which is configured to extract at least a portion of the light guided by and propagating within the substrate 420 from the substrate 420, and to guide the extracted light 460 to a viewing window 495, where an eye 490 of a user of the augmented reality system 400 may be located when the augmented reality system 400 is used. The plurality of output couplers 440 may replicate an exit pupil to increase the size of the viewing window 495 so that the displayed image is visible in a larger area. As with the input coupler 430, the output coupler 440 may include a grating coupler (e.g., a volume holographic grating or a surface relief grating), other diffractive optical elements (DOEs), prisms, and the like. For example, the output coupler 440 may include a reflective volume Bragg grating or a transmissive volume Bragg grating. The output coupler 440 may have different coupling (e.g., diffraction) efficiencies at different locations. The substrate 420 may also allow light 450 from the environment in front of the combiner 415 to pass through with little or no loss. The output coupler 440 may also allow light 450 to pass through with little loss. For example, in some embodiments, the output coupler 440 may have a very low diffraction efficiency for the light 450, so that the light 450 may be refracted or otherwise pass through the output coupler 440 with little loss, and thus may have a higher intensity than the extracted light 460. In some embodiments, the output coupler 440 may have a high diffraction efficiency for the light 450, and may diffract the light 450 in certain desired directions (i.e., diffraction angles) with little loss. As a result, the user may view a combined image of the environment in front of the combiner 415 and the image of the virtual object projected by the projector 410.

[0120] Figure 5AAn example of a near-eye display (NED) device 500 including a waveguide display 530 according to certain examples is shown. The NED device 500 may be an example of a near-eye display 120, an augmented reality system 400, or another type of display device. The NED device 500 may include a light source 510, a projection optical device 520, and a waveguide display 530. The light source 510 may include a plurality of light emitter panels for different colors, such as a red light emitter 512 panel, a green light emitter 514 panel, and a blue light emitter 516 panel. The red light emitters 512 are organized into an array; the green light emitters 514 are organized into an array; and the blue light emitters 516 are organized into an array. The size and spacing of the light emitters in the light source 510 may be small. For example, each light emitter may have a diameter of less than 2 μm (e.g., about 1.2 μm) and the spacing may be less than 2 μm (e.g., about 1.5 μm). Thus, the number of light emitters in each of the red light emitters 512, the green light emitters 514, and the blue light emitters 516 may be equal to or greater than the number of pixels in a display image, such as 960×720, 1280×720, 1440×1080, 1920×1080, 2160×1080, or 2560×1080 pixels. Thus, a display image may be generated simultaneously by the light source 510. A scanning element may not be used in the NED device 500.

[0121] Before reaching the waveguide display 530, the light emitted by the light source 510 can be conditioned by the projection optical device 520, which can include a lens array. The projection optical device 520 can collimate or focus the light emitted by the light source 510 to the waveguide display 530, and the waveguide display 530 can include a coupler 532 for coupling the light emitted by the light source 510 into the waveguide display 530. The light coupled into the waveguide display 530 can be, for example, Figure 4 The total internal reflection propagates within the waveguide display 530. The coupler 532 may also couple a portion of the light propagating within the waveguide display 530 out of the waveguide display 530 and toward the eye 590 of the user.

[0122] Figure 5BAn example of a near-eye display (NED) device 550 including a waveguide display 580 according to certain examples is shown. In some examples, the NED device 550 can use a scanning mirror 570 to project light from a light source 540 to an image field where a user's eye 590 may be located. The NED device 550 can be an example of a near-eye display 120, an augmented reality system 400, or another type of display device. The light source 540 can include one or more rows or one or more columns of light emitters of different colors, such as multiple rows of red light emitters 542, multiple rows of green light emitters 544, and multiple rows of blue light emitters 546. For example, the red light emitters 542, the green light emitters 544, and the blue light emitters 546 can each include N rows, each row including, for example, 2560 light emitters (pixels). The red light emitters 542 are organized into an array; the green light emitters 544 are organized into an array; and the blue light emitters 546 are organized into an array. In some examples, the light source 540 can include a single row of light emitters for each color. In some examples, light source 540 may include multiple columns of light emitters for each of the colors red, green, and blue, where each column may include, for example, 1080 light emitters. In some examples, the size and / or spacing of the light emitters in light source 540 may be relatively large (e.g., approximately 3 μm-5 μm), and thus light source 540 may not include enough light emitters to simultaneously generate a complete display image. For example, the number of light emitters of a single color may be less than the number of pixels in the display image (e.g., 2560×1080 pixels). The light emitted by light source 540 may be a set of collimated or divergent light beams.

[0123] Before reaching the scanning mirror 570, the light emitted by the light source 540 can be conditioned by various optical devices, such as a collimating lens or a freeform optical element 560. The freeform optical element 560 may include, for example, a multi-facet prism or another light folding element, which can direct the light emitted by the light source 540 to the scanning mirror 570, such as changing the propagation direction of the light emitted by the light source 540, for example, by about 90° or more. In some examples, the freeform optical element 560 may be rotatable to scan the light. The scanning mirror 570 and / or the freeform optical element 560 can reflect and project the light emitted by the light source 540 to the waveguide display 580, which may include a coupler 582 for coupling the light emitted by the light source 540 into the waveguide display 580. The light coupled into the waveguide display 580 can be, for example, Figure 4The total internal reflection propagates within the waveguide display 580. The coupler 582 may also couple a portion of the light propagating within the waveguide display 580 out of the waveguide display 580 and toward the eye 590 of the user.

[0124] The scanning mirror 570 may include a micro-electromechanical system (MEMS) mirror or any other suitable mirror. The scanning mirror 570 may rotate to scan in one dimension or two dimensions. As the scanning mirror 570 rotates, the light emitted by the light source 540 may be directed to different areas of the waveguide display 580, so that in each scanning cycle, a complete display image may be projected onto the waveguide display 580 and directed by the waveguide display 580 to the user's eye 590. For example, in the case where the light source 540 includes light emitters for all pixels in one or more rows or one or more columns, the scanning mirror 570 may rotate in the column or row direction (e.g., x or y direction) to scan the image. In the example where the light source 540 includes light emitters for some pixels but not all pixels in one or more rows or one or more columns, the scanning mirror 570 may rotate in both the row and column directions (e.g., x and y directions) to project the display image (e.g., using a raster-type scanning pattern).

[0125] The NED device 550 can operate in a predefined display cycle. A display cycle (e.g., a display cycle) can refer to the duration in which a complete image is scanned or projected. For example, a display cycle can be the inverse of a desired frame rate. In a NED device 550 that includes a scanning mirror 570, a display cycle can also be referred to as a scanning cycle or a scanning cycle. The light generated by the light source 540 can be synchronized with the rotation of the scanning mirror 570. For example, each scanning cycle can include multiple scanning steps, wherein the light source 540 can generate a different light pattern in each corresponding scanning step.

[0126] In each scanning cycle, as the scanning mirror 570 rotates, a display image can be projected onto the waveguide display 580 and the user's eye 590. The actual color value and light intensity (e.g., brightness) of a given pixel position of the display image can be the average of the light beams of three colors (e.g., red, green, and blue) that illuminate the pixel position during the scanning cycle. After completing a scanning cycle, the scanning mirror 570 can return to the initial position to project light for the first few rows of the next display image, or can rotate in the opposite direction or scan the pattern to project light for the next display image, where a new set of drive signals can be fed to the light source 540. The same process can be repeated as the scanning mirror 570 rotates in each scanning cycle. Therefore, different images can be projected to the user's eye 590 in different scanning cycles.

[0127] Figure 6 An example of an image source component 610 in a near-eye display system 600 according to some examples is shown. For example, the image source component 610 may include: a display panel 640, which may generate a display image to be projected to the user's eyes; and a projector 650, which may project the display image generated by the display panel 640 to the user's eyes as described above. Figure 4-5B The display panel 640 may include a light source 642 and a driver circuit 644 for the light source 642. For example, the light source 642 may include the light source 510 or 540. For example, the projector 650 may include the free-form optical element 560, the scanning mirror 570, and / or the projection optical device 520 described above. The near-eye display system 600 may also include a controller 620 that synchronously controls the light source 642 and the projector 650 (e.g., the scanning mirror 570). The image source component 610 may generate image light and output the image light to the waveguide display ( Figure 6 5 (not shown), such as waveguide display 530 or 580. As described above, the waveguide display can receive image light at one or more input coupling elements and direct the received image light to one or more output coupling elements. The input coupling elements and the output coupling elements can include, for example, diffraction gratings, holographic gratings, prisms, or any combination thereof. The input coupling elements can be selected to cause total internal reflection in the waveguide display. The output coupling elements can couple part of the totally internally reflected image light out of the waveguide display.

[0128] As described above, the light source 642 may include a plurality of light emitters arranged in an array or matrix. Each light emitter may emit monochromatic light, such as red light, blue light, green light, infrared light, etc. Although RGB colors are often discussed in the present disclosure, the examples described herein are not limited to using red, green, and blue as primary colors. Other colors may also be used as primary colors of the near-eye display system 600. In some examples, the display panel may use more than three primary colors. Each pixel in the light source 642 may include three sub-pixels, including a red micro-LED, a green micro-LED, and a blue micro-LED. Semiconductor LEDs typically include an active light-emitting layer within a multilayer semiconductor material. The multilayer semiconductor material may include different composite materials or the same base material with different dopants and / or different doping densities. For example, the multilayer semiconductor material may include an n-type material layer, an active region that may include a heterostructure (e.g., one or more quantum wells), and a p-type material layer. The multilayer semiconductor material may be grown on a surface of a substrate having a specific orientation. In some examples, in order to improve light extraction efficiency, a mesa including at least some semiconductor material layers may be formed.

[0129] Controller 620 can control image rendering operations of image source component 610, such as operation of light source 642 and / or projector 650. For example, controller 620 can determine instructions for image source component 610 to render one or more display images. The instructions can include display instructions and scanning instructions. In some examples, the display instructions can include an image file (e.g., a bitmap file). For example, the display instructions can be sent from a console (e.g., as described above). Figure 1 The controller 620 may include a combination of hardware, software, and / or firmware not shown here to avoid obscuring other aspects of the present disclosure.

[0130] In some examples, controller 620 may be a graphics processing unit (GPU) of a display device. In other examples, controller 620 may be another type of processor. Operations performed by controller 620 may include acquiring content for display and dividing the content into discrete portions. Controller 620 may provide scanning instructions to light source 642, the scanning instructions including addresses corresponding to individual source elements of light source 642 and / or electrical biases applied to the individual source elements. Controller 620 may instruct light source 642 to sequentially present discrete portions using light emitters corresponding to one or more rows of pixels in an image ultimately displayed to a user. Controller 620 may also instruct projector 650 to perform different adjustments to the light. For example, controller 620 may control projector 650 to scan discrete portions to the image as described above with reference to FIG. Figure 5B The present invention relates to a waveguide display (e.g., waveguide display 580) that is coupled to different regions of the element. Therefore, each discrete portion is presented at a different corresponding position at the exit pupil of the waveguide display. Although each discrete portion is presented at a different corresponding time, the presentation and scanning of the discrete portions occurs quickly enough so that the user's eyes can integrate the different portions into a single image or a series of images.

[0131] Image processor 630 may be a general purpose processor and / or one or more dedicated circuits dedicated to performing the features described herein. In one example, a general purpose processor may be coupled to a memory to execute software instructions that cause the processor to perform specific processes described herein. In another example, image processor 630 may be one or more circuits dedicated to performing specific features. Although Figure 6The image processor 630 in FIG. 6 is shown as a separate unit from the controller 620 and the driver circuit 644, but in other examples, the image processor 630 may be a subunit of the controller 620 or the driver circuit 644. In other words, in these examples, the controller 620 or the driver circuit 644 may perform various image processing functions of the image processor 630. The image processor 630 may also be referred to as an image processing circuit.

[0132] exist Figure 6 In the example shown, the light source 642 can be driven by a driver circuit 644 based on data or instructions (e.g., display and scanning instructions) sent from the controller 620 or the image processor 630. In one example, the driver circuit 644 may include a circuit board connected to each light emitter of the light source 642 and mechanically holding each light emitter of the light source 642. The light source 642 may emit light according to one or more illumination parameters set by the controller 620 and potentially adjusted by the image processor 630 and the driver circuit 644. The light source 642 may generate light using the illumination parameters. For example, the illumination parameters may include source wavelength, pulse rate, pulse amplitude, beam type (continuous or pulsed), one or more other parameters that may affect the emitted light, or any combination thereof. In some examples, the source light generated by the light source 642 may include multiple beams of red light, green light, and blue light, or any combination thereof.

[0133] Projector 650 may perform a set of optical functions, such as focusing, combining, adjusting, or scanning image light generated by light source 642. In some examples, projector 650 may include a combining assembly, a light adjustment assembly, or a scanning mirror assembly. Projector 650 may include one or more optical components that optically adjust and potentially redirect light from light source 642. An example of adjusting light may include adjusting light, such as expanding, collimating, correcting one or more optical errors (e.g., field curvature, chromatic aberration, etc.), some other adjustment of light, or any combination thereof. For example, the optical components of projector 650 may include lenses, mirrors, apertures, gratings, or any combination thereof.

[0134] The projector 650 can redirect the image light via one or more reflective and / or refractive parts thereof so that the image light is projected toward the waveguide display in a specific orientation. The position at which the image light is redirected toward the waveguide display may depend on the specific orientation of the one or more reflective and / or refractive parts. In some examples, the projector 650 includes a single scanning mirror that scans in at least two dimensions. In other examples, the projector 650 may include multiple scanning mirrors, each scanning mirror scanning in directions orthogonal to each other. The projector 650 may perform (horizontal or vertical) raster scanning, double resonance scanning, or any combination thereof. In some examples, the projector 650 may perform controlled vibrations in the horizontal and / or vertical directions at a specific oscillation frequency to scan in two dimensions and generate a two-dimensional projection image of the media presented to the user's eyes. In other examples, the projector 650 may include a lens or prism that can be used for similar or identical functions to one or more scanning mirrors. In some examples, the image source component 610 may not include a projector, wherein the light emitted by the light source 642 may be directly incident on the waveguide display.

[0135] In semiconductor LEDs, photons are typically generated by recombination of electrons and holes within the active region (e.g., one or more semiconductor layers) with a certain internal quantum efficiency, where the internal quantum efficiency is the proportion of radiative electron-hole recombination in the active region that emits a photon. The generated light can then be extracted from the LED in a specific direction or within a specific solid angle. The ratio of the number of emitted photons extracted from the LED to the number of electrons that pass through the LED is called the external quantum efficiency, which describes the efficiency of the LED in converting injected electrons into photons extracted from the device.

[0136] The external quantum efficiency can be proportional to the injection efficiency, internal quantum efficiency, and extraction efficiency. The injection efficiency refers to the proportion of electrons that are injected through the device into the active region. The extraction efficiency is the proportion of photons generated in the active region that escape from the device. For LEDs (especially micro-LEDs with reduced physical size), it can be challenging to improve the internal and external quantum efficiency and / or control the emission spectrum. In some examples, to improve the light extraction efficiency, a mesa can be formed that includes at least some semiconductor material layers.

[0137] Fig. 7AAn example of an LED 700 having a vertical table structure is shown. LED 700 may be a light emitter in light source 510, 540, or 642. LED 700 may be a micro-LED made of an inorganic material (e.g., a multilayer semiconductor material). A layered semiconductor light emitting device may include a multilayer III-V semiconductor material. The III-V semiconductor material may include one or more III-group elements (such as aluminum (Al), gallium (Ga), or indium (In)) combined with a V-group element (such as nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb)). When the V-group element of the III-V semiconductor material includes nitrogen, the III-V semiconductor material is referred to as a III-group nitride material. A layered semiconductor light emitting device may be manufactured by growing multiple epitaxial layers on a substrate using techniques such as vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), molecular beam epitaxy (MBE), or metal organic chemical vapor deposition (MOCVD). For example, layers of semiconductor material can be grown layer by layer on a substrate having a specific lattice orientation (e.g., a polar orientation, a non-polar orientation, or a semi-polar orientation), such as a GaN substrate, a GaAs substrate, or a GaP substrate, or substrates including but not limited to: sapphire, silicon carbide, silicon, zinc oxide, boron nitride, lithium aluminate, lithium niobate, germanium, aluminum nitride, lithium gallate, partially substituted spinel, or a quaternary tetragonal oxide sharing a β-LiAlO2 structure, wherein the substrate can be cut in a specific direction to expose a specific plane as a growth surface.

[0138] exist Fig. 7AIn the example shown, the LED 700 may include a substrate 710, which may include, for example, a sapphire substrate or a GaN substrate. A semiconductor layer 720 may be grown on the substrate 710. The semiconductor layer 720 may include a III-V material (such as GaN) and may be p-type doped (e.g., doped with Mg, Ca, Zn, or Be) or n-type doped (e.g., doped with Si or Ge). One or more active layers 730 may be grown on the semiconductor layer 720 to form an active region. The active layer 730 may include a III-V material (such as one or more InGaN layers, one or more AlInGaP layers, and / or one or more GaN layers), which may form one or more heterostructures, such as one or more quantum wells or MQWs. A semiconductor layer 740 may be grown on the active layer 730. The semiconductor layer 740 may include a III-V material such as GaN and may be p-type doped (e.g., doped with Mg, Ca, Zn, or Be) or n-type doped (e.g., doped with Si or Ge). One of the semiconductor layer 720 and the semiconductor layer 740 may be a p-type layer and the other may be an n-type layer. The semiconductor layer 720 and the semiconductor layer 740 sandwich the active layer 730 to form a light emitting region. For example, the LED 700 may include an InGaN layer between a p-type GaN layer doped with magnesium and an n-type GaN layer doped with silicon or oxygen. In some examples, the LED 700 may include an AlInGaP layer between a p-type AlInGaP layer doped with zinc or magnesium and an n-type AlInGaP layer doped with selenium, silicon, or tellurium.

[0139] In some examples, an electron blocking layer (EBL) may be grown ( Fig. 7A ) to form a layer between the active layer 730 and at least one of the semiconductor layer 720 or the semiconductor layer 740. The EBL can reduce electron leakage current and improve the efficiency of the LED. In some examples, the heavily doped semiconductor layer 750 (e.g., P + or P ++ A semiconductor layer 740 may be formed on the semiconductor layer 740 and serve as a contact layer for forming an ohmic contact and reducing the contact resistance of the device. In some examples, a conductive layer 760 may be formed on the heavily doped semiconductor layer 750. The conductive layer 760 may include, for example, indium tin oxide (ITO) or an Al / Ni / Au film. In one example, the conductive layer 760 may include a transparent ITO layer.

[0140] In order to contact the semiconductor layer 720 (e.g., n-GaN layer) and more efficiently extract the light emitted by the active layer 730 from the LED 700, the semiconductor material layer (including the heavily doped semiconductor layer 750, the semiconductor layer 740, the active layer 730, and the semiconductor layer 720) can be etched to expose the semiconductor layer 720 and form a mesa structure including layers 720-760. The mesa structure can confine carriers within the device. Etching the mesa structure can result in the formation of a mesa sidewall 732 that can be orthogonal to the growth plane. A passivation layer 770 can be formed on the sidewall 732 of the mesa structure. The passivation layer 770 can include an oxide layer, such as a SiO2 layer, and can act as a reflector to reflect the emitted light from the LED 700. The contact layer 780 can include a metal layer (e.g., Al, Au, Ni, Ti, or any combination thereof), which can be formed on the semiconductor layer 720 and can act as an electrode of the LED 700. Furthermore, another contact layer 790 , such as an Al / Ni / Au metal layer, may be formed on the conductive layer 760 and may serve as another electrode of the LED 700 .

[0141] When a voltage signal is applied to the contact layers 780 and 790, electrons and holes can recombine in the active layer 730, where the recombination of the electrons and holes can cause photon emission. The wavelength and energy of the emitted photons can depend on the band gap between the valence band and the conduction band in the active layer 730. For example, an InGaN active layer can emit green or blue light, an AlGaN active layer can emit blue to ultraviolet light, and an AlInGaP active layer can emit red, orange, yellow, or green light. The emitted photons can be reflected by the passivation layer 770 and can leave the LED 700 from the top (e.g., the conductive layer 760 and the contact layer 790) or the bottom (e.g., the substrate 710).

[0142] In some examples, the LED 700 can include one or more other components (e.g., a lens) on the light emitting surface (e.g., substrate 710) to focus or collimate the emitted light or couple the emitted light into a waveguide. In some examples, the LED can include a table of another shape (such as a plane, a cone, a semi-parabola, or a parabola), and the base area of ​​the table can be circular, rectangular, hexagonal, or triangular. For example, the LED can include a table of a curved shape (e.g., a parabola shape) and / or a non-curved shape (e.g., a cone shape). The table can be truncated or not truncated.

[0143] Figure 7B705 is a cross-sectional view of an example of an LED 705 having a parabolic mesa structure. Similar to LED 700, LED 705 may include multiple layers of semiconductor materials, such as multiple layers of III-V semiconductor materials. The semiconductor material layers may be epitaxially grown on a substrate 715 (such as a GaN substrate or a sapphire substrate). For example, a semiconductor layer 725 may be grown on substrate 715. The semiconductor layer 725 may include a III-V material (such as GaN) and may be p-type doped (e.g., doped with Mg, Ca, Zn, or Be) or n-type doped (e.g., doped with Si or Ge). One or more active layers 735 may be grown on the semiconductor layer 725. The active layer 735 may include a III-V material (such as one or more InGaN layers, one or more AlInGaP layers, and / or one or more GaN layers), which may form one or more heterostructures, such as one or more quantum wells. A semiconductor layer 745 may be grown on the active layer 735. The semiconductor layer 745 may include a III-V material such as GaN and may be p-type doped (e.g., doped with Mg, Ca, Zn, or Be) or n-type doped (e.g., doped with Si or Ge). One of the semiconductor layer 725 and the semiconductor layer 745 may be a p-type layer and the other may be an n-type layer.

[0144] In order to make contact with the semiconductor layer 725 (e.g., an n-type GaN layer) and more efficiently extract light emitted by the active layer 735 from the LED 705, the semiconductor layer can be etched to expose the semiconductor layer 725 and form a mesa structure including layers 725-745. The mesa structure can confine carriers within the injection region of the device. Etching the mesa structure can result in the formation of mesa sidewalls (also referred to herein as facets), which may be non-parallel to or in some cases orthogonal to the growth plane associated with the crystal growth of the layers 725-745.

[0145] like Figure 7B As shown, LED 705 can have a table structure including a flat top. A dielectric layer 775 (e.g., SiO2 or SiNx) can be formed on the facets of the table structure. In some examples, the dielectric layer 775 can include a multilayer dielectric material. In some examples, a metal layer 795 can be formed on the dielectric layer 775. The metal layer 795 can include one or more metal or metal alloy materials, such as aluminum (Al), silver (Ag), gold (Au), platinum (Pt), titanium (Ti), copper (Cu) or any combination thereof. The dielectric layer 775 and the metal layer 795 can form a table reflector that can reflect the light emitted by the active layer 735 toward the substrate 715. In some examples, the table reflector can be parabolic in shape to act as a parabolic reflector that can at least partially collimate the emitted light.

[0146] Electrical contacts 765 and 785 may be formed on semiconductor layer 745 and semiconductor layer 725, respectively, to act as electrodes. Electrical contacts 765 and 785 may each include a conductive material such as Al, Au, Pt, Ag, Ni, Ti, Cu, or any combination thereof (e.g., Ag / Pt / Au or Al / Ni / Au), and may act as electrodes of LED 705. Figure 7B In the example shown, the electrical contact 785 can be an n-type contact and the electrical contact 765 can be a p-type contact. The electrical contact 765 and the semiconductor layer 745 (e.g., a p-type semiconductor layer) can form a back reflector for reflecting light emitted by the active layer 735 back toward the substrate 715. In some examples, the electrical contact 765 and the metal layer 795 include (one or more) the same material and can be formed using the same process. In some examples, an additional conductive layer (not shown) can be included as an intermediate conductive layer between the electrical contacts 765 and 785 and the semiconductor layer.

[0147] When a voltage signal is applied across contacts 765 and 785, electrons and holes can recombine in active layer 735. The recombination of electrons and holes can cause photon emission, thereby generating light. The wavelength and energy of the emitted photons can depend on the energy band gap between the valence band and the conduction band in active layer 735. For example, an InGaN active layer can emit green or blue light, while an AlInGaP active layer can emit red, orange, yellow, or green light. The emitted photons can propagate in many different directions and can be reflected by the mesa reflector and / or the back reflector and can be, for example, reflected from the Figure 7B The bottom side (e.g., substrate 715) shown in FIG is away from the LED 705. One or more other secondary optical components (such as a lens or grating) can be formed on the light emitting surface (such as substrate 715) to focus or collimate the emitted light and / or couple the emitted light into a waveguide.

[0148] A one-dimensional array or a two-dimensional array of the above-mentioned LEDs can be manufactured on a wafer to form a light source (e.g., light source 642). A driver circuit (e.g., driver circuit 644) can be manufactured on a silicon wafer, for example, using a CMOS process. The LEDs and driver circuits on the wafer can be diced and then bonded together, or can be bonded at the wafer level and then diced. Various bonding techniques can be used to bond the LEDs and driver circuits, such as adhesive bonding, metal-to-metal bonding, metal oxide bonding, wafer-to-wafer bonding, die-to-wafer bonding, hybrid bonding, etc.

[0149] Fig. 8A An example of a method for wafer-to-wafer bonding of an LED array according to certain examples is shown. Fig. 8AIn the example shown, the LED array 801 may include a plurality of LEDs 807 on a carrier substrate 805. The carrier substrate 805 may include various materials, such as GaAs, InP, GaN, AlN, sapphire, SiC, Si, etc. The LEDs 807 may be manufactured by, for example, growing various epitaxial layers, forming mesa structures, and forming electrical contacts or electrodes before performing bonding. The epitaxial layers may include various materials, such as GaN, InGaN, (AlGaIn)P, (AlGaIn)AsP, (AlGaIn)AsN, (AlGaIn)Pas, (Eu:InGa)N, (AlGaIn)N, etc., and may include an n-type layer, a p-type layer, and an active layer, the active layer including one or more heterostructures, such as one or more quantum wells or MQWs. The electrical contacts may include various conductive materials, such as metals or metal alloys.

[0150] Wafer 803 may include a base layer 809 having passive or active integrated circuits (e.g., driver circuit 811) fabricated thereon. Base layer 809 may include, for example, a silicon wafer. Driver circuit 811 may be used to control the operation of LED 807. For example, the driver circuit for each LED 807 may include a 2T1C pixel structure having two transistors and one capacitor. Wafer 803 may also include a bonding layer 813. Bonding layer 813 may include various materials such as metals, oxides, dielectrics, CuSn, AuTi, etc. In some examples, a patterned layer 815 may be formed on the surface of bonding layer 813, wherein patterned layer 815 may include a metallic grid made of a conductive material such as Cu, Ag, Au, Al, etc.

[0151] The LED array 801 can be bonded to the wafer 803 via a bonding layer 813 or a patterned layer 815. For example, the patterned layer 815 can include metal pads or bumps made of various materials (such as CuSn, AuSn, or nanoporous Au) that can be used to align the LEDs 807 in the LED array 801 with the corresponding driver circuits 811 on the wafer 803. In one example, the LED array 801 can be directed toward the wafer 803 until the LEDs 807 contact the corresponding metal pads or bumps corresponding to the driver circuits 811. Some or all of the LEDs 807 can be aligned with the driver circuits 811 and can then be bonded to the wafer 803 via the patterned layer 815 by various bonding techniques (such as metal-to-metal bonding). After the LEDs 807 have been bonded to the wafer 803, the carrier substrate 805 can be removed from the LEDs 807.

[0152] Figure 8BAn example of a method for wafer-to-wafer bonding of an LED array according to certain examples is shown. Figure 8B As shown, the first wafer 802 may include a substrate 804, a first semiconductor layer 806, an active layer 808, and a second semiconductor layer 810. The substrate 804 may include various materials, such as GaAs, InP, GaN, AlN, sapphire, SiC, Si, etc. The first semiconductor layer 806, the active layer 808, and the second semiconductor layer 810 may include various semiconductor materials, such as GaN, InGaN, (AlGaIn) P, (AlGaIn) AsP, (AlGaIn) AsN, (AlGaIn) Pas, (Eu: InGa) N, (AlGaIn) N, etc. In some examples, the first semiconductor layer 806 may be an n-type layer, and the second semiconductor layer 810 may be a p-type layer. For example, the first semiconductor layer 806 may be an n-type doped GaN layer (e.g., doped with Si or Ge), and the second semiconductor layer 810 may be a p-type doped GaN layer (e.g., doped with Mg, Ca, Zn, or Be). For example, the active layer 808 may include one or more GaN layers, one or more InGaN layers, one or more AlInGaP layers, etc. The active layer 808 may form one or more heterostructures, such as one or more quantum wells or MQWs.

[0153] In some examples, the first wafer 802 may also include a bonding layer. The bonding layer 812 may include various materials, such as metals, oxides, dielectrics, CuSn, AuTi, etc. In one example, the bonding layer 812 may include a p-contact and / or an n-contact (not shown). In some examples, other layers may also be included on the first wafer 802 (such as a buffer layer between the substrate 804 and the first semiconductor layer 806). The buffer layer may include various materials, such as polycrystalline GaN or AlN. In some examples, a contact layer may be between the second semiconductor layer 810 and the bonding layer 812. The contact layer may include any suitable material for providing electrical contact to the second semiconductor layer 810 and / or the first semiconductor layer 806.

[0154] The first wafer 802 can be bonded to the wafer 803 including the driver circuit 811 and the bonding layer 813 as described above via the bonding layer 813 and / or the bonding layer 812. The bonding layer 812 and the bonding layer 813 can be made of the same material or different materials. The bonding layer 813 and the bonding layer 812 can be substantially flat. The first wafer 802 can be bonded to the wafer 803 by various methods (such as metal-to-metal bonding, eutectic bonding, metal oxide bonding, anodic bonding, thermocompression bonding, ultraviolet (UV) bonding and / or melt bonding).

[0155] like Figure 8BAs shown, the first wafer 802 can be bonded to the wafer 803 with the p-side (e.g., the second semiconductor layer 810) of the first wafer 802 facing down (i.e., toward the wafer 803). After bonding, the substrate 804 can be removed from the first wafer 802, and the first wafer 802 can then be processed from the n-side. For example, the processing can include forming a specific mesa shape for an individual LED, and forming an optical component corresponding to the individual LED.

[0156] Figure 9A-9D An example of a hybrid bonding method for an LED array according to certain examples is shown. Hybrid bonding can generally include wafer cleaning and activation, high precision alignment of contacts of one wafer with contacts of another wafer, dielectric bonding of dielectric materials at the wafer surface at room temperature, and metallic bonding of the contacts by an annealing process at an elevated temperature. Fig. 9A A substrate 910 is shown with passive or active circuits 920 fabricated thereon. Figure 8A-B As described, substrate 910 may include, for example, a silicon wafer. Circuit 920 may include a driver circuit for an LED array. The bonding layer may include a dielectric region 940 and a contact pad 930 connected to circuit 920 via an electrical interconnect 922. Contact pad 930 may include, for example, Cu, Ag, Au, Al, W, Mo, Ni, Ti, Pt, Pd, etc. The dielectric material in dielectric region 940 may include SiCN, SiO2, SiN, Al2O3, HfO2, ZrO2, Ta2O5, etc. The bonding layer may be planarized and polished using, for example, chemical mechanical polishing, wherein planarization or polishing may cause a depression (bowl-shaped profile) in the contact pad. The surface of the bonding layer may be cleaned and activated by, for example, an ion (e.g., plasma) or fast atom (e.g., Ar) beam 905. The activated surface may be atomically clean and reactive when the wafers are in contact, for example, at room temperature, for forming direct bonds between wafers.

[0157] Fig. 9B It is shown that the above reference includes Figure 7A-Figure 8BThe wafer 950 on which the micro LED 970 array is manufactured is described. The wafer 950 may be a carrier wafer and may include, for example, GaAs, InP, GaN, AlN, sapphire, SiC, Si, etc. The micro LED 970 may include an n-type layer, an active region, and a p-type layer epitaxially grown on the wafer 950. The epitaxial layer may include the various III-V semiconductor materials described above, and may be processed from the p-type layer side to etch a mesa structure in the epitaxial layer, such as a basic vertical structure, a parabolic structure, a conical structure, etc. A passivation layer and / or a reflective layer may be formed on the sidewalls of the mesa structure. A p-contact 980 and an n-contact 982 may be formed in a dielectric material layer 960 deposited on the mesa structure, and electrical contacts may be formed with the p-type layer and the n-type layer, respectively. The dielectric material in the dielectric material layer 960 may include, for example, SiCN, SiO2, SiN, Al2O3, HfO2, ZrO2, Ta2O5, etc. The p-contact 980 and the n-contact 982 may include, for example, Cu, Ag, Au, Al, W, Mo, Ni, Ti, Pt, Pd, etc. The top surfaces of the p-contact 980, the n-contact 982, and the dielectric material layer 960 may form a bonding layer. The bonding layer may be planarized and polished using, for example, chemical mechanical polishing, wherein the polishing may cause depressions in the p-contact 980 and the n-contact 982. The bonding layer may then be cleaned and activated by, for example, an ion (e.g., plasma) or fast atom (e.g., Ar) beam 915. The activated surface may be atomically clean and reactive when the wafers are in contact, for example, at room temperature, for forming direct bonds between the wafers.

[0158] Fig. 9C A room temperature bonding process for bonding dielectric materials in a bonding layer is shown. For example, after a bonding layer including a dielectric region 940 and a contact pad 930 and a bonding layer including a p-contact 980, an n-contact 982, and a dielectric material layer 960 is surface activated, a wafer 950 and a micro-LED 970 can be inverted and contacted with a substrate 910 and a circuit formed thereon. In some examples, a compressive pressure 925 can be applied to the substrate 910 and the wafer 950 so that the bonding layers are pressed against each other. Due to the surface activation and the depression in the contact, the dielectric region 940 and the dielectric material layer 960 can be in direct contact due to surface attraction, and can react and form chemical bonds between them because the surface atoms can have dangling bonds and may be in an unstable energy state after activation. Therefore, the dielectric materials in the dielectric region 940 and the dielectric material layer 960 can be bonded together with or without heat treatment or pressure.

[0159] Fig.9DAn annealing process for bonding contacts in the bonding layer is shown after the dielectric material is bonded in the bonding layer. For example, the contact pad 930 and the p-contact 980 or the n-contact 982 can be bonded together by annealing at a temperature of, for example, about 200° C.-400° C. or higher. During the annealing process, the heat 935 can cause the contacts to expand more than the dielectric material (due to different thermal expansion coefficients), and thus can close the recessed gap between the contacts so that the contact pad 930 and the p-contact 980 or the n-contact 982 can contact and can form a direct metal bond at the activated surface.

[0160] In some examples where the two bonded wafers include materials with different coefficients of thermal expansion (CTE), the dielectric material bonded at room temperature can help reduce or prevent misalignment of contact pads caused by different thermal expansion. In some examples, to further reduce or avoid misalignment of contact pads at high temperatures during annealing, grooves can be formed between micro-LEDs, between groups of micro-LEDs, through part or all of the substrate, etc. before bonding.

[0161] After the microLED is bonded to the driver circuit, the substrate on which the microLED is fabricated can be thinned or removed, and various secondary optical components can be fabricated on the light emitting surface of the microLED to, for example, extract, collimate, and redirect light emitted from the active area of ​​the microLED. In one example, a microlens can be formed on the microLED, wherein each microlens can correspond to a corresponding microLED and can help improve the light extraction efficiency and collimate the light emitted by the microLED. In some examples, the secondary optical components can be fabricated in the substrate or n-type layer of the microLED. In some examples, the secondary optical components can be fabricated in a dielectric layer deposited on the n-type side of the microLED. Examples of secondary optical components can include lenses, gratings, anti-reflective (AR) coatings, prisms, photonic crystals, and the like.

[0162] Fig.10 An example of an LED array 1000 having secondary optics fabricated thereon is shown according to certain examples. The LED array 1000 may be fabricated using the LED arrays described above with reference to, for example, Figures 8A-9D The LED chip or wafer is bonded to a silicon wafer including circuits fabricated thereon using any suitable bonding technique described. Fig.10 In the example shown, the LED array 1000 can be used as described above with reference to Figure 9A-9DThe LED array 1000 may include a substrate 1010, which may be, for example, a silicon wafer. An integrated circuit 1020 (such as an LED driver circuit) may be fabricated on the substrate 1010. The integrated circuit 1020 may be connected to a p-contact 1074 and an n-contact 1072 of a micro LED 1070 via an interconnect 1022 and a contact pad 1030, wherein the contact pad 1030 may form a metal bond with the p-contact 1074 and the n-contact 1072. The dielectric layer 1040 on the substrate 1010 may be bonded to the dielectric layer 1060 by fusion bonding.

[0163] The substrate (not shown) of the LED chip or wafer may be thinned or may be removed to expose the n-type layer 1050 of the micro-LEDs 1070. Various secondary optical components, such as spherical micro-lenses 1082, gratings 1084, micro-lenses 1086, anti-reflective layers 1088, etc., may be formed in or on top of the n-type layer 1050. For example, a spherical micro-lens array may be etched in the semiconductor material of the micro-LEDs 1070 using a grayscale mask and a photoresist having a linear response to exposure light, or using an etch mask formed by thermal reflowing of a patterned photoresist layer. Secondary optical components may also be etched in a dielectric layer deposited on the n-type layer 1050 using similar photolithography techniques or other techniques. For example, a micro-lens array may be formed in a polymer layer by thermal reflow of a polymer layer patterned using a binary mask. The microlens array in the polymer layer can be used as a secondary optical component or can be used as an etching mask to transfer the profile of the microlens array into a dielectric layer or a semiconductor layer. The dielectric layer can include, for example, SiCN, SiO2, SiN, Al2O3, HfO2, ZrO2, Ta2O5, etc. In some examples, the micro-LED 1070 can have multiple corresponding secondary optical components, such as microlenses and anti-reflective coatings, microlenses etched in semiconductor materials and microlenses etched in dielectric material layers, microlenses and gratings, spherical lenses and aspherical lenses, etc. Fig.10 Three different secondary optics are shown in to illustrate some examples of secondary optics that may be formed on micro LEDs 1070, which does not necessarily mean that a different secondary optic is used simultaneously for each LED array.

[0164] Fig.11 1 is a simplified block diagram of an example of a display device 1100 according to some examples. The display device 1100 can include a display panel 1130 that includes an array (eg, a 2D array) of pixels 1112. The display panel 1130 can be an example of the display panel 640. Fig.11A block diagram of one pixel 1112 is shown, which can be similar to other pixels 1112 in the pixel array. Pixel 1112 can be an example of a portion of a light source 642 and a driver 644. Various functional components of each pixel 1112 can use digital comparison to generate a digital PWM signal to control a micro LED. Pixel 1112 can include a micro LED 1105, which can emit light at an intensity level controlled by a PWM signal. The circuit that controls the micro LED 1105 in pixel 1112 can be an example of a portion of a driver circuit 644, and can include a memory device 1102, a comparator 1104, a PWM latch circuit 1106, and an LED driver circuit 1108. Memory device 1102 can be part of pixel 1112, or can be external to pixel 1112. Memory device 1102 can include, for example, an SRAM cell, and can store intensity data for pixel 1112. Memory device 1102 can be connected to comparator 1104, which can be connected to PWM latch circuit 1106. The PWM latch circuit 1106 can be connected to the LED driver circuit 1108 to control the LED driver circuit 1108 to provide pulse width modulation of the drive current, which can be an approximately constant current. The LED driver circuit 1108 can drive the micro LED 1105 with the drive current for different time periods based on the PWM signal to emit different amounts of light during the PWM frame (also referred to as the PWM cycle). In general, the longer the micro LED 1105 is driven at the current level within the PWM cycle, the brighter the micro LED 1105 can be perceived by an observer.

[0165] The display device 1100 may also include a row driver 1114, a column driver 1116, and a counter 1110. In some examples, the row driver 1114, the column driver 1116, and the counter 1110 may be part of the peripheral circuitry of the display panel 1130. The row driver 1114 and the column driver 1116 may be connected to the pixels 1112. For example, the row driver 1114 may be connected to the memory device 1102, the comparator 1104, and the PWM latch circuit 1106. The column driver 1116 may be connected to the memory device 1102. The display device 1100 may also include a controller 1140, which may include a processor 1142 and a display memory device 1144. The controller 1140 may be connected to the row driver 1114 and the column driver 1116 to control the operation of the row driver 1114 and the column driver 1116. For example, processor 1142 of controller 1140 may provide control signals to row driver 1114 and column driver 1116 to operate pixel 1112. Counter 1110 may be coupled to display memory device 1144, which may store, for example, calibration data and / or a gamma correction look-up table (LUT).

[0166] The memory device 1102 may include digital data storage cells (such as cells of SRAM) or some other type of memory. For example, the memory device 1102 may include a plurality of memory cells for storing display data (e.g., intensity data) for the pixel 1112. Each cell in the memory device 1102 may be connected to the row driver 1114 via a word line (WL) and may be connected to the row driver 1114 via a bit line (BL) and an inverse bit line (inverse bit line). Connected to column driver 1116. The memory device 1102 can receive a WL signal from the row driver 1114 for memory word selection, and can receive a control word in the form of data bits from the column driver 1116 for writing to the selected memory cell. The bit value of the data bit D defines the intensity level of the pixel of the PWM frame. The number of data bits (or bit cells) in the control word may vary. In one example, each control word in the memory device 1102 may include 3 bit cells that store a 3-bit value representing one of eight brightness levels (e.g., 000, 001, 010, 011, 100, 101, 110, and 111). In another example, each control word in the memory device 1102 may include 8 bit cells that store an 8-bit value representing one of 256 brightness levels. Additional details about the memory device 1102 are described below in conjunction with, for example Fig. 12A and Fig. 12B Described.

[0167] The counter 1110 may be used to generate a counter value (e.g., a clock cycle count) based on a clock signal. The counter value of the counter 1110 may be compared with the value of the control word from the memory device 1102 by the comparator 1104 to generate a comparison result. For example, the comparison result may be generated based on an exclusive OR (XOR) of each data bit in the control word and the corresponding bit of the counter value. The comparator 1104 may include a dynamic comparison node that switches between a high level and a low level according to the comparison result, and the comparison result may be output to the PWM latch circuit 1106 to generate a PWM signal. Alternatively, the comparator 1104 may include a statically driven comparison node that switches between a high level and a low level according to the comparison result, and the comparison result may be output to the PWM latch circuit 1106 to generate a PWM signal.

[0168] The LED driver circuit 1108 may include one or more LED driving transistors. One of the one or more LED driving transistors may have a source or drain terminal connected to the micro LED 1105. One of the one or more LED driving transistors may include a gate terminal connected to the PWM latch circuit 1106 to receive a PWM signal for modulating the current flowing through the source terminal and the drain terminal of the driving transistor into the micro LED 1105.

[0169] Fig. 12A An example of an SRAM cell 1200 that can be used as a bit cell for storing intensity data is shown. SRAM retains its stored information as long as power is applied, unlike dynamic RAM (DRAM) that requires periodic refresh or non-volatile memory that does not require power for data retention. SRAM can be randomly accessed so that each cell in the array can be read or written in any order, regardless of which cell was accessed last. Fig. 12A The SRAM cell 1200 shown in FIG. 1 is a 6-transistor SRAM cell that can store one bit of data. The SRAM cell 1200 includes two CMOS inverters formed by MOSFETs M1 / M2 and M3 / M4, respectively. The output of each of the two inverters is fed to the other inverter as an input of the other inverter to form a feedback loop. The feedback loop can stabilize the inverters to their corresponding states.

[0170] Access transistors M5 and M6, word line WL, and bit line BL and Used to read from and write to the SRAM cell 1200. In standby mode, the word line WL is low, and thus the access transistors M5 and M6 are turned off. The two inverters are in a complementary state. When the P-channel MOSFET M2 of the left inverter is turned on, the output of the left inverter is high, and thus the P-channel MOSFET M4 of the right inverter is turned off, and the output of the right inverter is low to turn on the P-channel MOSFET M2 of the left inverter.

[0171] To write a data bit into the SRAM cell 1200, the data bit may be driven on the bit line BL and the reverse bit line BL may be driven on the reverse bit line BL. The inverted data bit is driven on. Access transistors M5 and M6 can then be turned on by setting the word line WL to a high level. Since the driver of the bit line may be much stronger than the MOSFETs M1-M4, the bit line may overpower the inverter transistors to apply new data in the SRAM cell 1200. In order to overpower the feedback loop formed by the two inverters, access transistor M5 may need to be stronger than the P-channel MOSFET M2 of the left inverter, and / or access transistor M6 may need to be stronger than the P-channel MOSFET M4 of the right inverter. Once the data bit is stored in the inverter, access transistors M5 and M6 can be turned off by setting the word line WL to a low level, and the state of the two inverters is maintained by the feedback loop.

[0172] To read the stored data bit from the SRAM cell 1200, the bit line BL and the inverted bit line can be precharged to a high level. The word line WL can then be set to a high level to turn on access transistors M5 and M6. The bit line BL or the reverse bit line may be pulled down to a low level according to the data bit stored in the SRAM cell 1200. For example, if "1" is stored in the SRAM cell 1200, then can be at a low level and invert the bit line Q can be pulled to a low level, while Q can be at a higher level, and thus the bit line BL can be kept at a high level.

[0173] Fig. 12B 1 is a simplified block diagram of a portion of an example of a display panel 1205 including an array of unit pixels and a customized SRAM bit cell 1210. The display panel 1205 may include unit pixels (e.g., as described above with respect to Fig.111112) as described above, wherein each unit pixel may include a bit cell for storing a control word for the unit pixel and a PWM generation circuit 1220 for generating a PWM signal. The PWM generation circuit 1220 may, for example, include a comparator and a PWM latch circuit as described above. The control word for each pixel may include a plurality of bit cells (in Fig. 12B Only two bit cells are shown).

[0174] like Fig. 12B As shown, the SRAM bit cell 1210 is not a standard 6-transistor SRAM cell, which uses the same method as described above with respect to Fig. 12A Instead, the SRAM bit cell 1210 can be modified so that the internal storage node of each customized SRAM bit cell 1210 can be connected to the PWM generation circuit 1220 through the additional interconnect 1212 for reading the customized SRAM bit cell 1210 to generate the PWM signal, while the writing to the customized SRAM bit cell 1210 can still be performed through the bit line.

[0175] Fig.13A 1 shows an example of a unit pixel 1300 in an example of a display panel such as display panel 1130 or 1205. The unit pixel 1300 may be similar to the above description of the unit pixel 1300. Fig.11 13. The pixel 1112 described in the embodiment of the present invention may include a bit cell 1310, a comparator 1320, a PWM latch circuit 1330, an analog driver circuit 1340, and a micro LED 1350. In the example shown, the bit cell 1310 includes 4 bit cells, and thus the unit pixel 1300 has a bit depth of 4 and can emit light at 16 different intensity levels. The bit cell 1310 may include a customized SRAM bit cell, such as the customized SRAM bit cell 1210 described above. The comparator 1320 may be similar to the comparator 1104 described above, and the PWM latch circuit 1330 may be similar to the PWM latch circuit 1106. The output of the PWM latch circuit 1330 may be a PWM signal including pulses of a desired width. The analog driver circuit 1340 may include, for example, a current source and one or more LED drive transistors, wherein the LED drive transistor may be controlled by a PWM signal to connect or disconnect the micro LED 1350 to the current source. The unit pixel 1300 may have a linear dimension of several microns (e.g., about 2 μm).

[0176] Fig. 13BAn example of a display panel 1305 including a two-dimensional array of unit pixels 1300 is shown. In the display panel 1305, the above-mentioned unit pixels 1300 can be arranged in a 2D array having thousands or millions of unit pixels 1300 and having a linear size of about several millimeters (e.g., about 4 mm×3 mm). The display panel 1305 may also include a peripheral circuit 1360 at the outer edge of the 2D array of unit pixels 1300. The peripheral circuit 1360 may include, for example, a column driver, a row driver, a counter, etc. As described above, the column driver and the row driver may be used to select a unit pixel, write a control word to a bit cell of the unit pixel, and read a data bit from the bit cell. Since the 2D array of unit pixels 1300 may have a linear size of several millimeters, the control signal generated by the peripheral circuit 1360 of the unit pixel 1300 in the middle of the 2D array of unit pixels (e.g., word line and bit line signals of the bit cell and counter data bits) may need to travel a long distance (e.g., up to half the length or width of the 2D array) before reaching the unit pixel.

[0177] Fig.14 An example of a plan view of a driver circuit for an example of a micro LED display panel 1400 is shown. The micro LED display panel 1400 may be an example of a display panel 1305. In the example shown, the micro LED display panel 1400 may include a micro LED device (not shown) including a 2D array of micro LEDs having a small pitch (e.g., less than about 5 μm or less than about 2 μm). The micro LED display panel 1400 may also include a silicon backplane device 1410 including a driver circuit for controlling the operation of the micro LED device. The silicon backplane device 1410 and the micro LED device may be bonded together at the wafer level or wafer level as described above (e.g., using a micro LED alignment mark 1412 on the silicon backplane device 1410), so that the anode and cathode of the micro LED of the micro LED device can be connected to the circuit on the silicon backplane device 1410. In some examples, at least a portion of the silicon backplane device 1410 may be implemented in a thin film transistor (TFT) layer. The silicon backplane device 1410 may include a 2D pixel array 1420. The 2D pixel array 1420 may include unit pixel driving circuits for individual unit pixels arranged in a two-dimensional array as described above.

[0178] The silicon backplane device 1410 may include various peripheral circuits for controlling the operation of the 2D pixel array 1420. The peripheral circuits may include, for example, a digital PWM control circuit 1430, a pixel write buffer 1440, other digital control circuits 1450, an I / O circuit 1460 for digital data and control, an analog bias and reference circuit 1470, an I / O circuit 1480 for analog power and signals, a micro LED test circuit 1490, etc. The silicon backplane device 1410 may also include a row driver buffer 1422 and a column interface 1424 at the periphery of the 2D pixel array 1420.

[0179] As described above, the 2D pixel array 1420 may have a linear dimension of several millimeters (e.g., about 3 mm or 4 mm). Therefore, the control signal (e.g., word line and bit line signal of the bit cell, PWM control signal, counter data bit, clock signal, etc.) generated by the peripheral circuit outside the 2D pixel array 1420 for the unit pixel in the middle of the 2D pixel array 1420 may need to travel a long distance before reaching the target unit pixel. In order to reduce the length of these interconnects, the row driver may be arranged on the opposite sides of the 2D pixel array 1420, so that half of the unit pixel can be controlled by the row driver on one side, and the other half of the unit pixel can be controlled by the row driver on the other side. Similarly, the column driver may be arranged on the opposite sides of the 2D pixel array 1420, so that half of the unit pixel can be controlled by the column driver on one side, and the other half of the unit pixel can be controlled by the column driver on the other side. The buffer can also be used to increase the drive strength. Therefore, the 2D pixel array 1420 may include four quadrants, each of which may be driven by a group of column drivers and row drivers.

[0180] exist Figure 12B-Figure 14 In the example shown, the unit pixels are evenly arranged in a 2D array, and each unit pixel has its own bit cell, comparator, PWM latch circuit, and analog driver. Transition regions and / or intervals may be required between different types of devices in each unit pixel and between unit pixels (e.g., between SRAM cells, digital logic, analog circuits, high-voltage circuits, etc.). Therefore, a larger portion of the 2D array of unit pixels may be used as a transition region or interval between different types of devices. As described above, the micro LED array may have a pitch of only a few microns. Therefore, there may be only enough space in each unit pixel to include a small number (e.g., about 4) of bit cells. As described above, it is generally desirable that the bit depth is greater than, for example, 6, in order to display an image with a sufficient number of brightness changes. There may be some techniques to increase the effectively perceived bit depth to exceed the number of physical bit cells in each unit pixel.

[0181] Fig.15A1500 is included, which shows an example of improving perceived bit depth by modifying PWM timing based on a nonlinear power law transformation according to certain examples. The human eye's response to light can be nonlinear. According to B=L 1 / γ , the perceived brightness B can be a nonlinear function of the beam luminance L, where γ (gamma) can be greater than 1, for example, between about 1.5 and 3 (e.g., about 2). Therefore, as the luminance L increases, more and more additional light may be required to produce a perceptible brightness difference. In other words, when the luminance is low, a small change in luminance may result in a large change in perceived brightness; however, when the luminance is high, a large change in luminance may only result in a small change in perceived brightness. Therefore, if the control word representing the intensity level or brightness of a unit pixel is linearly transformed into an on time (ON time) or a pulse width, the brightness of the emitted light perceived by the human eye may not correspond to the control word or the desired brightness, and the human eye may not notice some changes in brightness at high luminance levels. Due to the sensitivity of the human eye at low luminance levels, if increasing the value of the control word by 1 when the luminance level is low can result in a small increase in the luminance of the emitted light, and increasing the value of the control word by 1 when the luminance level is high can result in a large increase in the luminance of the emitted light, then the perceived bit depth can be effectively increased.

[0182] exist Fig.15A In the example shown, the unit pixel may have 4 bit cells and therefore have a physical bit depth of 4, which may correspond to 16 different control word values ​​0-15. When the control word value is small, increasing the control word value by 1 may result in a smaller change in pulse width or on-time (and therefore luminance), which may still result in a larger increase in perceived brightness (due to the sensitivity of the human eye at low luminance levels). When the control word value is large, increasing the control word value by 1 may result in a larger change in pulse width or on-time (and therefore luminance) so as to result in a significant change in perceived brightness. In this way, the perceived bit depth may be higher than the physical bit depth, for example, about 1.5 bits higher than the physical bit depth. Thus, a unit pixel with 4 bit cells may have a perceived bit depth of about 5.5 bits.

[0183] Using a non-linear gamma-law transform to increase the perceived bit depth may require some additional circuitry (eg, circuitry to determine the pulse width modulation based on a control word and a non-linear power law) or a lookup table storing the relationship between control word values ​​and pulse widths.

[0184] Fig. 15BAn example of using temporal jittering to improve perceived bit depth according to certain examples is shown. Temporal jittering (also known as frame rate control) can be implemented by increasing the frame rate of the display and cycling between images of different intensity levels within each original content frame period to simulate intermediate intensity levels and thus effectively increase the bit depth. For example, video data with a specific content frame rate can be processed by a graphics and display processing unit 1510, which creates subframes based on the original content frame. The subframes may include image frames with different intensity levels and need to be cycled through during the original content frame period. Then, the new subframes can be displayed by the backplane driver 1520 at a higher frame rate to simulate intensity levels different from the intensity levels of the subframes. In this way, by including more subframes in the original content frame period, many different color levels can be generated. However, increasing the perceived bit depth using temporal jittering may significantly increase power consumption due to the increased frame rate, which may be two, three, four times or more.

[0185] As described above, since the 2D array of unit pixels in the display panel can have a linear dimension of several millimeters, the control signals (e.g., word line and bit line signals of the bit cell and the counter data bit) generated by the peripheral circuits of the unit pixels in the middle of the 2D array of unit pixels may need to travel a long distance before reaching the target unit pixel. The long wires used for these signals may have high resistance and high capacitance (load), and therefore may have high losses and long RC time delays for the signals. The long wires may also have large inductance values, and therefore have low bandwidth, and therefore may increase the rise and / or fall time of the signal, which may affect the timing tolerance of the device.

[0186] Fig.16A Shown in Fig.14 A simplified model 1600 of a driver circuit in an example of a micro LED display panel is shown. In the example shown, a driver 1610 (e.g., an inverter) can drive a long interconnect wire 1620. Multiple load devices 1630 (e.g., transistors, gates, etc.) can be coupled to the interconnect wire 1620 at different distances from the driver 1610.

[0187] Fig. 16B Shown in Fig.16A An example of a simulated waveform at the end of the driver circuit shown in FIG. Fig. 16B, curve 1640 shows an input signal (e.g., rising edge) to driver 1610 (e.g., inverter). Curve 1650 shows an output signal (e.g., falling edge) of driver 1610. Because an inverter is used as an example of driver 1610, the output signal may be opposite to the input signal. Curve 1660 shows a drive signal received by the last load device 1630 on interconnect wire 1620. Because no buffer or repeater is used on interconnect wire 1620, when the output signal of driver 1610 reaches the last load device 1630, the fall time may become longer, as shown in curve 1660.

[0188] Fig.17A A simplified model of a bit cell 1700 with long bit lines 1710 and 1720 is shown. The bit cell 1700 may be similar to the 6-transistor SRAM cell 1200 or 1210 described above. In the example shown, the bit line BL 1710 and the reverse bit line 1720 may have a length of about 1.5 mm. Fig. 12A As described above, during a write operation, if the new value is different from the stored value, the new value can be forced into the SRAM cell to destroy the cell stability. For example, the internal node N1 can be at a low level, the bit line BL 1710 can be at a high level, and the internal node N2 can be at a high level, the reverse bit line 1720 can be at a low level.

[0189] Fig. 17B 1705 is included, which shows an example of simulated write noise margin (WNM) of the bit cell 1700 with different bit line conductor resistances. In the simulation, the bit line BL 1710 and the reverse bit line 1720 may have low resistance (e.g., wider and / or shorter metal traces), medium resistance (e.g., metal traces with medium width and / or length), and high resistance (e.g., narrow and / or long metal traces). Simulated read voltage transfer curves for different resistances may be approximately the same as shown in read voltage transfer curve 1730. Simulated write voltage transfer curves for low resistance, medium resistance, and high resistance may be shown by write voltage transfer curves 1740, 1750, and 1760, respectively. The write noise margin may be determined based on the side of the largest square between the read voltage transfer curve and the write voltage transfer curve for the same memory cell. Therefore, when the bit line includes wider and / or shorter metal traces and thus has low resistance, the largest square between the read voltage transfer curve 1730 and the corresponding write voltage transfer curve 1740 may be square 1742, which shows a larger write noise margin. When the bit line includes a narrow and / or long metal trace and thus has a high resistance, the largest square between the read voltage transfer curve 1730 and the corresponding write voltage transfer curve 1760 may be square 1762, which shows a small write noise margin. When the bit line includes a metal trace with a medium width and / or length and thus has a medium resistance, the largest square between the read voltage transfer curve 1730 and the corresponding write voltage transfer curve 1750 may be square 1752, which shows a medium write noise margin. Therefore, in order to achieve a sufficiently high write noise margin, the long bit line BL 1710 and the inverted bit line BL 1710 are preferably connected to the inverted bit line BL 1710. 1720 may need to have wider traces, which may use a larger routing area. Alternatively or additionally, the supply voltage VDD may be increased, for example, by about 300 mV or more, to mitigate the reduced noise margin caused by the large resistor. However, increasing VDD may result in a significant increase in power consumption (approximately proportional to the square of VDD).

[0190] In addition, Figure 12B-Figure 14 In the example of a 2D array of unit pixels shown, each bit line may need to drive several thousand bit cells (e.g., >4000 bit cells), and each word line may need to drive several hundred bit cells (e.g., close to about 1000 bit cells). However, for SRAM, the maximum load recommended by the wafer foundry may be about 256 bit cells per bit line and about 512 bit cells per word line.

[0191] Furthermore, due to the small size of the LED driver transistors and the variability of the LED driver transistors (eg, caused by random dopant fluctuations), the drive current of the micro-LEDs, and thus the brightness of the micro-LEDs, may also vary significantly.

[0192] Fig.18Graph 1800 is included, which shows an example of the distribution of simulated drive current of a CMOS driver due to variations in the LED drive transistor. As shown in graph 1800, the target drive current can be about 240nA. However, due to random dopant fluctuations and the small size of the LED drive transistor, the drive current can vary, for example, from about 130nA to about 350nA, where sigma (δ) is about 36nA. Based on the expected typical light output of a drive current that is within ±3δ of the average drive current, the drive current variation shown in graph 1800 may result in a brightness difference of about 3.11 times. The brightness variation may be visible to the human eye and may need to be offset by calibration using some bits of the intensity data, which may reduce the effective bit depth of the intensity data.

[0193] Therefore, in a unit pixel based architecture (e.g. Figure 12B-Figure 14 As shown in FIG. 1 , due to the limited real estate available for the pixel array drive circuits that need to drive thousands or millions of micro-LEDs with small pitches, the bit depth may be limited, non-standard SRAM cells may need to be used, repeaters and other peripheral circuits may not be dispersed in the 2D array of unit pixels, the resistance and loss of control signals may be large for some circuits in the 2D array, the brightness of the micro-LEDs may vary greatly, and there may be no space for DFT circuits. Therefore, it may be difficult to achieve the desired bit depth (e.g., ≥6 bits), low drive current and brightness variation, high noise margin, low power consumption, high yield using conventional foundry processes, and DFT functionality using a unit pixel architecture.

[0194] According to some examples, the macro-pixel architecture can be used to accommodate more bit cells and circuits with other functions in the same available area for the micro-LED array. The macro-pixel architecture can enable the sharing of some circuits between pixels and reduce some transition areas, so that for each pixel in a pixel array with an average pitch of about 1.8 μm, a bit depth of 6 or more (e.g., 8 or 9) may be possible, additional logic functions may be included, and the circuit may be made more robust and manufacturable (e.g., with standard SRAM cells, wider interconnects, and low analog circuit mismatch). In the macro-pixel architecture disclosed herein, some circuits (e.g., comparators) may be shared between multiple adjacent pixels (e.g., by time division multiplexing). In addition, bit cells (e.g., memories such as SRAM cells), digital logic, and high-voltage LED drive transistors may each be combined together in a continuous layout area to reduce the transition area that may otherwise be required, because according to design and process rules, adjoining different types of circuits will require transition areas and spacing. Gathering the same type of circuits in a continuous layout can minimize the "transition area" between different types of circuits and leave more space for other circuits or components.

[0195] According to an example disclosed herein, a macro pixel may include 8 or more pixels, for example, 12 pixels. The macro pixel may include a bit cell (e.g., an SRAM cell) organized in a continuous 2D array, the continuous 2D array including 12 words, where each word is 6 bits. The continuous 2D array of bit cells may include SRAM cells of standard wafer foundry, rather than custom-designed bit cells as in the unit pixel design, and may therefore be more reliably manufactured in a wafer foundry. The input and output (I / O) circuits for the continuous 2D array of bit cells may perform functions similar to those of the SRAM peripheral circuits in the SRAM array of standard wafer foundry. The macro pixel may also include other types of circuits (e.g., digital logic, analog circuits, high-voltage circuits, etc.), which are also arranged in a continuous array based on the type of circuit, thereby reducing the transition area between different types of circuits and leaving more space for additional circuits and functions. In addition, the comparator logic that compares the pixel value from the SRAM with the counter value may be shared by 12 pixels through time division multiplexing to further reduce the silicon area used. The PWM latch circuit for each pixel can be set or cleared based on a comparator output, which can be generated based on the state of the PWM signal relative to the counter value. The output of the PWM latch circuit can control an analog circuit (e.g., a micro LED driver or current mirror) including thick oxide transistors to provide a constant current to the micro LED for different durations, thereby producing light of different intensities. Due to the additional available space as a result of circuit sharing and reduced transition area, a DFT circuit can be included in the pixel array driver circuit to obtain observability of, for example, the PWM latch state, current mirror, and / or micro LED IV characteristics. The high area efficiency of macro pixels can also enable more design flexibility, such as using the standard bit cells and design rules described above, thereby increasing manufacturing portability and enabling flexibility in selecting manufacturing partners based on other technology or business capabilities.

[0196] Fig.19AAn example of a macro pixel 1900 in a display panel according to some examples is shown. In the example shown, the macro pixel 1900 may include 18 micro LEDs 1910 and a circuit for driving the 18 micro LEDs 1910. The circuit for driving the 18 micro LEDs 1910 may include an IO circuit 1920, 9 bit cells 1930 for each micro LED 1910, a shared comparator 1940, a PWM latch circuit 1950 for each micro LED 1910, an analog driver circuit 1960 for each micro LED 1910, and a DFT circuit 1970. As described above, the micro LEDs 1910 and the driving circuit may be manufactured on different wafers and then bonded together by, for example, wafer-to-wafer bonding or wafer-to-wafer bonding. In some examples, at least a portion of the driving circuit may be implemented using TFTs.

[0197] Despite Fig.19A The macropixel 1900 shown in the figure includes 18 micro LEDs 1910 and circuits for driving the 18 micro LEDs 1910, but the macropixels disclosed herein may include any number of micro LEDs 1910 and corresponding driving circuits. For example, the macropixel may include 8, 10, 12, 16, 18 or more micro LEDs and corresponding driving circuits. In addition, the bit depth of each micro LED may be different from 9, such as 6 or 8. In some examples, the macropixel may not include the DFT circuit 1970. In some examples, the macropixel may include some peripheral circuits.

[0198] The bit cells 1930 in the macropixel 1900 may include standard SRAM cells (e.g., the 6T SRAM cells described above), and thus may be arranged as an SRAM cell array as in other SRAM memory devices to optimize floor plans and layouts. The comparator 1940 may be similar to the comparators 1104 and 1320 described above, but may be shared by all pixels in the macropixel 1900, for example, by time division multiplexing. In one example, the comparator 1940 may compare the counter value to each readout control word one at a time. The PWM latch circuit 1950 may be similar to the PWM latch circuits 1106 and 1330 described above. The analog driver circuit 1960 may be similar to the LED driver circuit 1108 or the analog driver circuit 1340 described above. The DFT circuit 1970 may be used to measure, for example, current-voltage (IV) characteristics of devices and components in a circuit (e.g., digital logic, SRAM, analog devices, or other circuit components).

[0199] Since some circuits (e.g., comparators) are shared between pixels, the size of a macropixel including multiple pixels can be much smaller than the total size of the same number of unit pixels. In addition, the plan view and layout of the macropixel 1900 can be optimized by arranging the same type of circuits together (as described in detail below) to reduce the transition area between different types of circuits, thereby further reducing the silicon area used by the macropixel.

[0200] Fig.19B An example of a plan view 1905 of a display panel including macro pixels according to certain examples is shown. In the example shown, the above-mentioned macro pixels 1900 can be arranged in a 2D array to form a display backplane for a 2D array of micro LEDs. For example, the macro pixels 1900 can be arranged in a hierarchy including many slices, wherein each slice can include multiple sub-arrays, and each sub-array can include multiple macro pixels. In some embodiments, peripheral circuits and / or repeaters can be included in each slice, each sub-array, or each macro pixel. In some embodiments, peripheral circuits and / or repeaters can be included in some but not all slices, some but not all sub-arrays, or some but not all macro pixels. For example, a repeater can be included only in an area that may be far from the periphery of the 2D array (e.g., an area adjacent to the center of the 2D array).

[0201] Fig. 20A Another example of a macro pixel 2000 in a display panel according to some examples is shown. In the example shown, the macro pixel 2000 may include 12 micro LEDs 2010 and a circuit for driving the 12 micro LEDs 2010. The circuit for driving the 12 micro LEDs 2010 may include an I / O circuit 2020, 6 bit cells 2030 for each micro LED 2010, a shared comparator 2040, a PWM latch circuit 2050 for each micro LED 2010, an analog driver circuit 2060 for each micro LED 2010, and a DFT circuit 2070. As described above, the micro LEDs 2010 and the circuit for driving the micro LEDs 2010 may be manufactured on different wafers and then bonded together by, for example, wafer-to-wafer bonding or wafer-to-wafer bonding. In some examples, at least a portion of the circuit for driving the micro LEDs 2010 may be implemented using TFTs.

[0202] The bit cells 2030 in the macropixel 2000 may include standard SRAM cells (e.g., the 6T SRAM cells described above), and thus may be arranged as an SRAM cell array to optimize floor plans and layouts as in other SRAM memory devices. The comparator 2040 may be similar to the comparator 1940 described above, and may be shared by all pixels in the macropixel 2000 through time division multiplexing. For example, the comparator 2040 may compare the counter value with each readout control word one at a time. The PWM latch circuit 2050 may be similar to the PWM latch circuits 1106, 1330, and 1950 described above. The analog driver circuit 2060 may be similar to the LED driver circuit 1108 described above or the analog driver circuits 1340 or 1960. The DFT circuit 2070 may be similar to the DFT circuit 1970, and may be used to measure, for example, current-voltage (IV) characteristics of devices and components in a circuit (e.g., digital logic, SRAM, analog devices, PWM latch circuit 2050, or other circuit components).

[0203] Fig. 20B Including showing according to some examples Fig. 20A A simplified schematic diagram of the circuitry of an example of a macropixel 2000 is shown in . In the example shown, the bit cells 2030 may include 6×12 bit cells arranged in 6 rows and 12 columns. Each of the 6 rows includes 12 bit cells driven by the same bit line and connected to the comparator 2040 through the I / O circuit 2020. Each of the 12 columns includes 6 bit cells for storing a control word for the pixel. The 6 bit cells in each column are connected to the same word line and can be selected together. A detailed schematic diagram of the bit cells 2030 and the I / O circuit 2020 is shown below. Fig.21 Shown in.

[0204] Fig.21 A simplified schematic diagram of a 2D array of SRAM bit cells coupled to PWM logic via bit lines and I / O circuits in an example of a macropixel 2100 according to certain examples is shown. The macropixel 2100 can be an example of a macropixel 2000. In the example shown, the macropixel 2100 can include 12 pixels, where each pixel can have a bit depth of 6. The 6×12 bit cells 2110 of the 12 pixels in the macropixel 2100 can be arranged into a continuous SRAM block, which includes a continuous 2D array of SRAM cells and an I / O circuit 2140 for reading the 2D array of SRAM cells. Each bit cell 2110 can be a 2D array of SRAM cells including 6 transistors, a word line, and two bit lines (such as Fig. 12A and Fig.21 No additional interconnects (e.g., Fig. 12B Interconnect 1212 shown in ).

[0205] An SRAM block including a continuous 2D array of SRAM cells in a macropixel 2100 may include 12 columns and 6 rows, where 72 bit cells may be connected by 12 word lines 2120 (W[0], W[1], ..., and W

[11] ) and 12 bit lines 2130 (including inverted bit lines). The 6 bit cells in each column may be used to store a control word for the pixel and may be connected to the same word line 2120. The bit lines of the 12 bit cells in each row may be connected together and may be connected to PWM logic 2150 via corresponding I / O circuits 2140. When a word line 2120 (e.g., W[i]) is activated, the bit cells in the corresponding column may be read out and the stored data bits may be sent to PWM logic 2150 via I / O circuits 2140 for generating a PWM signal to drive the micro LEDs of the pixel. I / O circuits 2140 may be an example of I / O circuits 2020. PWM logic 2150 may include a shared comparator (e.g., comparator 2040) and a PWM latch (e.g., PWM latch circuit 2050) for each pixel. The 12 control words stored in 12 columns for 12 pixels may be read out sequentially to generate corresponding PWM signals for controlling corresponding micro LEDs.

[0206] Return to reference Fig. 20B , most of the comparator 2040 can be shared by 12 pixels by, for example, time division multiplexing. The comparator 2040 can be used to compare the stored control word of the pixel with the counter value from the counter in the peripheral circuit as described above. The output of the comparator 2040 of each pixel can be latched by the corresponding PWM latch circuit 2050 of the pixel, wherein the output of the corresponding PWM latch circuit 2050 can be a PWM signal for controlling the corresponding analog driver circuit 2060 of the pixel.

[0207] The analog driver circuit 2060 for each pixel may include an LED drive transistor 2064 controlled by a reference signal to control the level of drive current provided to the micro LED 2010 of the pixel. The LED drive transistor 2064 may be a thick gate oxide transistor. A constant reference signal provided to the gate of the LED drive transistor 2064 by a circuit external to the macro pixel may be used to control the constant V GS is applied to the LED driving transistor 2064 which can operate in the saturation region. Therefore, the LED driving transistor 2064 can have an I DS, to act as a current mirror. Since a constant driving current (rather than a constant driving voltage) is provided to the micro LED 2010, a change in the contact resistance of the micro LED 2010 may not result in a change in the brightness of the micro LED 2010. The second LED driving transistor 2062 may be controlled to turn on and off by a PWM signal generated by a corresponding PWM latch circuit 2050, so that an approximately constant driving current can be provided to the micro LED 2010 during a portion of a PWM frame corresponding to the PWM signal. The second LED driving transistor 2062 may be a thin gate oxide transistor.

[0208] exist Fig. 20B In the example shown, each pixel can include a DFT circuit 2070. The DFT circuit 2070 can be connected to the analog driver circuit 2060 to measure, for example, a voltage and / or a pulse width modulated current signal at an internal node. In various examples, the DFT circuit 2070 can also be connected to other nodes in the analog driver circuit 2060, the PWM latch circuit 2050, the comparator 2040, or other circuits of the macro pixel.

[0209] Fig. 22 An example of a plan view 2200 of an example of a macro pixel 2000 according to certain examples is shown. An area 2210 in the plan view 2200 can be used for 6×12 bit cells 2030 arranged in 6 rows and 12 columns, where 6 bit cells 2030 in each column can be used to store a control word for the pixel. Six I / O circuits 2020 can be placed in a column in the area 2220 of the plan view 2200, where each I / O circuit 2020 can be aligned with a row of bit cells 2030 for sending data bits of the control word to the comparator 2040. Because the circuit types, design rules, and / or manufacturing processes of the bit cells 2030 and the I / O circuits 2020 are different, there can be a transition area 2270 between the area 2210 of the bit cells 2030 and the area 2220 of the I / O circuits 2020 to isolate the bit cells (SRAM) and the I / O circuits (digital circuits). The minimum width of a transition region between two different types of circuits may depend on, for example, the type of circuit, desired performance (eg, low noise), operating conditions, and manufacturing capabilities.

[0210] The comparator 2040 may be placed in the region 2230 adjacent to the I / O circuit 2020. The six PWM latch circuits 2050 for the six pixels may be placed in the region 2240 adjacent to the comparator 2040. The DFT circuit 2070 for the same six pixels may be placed in the region 2260 adjacent to the region 2240. The other six PWM latch circuits 2050 for the other six pixels of the macropixel 2000 may be placed in the region 2242, which is separated from the region 2210 for the bit cell 2030 by the transition region 2272. The DFT circuit 2070 for the other six pixels may be placed in the region 2262 adjacent to the region 2242. The digital circuits including the I / O circuit 2020, the comparator 2040, the PWM latch circuit 2050, and the DFT circuit 2070 may be placed together in a continuous region without a transition region or space between them.

[0211] The analog driver circuit 2060 may be placed in an area separated from the digital circuit (e.g., the PWM latch circuit 2050 and the DFT circuit 2070) by a transition area to separate the analog circuit from the digital circuit. For example, the analog driver circuit 2060 for six pixels may be placed in the area 2250, and the analog driver circuit 2060 for the other six pixels may be placed in the area 2252. The area 2250 may be separated from the area 2260 by the transition area 2270, and the area 2252 may be separated from the area 2262 by the transition area 2272.

[0212] Because the transition area in the plan view 2200 can be minimized and the comparator 2040 can be shared between pixels in the macro pixel, the size of the macro pixel can be smaller than the total size of the 12 micro LEDs on the micro LED wafer. Therefore, for each macro pixel, there may be some extra space 2280 and 2282 in the plan view 2200. As described above, the extra space in multiple macro pixels can be used to place, for example, wider traces, larger analog circuits and devices (e.g., transistors), repeaters, buffers, NAND gates (e.g., for addressing), clock circuits, circuits for turning off certain macro pixels, or other peripheral circuits.

[0213] Fig.23AAn example of a portion of a plan view 2300 of a display panel including an array of unit pixels is shown. Each unit pixel can be placed in an area 2310 including a plurality of sub-areas, such as a sub-area 2312 for placing 4 bit cells, a sub-area 2314 for a comparator, a sub-area 2316 for a PWM latch circuit, and a sub-area 2318 for an analog driver circuit. In the example shown, 4 unit pixels can form a tile 2302, wherein the bit cells of 4 adjacent unit pixels can be placed together and surrounded by a transition region 2320. Similarly, the comparators of 4 adjacent unit pixels can be placed together and surrounded by a transition region 2320, the PWM latch circuits of 4 adjacent unit pixels can be placed together and surrounded by a transition region 2320, and the analog driver circuits of 4 adjacent unit pixels can be placed together and surrounded by a transition region 2320. The tile 2302 can be repeated to form a 2D array of unit pixels. Fig.23A The portion of the plan view shown may include 12 tiles 2302 including 48 unit pixels.

[0214] like Fig.23A As shown, a larger portion (e.g., about 30% to about 50%) of the area 2310 of each unit pixel may be used as the transition area 2320. Therefore, for each unit pixel, there may not be room in the area 2310 for accommodating more bit cells. Fig.23A In the example shown, each unit pixel may include only 4 bit cells. Therefore, the display panel may need to use other techniques (such as the power law transformation and / or time dithering techniques described above) to increase the perceived bit depth to 6 or more bits, which may result in very high power consumption. In addition, the area 2310 for each unit pixel may not have space for I / O circuits, DFT circuits, repeaters, buffers, or other peripheral circuits.

[0215] Fig. 23B An example of a portion of a plan view 2350 of a display panel including a macro pixel array according to some examples is shown. The total area of ​​the plan view 2350 can be the same as the total area of ​​the plan view 2300, and can also be the same as the total area of ​​48 micro LEDs in the micro LED array. The portion of the plan view 2350 of the display panel can include four regions 2360, each of which can be used to place one macro pixel including 12 pixels. Fig. 23B The four regions 2360 shown in FIG. 23 can be used to place the driving circuits of 12×4 pixels. Each macro pixel can have Fig. 22The plan view shown in FIG. 23 and may include a sub-region 2362 for placing 6×12 bit cells, a sub-region 2372 for placing I / O circuits, a sub-region 2364 for placing comparators, a sub-region 2366 for placing PWM latch circuits, a sub-region 2374 for placing DFT circuits, and a sub-region 2368 for placing analog driver circuits. Each region 2360 may also include some transition regions 2370, which may occupy only a small portion of the region 2360 (e.g., less than about 20%, 15%, or 10%), such as Fig. 23B shown.

[0216] and Fig.23A Compared to the plan view 2300 shown in FIG. 2 , the plan view 2350 can accommodate more bit cells (e.g., ≥ 6 bit cells) per pixel, include additional circuits (e.g., DFT circuits), and use less area. There may also be some additional space 2380 that can be used to place other circuits, such as local control circuits, buffers, repeaters, etc. The higher area efficiency of the macropixel can enable more design flexibility (e.g., using standard bit cells and design rules), thereby increasing manufacturing portability and enabling the selection of manufacturing partners based on other considerations.

[0217] Fig.24A A simplified block diagram of an example of a slice 2400 of a display panel including a macropixel array according to some examples is shown. Fig.24A In the example shown in , the slice 2400 may include a plurality of sub-arrays 2410 that may be arranged in a linear array. Each sub-array 2410 may include a plurality of macro-pixels 2412 arranged in an array. Fig.24A In the example shown in , each sub-array 2410 may include 8 macro-pixels 2412. As described above, each macro-pixel 2412 may include a plurality of pixels, such as 8, 10, 12, 16, or 18 pixels. Fig.24A In the example shown in , each macro pixel may include 12 pixels. Therefore, each sub-array 2410 may include a driving circuit for 96 micro LEDs (comprising, for example, 6×12×8=576 bit cells).

[0218] In addition, each subarray 2410 may include local repeaters and peripheral logic 2414, which may include, for example, one or more repeaters (e.g., inverters for boosting signal levels and adjusting waveforms), buffers, circuits for subarray addressing (e.g., decoders for selecting subarrays), clock circuits, local control circuits (e.g., for shutting down or gating clocks to subarrays), and / or other circuits for supporting data movement. In addition, each slice may include additional slice-level peripheral circuits 2420, which may include, for example, counter circuits for generating counter values ​​to generate PWM signals, power-law lookup tables, column drivers, row drivers, circuits for selecting slices or shutting down slices, etc.

[0219] Fig. 24B A simplified block diagram of an example of a display backplane 2405 including a 2D array of macropixels arranged in a hierarchical structure according to some examples is shown. In the example shown, the display backplane 2405 may include a 2D array of slices 2400. As described above with respect to Fig.24A As described, each slice 2400 may include multiple sub-arrays, for example, dozens (such as, about 50 or 60) sub-arrays. Each sub-array may include multiple macro-pixels, for example, 8 or more macro-pixels. Each macro-pixel may include multiple pixels, for example, 8, 10, 12, 14, 16, 18 or 20 pixels. Each sub-array may include local repeaters and / or other peripheral circuits. Each slice may also include additional peripheral circuits. Multiple hierarchical levels and local peripheral circuits within the display backplane 2405 may enable data in the SRAM and PWM logic to be efficiently and electrically robustly moved.

[0220] exist Fig. 24BIn the example shown, a subarray including a peripheral logic circuit (e.g., a local repeater) of the subarray can be within the display area 2402 of the display panel, where the peripheral logic circuit drives a signal for sorting macropixels and feeding data to the macropixels. The peripheral logic circuits and repeaters within the display area 2402 can help solve some challenges associated with the above-mentioned unit pixel array architecture. For example, as described above, signals broadcast on a large (e.g., millimeter-level) pixel array may suffer from large attenuation or time delay due to large wire resistance and capacitance, which may affect timing and noise tolerance and cause errors, reliability or other performance issues. These challenges can be at least partially solved by making room for repeaters within the pixel array. Each slice, each subarray and / or each macropixel may include some local peripheral circuits and / or repeaters to achieve efficient and electrically robust movement of data in SRAM and PWM logic. Local repeaters and / or other peripheral circuits within the display area 2402 can, for example, boost signals on long bit lines and / or word lines, and adjust the waveforms of signals on bit lines and / or word lines so that the signals can have high amplitudes and short rise / fall times. Therefore, the signal level and timing (eg, rising / falling edges) of the signal from the peripheral circuit can be replicated or restored at the macro-pixel, thereby improving timing and noise margin (eg, write time margin).

[0221] In addition, local peripheral circuits at various hierarchical levels may include power saving features to control the pixel array at various granularities (e.g., at a macro-pixel level, at a sub-array level, or at a slice level). In an AR / VR display system, some displayed images may have a low fill factor without significantly affecting the user experience, such as having a completely transparent area for augmented reality display or displaying an image only in an area where the user's eyes are focused. In each 12×8 pixel area, more than 4000 bytes of local SRAM access and more than 6000 comparison operations per frame may be performed without affecting the display quality, which may consume a lot of power. Therefore, for images with a low fill factor, only a portion of the display panel may need to have a high-quality image, and therefore only the PWM signal for that portion of the display panel may be calculated. In addition, image data and PWM signals may not be required for areas outside the gaze area of ​​the user's eyes. Therefore, in some embodiments, certain areas of the display panel may be turned off, or may be kept at a low illumination intensity (e.g., by gating the clocks of these areas), thereby reducing the overall power consumption of the display panel. In the macropixel architecture disclosed herein, clock gating can be performed at the slice, subarray, or macropixel level, so that pixels outside the region of interest can be clock-gated for low-power, low-fill-factor workloads, thereby reducing power consumption of the display panel.

[0222] Additional slice-level peripheral circuits 2420 for each slice may be outside the display area 2402 and may include, for example, counter circuits and power-law lookup tables. Data loading and update paths 2430 may be within each slice 2400, from the slice-level peripheral circuits 2420 outside the display area 2402 to the subarrays and macropixels in the central region of the display area 2402. Power distribution paths 2440 may be orthogonal to the data loading and update paths 2430 and may span different slices.

[0223] Fig.25 A diagram 2500 is included that shows an example of Verilog simulation results of the operation of a macropixel in a display panel according to certain examples. In the simulation, the macropixel can be driven by, for example, 32 digital inputs / outputs and 3 analog inputs / outputs. These signals can be sequenced to load data into the macropixel and initiate comparison and PWM update operations. The diagram 2500 shows the simulated output PWM signal 2510 in four frames of the pixel, where the values ​​stored in the bit cells are 00, 01, 10, and 11 for frames 1-4, respectively.

[0224] Fig.26 Included is a chart 2600 showing an example of Spice simulation results of the operation of a macropixel in a display panel according to certain examples. In the simulation, the macropixel can be driven by, for example, 32 digital inputs / outputs and 3 analog inputs / outputs. These signals can be sequenced to load data into the macropixel and initiate comparison and PWM update operations. Chart 2600 shows the simulated output PWM signal 2610 in four frames of the pixel, where the values ​​stored in the bit cells are 00, 01, 10, and 11 for frames 1-4, respectively.

[0225] Fig. 27 A graph 2700 is included that illustrates an analog output PWM signal for a macropixel for different display values ​​according to some examples. In the example shown, the display value (control word) stored in the bit cell can increase from 0 to 127, and the pulse width of the analog output PWM signal can increase approximately linearly with the increase in the display value.

[0226] Fig.28 A chart 2800 is included, which shows an analog output PWM signal for a macro pixel with different display values ​​using a power law transformation according to some examples. In the example shown, the display value (control word) stored in the bit unit can increase from 0 to 127. The pulse width of the analog output PWM signal can increase nonlinearly with the increase of the display value according to the above power law (with a certain gamma value), so that the luminance of the micro LED driven by the PWM signal can increase nonlinearly with the increase of the display value.

[0227] Fig.29 An example of simulation results for a macropixel in rolling update mode with power-law (gamma) updating according to certain examples is shown. Fig.29 A mapping curve 2910 is included that shows a 6-bit display code for PWM and a corresponding ideal discretized update counter value (or clock period) (which may include some small discretization or quantization error) to achieve gamma correction in an example of an operating condition. In the example shown, the gamma value for gamma correction can be 1.9, the clock frequency can be about 25 MHz, the horizontal synchronization (HSYNC) period can be about 8 μs, and each row can be updated in about 800 μs (on time). For other operating conditions, the corresponding mapping curve 2910 may be different.

[0228] As described above, in the macropixel architecture disclosed herein, each macropixel can drive multiple micro-LEDs at the same time, but because the comparator is shared between the pixels in the macropixel through time division multiplexing, the PWM signal of only one pixel can be updated at a time. The update time may depend on, for example, the gamma value, the clock frequency, and the horizontal synchronization (HSYNC) frequency. Due to the time division multiplexing of the comparator, the update time of each pixel in the macropixel may be slightly different depending on the position of the pixel. Therefore, there may be some periodic artifacts that can be perceived by the human eye (e.g., due to the periodic arrangement of pixels and macropixels).

[0229] Simulation results show that the macropixel architecture disclosed herein is also robust in rolling update mode and is compatible with power-law transformations (e.g., gamma correction). For many display configurations, and for certain display codes, the macropixel architecture may only result in deviations from the ideal discretized gamma correction (e.g., due to update time mismatches between pixels) of less than 0.5% of the LSB. Fig.29 The deviation of the update counter value shown in the mapping curve 2910 of the 6-bit display code and the corresponding appropriate update counter value to the gamma value (e.g., 1.9) under operating conditions is shown. In some examples, to compensate for the perturbation of the ideal discretized gamma correction caused by the macropixel architecture, for some or all display codes, the actual mapping curve and corresponding gamma lookup table can be slightly modified (e.g., less than 0.5% of the LSB) to achieve conflict-free updates so that any deviation of the brightness of the micro LEDs from the desired brightness can be not spatially periodic and can be minimized.

[0230] Fig.30A simplified schematic diagram of an example of a DFT circuit 3000 in a macropixel-based display backplane according to certain examples is included. The DFT circuit 3000 may include an on-wafer low-yield analysis circuit that can be used to curve-trace individual transistors within a macropixel and read out the results in an automated manner. Fig.30 The macrocell is shown to include two DFT transistors 3010 and 3012 connected to an analog driver 3005 for each corresponding pixel in the macropixel. Fig.30 Also shown is a DFT circuit 3020 for controlling DFT transistors 3010 and 3012 outside the macro pixel array. DFT circuit 3000 may also include other devices (not shown) connected to the macro pixel. Fig.30 In-pixel DFT circuitry (eg, bit cells, comparator, and PWM latch circuits) is shown in FIG.

[0231] The DFT circuit 3000 can be used to measure the current-voltage (IV) characteristics of internal devices during the design, debugging and / or process development phases to determine the root cause of failures or errors in the design or manufacturing process. The DFT circuit 3000 can also be used for manufacturing testing during mass production to screen defective devices by electrically controlling and observing internal signals in logic, SRAM, and analog circuits.

[0232] As described above, the drive current of the analog LED driver transistor in the unit pixel structure may vary significantly (e.g., due to random dopant fluctuations) and may result in brightness differences of about 3 times or more. Due to the additional space available in the macro pixel structure, the size of the analog LED driver transistor can be increased to reduce the variation of the analog LED driver transistor (e.g., drive current) caused by random dopant fluctuations. For example, the channel length L of the LED driver transistor 2064 can be increased to increase the size of the LED driver transistor 2064 (to be larger than the minimum size specified by the wafer foundry, such as larger than about 400nm) so that the drive current (I ds ) can be much smaller due to the averaging of random dopant fluctuations in a larger area. Therefore, the brightness variation of the micro-LED can also be reduced. In addition, increasing the channel length of the LED driver transistor 2064 can also advantageously bias the LED driver transistor 2064 in a more stable bias region for low current levels (e.g., a few hundred nanoamperes, such as about 250nA). In some examples, the change in the drive current of the LED driver transistor can be measured, for example, using the above-mentioned DFT circuit, and then compensation can be made based on a calibration factor determined using the measured change.

[0233] Fig.31It is shown that according to some examples, the drive current uniformity and LED brightness uniformity can be improved by increasing the size of the LED drive transistor. Fig.31 , chart 3110 shows an example of a distribution of simulated drive currents of LED drive transistors in a display panel based on a unit pixel due to variations in the LED drive transistors (e.g., caused by random dopant fluctuations). Chart 3110 may be the same as chart 1800 described above. As shown, the target drive current may be approximately 240 nA. However, the drive current may vary with a standard deviation δ of approximately 36 nA. Based on the micro-LED output characteristics (e.g., light-current-voltage (LIV) curve), the drive current variation shown in chart 3110 may result in a brightness difference of approximately 3.11 times based on the expected typical light output for a drive current within ±3δ of the average drive current.

[0234] Fig.31 Graph 3120 in shows an example of a distribution of analog drive current for an LED driver transistor (e.g., LED driver transistor 2064) with an increased channel length in a macropixel-based display panel according to certain examples. Graph 3120 shows that, as the size (e.g., channel length) increases, the distribution of the analog drive current of the LED driver transistor can have an average value of about 240 nA and a standard deviation δ (e.g., about 15 nA) of less than about 20 nA. Based on the output characteristics of the micro-LEDs (e.g., LIV curve), the drive current variation shown in graph 3120 can result in a brightness difference of about 1.55 times, which can be half the variation shown in graph 3110, based on the expected typical light output for a drive current within ±3δ of the average drive current. Thus, using a larger LED driver transistor can significantly improve the uniformity of the drive current, and therefore improve the uniformity of the brightness of the micro-LEDs.

[0235] Fig.32 A simplified cross-sectional view of a device including a display backplane wafer 3210 bonded to a micro LED wafer 3220 via an interconnect layer 3230 is shown according to some examples. The display backplane wafer 3210 may include an example of the display backplane 2405 described above. Fig.32 The thick gate oxide LED driver transistor 3212 of the macro pixel (eg, LED driver transistor 2064) is shown. The thick gate oxide LED driver transistor 3212 of the macro pixel is arranged as described above with respect to, for example, Fig. 22 and Fig. 23B The same area of ​​the macro pixel described above can be used to reduce the transition area between the analog circuit and the digital logic or SRAM unit. Similarly, as described above, other circuits of the macro pixel (not in the Fig.3232). The micro LED wafer 3320 may include a two-dimensional array of micro LEDs 3222, which are evenly spaced at a pitch of, for example, 2 μm or 1.8 μm. The evenly spaced micro LEDs 3222 and corresponding thick gate oxide LED driver transistors 3212 may be connected together by an interconnect layer 3230, which may include a redistribution routing interconnect 3232. The redistribution routing interconnect 3232 may include, for example, metal traces in one or more metal layers and vias between one or more metal layers.

[0236] The macropixel architecture and display backplane based on the macropixel architecture described in this article can allow the use of 6 or more bit cells (e.g., 6, 7, 8, or 9 bit cells) for each 2μm or 1.8μm pixel to obtain better display quality with lower time jitter power overhead; reduce the variation of micro-LED drive current to make the brightness more uniform; improve the design tolerance of SRAM and other circuits and reduce digital VDD (e.g., by 300mV or more); include pixel testing and debugging functions; allow clock gating at the slice level, sub-array level, or macropixel level to reduce power for displaying low fill factor AR images; and eliminate strict process design rules to improve foundry portability.

[0237] The embodiments and examples disclosed herein may be used to implement components of an artificial reality system, or may be implemented in conjunction with an artificial reality system. Artificial reality is a form of reality that has been adjusted in some way before being presented to a user, which may include, for example, virtual reality, augmented reality, mixed reality, hybrid reality, or some combination and / or derivative thereof. Artificial reality content may include fully generated content or content generated in combination with captured (e.g., real world) content. Artificial reality content may include video, audio, tactile feedback, or some combination thereof, and any of which may be presented in a single channel or in multiple channels (e.g., stereoscopic video that produces a three-dimensional effect to the viewer). Additionally, in some embodiments and examples, artificial reality may also be associated with applications, products, accessories, services, or some combination thereof for, for example, creating content in artificial reality and / or otherwise using it in artificial reality (e.g., performing activities in artificial reality). Artificial reality systems that provide artificial reality content may be implemented on a variety of platforms, including an HMD connected to a host computer system, an independent HMD, a mobile device or computing system, or any other hardware platform capable of providing artificial reality content to one or more viewers.

[0238] Fig.333300 is a simplified block diagram of an example electronic system 3300 for implementing an example near-eye display (e.g., HMD device) of some examples disclosed herein. The electronic system 3300 can be used as an electronic system for the HMD device or other near-eye display described above. In this example, the electronic system 3300 may include one or more processors 3310 and a memory 3320. The processor 3310 may be configured to execute instructions for performing operations at multiple components, and may be, for example, a general-purpose processor or a microprocessor suitable for implementation in a portable electronic device. The processor 3310 may be communicatively coupled to multiple components within the electronic system 3300. To achieve such communicatively coupling, the processor 3310 may communicate with other illustrated components on a bus 3340. The bus 3340 may be any subsystem suitable for transmitting data within the electronic system 3300. The bus 3340 may include multiple computer buses and additional circuits to transmit data.

[0239] Memory 3320 may be coupled to processor 3310. In some examples, memory 3320 may provide both short-term storage and long-term storage, and may be divided into several units. Memory 3320 may be volatile (such as static random access memory (SRAM) and / or dynamic random access memory (DRAM)) and / or non-volatile (such as read-only memory (ROM), flash memory, etc.). In addition, memory 3320 may include a removable storage device such as a secure digital (SD) card. Memory 3320 may provide storage of computer-readable instructions, data structures, program modules, and other data for electronic system 3300. In some examples, memory 3320 may be distributed in different hardware modules. A set of instructions and / or codes may be stored in memory 3320. The instructions may be in the form of executable code that can be executed by the electronic system 3300, and / or may be in the form of source code and / or installable code that, when compiled and / or installed on the electronic system 3300 (e.g., using any of a variety of commonly available compilers, installers, compression / decompression utilities, etc.), may be in the form of executable code.

[0240] In some examples, the memory 3320 may store a plurality of application modules 3322 to 3324, which may include any number of applications. Examples of applications may include gaming applications, conference applications, video playback applications, or other suitable applications. These applications may include depth sensing functions or eye tracking functions. The application modules 3322-3324 may include specific instructions to be executed by the processor 3310. In some examples, some applications or portions of the application modules 3322-3324 may be executed by other hardware modules 3380. In some examples, the memory 3320 may additionally include a secure memory, which may include additional security controls to prevent copying or other unauthorized access to secure information.

[0241] In some examples, memory 3320 may include an operating system 3325 loaded therein. Operating system 3325 may be operable to initiate execution of instructions provided by application modules 3322-3324 and / or manage other hardware modules 3380 and interfaces with wireless communication subsystem 3330, which may include one or more wireless transceivers. Operating system 3325 may be adapted to perform other operations on components of electronic system 3300, including threading, resource management, data storage control, and other similar functions.

[0242] The wireless communication subsystem 3330 may include, for example, an infrared communication device, a wireless communication device and / or a chipset (such as, Device, IEEE 802.11 device, Wi-Fi device, WiMax device, cellular communication facility, etc.) and / or similar communication interface. Electronic system 3300 may include one or more antennas 3334 for wireless communication as part of wireless communication subsystem 3330 or as a separate component coupled to any part of the system. Depending on the desired functionality, wireless communication subsystem 3330 may include a separate transceiver to communicate with base transceiver stations and other wireless devices and access points, which may include communicating with different data networks and / or network types (such as wireless wide area networks (WWANs), wireless local area networks (WLANs), or wireless personal area networks (WPANs)). A WWAN may be, for example, a WiMax (IEEE 802.16) network. A WLAN may be, for example, an IEEE 802.11x network. A WPAN may be, for example, a Bluetooth network, IEEE802.15x, or some other type of network. The techniques described herein may also be used for any combination of WWANs, WLANs, and / or WPANs. Wireless communication subsystem 3330 may allow data to be exchanged with a network, other computer systems, and / or any other device described herein. The wireless communication subsystem 3330 may include means for sending or receiving data (e.g., an identifier of the HMD device, location data, geographic map, heat map, photo, or video) using an antenna 3334 and a wireless link 3332. The wireless communication subsystem 3330, the processor 3310, and the memory 3320 may together comprise at least a portion of one or more of the means for performing some of the functions disclosed herein.

[0243] The example of the electronic system 3300 may also include one or more sensors 3390. The sensor 3390 may include, for example, an image sensor, an accelerometer, a pressure sensor, a temperature sensor, a proximity sensor, a magnetometer, a gyroscope, an inertial sensor (e.g., a module combining an accelerometer and a gyroscope), an ambient light sensor, or any other similar module operable to provide a sensing output and / or receive a sensing input, such as a depth sensor or a position sensor. For example, in some embodiments, the sensor 3390 may include one or more inertial measurement units (IMUs) and / or one or more position sensors. The IMU may generate calibration data based on measurement signals received from one or more position sensors, the calibration data indicating an estimated position of the HMD device relative to an initial position of the HMD device. The position sensor may generate one or more measurement signals in response to a movement of the HMD device. Examples of position sensors may include, but are not limited to, one or more accelerometers, one or more gyroscopes, one or more magnetometers, another suitable type of sensor that detects movement, a type of sensor used for error correction of the IMU, or any combination thereof. The position sensors may be located external to the IMU, internal to the IMU, or any combination thereof.At least some of the sensors may use structured light patterns for sensing.

[0244] The electronic system 3300 may include a display module 3360. The display module 3360 may be a near-eye display and may graphically present information from the electronic system 3300, such as images, videos, and various instructions, to a user. Such information may be derived from one or more application modules 3322-3324, a virtual reality engine 3326, one or more other hardware modules 3380, a combination thereof, or any other suitable means for parsing graphical content for a user (e.g., via an operating system 3325). The display module 3360 may use LCD technology, LED technology (including, for example, OLED, ILED, μ-LED, AMOLED, TOLED, etc.), light emitting polymer display (LPD) technology, or some other display technology.

[0245] The electronic system 3300 may include a user input / output module 3370. The user input / output module 3370 may allow a user to send an action request to the electronic system 3300. The action request may be a request to perform a specific action. For example, the action request may be to start or end an application, or to perform a specific action within an application. The user input / output module 3370 may include one or more input devices. Example input devices may include a touch screen, a touch pad, a microphone, a button, a dial, a switch, a keyboard, a mouse, a game controller, or any other suitable device for receiving an action request and transmitting the received action request to the electronic system 3300. In some examples, the user input / output module 3370 may provide tactile feedback to the user according to instructions received from the electronic system 3300. For example, tactile feedback may be provided when an action request is received or an action request has been executed.

[0246] The electronic system 3300 may include a camera 3350, which may be used to take photos or videos of the user, for example, to track the user's eye position. The camera 3350 may also be used to take photos or videos of the environment, for example, for VR applications, AR applications, or MR applications. The camera 3350 may include, for example, a complementary metal oxide semiconductor (CMOS) image sensor having millions or tens of millions of pixels. In some embodiments, the camera 3350 may include two or more cameras, which may be used to capture 3D images.

[0247] In some examples, the electronic system 3300 may include multiple other hardware modules 3380. Each of the other hardware modules 3380 may be a physical module within the electronic system 3300. Although each of the other hardware modules 3380 may be permanently configured as a structure, some of the other hardware modules 3380 may be temporarily configured to perform a specific function or be temporarily activated. Examples of other hardware modules 3380 may include, for example, an audio output and / or input module (e.g., a microphone or speaker), a near field communication (NFC) module, a rechargeable battery, a battery management system, a wired / wireless battery charging system, and the like. In some examples, one or more functions of the other hardware modules 3380 may be implemented in software.

[0248] In some examples, the memory 3320 of the electronic system 3300 may also store a virtual reality engine 3326. The virtual reality engine 3326 may execute an application within the electronic system 3300 and receive position information, acceleration information, velocity information, predicted future position, or any combination thereof of the HMD device from various sensors. In some examples, the information received by the virtual reality engine 3326 may be used to generate a signal (e.g., a display instruction) for the display module 3360. For example, if the received information indicates that the user has looked to the left, the virtual reality engine 3326 may generate content for the HMD device that reflects the user's movement in the virtual environment. Additionally, the virtual reality engine 3326 may perform an action within the application in response to an action request received from the user input / output module 3370, and provide feedback to the user. The feedback provided may be visual feedback, auditory feedback, or tactile feedback. In some embodiments, the processor 3310 may include one or more GPUs that may execute the virtual reality engine 3326.

[0249] In various embodiments, the hardware and modules described above can be implemented on a single device, or on multiple devices that can communicate with each other using wired or wireless connections. For example, in some embodiments, some components or modules (e.g., GPU, virtual reality engine 3326, and applications (e.g., tracking applications)) can be implemented on a console separate from the head mounted display device. In some embodiments, a console can be connected to more than one HMD or can support more than one HMD.

[0250] In alternative configurations, different and / or additional components may be included in the electronic system 3300. Similarly, the functionality of one or more components may be distributed among the components in a manner different from that described above. For example, the electronic system 3300 may be modified to include other system environments, such as an AR system environment and / or an MR environment.

[0251] The methods, systems, and devices discussed above are examples. Various embodiments may omit, replace, or add various processes or components as appropriate. For example, in alternative configurations, the described methods may be performed in an order different from that described, and / or various stages may be added, omitted, and / or combined. In addition, the features described with respect to certain embodiments and examples may be combined in various other embodiments and examples. Different aspects and elements of the embodiments and examples may be combined in a similar manner. In addition, technology is constantly evolving, and therefore many elements are examples, which do not limit the scope of this disclosure to those specific examples.

[0252] Specific details are given in the description to provide a thorough understanding of the embodiments. However, embodiments can be implemented without these specific details. For example, in order to avoid obscuring the embodiments, well-known circuits, processes, systems, structures and techniques have been shown without unnecessary details. This description only provides examples and is not intended to limit the scope, applicability or configuration of the present invention. Instead, the foregoing description of embodiments and examples will provide enabling descriptions (enabling descriptions) for implementing various embodiments for those skilled in the art. Various changes can be made to the functions and arrangements of elements without departing from the scope of the present disclosure.

[0253] In addition, some embodiments and examples are described as processes depicted as flow charts or block diagrams. Although each can describe the operation as a sequential process, many operations can be performed in parallel or concurrently. In addition, the order of the operations can be rearranged. The process can have additional steps not included in the figure. In addition, the embodiment of the method can be implemented by hardware, software, firmware, middleware, microcode, hardware description language or any combination thereof. When implemented with software, firmware, middleware or microcode, the program code or code segment performing the associated task can be stored in a computer-readable medium such as a storage medium. The processor can perform the associated task.

[0254] It will be apparent to those skilled in the art that substantial variations may be made depending on specific requirements. For example, customized hardware or dedicated hardware may also be used, and / or specific elements may be implemented in hardware, software (including portable software, such as applets, etc.), or both. In addition, connections to other computing devices such as network input / output devices may be employed.

[0255] With reference to the accompanying drawings, the components that may include memory may include non-transitory machine-readable media. The terms "machine-readable medium" and "computer-readable medium" may refer to any storage medium that participates in providing data that enables a machine to operate in a particular manner. In the embodiments and examples provided above, various machine-readable media may be involved when providing instructions / codes to a processing unit and / or other devices for execution. Additionally or alternatively, a machine-readable medium may be used to store and / or carry such instructions / codes. In many embodiments, a computer-readable medium is a physical storage medium and / or a tangible storage medium. Such a medium may take a variety of forms, including but not limited to non-volatile media, volatile media, and transmission media. Common forms of computer-readable media include, for example, magnetic media and / or optical media (such as compact disks (CDs) or digital versatile disks (DVDs)), punch cards, paper tapes, any other physical media with hole patterns, RAM, programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), flash-EPROM, any other memory chip or box, a carrier wave as described below, or any other medium from which a computer can read instructions and / or codes. A computer program product may include code and / or machine executable instructions, which may represent a procedure, function, subprogram, program, routine, application (App), subroutine, module, software package, class, or any combination of instructions, data structures, or program statements.

[0256] Those skilled in the art will appreciate that the information and signals used to transmit the messages described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0257] The terms "and" and "or" as used herein may include multiple meanings, which are also expected to depend at least in part on the context in which such terms are used. Generally, "or", if used in an associative list, such as A, B, or C, is intended to mean A, B, and C (used herein in an inclusive sense) as well as A, B, or C (used herein in an exclusive sense). In addition, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in a singular form, or may be used to describe a certain combination of features, structures, or characteristics. However, it should be noted that this is merely an illustrative example, and the subject matter claimed is not limited to this example. In addition, the term "at least one of...", if used in an associative list, such as A, B, or C, may be interpreted to mean any combination of A, B, and / or C, such as A, AB, AC, BC, AA, ABC, AAB, AABBCCC, etc.

[0258] In addition, although certain embodiments and examples have been described using a specific combination of hardware and software, it should be appreciated that other combinations of hardware and software are possible. Certain embodiments and examples may be implemented in hardware only, or in software only, or using a combination thereof. In one example, the software may be implemented using a computer program product comprising computer program codes or instructions that may be executed by one or more processors for performing any or all steps, operations, or processes described in this disclosure, wherein the computer program may be stored on a non-transitory computer-readable medium. The various processes described herein may be implemented on the same processor or on different processors in any combination.

[0259] Where a device, system, component or module is described as being configured to perform certain operations or functions, such configuration may be accomplished, for example, by designing electronic circuits that perform the operations, by programming programmable electronic circuits (such as microprocessors) to perform the operations (such as by executing computer instructions or code), or by a processor or core programmed to execute code or instructions stored on a non-transitory memory medium, or any combination thereof. Processes may communicate using a variety of techniques (including, but not limited to, conventional techniques for inter-process communication), and different pairs of processes may use different techniques, or the same pair of processes may use different techniques at different times.

[0260] Therefore, the description and drawings should be regarded as illustrative rather than restrictive. However, it is obvious that additions, deletions, deletions and other modifications and changes may be made thereto without departing from the broader scope set forth in the claims. Therefore, although specific embodiments and examples have been described, these embodiments and examples are not intended to be limiting. Various modifications and equivalents are within the scope of the appended claims.

Claims

1. A display device, comprising: a first wafer including a 2D array of micro-LEDs in a display area; and a second wafer vertically bonded to the first wafer, the second wafer comprising a micro LED driver backplane, the micro LED driver backplane comprising a 2D array of sub-arrays, wherein each sub-array in the 2D array of sub-arrays comprises: a driving circuit configured to generate a pulse width modulated driving signal to drive a group of micro LEDs in the 2D array of micro LEDs; and a local peripheral circuit for controlling the driving circuit of the subarray, the local peripheral circuit being located within the display area and comprising at least one of: a buffer, a repeater, a clock gating circuit for gating an input clock signal to the subarray, or a subarray decoder for selecting the subarray; Wherein, each sub-array in the 2D array of sub-arrays includes a macro-pixel array, each macro-pixel in the macro-pixel array includes a continuous 2D array of bit cells, and the continuous 2D array of bit cells stores display data bits for driving a subset of micro-LEDs of the group of micro-LEDs.

2. The display device according to claim 1, wherein: each bit cell in the contiguous 2D array of bit cells comprises a six-transistor static random access memory cell including a word line, two bit lines, and two internal state storage nodes for storing a corresponding one of the display data bits; and Each bit cell in the contiguous 2D array of bit cells is configured to read the corresponding one of the display data bits from the bit cell via the two bit lines.

3. The display device according to claim 1, wherein: Each macropixel in the macropixel array further includes: a respective current driver for each micro-LED in the subset of micro-LEDs, the respective current driver being configured to provide a drive current to the micro-LED; a comparator configured to compare, for each micro LED in the subset of micro LEDs, the display data bit used to drive the micro LED with a counter value; and a respective pulse width modulation latch for each micro LED in the subset of micro LEDs, the respective pulse width modulation latch being configured to generate a pulse width modulation control signal based on an output for the micro LED generated by the comparator, the pulse width modulation control signal being used to modulate the drive current of the respective current driver for the micro LED to generate a respective pulse width modulation drive signal in the pulse width modulation drive signal.

4. The display device according to claim 3, wherein: The respective current drivers for two or more micro LEDs in the subset of micro LEDs are arranged consecutively in an area of ​​the macro pixel that is separated from an area of ​​the macro pixel for other circuits by a transition area.

5. The display device according to claim 3, wherein: The respective current drivers for the subset of micro LEDs are connected to the subset of micro LEDs in the 2D array of micro LEDs through an interconnect layer including redistribution routing interconnects.

6. The display device according to claim 3, wherein: The respective pulse width modulation latches for two or more micro LEDs in the subset of micro LEDs are arranged consecutively in the area of ​​the macro pixel.

7. The display device according to claim 6, wherein: The comparator is configured as: reading and comparing display data bits for driving a first micro LED in the subset of micro LEDs within a first time window; and Display data bits used to drive a second micro LED in the subset of micro LEDs are read and compared within a second time window.

8. The display device according to any one of claims 1 to 7, wherein: Each macro-pixel in the macro-pixel array also includes a corresponding design-for-testability circuit for each micro-LED in the subset of micro-LEDs.

9. The display device according to claim 8, wherein: Each macropixel in the macropixel array further includes corresponding input / output circuitry configured to read a display data bit stored in each row or column of the contiguous 2D array of bit cells.

10. The display device according to claim 8, wherein: The contiguous 2D array of bit cells includes at least 6 bit cells for each micro LED in the subset of micro LEDs.

11. The display device according to claim 8, wherein: The micro-LED subset includes 8 or more micro-LEDs.

12. The display device according to claim 1, wherein: A plurality of sub-arrays of the 2D array of sub-arrays are included in a slice of the micro LED driver backplane, the slice including a slice peripheral circuit for controlling the plurality of sub-arrays.

13. The display device according to claim 12, wherein: The slice peripheral circuit includes at least one of a counter or a lookup table for gamma correction.

14. The display device according to claim 12, wherein: The micro LED driver backplane includes peripheral circuits external to the 2D array of sub-arrays.

15. The display device according to claim 12, wherein: The peripheral circuit includes at least one of a counter or a lookup table for gamma correction, the lookup table storing display data codes and corresponding counter values.

16. The display device according to claim 15, wherein: The corresponding counter value of at least one display data code in the lookup table is different from an ideal counter value determined for the at least one display data code based on a gamma value.

17. The display device according to claim 12, wherein: The repeater is configured to replicate a control signal generated by the peripheral circuit and used to control the driving circuit of the sub-array.

18. The display device according to claim 17, wherein: The peripheral circuit can be configured to send a control signal to the clock gating circuit for gating the input clock signal to the sub-array to disable the drive circuit configured to generate the pulse width modulated drive signal.

19. The display device according to claim 17, wherein: The pitch of the 2D array of micro LEDs is equal to or less than 2 μm.

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